A photonic computing chip architecture and method of operation

Abstract

The application relates to the technical field of photonic computing, and discloses a photonic computing chip architecture which comprises a host computer, an analog front end, an adjustable multi-wavelength light source, a first modulator array, a wavelength multiplexer, a signal beam splitter, a second modulator array, a wavelength demultiplexer array, an optical detector array and a support device; the host computer divides data into a first signal sequence and a second signal sequence, realizes multiplexing of the first signal sequence and the second signal sequence, greatly expands the parallel degree of computation, thereby increases the throughput, and reduces the energy consumption of each multiplication and addition operation. Moreover, the application adds a phase modulation function to the first modulator array and the second modulator array, and introduces coherent detection in the optical detector array, so that the data operation delay and energy consumption of real numbers or complex numbers are lower, the number of devices required to be integrated on the photonic chip is reduced, the cost is lower, and the manufacturing difficulty is reduced. The application further provides an operation method of the photonic computing chip architecture.

Description

Technical Field

[0001] This invention relates to the field of photonic computing technology, and in particular to a photonic computing chip architecture and computing method. Background Technology

[0002] The rapid development of data-driven intelligent technologies such as machine learning and general artificial intelligence relies heavily on the fast and efficient computation and processing of massive amounts of multimodal data. As Moore's Law gradually fails and the development of traditional computer processors approaches their physical limits, processing massive amounts of data while maintaining low energy consumption has become a significant challenge. Alleviating this challenge urgently requires a data computing and processing technology that simultaneously offers high data throughput and low power consumption.

[0003] In recent years, photonic computing technology has demonstrated advantages in high throughput, low latency, and low energy consumption in data computation and processing in numerous scientific studies, and it is expected to become a solution to overcome the aforementioned contradictions. Integrated photonic circuits are a type of technology with advantages such as compact size, powerful functionality, low computational latency, and low energy consumption. Although existing research has demonstrated or pointed out the specific designs and implementation schemes of various integrated photonic circuits, most of them require the introduction of mechanisms such as multi-device collaboration, multi-multiplexed wavelength coordination, and optoelectronic domain collaboration in a single operation to complete the multiplication and accumulation operations of data, resulting in complex implementation and operation methods. Furthermore, the scalability of their computational scale is limited by the area of ​​the integrated photonic chip and the number of available wavelengths, which restricts their actual achievable throughput. In practical application scenarios, they also have disadvantages such as inflexibility and speed limitations in switching computational functions and computational tasks. Summary of the Invention

[0004] The purpose of this invention is to provide a photonic computing chip architecture and computing method that can greatly expand the parallelism of computing and thus increase throughput, while reducing the energy consumption of each multiply-accumulate operation.

[0005] To achieve the above objectives, the present invention provides a photonic computing chip architecture, including a host computer, an analog front-end, an adjustable multi-wavelength light source, a first modulator array, a wavelength multiplexer, a signal beam splitter, a second modulator array, a wavelength demultiplexer array, a photodetector array, and supporting equipment. The first modulator array includes multiple optical amplitude modulators, and the second modulator array includes multiple ring modulators.

[0006] The host computer is connected to the analog front end, which is connected to the first modulator array and the second modulator array respectively. The adjustable multi-wavelength light source, the first modulator array, the wavelength multiplexer, the signal beam splitter, the second modulator array, the wavelength demultiplexer array, and the photodetector array are connected in sequence.

[0007] The host computer is used for data storage. According to the operation task, it reads the stored data and arranges it into a first signal sequence and a second signal sequence. It sets the symbol arrangement order and symbol period of the first signal sequence and the second signal sequence according to the operation type. It processes the first signal sequence and the second signal sequence according to the photodetector type of the photodetector array, the modulator type of the first modulator array and the second modulator array, and the data type.

[0008] The analog front end is used to drive the first modulator array according to the first signal sequence, drive the second modulator array according to the second signal sequence, transmit the signal of the photodetector array to the host computer, and set the working voltage bias point for the modulators in the first modulator array and the second modulator array and the photodetector in the photodetector array.

[0009] The tunable multi-wavelength light source is used to emit multiple operating wavelengths that are equal to the resonant wavelength of the loop modulator in the second modulator array, and outputs them to the first modulator array.

[0010] Each optical amplitude modulator in the first modulator array is used to modulate the input wavelength;

[0011] A wavelength multiplexer is used to spatially combine signals of multiple wavelengths output from the first modulator array into a single channel;

[0012] The signal beam splitter is used to distribute the multi-wavelength signal output from the wavelength multiplexer evenly to each ring modulator in the second modulator array.

[0013] Each ring modulator in the second modulator array is used to modulate the signal output from the wavelength multiplexer and the second signal sequence transmitted through the analog front end.

[0014] The wavelength demultiplexer array is used to separate the signals of multiple wavelengths processed by each ring modulator in the second modulator array according to wavelength, and then input them into the photodetector array.

[0015] The photodetector array is used to introduce reference light from a tunable multi-wavelength source, detect the signal input to the wavelength demultiplexer array, and transmit it back to the analog front end.

[0016] The support equipment is used to keep the host computer, analog front end, adjustable multi-wavelength light source, first modulator array, wavelength multiplexer, signal beam splitter, second modulator array, wavelength demultiplexer array, and photodetector array stable.

[0017] As a preferred solution, the host computer includes a data storage module, a data scheduling and control module, and a data processing module.

[0018] The data storage module is used to store data;

[0019] The data scheduling and control module is used to retrieve the corresponding data from the data storage module according to the operation task to be executed, and arrange it into a first signal sequence and a second signal sequence. The module sets the symbol arrangement order and symbol period of the first signal sequence and the second signal sequence according to the operation type. The module processes the first signal sequence and the second signal sequence according to the photodetector type of the photodetector array, the modulator type of the first modulator array and the second modulator array, and the data type.

[0020] The data processing module is used to convert the second signal sequence and to sample and process the signal detected by the photodetector array transmitted back from the analog front end to obtain the final calculation result and store it back to the data storage module.

[0021] As a preferred embodiment, the analog front-end includes a digital-to-analog converter, an analog-to-digital converter, an RF amplifier, and a transimpedance amplifier.

[0022] A digital-to-analog converter is used to convert the digital signals of the first and second signal sequences transmitted from the host computer into analog driving voltage signals with a specified symbol period.

[0023] An analog-to-digital converter is used to convert analog signals detected by an array of photodetectors into digital signals at specified symbol periods;

[0024] The radio frequency amplifier is used to amplify the analog drive voltage signal converted by the digital-to-analog converter to a level sufficient to modulate the modulators in the first modulator array and the second modulator array;

[0025] Transimpedance amplifiers are used to convert the photocurrent detected by a photodetector array into voltage and amplify it.

[0026] As a preferred embodiment, the support device includes multiple temperature sensors, vibration sensors, a temperature controller, and a displacement actuator. The multiple temperature sensors are used to detect the temperature of the host computer, analog front end, adjustable multi-wavelength light source, first modulator array, wavelength multiplexer, signal beam splitter, second modulator array, wavelength demultiplexer array, and photodetector array, respectively. The multiple vibration sensors are used to detect the mechanical vibration of the host computer, analog front end, adjustable multi-wavelength light source, first modulator array, wavelength multiplexer, signal beam splitter, second modulator array, wavelength demultiplexer array, and photodetector array, respectively. The temperature controller is used to perform temperature compensation based on the detection values ​​of the temperature sensors, and the displacement actuator is used to perform vibration compensation based on the detection values ​​of the vibration sensors.

[0027] This invention also provides a computation method for a photonic computing chip architecture, which, based on the aforementioned photonic computing chip architecture, is characterized by comprising the following steps:

[0028] S1: Start the support equipment to maintain the temperature of each component;

[0029] S2: By simulating the front end, set the operating voltage bias points of the modulators in the first modulator array, the second modulator array, and the photodetectors in the photodetector array;

[0030] S3: Configure an adjustable multi-wavelength light source so that the number of working wavelengths emitted by the adjustable multi-wavelength light source is equal to the number of ring modulators in the second modulator array, the working wavelengths correspond one-to-one with the ring modulators, and the working wavelengths are equal to the resonant wavelengths of their corresponding ring modulators.

[0031] S4: The host computer reads the stored data according to the computing task and arranges it into a first signal sequence and a second signal sequence, specifying the relative delay between the first signal sequence and the second signal sequence;

[0032] S5: The host computer sets the symbol arrangement order and symbol period of the first and second signal sequences according to the operation type;

[0033] S6: The host computer processes the first signal sequence and the second signal sequence according to the photodetector type of the photodetector array, the modulator type of the first modulator array, the second modulator array, and the data type.

[0034] S7: The host computer converts the second signal sequence;

[0035] S8: The first signal sequence processed in step S5 and the second signal sequence converted in step S6 are passed through the analog front end to drive the first modulator array and the second modulator array respectively.

[0036] S9: The tunable multi-wavelength light source emits the working wavelength and passes through the first modulator sequence, wavelength multiplexer, signal beam splitter, second modulator array, and wavelength demultiplexer array in sequence to perform multi-path parallel computing;

[0037] S10: The photodetector array receives multiple signals from the wavelength demultiplexer array and converts them into photocurrent signals;

[0038] S11: The multi-channel photocurrent signals detected in step S9 are amplified by the analog front end and then transmitted back to the host computer;

[0039] S12: The host computer samples and processes the returned signal to obtain the calculation result;

[0040] S13: After the operation is completed, the host computer controls the host computer, analog front end, adjustable multi-wavelength light source, first modulator array, wavelength multiplexer, signal beam splitter, second modulator array, wavelength demultiplexer array, photodetector array and support equipment to reset.

[0041] As a preferred embodiment, in step S2, if the operation is a real number, the number of digital-to-analog converters and RF amplifiers in the analog front end is the same as the total number of modulators in the first modulator array and the second modulator array, with each group of digital-to-analog converters and RF amplifiers corresponding to one modulator; if the operation is a complex number, the number of digital-to-analog converters and RF amplifiers is twice the total number of modulators in the first modulator array and the second modulator array, with each pair of digital-to-analog converters and RF amplifiers corresponding to one modulator.

[0042] If the photodetector array is for intensity detection, the number of analog-to-digital converters and transimpedance amplifiers is the same as the number of photodetectors, and each group of analog-to-digital converters and transimpedance amplifiers corresponds to one photodetector; if the photodetector sequence is for coherent detection, the number of analog-to-digital converters and transimpedance amplifiers is twice the number of photodetectors, and each group of analog-to-digital converters and transimpedance amplifiers corresponds to the output component of one photodetector, and the output component of the photodetector is either real or imaginary.

[0043] The modulation voltage amplified by the radio frequency amplifier enables the modulator to operate within the linear region of optical amplitude.

[0044] Using a bias controller, the operating voltage bias point of the modulator in the first modulator array should be set at the zero point of the linear region of the positive slope of the optical amplitude; the operating voltage bias point of the modulator in the second modulator array should be set at the overcoupling point; and the operating voltage bias point of the optical modulator should be set at a suitable reverse bias state.

[0045] As a preferred option, in step S5, if vector dot product is to be performed, the first signal sequence and the second signal sequence are two vectors, and the symbol period of both is set to the loop delay of the loop modulator, so that the symbols of the two vectors are aligned one by one in the time domain.

[0046] To perform an M×N matrix-vector multiplication operation, the matrix is ​​arranged column-wise and end-to-end to form an MN-dimensional vector as the first signal sequence, with the symbol period set to the loop delay of the loop modulator 1 / M. The vector is then set as the second signal sequence, with the symbol period set to the loop delay of the loop modulator. In the time domain, each vector symbol is aligned with the M symbols in the corresponding column of the matrix.

[0047] If you want to perform convolution operations using a single convolution kernel, you can convert the convolution operation into a matrix-vector multiplication operation by performing the required vector dot product. The convolved data is converted into a matrix, which is the first signal sequence, and the convolution kernel is converted into a vector, which is the second signal sequence.

[0048] To perform convolution operations using K convolution kernels, the convolution operation can be converted into K matrix-vector multiplication operations by the required vector dot product. The convolutioned data is converted into a matrix, which is the first signal sequence. The symbol period is set to the loop delay of the loop modulator, which is 1 / M. The K convolution kernels are converted into K vectors, which can be further interleaved into the same second signal sequence. The symbol period is set to the loop delay of the loop modulator, which is 1 / MK. In the time domain, each symbol in the first signal sequence is aligned with the corresponding K symbols in the second signal sequence.

[0049] As a preferred option, in step S6, if the photodetector array only supports intensity detection and the calculation only involves non-negative real numbers, then the first signal sequence and the second signal sequence do not need further processing.

[0050] If the photodetector array only supports intensity detection and the calculation involves positive and negative real numbers, then the first signal sequence and the second signal sequence need to be decomposed into positive and negative components, and the negative component is taken as the opposite number, forming a total of 4 parts: "positive-positive, positive-negative, negative-positive, negative-negative". The calculations are performed separately, and the results are further processed and merged in the data processing section.

[0051] If the photodetector array only supports intensity detection and the operation involves complex numbers, the signal sequence needs to be decomposed into four components: real part positive, real part negative, imaginary part positive, and imaginary part negative. The negative component is then inversely represented, forming a total of 16 parts for operation. The results are then further processed and merged in the data processing section.

[0052] If the photodetector array supports coherent detection, the computation involves positive and negative real numbers and complex numbers, so the signal sequence requires no further processing. For positive and negative real numbers, simply ignore the imaginary part of the complex number result.

[0053] As a preferred embodiment, in step S7, the conversion of the second signal sequence should follow the following rules: assuming the second signal sequence is [ω1,…,ω...] N ],

[0054] The transformed second signal sequence is [ω′1,…,ω′ N Then, for the nth element (n = 1, 2, ..., N) in the sequence, the following transformation relationship holds:

[0055]

[0056]

[0057]

[0058] In the formula, k represents the index of the element related to the calculation of the nth element, and its value ranges from n+1 to N, β g It is the propagation constant of the signal on the optical chip, Δln It is the change in the length of the modulator arm in the second modulator array, c n and s n They represent β respectively g Δl n The values ​​of the cosine and sine functions.

[0059] As a preferred embodiment, in step S13, during the reset phase, both the first signal sequence and the second signal sequence need to be set to zero, maintaining at least one loop delay time.

[0060] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0061] This invention divides data into a first signal sequence and a second signal sequence via a host computer, and sets up a first modulator array and a second modulator array. Each of the first and second modulator arrays includes multiple modulators, and multiple operating wavelengths are emitted through an adjustable multi-wavelength light source, enabling the multiplexing of the first and second signal sequences. This greatly expands the parallelism of computation, thereby increasing throughput and reducing the energy consumption of each multiply-accumulate operation. Moreover, by adding phase modulation functionality to the first and second modulator arrays and introducing coherent detection in the photodetector array, this invention can further reduce the latency and energy consumption of real or complex number data operations, reduce the number of devices that need to be integrated on the photonic chip, lower the cost, and reduce the manufacturing difficulty. Attached Figure Description

[0062] Figure 1 This is a schematic diagram of the photonic computing chip architecture according to an embodiment of the present invention.

[0063] Figure 2 This is a flowchart of the photonic computing chip architecture operation method according to an embodiment of the present invention.

[0064] In the diagram, 1-host computer; 2-analog front end; 3-tunable multi-wavelength light source; 4-first modulator array; 5-wavelength multiplexer; 6-signal beam splitter; 7-second modulator array; 8-long demultiplexer array; 9-photodetector array; 10-support equipment. Detailed Implementation

[0065] The specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples. The following examples are for illustrative purposes only and are not intended to limit the scope of the invention.

[0066] In the description of this invention, it should be noted that the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0067] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0068] Furthermore, in the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0069] Example 1

[0070] like Figure 1 As shown, a preferred embodiment of the photonic computing chip architecture of the present invention includes a host computer 1, an analog front-end 2, an adjustable multi-wavelength light source 3, a first modulator array 4, a wavelength multiplexer 5, a signal beam splitter 6, a second modulator array 7, a wavelength demultiplexer array 8, a photodetector array 9, and a support device 10. The first modulator array 4 includes multiple optical amplitude modulators, and the second modulator array 7 includes multiple ring modulators.

[0071] The host computer 1 is connected to the analog front end 2. The analog front end 2 is connected to the first modulator array 4 and the second modulator array 7 respectively. The adjustable multi-wavelength light source 3, the first modulator array 4, the wavelength multiplexer 5, the signal beam splitter 6, the second modulator array 7, the wavelength demultiplexer array 8, and the photodetector array 9 are connected in sequence.

[0072] The host computer 1 is used for data storage. According to the operation task, it reads the stored data and arranges it into a first signal sequence and a second signal sequence. It sets the symbol arrangement order and symbol period of the first signal sequence and the second signal sequence according to the operation type. According to the photodetector type of the photodetector array 9 and the modulator type and data type of the first modulator array 4 and the second modulator array 7, it processes the first signal sequence and the second signal sequence.

[0073] The analog front end 2 is used to drive the first modulator array 4 according to the first signal sequence, drive the second modulator array 7 according to the second signal sequence, transmit the signal of the photodetector array 9 to the host computer 1, and set the working voltage bias point for the modulators in the first modulator array 4 and the second modulator array 7 and the photodetector in the photodetector array 9.

[0074] The tunable multi-wavelength light source 3 is used to emit multiple working wavelengths that are equal to the resonant wavelength of the loop modulator in the second modulator array 7, and output them to the first modulator array 4.

[0075] Each optical amplitude modulator in the first modulator array 4 is used to modulate the input wavelength.

[0076] Wavelength multiplexer 5 is used to spatially combine multiple wavelength signals output by the first modulator array 4 into one channel;

[0077] The signal beam splitter 6 is used to distribute the multi-wavelength signal output from the wavelength multiplexer 5 evenly to each ring modulator in the second modulator array 7.

[0078] Each ring modulator in the second modulator array 7 is used to modulate the signal output by the wavelength multiplexer 5 and the second signal sequence transmitted through the analog front end 2.

[0079] Wavelength demultiplexer array 8 is used to separate the signals of multiple wavelengths processed by each ring modulator in the second modulator array 7 according to wavelength, and then input them into photodetector array 9.

[0080] The photodetector array 9 is used to introduce reference light from the tunable multi-wavelength light source 3, detect the signal input to the wavelength demultiplexer array 8 and transmit it back to the analog front end 2;

[0081] Support device 10 is used to keep the host computer 1, analog front end 2, adjustable multi-wavelength light source 3, first modulator array 4, wavelength multiplexer 5, signal beam splitter 6, second modulator array 7, wavelength demultiplexer array 8, and photodetector array 9 stable.

[0082] In this embodiment, the host computer 1 divides the data into a first signal sequence and a second signal sequence, and sets up a first modulator array 4 and a second modulator array 7. Each of the first modulator array 4 and the second modulator array 7 includes multiple modulators, and emits multiple working wavelengths through an adjustable multi-wavelength light source 3 to realize the multiplexing of the first signal sequence and the second signal sequence, greatly expanding the parallelism of the calculation and thus increasing the throughput, while reducing the energy consumption of each multiply-accumulate operation.

[0083] Example 2

[0084] The difference between this embodiment and Embodiment 1 is that, based on Embodiment 1, this embodiment provides a further explanation of the host computer 1.

[0085] In this embodiment, the host computer 1 includes a data storage module, a data scheduling and control module, and a data processing module. The data storage module is used to store data.

[0086] The data scheduling and control module is used to retrieve the corresponding data from the data storage module according to the operation task to be executed, and arrange it into a first signal sequence and a second signal sequence. The module sets the symbol arrangement order and symbol period of the first signal sequence and the second signal sequence according to the operation type. The module processes the first signal sequence and the second signal sequence according to the photodetector type of the photodetector array 9 and the modulator type and data type of the first modulator array 4 and the second modulator array 7.

[0087] The data processing module is used to convert the second signal sequence and to sample and process the signal detected by the photodetector array 9 transmitted back from the analog front end 2 to obtain the final calculation result and store it back to the data storage module.

[0088] The data storage module is used to temporarily store data that needs to be used for calculation or results that have already been calculated and processed.

[0089] The data scheduling and control module can retrieve corresponding data from the data storage module according to the computational task to be executed, arrange it into first and second signal sequences, and specify the symbol period and relative delay of the two signal sequences. Furthermore, it decomposes the first signal sequence into N1 sub-sequences based on the number of wavelengths N1, and distributes them to multiple modulators in the first modulator array 4. Similarly, it decomposes the second signal sequence into N2 sub-sequences based on the number of ring modulators N2, and distributes them to multiple modulators in the second modulator array 7. Simultaneously, this module is also responsible for resetting the entire photonic computing chip architecture system.

[0090] In this process, if vector dot product is to be performed, the first signal sequence and the second signal sequence are two vectors, and the symbol period of both is set to the loop delay of the loop modulator. In the time domain, the symbols of the two vectors are aligned one by one.

[0091] To perform an M×N matrix-vector multiplication operation, the matrix is ​​arranged column-wise and end-to-end to form an MN-dimensional vector as the first signal sequence, with the symbol period set to the loop delay of the loop modulator 1 / M. The vector is then set as the second signal sequence, with the symbol period set to the loop delay of the loop modulator. In the time domain, each vector symbol is aligned with the M symbols in the corresponding column of the matrix.

[0092] If you want to perform convolution operations using a single convolution kernel, you can convert the convolution operation into a matrix-vector multiplication operation by performing the required vector dot product. The convolved data is converted into a matrix, which is the first signal sequence, and the convolution kernel is converted into a vector, which is the second signal sequence.

[0093] To perform convolution operations using K convolution kernels, the convolution operation can be converted into K matrix-vector multiplication operations by the required vector dot product. The convolutioned data is converted into a matrix, which is the first signal sequence. The symbol period is set to the loop delay of the loop modulator, which is 1 / M. The K convolution kernels are converted into K vectors, which can be further interleaved into the same second signal sequence. The symbol period is set to the loop delay of the loop modulator, which is 1 / MK. In the time domain, each symbol in the first signal sequence is aligned with the corresponding K symbols in the second signal sequence.

[0094] Furthermore, the data scheduling and control module can select to further process the first signal sequence and the second signal sequence based on the configuration of the photonic hardware and the data type of the operation.

[0095] If the optical detector array only supports intensity detection and the calculations only involve non-negative real numbers, then the signal sequence does not require further processing.

[0096] If the optical detection array only supports intensity detection and the calculation involves positive and negative real numbers, the signal sequence needs to be decomposed into positive and negative components, and the negative component is taken as the opposite number, forming a total of 4 parts: "positive-positive, positive-negative, negative-positive, negative-negative". The calculations are performed separately, and the results are further processed and merged in the data processing section.

[0097] If the optical detector array only supports intensity detection and the operation involves complex numbers, then the signal sequence needs to be decomposed into four components: real part positive, real part negative, imaginary part positive, and imaginary part negative. The negative component is then inversely represented, forming a total of 16 parts for operation. The results are then further processed and merged in the data processing section.

[0098] If the photodetector array supports coherent detection, the computation involves positive and negative real numbers and complex numbers, so the signal sequence does not require further processing. For positive and negative real numbers, simply ignore the imaginary part of the complex number result.

[0099] In addition, during the reset phase, the data scheduling control module sets both the first and second signal sequences to zero and maintains this for at least one loop delay.

[0100] The data processing module is used to convert the second signal sequence, and can sample and process the returned detected signal to obtain the final calculation result, and store it back to the data storage module.

[0101] The transformation of the second signal sequence should follow these rules: Assume the second signal sequence is [ω1,…,ω...]. NThe transformed second signal sequence is [ω11,…,ω′]. N Then, for the nth element (n = 1, 2, ..., N) in the sequence, the following transformation relationship holds:

[0102]

[0103]

[0104]

[0105] In the formula, k represents the index of the element related to the calculation of the nth element, and its value ranges from n+1 to N, β g It is the propagation constant of the signal on the optical chip, Δl n It is the change in the length of the modulator arm in the second modulator array, c n and s n They represent β respectively g Δl n The values ​​of the cosine and sine functions.

[0106] In addition, the data processing module samples the returned signals. Specifically, for each calculation, only the output signal of the last loop iteration needs to be sampled.

[0107] Furthermore, the data processing module processes the returned signal, and if it contains positive components, negative components, real components, imaginary components, etc., it re-merges these components into positive and negative real numbers or complex numbers. The results of convolution operations performed on K convolution kernels need to be de-interleaved and rearranged into K convolution results. Finally, the operation results are transmitted back to the data storage unit.

[0108] The other structures in this embodiment are the same as in Embodiment 1, and will not be described again here.

[0109] Example 3

[0110] The difference between this embodiment and embodiment two is that, based on embodiment two, this embodiment provides a further explanation of the simulated front end 2.

[0111] In this embodiment, the analog front-end 2 includes a digital-to-analog converter (DAC), an analog-to-digital converter (ADC), a radio frequency amplifier (RF amplifier), and a transimpedance amplifier. The DAC is used to convert the digital signals of the first and second signal sequences transmitted by the host computer 1 into analog driving voltage signals at a specified symbol period. The ADC is used to convert the analog signals detected by the photodetector array 9 into digital signals at a specified symbol period. The RF amplifier is used to amplify the analog driving voltage signals converted by the DAC to amplify them sufficiently to modulate the modulators in the first modulator array 4 and the second modulator array 7. The transimpedance amplifier is used to convert the photocurrent detected by the photodetector array 9 into voltage and amplify it.

[0112] In real number operations, the number of digital-to-analog converters and radio frequency amplifiers is the same as the total number of modulators in the first and second modulator arrays 7, with each group of digital-to-analog converters and radio frequency amplifiers corresponding to one modulator; in complex number operations, the number of digital-to-analog converters and radio frequency amplifiers is twice the total number of modulators in the first and second modulator arrays 7, with each group of digital-to-analog converters and radio frequency amplifiers corresponding to one amplitude modulator or phase modulator.

[0113] If the optical detection sequence is intensity detection, the number of analog-to-digital converters and transimpedance amplifiers is the same as the number of photodetectors, and each group of analog-to-digital converters and transimpedance amplifiers corresponds to one photodetector; if the optical detection sequence is coherent detection, the number of analog-to-digital converters and transimpedance amplifiers is twice the number of photodetectors, and each group of analog-to-digital converters and transimpedance amplifiers corresponds to the output component (real part or imaginary part) of one photodetector.

[0114] The modulation voltage amplified by the RF amplifier should enable the modulator to operate within the linear region of optical amplitude.

[0115] The analog front end 2 also includes a bias controller, which sets the operating voltage bias point of the modulator in the first modulator array 4 to the zero point of the linear region of the positive slope of the optical amplitude; sets the operating voltage bias point of the modulator in the second modulator array 7 to the over-coupling point; and sets the operating voltage bias point of the optical modulator to a suitable reverse bias state.

[0116] The other structures in this embodiment are the same as in Embodiment 2, and will not be described again here.

[0117] Example 4

[0118] The difference between this embodiment and embodiment three is that, based on embodiment three, this embodiment further describes the tunable multi-wavelength light source 3, the first modulator array 4, the wavelength multiplexer 5, the signal beam splitter 6, the second modulator array 7, the wavelength demultiplexer array 8, the photodetector array 9, and the support device 10.

[0119] The tunable multi-wavelength light source 3 can emit multiple operating wavelengths (assuming N² wavelengths), each of which needs to be precisely tuned to the same wavelength as the resonant wavelength of the loop modulator in the second modulator array 7. The tunable multi-wavelength light source 3 can be various types of tunable optical frequency comb light sources, or it can be a discrete array of multiple tunable lasers.

[0120] The first modulator array 4 contains N1 identical optical amplitude modulators, which in this embodiment are Mach-Zehnder modulators. Each modulator's optical input is one of the multiplexed wavelengths, and its electrical input is one of the subsequences of the first signal sequence. The operating voltage bias point of these modulators is the zero point of the linear region of the positive slope of the optical amplitude. These modulators have the same modulation effect on the input wavelength. When performing complex number operations, each modulator in the first modulator array 4, in addition to controlling the optical amplitude (only phases 0 and π), also needs to perform free phase modulation. In the Mach-Zehnder structure, phase modulation can be achieved by changing the push-pull optical amplitude modulation to a dual-arm independently controlled modulation, or by adding an additional phase modulator at the output.

[0121] Wavelength multiplexer 5 spatially combines multiple wavelength signals output from the first modulator array 4 into a single channel.

[0122] Signal beam splitter 6 divides the multi-wavelength signal output from wavelength multiplexer 5 into N² parts. Each part contains every subsequence (every wavelength) of the first signal sequence. These subsequences are then fed into each ring modulator in the second modulator array 7.

[0123] The second modulator array 7 contains N2 identical ring modulators. In this embodiment, the ring modulator consists of two parts: an adjustable 2×2 Mach-Zehnder interferometer and a delay loop connecting one input and one output port of the Mach-Zehnder interferometer. The presence of these ring modulators allows them to have multiple resonant wavelengths, and these resonant wavelengths have the same transmittance and response to electrical modulation. The optical input of each modulator is a multi-wavelength optical signal containing information of the first signal sequence, and the electrical input is one subsequence of the second signal sequence. The operating voltage bias point is the overcoupling point. When performing complex number operations, each modulator in the first modulator array 4, in addition to controlling the optical amplitude (only phases 0 and π), also needs to perform free phase modulation. Phase modulation in the Mach-Zehnder structure can be achieved by changing the push-pull optical amplitude modulation to a modulation controlled independently by both arms, or by adding a phase modulator to the ring waveguide.

[0124] The wavelength demultiplexer array 8 contains N2 wavelength demultiplexers, each connected to the output of each loop modulator. Each wavelength demultiplexer can separate signals of multiple wavelengths processed simultaneously by the loop modulator according to wavelength, and then input them to the photodetector array 9.

[0125] If intensity detection is used in the photodetector array 9, there are a total of N1×N2 photodetectors in the photodetector array 9. Each photodetector corresponds to a demultiplexed wavelength and converts the detected light intensity into a photocurrent signal. If coherent detection is used, there are a total of N1×N2×4 photodetectors in the photodetector array 9. Every 4 photodetectors form a group and correspond to a demultiplexed wavelength. Reference light needs to be introduced from the tunable multi-wavelength light source 3. It can detect the light intensity of the four components of the complex number: the real part positive, the real part negative, the imaginary part positive, and the imaginary part negative, and convert them into a photocurrent signal.

[0126] By adding phase modulation functionality to the first modulator array 4 and the second modulator array 7, and introducing coherent detection in the photodetector array 9, the data processing delay and energy consumption of real or complex numbers can be reduced, the number of devices that need to be integrated on the photonic chip can be reduced, the cost can be lowered, and the processing difficulty can be reduced.

[0127] The support device 10 includes multiple temperature sensors, vibration sensors, a temperature controller, and a displacement actuator. The temperature sensors are used to detect the temperatures of the host computer 1, analog front-end 2, adjustable multi-wavelength light source 3, first modulator array 4, wavelength multiplexer 5, signal beam splitter 6, second modulator array 7, wavelength demultiplexer array 8, and photodetector array 9, respectively. The vibration sensors are used to detect the mechanical vibrations of the host computer 1, analog front-end 2, adjustable multi-wavelength light source 3, first modulator array 4, wavelength multiplexer 5, signal beam splitter 6, second modulator array 7, wavelength demultiplexer array 8, and photodetector array 9, respectively. The temperature controller performs temperature compensation based on the temperature sensor readings, and the displacement actuator performs vibration compensation based on the vibration sensor readings. The support device 10 is primarily an auxiliary device for maintaining the stability of the temperature and mechanical vibration of various modules and components, including but not limited to temperature and vibration sensors and corresponding temperature controllers and displacement actuators for compensation.

[0128] The other structures in this embodiment are the same as in Embodiment 3, and will not be described again here.

[0129] Example 5

[0130] like Figure 2 As shown, this embodiment of the invention provides a computational method for a photonic computing chip architecture. Based on the photonic computing chip architecture of the above embodiment, the method includes the following steps:

[0131] S1: Start support device 10 and maintain the temperature of each device; each device refers to the individual devices in the photonic computing chip architecture.

[0132] S2: By simulating the front end 2, set the operating voltage bias points of the modulators in the first modulator array 4, the second modulator array 7, and the photodetectors in the photodetector array 9.

[0133] S3: Configure the adjustable multi-wavelength light source 3 so that the number of working wavelengths emitted by the adjustable multi-wavelength light source 3 is equal to the number of ring modulators in the second modulator array 7, the working wavelengths correspond one-to-one with the ring modulators, and the working wavelengths are equal to the resonant wavelengths of their corresponding ring modulators.

[0134] S4: The host computer 1 reads the stored data according to the computing task and arranges it into a first signal sequence and a second signal sequence, and specifies the relative delay between the first signal sequence and the second signal sequence;

[0135] S5: The host computer 1 sets the symbol arrangement order and symbol period of the first signal sequence and the second signal sequence according to the operation type;

[0136] S6: The host computer 1 processes the first signal sequence and the second signal sequence according to the photodetector type of the photodetector array 9, the modulator type of the first modulator array 4, the modulator array 7, and the data type.

[0137] S7: The host computer 1 converts the second signal sequence;

[0138] S8: The first signal sequence processed in step S5 and the second signal sequence converted in step S6 are passed through the analog front end 2 to drive the first modulator array 4 and the second modulator array 7 respectively.

[0139] S9: The adjustable multi-wavelength light source 3 emits the working wavelength, which passes through the first modulator sequence, wavelength multiplexer 5, signal beam splitter 6, second modulator array 7, and wavelength demultiplexer array 8 in sequence to perform multi-channel parallel computing;

[0140] S10: The photodetector array 9 receives the multiple signals emitted by the wavelength demultiplexer array 8 and converts them into photocurrent signals;

[0141] S11: The multi-channel photocurrent signals detected in step S9 are amplified by the analog front-end 2 and then transmitted back to the host computer 1;

[0142] S12: The host computer 1 samples and processes the returned signal to obtain the calculation result;

[0143] S13: After the operation is completed, the host computer 1 controls the host computer 1, analog front end 2, adjustable multi-wavelength light source 3, first modulator array 4, wavelength multiplexer 5, signal beam splitter 6, second modulator array 7, wavelength demultiplexer array 8, photodetector array 9 and support equipment 10 to reset.

[0144] In step S2, if the operation is a real number operation, the number of digital-to-analog converters and radio frequency amplifiers in the analog front-end 2 is the total number of modulators in the first modulator array 4 and the second modulator array 7, with each group of digital-to-analog converters and radio frequency amplifiers corresponding to one modulator; if the operation is a complex number operation, the number of digital-to-analog converters and radio frequency amplifiers is twice the total number of modulators in the first modulator array 4 and the second modulator array 7, with each pair of digital-to-analog converters and radio frequency amplifiers corresponding to one modulator.

[0145] If the photodetector array 9 is for light intensity detection, the number of analog-to-digital converters and transimpedance amplifiers is the same as the number of photodetectors, and each group of analog-to-digital converters and transimpedance amplifiers corresponds to one photodetector; if the photodetector sequence is for coherent detection, the number of analog-to-digital converters and transimpedance amplifiers is twice the number of photodetectors, and each group of analog-to-digital converters and transimpedance amplifiers corresponds to the output component of one photodetector, and the output component of the photodetector is either real or imaginary.

[0146] The modulation voltage amplified by the radio frequency amplifier enables the modulator to operate within the linear region of optical amplitude.

[0147] Using a bias controller, the operating voltage bias point of the modulator in the first modulator array 4 should be set at the zero point of the linear region of the positive slope of the optical amplitude; the operating voltage bias point of the modulator in the second modulator array 7 should be set at the over-coupling point; and the operating voltage bias point of the optical modulator should be set at a suitable reverse bias state.

[0148] In step S5, if vector dot product is to be performed, the first signal sequence and the second signal sequence are two vectors, and the symbol period of both is set to the loop delay of the loop modulator. In the time domain, the symbols of the two vectors are aligned one by one.

[0149] To perform an M×N matrix-vector multiplication operation, the matrix is ​​arranged column-wise and end-to-end to form an MN-dimensional vector as the first signal sequence, with the symbol period set to the loop delay of the loop modulator 1 / M. The vector is then set as the second signal sequence, with the symbol period set to the loop delay of the loop modulator. In the time domain, each vector symbol is aligned with the M symbols in the corresponding column of the matrix.

[0150] If you want to perform convolution operations using a single convolution kernel, you can convert the convolution operation into a matrix-vector multiplication operation by performing the required vector dot product. The convolved data is converted into a matrix, which is the first signal sequence, and the convolution kernel is converted into a vector, which is the second signal sequence.

[0151] To perform convolution operations using K convolution kernels, the convolution operation can be converted into K matrix-vector multiplication operations by the required vector dot product. The convolutioned data is converted into a matrix, which is the first signal sequence. The symbol period is set to the loop delay of the loop modulator, which is 1 / M. The K convolution kernels are converted into K vectors, which can be further interleaved into the same second signal sequence. The symbol period is set to the loop delay of the loop modulator, which is 1 / MK. In the time domain, each symbol in the first signal sequence is aligned with the corresponding K symbols in the second signal sequence.

[0152] In step S6, if the photodetector array 9 only supports intensity detection and the calculation only involves non-negative real numbers, then the first signal sequence and the second signal sequence do not need further processing.

[0153] If the photodetector array 9 only supports intensity detection and the calculation involves positive and negative real numbers, then the first signal sequence and the second signal sequence need to be decomposed into positive and negative components, and the negative component is taken as the opposite number, forming a total of 4 parts: "positive-positive, positive-negative, negative-positive, negative-negative". The calculations are performed separately, and the results are further processed and merged in the data processing section.

[0154] If the photodetector array 9 only supports intensity detection and the operation involves complex numbers, then the signal sequence needs to be decomposed into four components: real part positive, real part negative, imaginary part positive, and imaginary part negative. The negative component is then inversely represented, forming a total of 16 parts for operation. The results are then further processed and merged in the data processing section.

[0155] If the photodetector array 9 supports coherent detection, the computation involves positive and negative real numbers and complex numbers, so the signal sequence does not require further processing. For positive and negative real numbers, simply ignore the imaginary part of the complex number result.

[0156] In step S7, the second signal sequence is transformed, following these rules: Assume the second signal sequence is [ω1,…,ω...]. N ],

[0157] The transformed second signal sequence is [ω′1,…,ω'] N ], then we have:

[0158]

[0159]

[0160]

[0161] In the formula, β g Δl n It is a phase change in the modulator caused by modulation.

[0162] Analog front-end 2 converts the digital signal sequence into an analog driving voltage signal at a specified symbol period using its digital-to-analog converter (DAC). It then converts the analog signal detected by the photodetector into a digital signal at the same specified symbol period using an analog-to-digital converter (ADC). Finally, it amplifies the driving voltage using an RF amplifier to a level sufficient to modulate the modulator. Finally, it converts the photocurrent detected by the photodetector into a voltage and amplifies it using a transimpedance amplifier. In step S8, the modulation voltage amplified by the RF amplifier in analog front-end 2 should ensure that the modulator operates within the linear amplitude region of the optical signal.

[0163] In step S12, the host computer 1 samples the returned signal. Specifically, for each calculation, only the output signal of the last loop iteration needs to be sampled. The processing of the returned signal involves combining positive, negative, real, and imaginary components, etc., into positive and negative real or complex numbers. The results of the convolution operation on K convolution kernels are de-interleaved and rearranged into K convolution results. Finally, the calculation results are stored.

[0164] In step S13, during the reset phase, both the first signal sequence and the second signal sequence need to be set to zero, maintaining at least one loop delay time.

[0165] In summary, this invention provides a photonic computing chip architecture, including a host computer 1, an analog front-end 2, a tunable multi-wavelength light source 3, a first modulator array 4, a wavelength multiplexer 5, a signal beam splitter 6, a second modulator array 7, a wavelength demultiplexer array 8, a photodetector array 9, and a support device 10. The host computer 1 divides data into a first signal sequence and a second signal sequence, and sets up the first modulator array 4 and the second modulator array 7. Each of the first modulator array 4 and the second modulator array 7 includes multiple modulators, and multiple operating wavelengths are emitted through the tunable multi-wavelength light source 3 to achieve multiplexing of the first and second signal sequences, greatly expanding the parallelism of computation and thus increasing throughput, while reducing the energy consumption of each multiply-accumulate operation. Furthermore, by adding phase modulation functionality to the first modulator array 4 and the second modulator array 7, and introducing coherent detection in the photodetector array 9, this invention can reduce the latency and energy consumption of real or complex number data operations, reduce the number of devices that need to be integrated on the photonic chip, lower the cost, and reduce the manufacturing difficulty. This invention also provides a computation method for the above-described photonic computing chip architecture.

[0166] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and substitutions can be made without departing from the technical principles of the present invention, and these improvements and substitutions should also be considered within the scope of protection of the present invention.

Claims

1. A photonic computing chip architecture, characterized in that, It includes a host computer (1), an analog front end (2), an adjustable multi-wavelength light source (3), a first modulator array (4), a wavelength multiplexer (5), a signal beam splitter (6), a second modulator array (7), a wavelength demultiplexer array (8), a photodetector array (9), and a support device (10). The first modulator array (4) includes multiple optical amplitude modulators, and the second modulator array (7) includes multiple ring modulators. The host computer (1) is connected to the analog front end (2), and the analog front end (2) is connected to the first modulator array (4) and the second modulator array (7) respectively. The adjustable multi-wavelength light source (3), the first modulator array (4), the wavelength multiplexer (5), the signal beam splitter (6), the second modulator array (7), the wavelength demultiplexer array (8), and the photodetector array (9) are connected in sequence. The host computer (1) is used for data storage. According to the operation task, it reads the stored data and arranges it into a first signal sequence and a second signal sequence. It sets the symbol arrangement order and symbol period of the first signal sequence and the second signal sequence according to the operation type. According to the photodetector type of the photodetector array (9), the modulator type of the first modulator array (4), the second modulator array (7), and the data type, it processes the first signal sequence and the second signal sequence. If the photodetector array (9) only supports intensity detection and the operation only involves non-negative real numbers, then the first signal sequence and the second signal sequence do not need further processing. If the photodetector array (9) only supports intensity detection and the operation involves positive and negative real numbers, then the first signal sequence and the second signal sequence need to be decomposed into positive and negative components, and the negative component is taken as the opposite number, forming a total of 4 parts: "positive-positive, positive-negative, negative-positive, negative-negative". The results are then further processed and merged in the data processing section. If the photodetector array (9) only supports intensity detection and the operation involves complex numbers, the signal sequence needs to be decomposed into four components: real part positive, real part negative, imaginary part positive, and imaginary part negative. The negative component is then reversed, forming a total of 16 parts for operation. The results are then further processed and merged in the data processing section. If the photodetector array (9) supports coherent detection, the operation involves positive and negative real numbers and complex numbers, then the signal sequence does not need further processing, and the positive and negative real numbers only need to ignore the imaginary part in the complex number result; The analog front end (2) is used to drive the first modulator array (4) according to the first signal sequence, drive the second modulator array (7) according to the second signal sequence, transmit the signal of the photodetector array (9) to the host computer (1), and set the working voltage bias point for the modulators in the first modulator array (4) and the second modulator array (7) and the photodetector in the photodetector array (9). By means of the bias controller, the working voltage bias point of the modulator in the first modulator array (4) should be set at the zero point of the linear region of the positive slope of the optical amplitude; The operating voltage bias point of the modulator in the second modulator array (7) should be set at the over-coupling point; the operating voltage bias point of the optical modulator should be set at a suitable reverse bias state. The tunable multi-wavelength light source (3) is used to emit multiple working wavelengths that are equal to the resonant wavelength of the loop modulator in the second modulator array (7) and output them to the first modulator array (4). Each optical amplitude modulator in the first modulator array (4) is used to modulate the input wavelength; The wavelength multiplexer (5) is used to spatially combine multiple wavelength signals output by the first modulator array (4) into one channel; The signal beam splitter (6) is used to distribute the multi-wavelength signal output by the wavelength multiplexer (5) evenly to each ring modulator in the second modulator array (7). Each ring modulator in the second modulator array (7) is used to modulate the signal output by the wavelength multiplexer (5) and the second signal sequence transmitted through the analog front end (2); The wavelength demultiplexer array (8) is used to separate the signals of multiple wavelengths processed by each ring modulator in the second modulator array (7) according to wavelength, and then input them into the photodetector array (9). The photodetector array (9) is used to introduce reference light from the tunable multi-wavelength light source (3), detect the signal input to the wavelength demultiplexer array (8), and transmit it back to the analog front end (2). Support equipment (10) is used to keep the host computer (1), analog front end (2), adjustable multi-wavelength light source (3), first modulator array (4), wavelength multiplexer (5), signal beam splitter (6), second modulator array (7), wavelength demultiplexer array (8), and photodetector array (9) stable.

2. The photonic computing chip architecture according to claim 1, characterized in that, The host computer (1) includes a data storage module, a data scheduling and control module, and a data processing module. The data storage module is used to store data; The data scheduling and control module is used to retrieve the corresponding data from the data storage module according to the operation task to be executed, and arrange it into a first signal sequence and a second signal sequence. The module sets the symbol arrangement order and symbol period of the first signal sequence and the second signal sequence according to the operation type. The module processes the first signal sequence and the second signal sequence according to the photodetector type of the photodetector array (9), the modulator type of the first modulator array (4), the second modulator array (7), and the data type. The data processing module is used to convert the second signal sequence and to sample and process the signal detected by the photodetector array (9) returned by the analog front end (2) to obtain the final calculation result and store it back to the data storage module.

3. The photonic computing chip architecture according to claim 1, characterized in that, The analog front-end (2) includes a digital-to-analog converter, an analog-to-digital converter, an RF amplifier, and a transimpedance amplifier. The digital-to-analog converter is used to convert the digital signals of the first signal sequence and the second signal sequence transmitted by the host computer (1) into analog signals of the driving voltage at a specified symbol period; An analog-to-digital converter is used to convert analog signals detected by the photodetector array (9) into digital signals with a specified symbol period; The radio frequency amplifier is used to amplify the analog drive voltage signal converted by the digital-to-analog converter to a level sufficient to modulate the modulators in the first modulator array (4) and the second modulator array (7); The transimpedance amplifier is used to convert the photocurrent detected by the photodetector array (9) into voltage and amplify it.

4. The photonic computing chip architecture according to claim 1, characterized in that, The supporting device (10) includes multiple temperature sensors, vibration sensors, temperature controllers, and displacement actuators. The multiple temperature sensors are used to detect the temperature of the host computer (1), analog front end (2), adjustable multi-wavelength light source (3), first modulator array (4), wavelength multiplexer (5), signal beam splitter (6), second modulator array (7), wavelength demultiplexer array (8), and photodetector array (9), respectively. The multiple vibration sensors are used to detect the mechanical vibration of the host computer (1), analog front end (2), adjustable multi-wavelength light source (3), first modulator array (4), wavelength multiplexer (5), signal beam splitter (6), second modulator array (7), wavelength demultiplexer array (8), and photodetector array (9), respectively. The temperature controller is used to perform temperature compensation based on the detection values ​​of the temperature sensors, and the displacement actuator is used to perform vibration compensation based on the detection values ​​of the vibration sensors.

5. A computational method for a photonic computing chip architecture, based on the photonic computing chip architecture according to any one of claims 1-4, characterized in that, Includes the following steps: S1: Start the support device (10) and maintain the temperature of each component; S2: By simulating the front end (2), set the operating voltage bias points of the modulators in the first modulator array (4), the second modulator array (7), and the photodetectors in the photodetector array (9); S3: Configure an adjustable multi-wavelength light source (3) so that the number of working wavelengths emitted by the adjustable multi-wavelength light source (3) is equal to the number of ring modulators in the second modulator array (7), the working wavelengths correspond one-to-one with the ring modulators, and the working wavelengths are equal to the resonant wavelengths of their corresponding ring modulators. S4: The host computer (1) reads the stored data according to the operation task and arranges it into a first signal sequence and a second signal sequence, and specifies the relative delay between the first signal sequence and the second signal sequence; S5: The host computer (1) sets the symbol arrangement order and symbol period of the first signal sequence and the second signal sequence according to the operation type; S6: The host computer (1) processes the first signal sequence and the second signal sequence according to the photodetector type of the photodetector array (9), the modulator type of the first modulator array (4), the second modulator array (7), and the data type; S7: The host computer (1) converts the second signal sequence; S8: The first signal sequence processed in step S5 and the second signal sequence converted in step S6 are passed through the analog front end (2) to drive the first modulator array (4) and the second modulator array (7) respectively. S9: The adjustable multi-wavelength light source (3) emits the working wavelength and passes through the first modulator sequence, wavelength multiplexer (5), signal beam splitter (6), second modulator array (7), and wavelength demultiplexer array (8) in sequence to perform multi-path parallel computing; S10: The photodetector array (9) receives the multiple signals emitted by the wavelength demultiplexer array (8) and converts them into photocurrent signals; S11: The multi-channel photocurrent signals detected in step S9 are amplified by the analog front end (2) and then transmitted back to the host computer (1). S12: The host computer (1) samples and processes the returned signal to obtain the calculation result; S13: After the operation is completed, the host computer (1) controls the host computer (1), analog front end (2), adjustable multi-wavelength light source (3), first modulator array (4), wavelength multiplexer (5), signal beam splitter (6), second modulator array (7), wavelength demultiplexer array (8), photodetector array (9) and support equipment (10) to reset.

6. The computational method for the photonic computing chip architecture according to claim 5, characterized in that, In step S2, if it is a real number operation, the number of digital-to-analog converters and radio frequency amplifiers in the analog front-end (2) is the total number of modulators in the first modulator array (4) and the second modulator array (7), and each group of digital-to-analog converters and radio frequency amplifiers corresponds to one modulator; if it is a complex number operation, the number of digital-to-analog converters and radio frequency amplifiers is twice the total number of modulators in the first modulator array (4) and the second modulator array (7), and each pair of digital-to-analog converters and radio frequency amplifiers corresponds to one modulator; If the photodetector array (9) is for light intensity detection, the number of analog-to-digital converters and transimpedance amplifiers is the same as the number of photodetectors, and each group of analog-to-digital converters and transimpedance amplifiers corresponds to one photodetector; if the photodetector sequence is for coherent detection, the number of analog-to-digital converters and transimpedance amplifiers is twice the number of photodetectors, and each group of analog-to-digital converters and transimpedance amplifiers corresponds to the output component of one photodetector, and the output component of the photodetector is either the real part or the imaginary part; The modulation voltage amplified by the radio frequency amplifier enables the modulator to operate within the linear region of optical amplitude. By means of the bias controller, the working voltage bias point of the modulator in the first modulator array (4) should be set at the zero point of the linear region of the positive slope of the optical amplitude; The operating voltage bias point of the modulator in the second modulator array (7) should be set at the over-coupling point; the operating voltage bias point of the optical modulator should be set at a suitable reverse bias state.

7. The computational method for the photonic computing chip architecture according to claim 5, characterized in that, In step S5, if vector dot product is to be performed, the first signal sequence and the second signal sequence are two vectors, and the symbol period of both is set to the loop delay of the loop modulator. In the time domain, the symbols of the two vectors are aligned one by one. To perform an M×N matrix-vector multiplication operation, the matrix is ​​arranged column-wise and end-to-end to form an MN-dimensional vector as the first signal sequence, with the symbol period set to the loop delay of the loop modulator 1 / M. The vector is then set as the second signal sequence, with the symbol period set to the loop delay of the loop modulator. In the time domain, each vector symbol is aligned with the M symbols in the corresponding column of the matrix. If you want to perform convolution operations using a single convolution kernel, you can convert the convolution operation into a matrix-vector multiplication operation by performing the required vector dot product. The convolved data is converted into a matrix, which is the first signal sequence, and the convolution kernel is converted into a vector, which is the second signal sequence. To perform convolution operations using K convolution kernels, the convolution operation can be converted into K matrix-vector multiplication operations by the required vector dot product. The convolutioned data is converted into a matrix, which is the first signal sequence. The symbol period is set to the loop delay of the loop modulator, 1 / M. The K convolution kernels are converted into K vectors, which can be further interleaved into the same second signal sequence. The symbol period is set to the loop delay of the loop modulator, 1 / MK. In the time domain, each symbol in the first signal sequence is aligned with the corresponding K symbols in the second signal sequence.

8. The computational method for the photonic computing chip architecture according to claim 5, characterized in that, In step S6, if the photodetector array (9) only supports intensity detection and the operation only involves non-negative real numbers, then the first signal sequence and the second signal sequence do not need further processing. If the photodetector array (9) only supports intensity detection and the operation involves positive and negative real numbers, then the first signal sequence and the second signal sequence need to be decomposed into positive and negative components, and the negative component is taken as the opposite number, forming a total of 4 parts: "positive-positive, positive-negative, negative-positive, negative-negative". The results are then further processed and merged in the data processing section. If the photodetector array (9) only supports intensity detection and the operation involves complex numbers, the signal sequence needs to be decomposed into four components: real part positive, real part negative, imaginary part positive, and imaginary part negative. The negative component is then reversed, forming a total of 16 parts for operation. The results are then further processed and merged in the data processing section. If the photodetector array (9) supports coherent detection, the operation involves positive and negative real numbers and complex numbers. Then the signal sequence does not need further processing, and the positive and negative real numbers only need to ignore the imaginary part in the complex number result.

9. The computational method for the photonic computing chip architecture according to claim 5, characterized in that, In step S7, the second signal sequence is transformed, following these rules: Assume the second signal sequence is... , The converted second signal sequence is Then for the first in the sequence elements ( The following transformation relationship exists: ； ； ； In the formula, Representation and calculation of the first Each element is the index of the related element, and its value range is... arrive , It is the propagation constant of the signal on the optical chip. It is the change in the length of the modulator arm in the second modulator array. and They represent The values ​​of the cosine and sine functions.

10. The computational method for the photonic computing chip architecture according to claim 5, characterized in that, In step S13, during the reset phase, both the first signal sequence and the second signal sequence need to be set to zero, maintaining at least one loop delay time.

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