Semiconductor test structure and semiconductor test method

Abstract

The embodiment of the invention provides a semiconductor test structure and a test method. The semiconductor test structure comprises a substrate; the epitaxial layer is arranged on the substrate; the field oxide layer is located on the epitaxial layer, an open area is arranged on the field oxide layer, a plurality of grooves are formed in the open area at intervals, and polycrystalline silicon is arranged in the grooves; the gate oxide layer is located between the groove and the epitaxial layer; the dielectric layer covers the outer surface, far away from the substrate, of the epitaxial layer; the metal layer is located on the dielectric layer, and the metal layer comprises a first bonding pad and a second bonding pad which are electrically connected with the two ends of the groove respectively; the plurality of contact through holes penetrate through the dielectric layer, and the metal layer is connected with the plurality of grooves through the plurality of contact through holes; according to the semiconductor test structure, voltage is applied to the first bonding pad and the second bonding pad so as to test the deviation condition of the contact hole of the semiconductor.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor testing structure and a semiconductor testing method. Background Art

[0002] In the manufacturing process of semiconductor devices such as power semiconductor MOSFET devices, the manufacture of contact holes connecting metal and silicon requires photolithography alignment, and overlay error is one of the key factors affecting device performance and yield. Traditional monitoring methods usually rely on complex photolithography data analysis, which is not only cumbersome but also difficult to manage, and it is difficult to detect abnormal process fluctuations in a timely manner. Although there are automatic compensation systems for overlay errors in the photolithography section, these systems can only reduce errors to a certain extent and cannot fully meet monitoring needs. Therefore, it is particularly important to develop a test structure that can efficiently monitor overlay errors. Summary of the invention

[0003] Therefore, in order to overcome at least some of the defects and shortcomings in the prior art, an embodiment of the present invention provides a semiconductor test structure and a semiconductor test method.

[0004] Specifically, on the one hand, the semiconductor test structure provided by an embodiment of the present invention includes: a substrate; an epitaxial layer, arranged on the substrate; a field oxide layer, located on the epitaxial layer, an open area is arranged on the field oxide layer, a plurality of grooves are arranged at intervals on the open area, and polysilicon is arranged in the grooves; a gate oxide layer, located between the grooves and the epitaxial layer; a dielectric layer, covering the outer surface of the epitaxial layer away from the substrate; a metal layer, located on the dielectric layer, the metal layer including a first pad and a second pad electrically connected to the two ends of the groove respectively; and a plurality of contact through holes, penetrating the dielectric layer, the metal layer being connected to the plurality of grooves through the plurality of contact through holes; the semiconductor test structure tests the offset of the contact holes of the semiconductor by applying voltage at the first pad and the second pad.

[0005] In a specific embodiment of the present invention, the plurality of contact through-holes include: a plurality of first contact through-holes, which are arranged one by one at the first ends of the plurality of grooves, and the second pads are electrically connected to the grooves through the first contact through-holes; a plurality of second contact through-holes, which are arranged one by one at the second ends of the plurality of grooves, and the first pads are electrically connected to the grooves through the second contact through-holes, and the plurality of second contact through-holes are divided into adjacent first, second and third parts, the second contact through-holes of the first part are arranged to overlap with the grooves, the second contact through-holes of the second part are in contact with the grooves but do not overlap, and the second contact through-holes of the third part are arranged to be spaced apart from the grooves and do not overlap.

[0006] In a specific embodiment of the present invention, the overlapping length between the second contact via and the trench decreases stepwise along the arrangement direction of the trench.

[0007] In a specific embodiment of the present invention, the step distance is 20-50 nm.

[0008] In a specific embodiment of the present invention, the offset of the contact hole of the semiconductor in the arrangement direction of the groove will cause the contact area between the second contact hole and the groove to increase or decrease, and the semiconductor test structure tests the offset of the contact hole of the semiconductor by applying voltage to the first pad and the second pad and the resistance change between the first pad and the second pad.

[0009] In a specific embodiment of the present invention, the number of the grooves is seven, the number of the second contact holes is also seven, and the overlapping lengths of the second contact holes and the grooves along the arrangement direction of the grooves are 200nm, 150nm, 100nm, 50nm, 0nm, -50nm, and -100nm respectively.

[0010] In a specific embodiment of the present invention, the groove extends along a first direction; or, the groove extends along a second direction.

[0011] On the other hand, an embodiment of the present invention also provides a semiconductor testing method, comprising: providing a substrate to be tested, the substrate to be tested comprising the semiconductor test structure and a semiconductor as described above; connecting the first pad and the second pad through a probe of a testing machine, and applying a voltage from the first pad to the second pad; and testing the offset of the contact hole of the semiconductor according to the resistance change between the first pad and the second pad.

[0012] In a specific embodiment of the present invention, the offset condition of the contact hole of the semiconductor is tested based on the resistance change between the first pad and the second pad, specifically: the test resistance between the first pad and the second pad is compared with a resistance threshold, and the offset condition of the contact hole of the semiconductor is obtained based on the comparison result.

[0013] In a specific embodiment of the present invention, when the test resistance is less than the resistance threshold, the contact hole of the semiconductor is left-shifted; when the test resistance is equal to the resistance threshold, the contact hole of the semiconductor is not shifted; when the test resistance is greater than the resistance threshold, the contact hole of the semiconductor is right-shifted.

[0014] As can be seen from the above, the semiconductor test structure provided by the embodiment of the present invention includes a substrate, an epitaxial layer, a field oxide layer, a gate oxide layer, a dielectric layer, a metal layer and a contact through-hole. A groove is set in the open area of ​​the field oxide layer, and the contact through-hole passes through the dielectric layer to connect the metal layer and the contact through-hole. A voltage is applied between the first pad and the second pad of the metal layer, and the offset of the contact hole of the semiconductor is tested according to the change of resistance or current between the first pad and the second pad, so as to characterize the semiconductor overlay error and realize comprehensive monitoring of process changes, which is conducive to timely troubleshooting and improving production efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0016] Figure 1 A schematic structural diagram of a semiconductor test structure provided by an embodiment of the present invention.

[0017] Figure 2 A schematic top view of a semiconductor test structure provided by an embodiment of the present invention.

[0018] Figure 3 A schematic top view of another semiconductor test structure provided by an embodiment of the present invention.

[0019] Figure 4 , Figure 5 and Figure 6 It is a schematic diagram of the equivalent circuit.

[0020] Figure 7 A schematic flow chart of a semiconductor testing method provided by an embodiment of the present invention.

[0021] Main component numbers:

[0022] 10. substrate; 20. epitaxial layer; 30. gate oxide layer; 40. trench; 41. first end; 42. second end; 50. contact hole; 51. first contact hole; 52. second contact hole; 60. dielectric layer; 70. metal layer; 71. first pad; 72. second pad. DETAILED DESCRIPTION

[0023] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments described in the present invention, all other embodiments obtained by ordinary technicians in this field without creative work belong to the protection scope of the present invention.

[0024] It should be noted that all directional indications (such as up, down, left, right, front, back, top, and bottom) in the embodiments of the present invention are only used to explain the relative position relationship, movement, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly. In addition, the term "vertical" involved in the embodiments of the invention and the claims means that the angle between the two elements is 90° or there is a deviation of -5° to +5°, and the term "parallel" involved means that the angle between the two elements is 0° or there is a deviation of -5° to +5°.

[0025] In the embodiments of the present invention, the descriptions of "first", "second", etc. are only for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" or "second" may explicitly or implicitly include at least one of the features.

[0026] See also Figure 1 The embodiment of the present invention provides a semiconductor test structure, which can be used, for example, for testing and monitoring the overlay error of a semiconductor device, such as a power semiconductor MOSFET device, during the manufacturing process. The semiconductor test structure may include: a substrate 10, an epitaxial layer 20, a field oxide layer, a gate oxide layer 30, a dielectric layer 60, a metal layer 70, and a plurality of contact holes 50.

[0027] The substrate 10 may be a single-layer structure, or may include a multi-layer structure composed of the same or different materials. The substrate 10 may be made of semiconductor materials such as Si, SiGe, SiGeC, SiC, GaAs, InAs, InP, and other III / V or II / VI compound semiconductors, or may include a layered substrate such as Si / SiGe, Si / SiC, silicon on insulator (SOI) or silicon germanium on insulator, or may include other materials other than semiconductor materials. The substrate 10 may be a wafer or a chip, and the present invention is not limited thereto.

[0028] The epitaxial layer 20 is disposed on the substrate 10, and specifically can be located on the upper surface of the epitaxial layer 20, for example. The field oxide layer is located on the epitaxial layer 20, and an open area is provided on the field oxide layer, and a plurality of grooves 40 are arranged at intervals on the open area, and polysilicon is arranged in the grooves 40, and the gate oxide layer 30 is located between the grooves 40 and the epitaxial layer 20. In the manufacturing process, for example, a plurality of grooves 40 arranged at intervals can be etched in the open area of ​​the field oxide layer, and the gate oxide layer 30 is first grown in the grooves 40 and then deposited to form polysilicon. The dielectric layer 60 covers the outer surface of the epitaxial layer 20 away from the substrate 10, and the metal layer 70 is located on the dielectric layer 60, and the metal layer 70 includes a first pad 71 and a second pad 72 respectively connected to the two ends of the groove 40, and a plurality of contact through holes 50 penetrate the dielectric layer 60, and the metal layer 70 is connected to the plurality of grooves 40 through the plurality of contact through holes 50, that is, the first pad 71 and the second pad 72 are connected to the plurality of grooves 40 through the plurality of contact through holes 50. The semiconductor test structure tests the offset of the contact hole of the semiconductor by applying voltage at the first pad 71 and the second pad 72. By applying voltage at both ends of the semiconductor test structure, resistance or current is generated. Since the resistance or current characteristics are related to the overlay error of the semiconductor, the offset of the contact hole of the semiconductor can be reflected by measuring the change in resistance or current, thereby characterizing the overlay accuracy.

[0029] In the production and manufacturing process of semiconductors, the manufacturing processes and procedures of semiconductors and semiconductor test structures are fully compatible, no additional mask is required, and the manufacturing cost will not be increased. The semiconductor test structure can be located in the cutting path area of ​​the substrate to be tested. The substrate to be tested may, for example, include a semiconductor and a semiconductor test structure. The cutting path area is located at the periphery of the semiconductor, and a semiconductor device can be obtained after cutting along the cutting path area. The semiconductor test structure does not occupy the area of ​​the device area, so as to avoid affecting the wiring design of the device area, thereby avoiding affecting the performance of the device and increasing the production cost. In some embodiments, the semiconductor test structure may not be set in the cutting path area, for example, it may be set inside the device. Of course, the present embodiment is not limited to this.

[0030] The semiconductor test structure provided by the embodiment of the present invention includes a substrate 10, an epitaxial layer 20, a field oxide layer, a gate oxide layer 30, a dielectric layer 60, a metal layer 70 and a contact through-hole 50. A groove 40 is set in an open area of ​​the field oxide layer, and the contact through-hole 50 passes through the dielectric layer 60 so that the metal layer 70 and the contact through-hole 50 are connected. A voltage is applied between a first pad 71 and a second pad 72 of the metal layer 70, and the offset of the contact hole of the semiconductor is tested according to the change of resistance or current between the first pad 71 and the second pad 72, so as to characterize the semiconductor overlay error and realize comprehensive monitoring of process changes, which is conducive to timely troubleshooting and improving production efficiency.

[0031] See also Figure 2 and Figure 3, the plurality of contact through-holes 50 may, for example, include a plurality of first contact through-holes 51 and a plurality of second contact through-holes 52. The groove 40 includes a first end 41 and a second end 42 opposite to each other, the plurality of first contact through-holes 51 are arranged one-to-one at the first end 41 of the groove 40, the second pad 72 is electrically connected to the groove 40 through the first contact through-holes 51, the plurality of second contact through-holes 52 are arranged one-to-one at the second ends 42 of the plurality of grooves 40, and the first pad 71 is electrically connected to the groove 40 through the second contact through-holes 52. The plurality of grooves 40 may, for example, be arranged at equal intervals, the plurality of first contact through-holes 51 may, for example, have the same shape and size, the first contact through-hole 51 completely overlaps with the groove 40, the plurality of second contact through-holes 52 may, for example, have the same shape and size, but the size of the first contact through-hole 51 may, for example, be smaller, and the size of the second contact through-hole 52 is larger than the size of the first contact through-hole 51.

[0032] In this embodiment, the plurality of second contact holes 52 may be, for example, divided into adjacent first, second, and third parts, wherein the second contact holes 52 of the first part overlap with the groove 40, the second contact holes 52 of the second part contact with the groove 40 but do not overlap, and the second contact holes 52 of the third part are spaced apart from and do not overlap with the groove 40. The number of the second contact holes 52 is at least three, wherein one second contact hole 52 overlaps with the groove 40, and may overlap partially, another second contact hole 52 contacts with the groove 40 but does not overlap, and another second contact hole 52 is spaced apart from and does not overlap with the groove 40. By setting three overlapping situations, more offset situations can be covered to increase the measurement range.

[0033] like Figure 2 As shown, in a specific implementation of the present embodiment, the groove 40 may extend, for example, along a first direction, and the first direction may be, for example, a horizontal direction. The first contact hole 51 is located in the middle of the polysilicon of the groove 40. Since the size of the first contact hole 51 is relatively small, no matter how the first contact hole 51 is offset in the first direction, i.e., the horizontal direction, it can always contact the polysilicon of the groove 40 and the contact area is the same. The offset of the second contact hole 52 in the horizontal direction may cause the contact area between the second contact hole 52 and the polysilicon of the groove 40 to increase or decrease, so that when a voltage is applied to the first pad 71 and the second pad 72, the resistance or current between the first pad 71 and the second pad 72 may change, thereby characterizing the offset of the contact hole of the semiconductor in the horizontal direction.

[0034] like Figure 3As shown, in a specific implementation of the present embodiment, the groove 40 may extend, for example, along the second direction, and the second direction may be, for example, a vertical direction. The first contact hole 51 is located in the middle of the polysilicon of the groove 40. Since the size of the first contact hole 51 is relatively small, no matter how the first contact hole 51 is offset in the second direction, i.e., the vertical direction, it can always contact the polysilicon of the groove 40 and the contact area is the same. The offset of the second contact hole 52 in the vertical direction may cause the contact area between the second contact hole 52 and the polysilicon of the groove 40 to increase or decrease, so that when a voltage is applied to the first pad 71 and the second pad 72, the resistance or current between the first pad 71 and the second pad 72 may change, thereby characterizing the offset of the contact hole of the semiconductor in the vertical direction.

[0035] The offset of the semiconductor contact hole in the arrangement direction of the groove 40 will cause the contact area between the second contact through hole 52 and the polysilicon of the groove 40 to increase or decrease. The semiconductor test structure tests the offset of the semiconductor contact hole by applying voltage to the first pad 71 and the second pad 72 and the resistance change between the first pad 71 and the second pad 72. By comparing the test resistance between the first pad 71 and the second pad 72 with the resistance threshold, the offset of the semiconductor contact hole is obtained according to the comparison result. The first pad 71 and the second pad 72 are connected by a test machine probe, and an appropriate voltage is applied from the first pad 71 to the second pad 72, and then the test machine records the resistance value between the first pad 71 and the second pad 72. When the test resistance is less than the resistance threshold, the semiconductor contact hole is left-offset; when the test resistance is equal to the resistance threshold, the semiconductor contact hole is not offset; when the test resistance is greater than the resistance threshold, the semiconductor contact hole is right-offset. See. Figure 4 , Figure 5 and Figure 6 For example, when the resistance is 1Ω in the initial state, there are four second contact holes 52 overlapping the polysilicon of the trench 40, and each resistance is 0.25Ω. When the test structure is offset to the right by 50nm, there are five second contact holes 52 overlapping the polysilicon of the trench 40, the parallel resistance increases, the total resistance decreases, and the total resistance is 0.8Ω at this time, and the contact hole of the semiconductor is offset to the left; when the test structure is offset to the left by 50nm, there are three second contact holes 52 overlapping the polysilicon of the trench 40, the parallel resistance decreases, the total resistance increases, and the total resistance is 1.3Ω at this time, and the contact hole of the semiconductor is offset to the right.

[0036] Furthermore, the overlapping length of the second contact through hole 52 and the groove 40 is reduced in a step-by-step manner along the arrangement direction of the groove 40, and such a setting can increase the effective measurement range. Preferably, the step distance may be, for example, 20 to 50 nm. In a specific implementation of the present embodiment, the number of grooves 40 is seven, and the number of second contact through holes 52 is also seven, and the overlapping length of the second contact through hole 52 and the groove 40 along the arrangement direction of the groove 40 is 200 nm, 150 nm, 100 nm, 50 nm, 0 nm, -50 nm, -100 nm, respectively. Of course, the present embodiment is not limited to this. In the present embodiment, the number of grooves 40 and the step distance of the overlap between the second contact through hole 52 and the groove 40 can be set according to actual needs.

[0037] See also Figure 7 The embodiment of the present invention further provides a semiconductor testing method, which may include the following steps:

[0038] S10, providing a substrate to be tested, wherein the substrate to be tested includes the semiconductor test structure and a semiconductor as described above;

[0039] S20, connecting the first pad and the second pad through a probe of a test machine, and applying a voltage from the first pad to the second pad;

[0040] S30, testing the offset of the contact hole of the semiconductor according to the resistance change between the first pad and the second pad.

[0041] The semiconductor test method provided in this embodiment is implemented by the above-mentioned semiconductor test structure. Specifically, in the production process of semiconductors, the manufacturing processes and procedures of semiconductors and semiconductor test structures are fully compatible, no additional mask is required, and the manufacturing cost will not be increased. The semiconductor test structure can be located in the cutting road area of ​​the substrate to be tested. The substrate to be tested may, for example, include a semiconductor and a semiconductor test structure. The cutting road area is located at the periphery of the semiconductor. After cutting along the cutting road area, a semiconductor device can be obtained. The semiconductor test structure does not occupy the area of ​​the device area, so as to avoid affecting the wiring design of the device area, thereby avoiding affecting the performance of the device and increasing the production cost. In some embodiments, the semiconductor test structure may not be set in the cutting road area, for example, it may be set in the device. Of course, this embodiment is not limited to this. The first pad 71 and the second pad 72 of the semiconductor test structure are connected by a probe of the test machine and a voltage is applied. The first pad 71 and the second pad 72 are connected by a probe of the test machine, and an appropriate voltage is applied from the first pad 71 to the second pad 72. Then the test machine records the resistance value between the first pad 71 and the second pad 72, and tests the offset of the contact hole of the semiconductor according to the resistance change between the first pad 71 and the second pad 72. In some other embodiments, for example, a test machine may record the current value between the first pad 71 and the second pad 72 , and test the offset of the contact hole of the semiconductor according to the current change between the first pad 71 and the second pad 72 .

[0042] Specifically, for example, the test resistance between the first pad 71 and the second pad 72 can be compared with the resistance threshold, and the offset of the contact hole of the semiconductor can be obtained according to the comparison result. When the test resistance is less than the resistance threshold, the contact hole of the semiconductor is offset to the left; when the test resistance is equal to the resistance threshold, the contact hole of the semiconductor is not offset; when the test resistance is greater than the resistance threshold, the contact hole of the semiconductor is offset to the right. Figure 4 , Figure 5 and Figure 6 For example, when the resistance is 1Ω in the initial state, there are four second contact holes 52 overlapping the polysilicon of the trench 40, and each resistance is 0.25Ω. When the test structure is offset to the right by 50nm, there are five second contact holes 52 overlapping the polysilicon of the trench 40, the parallel resistance increases, the total resistance decreases, and the total resistance is 0.8Ω at this time, and the contact hole of the semiconductor is offset to the left; when the test structure is offset to the left by 50nm, there are three second contact holes 52 overlapping the polysilicon of the trench 40, the parallel resistance decreases, the total resistance increases, and the total resistance is 1.3Ω at this time, and the contact hole of the semiconductor is offset to the right.

[0043] The semiconductor test structure provided by the embodiment of the present invention includes a substrate 10, an epitaxial layer 20, a field oxide layer, a gate oxide layer 30, a dielectric layer 60, a metal layer 70 and a contact through hole 50. A groove 40 is set in the open area of ​​the field oxide layer, and the contact through hole 50 passes through the dielectric layer 60 so that the metal layer 70 and the contact through hole 50 are connected. The semiconductor test method provided by this embodiment generates resistance by applying a voltage between the first pad 71 and the second pad 72 of the metal layer 70 to test the offset of the contact hole of the semiconductor, so as to characterize the semiconductor overlay error and realize comprehensive monitoring of process changes, which is conducive to timely troubleshooting and improving production efficiency. In addition, by setting a plurality of second contact through holes 52, the first part is overlapped with the groove 40, the second part contacts with the groove 40 but does not overlap, and the third part is spaced and does not overlap with the groove 40. By setting three overlapping situations, more offset situations can be covered to increase the measurement range. Furthermore, the overlapping length between the second contact through hole 52 and the groove 40 is reduced stepwise along the arrangement direction of the groove 40. This arrangement can further increase the effective measurement range, improve the monitoring effect, and facilitate timely troubleshooting and improved production efficiency.

[0044] In addition, it can be understood that the aforementioned embodiments are only exemplary descriptions of the present invention. Under the premise that the technical features do not conflict, the structures do not contradict, and the purpose of the present invention is not violated, the technical solutions of the various embodiments can be arbitrarily combined and used in combination.

[0045] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor test structure, characterized in that: include: substrate; an epitaxial layer, disposed on the substrate; A field oxide layer, located on the epitaxial layer, an open area is provided on the field oxide layer, a plurality of grooves are arranged at intervals on the open area, and polysilicon is arranged in the grooves; A gate oxide layer, located between the trench and the epitaxial layer; A dielectric layer covering an outer surface of the epitaxial layer away from the substrate; a metal layer, located on the dielectric layer, the metal layer comprising a first pad and a second pad electrically connected to two ends of the trench respectively; and A plurality of contact through holes penetrating the dielectric layer, wherein the metal layer is connected to the plurality of grooves through the plurality of contact through holes; The semiconductor test structure tests the offset of a contact hole of a semiconductor by applying voltage to the first pad and the second pad.

2. The semiconductor test structure according to claim 1, characterized in that: The plurality of contact vias include: A plurality of first contact through holes are arranged at the first ends of the plurality of the grooves in a one-to-one correspondence, and the second pad is electrically connected to the grooves through the first contact through holes; A plurality of second contact through holes are arranged one by one at the second ends of the plurality of grooves, the first pad is electrically connected to the grooves through the second contact through holes, the plurality of second contact through holes are divided into adjacent first, second and third parts, the second contact through holes of the first part are arranged to overlap with the grooves, the second contact through holes of the second part are in contact with the grooves but do not overlap, and the second contact through holes of the third part are arranged to be spaced apart from and do not overlap with the grooves.

3. The semiconductor test structure according to claim 2, characterized in that: The overlapping length between the second contact through hole and the trench decreases stepwise along the arrangement direction of the trench.

4. The semiconductor test structure according to claim 3, characterized in that: The step distance is 20-50 nm.

5. The semiconductor test structure according to claim 4, characterized in that: The offset of the contact hole of the semiconductor in the arrangement direction of the groove will cause the contact area between the second contact hole and the groove to increase or decrease. The semiconductor test structure tests the offset of the contact hole of the semiconductor by applying voltage to the first pad and the second pad and by the resistance change between the first pad and the second pad.

6. The semiconductor test structure according to claim 3, characterized in that: The number of the grooves is seven, the number of the second contact holes is also seven, and the overlapping lengths of the second contact holes and the grooves along the arrangement direction of the grooves are 200nm, 150nm, 100nm, 50nm, 0nm, -50nm, and -100nm respectively.

7. The semiconductor test structure according to any one of claims 1 to 6, characterized in that: The groove extends along a first direction; or, the groove extends along a second direction.

8. A semiconductor testing method, characterized in that: include: Providing a substrate to be tested, wherein the substrate to be tested comprises the semiconductor test structure according to any one of claims 1 to 7 and a semiconductor; Connecting the first pad and the second pad through a probe of a test machine, and applying a voltage from the first pad to the second pad; The offset of the contact hole of the semiconductor is tested according to the resistance change between the first pad and the second pad.

9. The semiconductor testing method according to claim 8, characterized in that: The step of testing the offset of the contact hole of the semiconductor according to the resistance change between the first pad and the second pad is specifically as follows: The test resistance between the first pad and the second pad is compared with a resistance threshold, and the offset of the contact hole of the semiconductor is obtained according to the comparison result.

10. The semiconductor testing method according to claim 9, wherein: When the test resistance is smaller than the resistance threshold, the contact hole of the semiconductor is shifted to the left; when the test resistance is equal to the resistance threshold, the contact hole of the semiconductor is not shifted; when the test resistance is larger than the resistance threshold, the contact hole of the semiconductor is shifted to the right.

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