Buck power supply chip and overcurrent protection circuit and control circuit thereof

Abstract

The embodiment of the invention provides a Buck power supply chip and an over-current protection circuit and a control circuit thereof, the over-current protection circuit comprises an over-current detection module and an over-current trigger module, the over-current detection module determines an over-current marking signal according to a comparison result of a switch node voltage and an over-current threshold voltage when a lower tube is turned on, and the over-current marking signal is used for outputting the over-current marking signal according to the comparison result of the switch node voltage and the over-current threshold voltage. The over-current trigger module determines an over-current trigger signal according to a comparison result of the reference voltage and the feedback voltage of the Buck power supply chip and the over-current mark signal so as to determine whether the Buck power supply chip is over-current or not, so that the Buck power supply chip can be closed during over-current, and the damage risk of the Buck power supply chip can be reduced.

Description

Technical Field

[0001] The disclosed embodiments relate to the technical field of integrated circuits, and in particular to a Buck power chip and an overcurrent protection circuit and a control circuit thereof. Background Art

[0002] Taking the Buck power chip with a constant on time (COT) architecture as an example, the overcurrent detection circuit of the related technology only provides protection to limit the current from continuing to increase after detecting the inductor overcurrent, and there is no further or more protection measures for overcurrent. When the power chip is overcurrent, the output voltage will be reduced due to the limitation of the continued increase of the output current, and then the power chip will be shut down through the undervoltage protection of the output voltage (the undervoltage protection threshold is usually set to 60%), that is, the shutdown of the power chip is based on undervoltage protection rather than overcurrent shutdown.

[0003] However, when an overcurrent occurs in the power chip and the output voltage does not reach the undervoltage protection threshold, the power chip will continue to operate in an overcurrent state, resulting in a greater risk of damage to the power chip. Summary of the invention

[0004] The disclosed embodiment provides a Buck power chip and an overcurrent protection circuit and a control circuit thereof, which can shut down the Buck power chip in time when the Buck power chip is overcurrent, thereby reducing the risk of damage to the Buck power chip.

[0005] In a first aspect, the present disclosure provides an overcurrent protection circuit for a Buck power chip, wherein the Buck power chip comprises an upper tube and a lower tube, wherein a connection point between the upper tube and the lower tube is a switch node, and the overcurrent protection circuit comprises: an overcurrent detection module and an overcurrent trigger module.

[0006] The overcurrent detection module is configured to determine an overcurrent flag signal according to a comparison result between the switch node voltage and the overcurrent threshold voltage when the lower tube is turned on. The overcurrent trigger module is configured to determine an overcurrent trigger signal according to a comparison result between a reference voltage and a feedback voltage of the Buck power chip and the overcurrent flag signal, so that the Buck power chip is turned off when overcurrent occurs. The overcurrent trigger signal is used to indicate whether the Buck power chip is overcurrent.

[0007] In some embodiments of the present disclosure, the overcurrent detection module includes an RS trigger, a reset end of the RS trigger is used to receive a first comparison signal, a set end of the RS trigger is used to receive a lower tube control signal, and an output end of the RS trigger is connected to an input end of the overcurrent trigger module.

[0008] In some embodiments of the present disclosure, the overcurrent detection module also includes a first comparator, a non-phase input terminal of the first comparator is connected to the switch node, an inverting input terminal of the first comparator is used to receive the overcurrent threshold voltage, and an output terminal of the first comparator is connected to the reset terminal of the RS trigger.

[0009] In some embodiments of the present disclosure, the overcurrent trigger module includes a logic unit and an adder counter, the first input end of the logic unit is connected to the output end of the overcurrent detection module, the second input end of the logic unit is used to receive a second comparison signal, the output end of the logic unit is connected to the input end of the adder counter, and the output end of the adder counter is used to output the overcurrent trigger signal.

[0010] The logic unit is configured to, when the overcurrent flag signal is at a high level, pull up the overcurrent verification signal if the reference voltage is greater than or equal to the feedback voltage, and pull down the overcurrent verification signal if the reference voltage is less than the feedback voltage.

[0011] The adder counter is configured to, when the number of consecutive target edges of the overcurrent verification signal is equal to a preset value, pull up the overcurrent trigger signal to turn off the upper tube and the lower tube; when the number of consecutive target edges is less than the preset value, pull down the overcurrent trigger signal; wherein the target edge is a rising edge or a falling edge.

[0012] In some embodiments of the present disclosure, the logic unit includes an AND gate, a first input end of the AND gate is connected to the output end of the overcurrent detection module, a second input end of the AND gate is used to receive the second comparison signal, and an output end of the AND gate is connected to the input end of the counter.

[0013] In some embodiments of the present disclosure, the overcurrent trigger module also includes a reset unit, a first input end of the reset unit is connected to the output end of the overcurrent detection module, a second input end of the reset unit is used to receive the second comparison signal, and an output end of the reset unit is connected to the reset end of the adder counter.

[0014] The reset unit is configured to sample the overcurrent flag signal at a rising edge of the second comparison signal to obtain a counting reset signal.

[0015] The adder counter is further configured to pull down the overcurrent trigger signal according to the count reset signal to reset the overcurrent trigger signal when the overcurrent flag signal at the rising edge of the second comparison signal is at a low level.

[0016] In some embodiments of the present disclosure, the reset unit includes a D flip-flop, the input end of the D flip-flop is connected to the output end of the overcurrent detection module, the clock end of the D flip-flop is used to receive the second comparison signal, and the inverting output end of the D flip-flop is connected to the reset end of the adder counter.

[0017] The D flip-flop is configured to pull up the count reset signal whenever the overcurrent flag signal at a rising edge of the second comparison signal is at a low level.

[0018] In some embodiments of the present disclosure, the overcurrent trigger module also includes a second comparator, the non-phase input terminal of the second comparator is used to receive the reference voltage, the inverting input terminal of the second comparator is connected to the feedback terminal of the Buck power chip, and the output terminal of the second comparator is connected to the second input terminal of the logic unit.

[0019] In a second aspect, the present disclosure provides a control circuit of a Buck power chip, comprising a drive module and any overcurrent protection circuit provided in the first aspect.

[0020] In a third aspect, the present disclosure provides a Buck power chip, including an upper tube, a lower tube and the control circuit provided in the second aspect.

[0021] In the technical solution provided by the present disclosure, the overcurrent protection circuit of the Buck power chip includes an overcurrent detection module and an overcurrent trigger module. When the lower tube of the overcurrent detection module is turned on, the overcurrent marking signal is determined according to the comparison result of the switch node voltage and the overcurrent threshold voltage. The overcurrent trigger module determines the overcurrent trigger signal according to the comparison result of the reference voltage and the feedback voltage of the Buck power chip and the overcurrent marking signal to determine whether the Buck power chip is overcurrent, so that the Buck power chip can be turned off when overcurrent occurs, which can reduce the risk of damage to the Buck power chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the specific implementation methods of the embodiments of the present application or the technical solutions in the related technologies, the drawings required for use in the specific implementation methods or the related technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some implementation methods of the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0023] Figure 1 A schematic diagram of the structure of a Buck power chip provided in an embodiment of the present disclosure.

[0024] Figure 2 A circuit diagram of a control circuit provided in an embodiment of the present disclosure.

[0025] Figure 3A This is a working waveform diagram of the control circuit provided in the embodiment of the present disclosure when the Buck power chip works normally.

[0026] Figure 3B This is a working waveform diagram of the control circuit provided in the embodiment of the present disclosure when the Buck power chip is overcurrent.

[0027] Figure 4 A schematic diagram of the structure of an overcurrent protection circuit provided in an embodiment of the present disclosure.

[0028] Figure 5 A circuit diagram of an overcurrent protection circuit provided in an embodiment of the present disclosure.

[0029] Figure 6 A circuit diagram of another overcurrent protection circuit is provided for an embodiment of the present disclosure.

[0030] Figure 7 This is a working timing diagram of the overcurrent protection circuit provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0031] In order to enable those skilled in the art to better understand the embodiments of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only implementation methods of a part of the embodiments of the present application, rather than all implementation methods. Based on the embodiments in the embodiments of the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the embodiments of the present application.

[0032] It should be noted that the terms "first", "second", etc. in the specification and claims of the embodiments of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the embodiments of the present application described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0033] In addition, the terms "installed", "set", "provided with", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral structure; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be an internal connection between two devices, elements, or components. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of the present application can be understood according to the specific circumstances.

[0034] Figure 1 A schematic diagram of the structure of a Buck power chip provided in an embodiment of the present disclosure is shown in FIG. Figure 1 As shown, the Buck power chip includes: an upper tube HQ, a lower tube LQ, an energy storage inductor L, a first capacitor C1, a second capacitor C2, a first feedback resistor R1 and a second feedback resistor R2.

[0035] Among them, the first electrode plate of the first capacitor C1 is connected to the second electrode plate of the first capacitor C1 and the ground through the upper tube HQ and the lower tube LQ, the connection point of the upper tube HQ and the lower tube LQ is the switch node SW, the first end of the energy storage inductor L is connected to the switch node SW, the second end of the energy storage inductor L is grounded through the first feedback resistor R1 and the second feedback resistor R2, the connection point of the first feedback resistor R1 and the second feedback resistor R2 is the feedback terminal FB, and the second capacitor C2 is connected between the second end of the energy storage inductor L and the ground.

[0036] When the upper tube HQ is turned on, the lower tube LQ is turned off, and the energy storage inductor L is excited and charged. When the upper tube HQ is turned off, the lower tube LQ is turned on, and the energy storage inductor L is demagnetized and discharged. At the same time, only one of the upper tube HQ and the lower tube LQ can be turned on. In this way, the Buck power chip can realize the excitation and demagnetization of the energy storage inductor L by alternating the conduction of the upper tube HQ and the lower tube LQ, thereby realizing the step-down function.

[0037] Continue to see Figure 1 The Buck power chip also includes a control circuit 10, a first input end of the control circuit 10 receives a reference voltage Vref, a second input end of the control circuit 10 is connected to a feedback end FB to receive a feedback voltage Vfb of the Buck power chip, a first output end of the control circuit 10 is connected to a control end of an upper tube HQ, and provides an upper tube drive signal hsdr to the upper tube HQ to drive the upper tube HQ to turn on or off, and a second output end of the control circuit 10 is connected to a control end of a lower tube LQ, and provides a lower tube drive signal lsdr to the lower tube LQ to drive the lower tube LQ to turn on or off.

[0038] Figure 2 A schematic diagram of a control circuit provided in an embodiment of the present disclosure is shown in FIG. Figure 2As shown, the control circuit 10 includes an overcurrent protection circuit 100, a driving module 11, a trigger 12, a timing module 13, a first logic device LG1, a second logic device LG2 and a third logic device LG3.

[0039] The trigger 12 is an RS trigger, the set end S of the trigger 12 is connected to the output end of the first logic device LG1, the reset end R of the trigger 12 is connected to the output end of the timing module 13 to receive the reset signal Reset, the output end Q of the trigger 12 is connected to the positive phase input end of the second logic device LG2 to provide the upper tube control signal Highside to the second logic device LG2, and the trigger 12

[0040] The inverting output terminal Q of —— is connected to the non-inverting input terminal of the third logic device LG3 to provide the lower tube control signal Lowside to the third logic device LG3.

[0041] The first output terminal of the overcurrent protection circuit 100 is connected to the inverting input terminal of the first logic device LG1 to provide the overcurrent flag signal OCL to the first logic device LG1, and the non-inverting input terminal of the first logic device LG1 receives the second comparison signal Loop, and the second comparison signal Loop can represent the magnitude of the reference voltage Vref and the feedback voltage Vfb. When the reference voltage Vref is greater than or equal to the feedback voltage Vfb, the second comparison signal Loop is at a high level, and when the reference voltage Vref is less than the feedback voltage Vfb, the second comparison signal Loop is at a low level.

[0042] The second output end of the overcurrent protection circuit 100 is connected to the inverting input end of the second logic device LG2 and the inverting input end of the third logic device LG3 to provide an overcurrent trigger signal OCTrigger to the second logic device LG2 and the third logic device LG3, the output end of the second logic device LG2 is connected to the first input end of the driving module 11, the output end of the third logic device LG3 is connected to the second input end of the driving module 11, the first output end of the driving module 11 is connected to the control end of the upper tube HQ, and the second output end of the driving module 11 is connected to the control end of the lower tube LQ.

[0044] A first input terminal of the overcurrent protection circuit 100 is connected to the inverting output terminal Q of the trigger 12 to receive the low-side control signal Lowside, and a second input terminal of the overcurrent protection circuit 100 is connected to the switch node SW to receive the switch node voltage Vsw.

[0045] The overcurrent protection circuit 100 can determine the overcurrent flag signal OCL based on the comparison result between the switch node voltage Vsw and the overcurrent threshold voltage Vth when the lower tube LQ is turned on, that is, when the lower tube control signal Lowside is the on signal, to determine whether the inductor current is overcurrent. Since the switch node voltage Vsw and the overcurrent threshold voltage Vth are both negative values ​​when the lower tube LQ is turned on, when the switch node voltage Vsw is greater than or equal to the overcurrent threshold voltage Vth, the overcurrent flag signal OCL is at a low level, and the inductor current is not overcurrent; when the switch node voltage Vsw is less than the overcurrent threshold voltage Vth, the overcurrent flag signal OCL is at a high level, and the inductor current is overcurrent.

[0046] The overcurrent protection circuit 100 can also determine the overcurrent trigger signal OC Trigger according to the comparison result of the reference voltage Vref and the feedback voltage Vfb and the overcurrent flag signal OCL to determine whether the Buck power chip is overcurrent. When the overcurrent trigger signal OC Trigger is at a high level, the Buck power chip is overcurrent, and when the overcurrent trigger signal OC Trigger is at a low level, the Buck power chip is not overcurrent.

[0047] For example, when the reference voltage Vref is greater than or equal to the feedback voltage Vfb and the overcurrent flag signal OCL is at a high level, the overcurrent trigger signal OC Trigger is at a high level; when the reference voltage Vref is less than the feedback voltage Vfb or the overcurrent flag signal OCL is at a low level, the overcurrent trigger signal OC Trigger is at a low level.

[0048] The first logic device LG1 can perform an AND operation on the inverted signal of the overcurrent flag signal OCL and the second comparison signal Loop, the second logic device LG2 can perform an AND operation on the overcurrent trigger signal OC Trigger and the upper tube control signal High side, and the third logic device LG3 can perform an AND operation on the overcurrent trigger signal OC Trigger and the lower tube control signal Low side.

[0049] When the second comparison signal Loop is at a high level and the overcurrent mark signal OCL is at a low level, the overcurrent trigger signal OCTrigger is at a low level, the first logic device LG1 provides a high level to the set end S of the trigger 12, the upper tube control signal High side output by the trigger 12 is at a high level, the lower tube control signal Low side output by the trigger 12 is at a low level, the second logic device LG2 provides a high level to the driving module 11, and the third logic device LG3 provides a low level to the driving module 11.

[0050] At this time, the driving module 11 drives the upper tube HQ to turn on according to the high level provided by the second logic device LG2, and drives the lower tube LQ to turn off according to the low level provided by the third logic device LG3. The timing module 13 starts timing, and when the timing duration is a fixed duration, the timing module 13 pulls up the reset signal Reset and provides it to the reset terminal R of the trigger 12, then the trigger 12 pulls down the upper tube control signal High side to turn off the upper tube HQ, and pulls up the lower tube control signal Low side to turn on the lower tube LQ.

[0051] When the overcurrent flag signal OCL and the second comparison signal Loop are high, the overcurrent trigger signal OC Trigger is high, that is, the Buck power chip is overcurrent, the first logic device LG1 provides a low level to the set end S of the trigger 12, the upper tube control signal High side output by the trigger 12 is low, the lower tube control signal Low side output by the trigger 12 is high, the second logic device LG2 provides a low level to the driving module 11, and the third logic device LG3 provides a low level to the driving module 11.

[0052] At this time, the driving module 11 drives the upper tube HQ to turn off according to the low level provided by the second logic device LG2, and drives the lower tube LQ to turn off according to the low level provided by the third logic device LG3, so that the Buck power chip can be turned off.

[0053] Figure 3A The working waveform diagram of the control circuit provided in the embodiment of the present disclosure when the Buck power chip is working normally is as follows: Figure 3A As shown, when the Buck power chip works normally, the upper tube control signal High side is the second comparison signal Loop, and when the lower tube control signal Low side is at a high level, the overcurrent flag signal OCL is pulled high.

[0054] Since the Buck power chip works normally, the switch node voltage Vsw is greater than or equal to the overcurrent threshold voltage Vth, for example, the overcurrent threshold voltage is -50V. Therefore, after the overcurrent flag signal OCL is set to a high level, the overcurrent flag signal OCL is pulled low.

[0055] Figure 3B The working waveform diagram of the control circuit provided in the embodiment of the present disclosure when the Buck power chip is overcurrent, such as Figure 3B As shown, when the Buck power chip is over-current, the second comparison signal Loop maintains a high level, and when the lower tube control signal Low side is a high level, the over-current flag signal OCL is pulled high.

[0056] Due to the overcurrent of the Buck power chip, the switch node voltage Vsw is less than the overcurrent threshold voltage Vth. For example, the overcurrent threshold voltage is -50V. Therefore, after the overcurrent flag signal OCL is set to a high level, the overcurrent flag signal OCL is maintained at a high level until the switch node voltage Vsw rises to be equal to the overcurrent threshold voltage Vth, thereby pulling down the overcurrent flag signal OCL.

[0057] In this way, when the lower tube is turned on, the overcurrent protection circuit 100 can determine the overcurrent flag signal according to the comparison result of the switch node voltage and the overcurrent threshold voltage, and determine the overcurrent trigger signal according to the comparison result of the reference voltage and the feedback voltage of the Buck power chip and the overcurrent flag signal. The overcurrent trigger signal is used to indicate whether the Buck power chip is overcurrent. When the Buck power chip is overcurrent, the control circuit 10 can turn off the Buck power chip according to the overcurrent flag signal and the overcurrent trigger signal to avoid the Buck power chip from working in the overcurrent state for a long time, thereby reducing the risk of damage to the Buck power chip.

[0058] The overcurrent protection circuit provided by the present disclosure is described in detail below with reference to several specific embodiments.

[0059] Figure 4 A schematic diagram of the structure of an overcurrent protection circuit provided by an embodiment of the present disclosure is shown in FIG. Figure 4 As shown, the overcurrent protection circuit 100 includes an overcurrent detection module 110 and an overcurrent triggering module 120 .

[0060] Combination Figure 2 and Figure 4 As shown, the output end of the overcurrent detection module 110 is connected to the input end of the overcurrent trigger module 120 and the inverting input end of the first logic LG1, and the output end of the overcurrent trigger module 120 is connected to the inverting input end of the second logic LG2 and the inverting input end of the third logic LG3.

[0061] The overcurrent detection module 110 is configured to determine the overcurrent flag signal OCL according to the comparison result between the switch node voltage Vsw and the overcurrent threshold voltage Vth when the lower tube LQ is turned on. The overcurrent trigger module 120 is configured to determine the overcurrent trigger signal OC Trigger according to the comparison result between the reference voltage Vref and the feedback voltage Vfb of the Buck power chip and the overcurrent flag signal OCL, so as to shut down the Buck power chip when overcurrent occurs.

[0062] For example, Figure 5 A circuit diagram of an overcurrent protection circuit provided by an embodiment of the present disclosure is shown in FIG. Figure 5As shown, the overcurrent detection module 110 includes an RS trigger RSFF, a reset terminal R of the RS trigger RSFF receives a first comparison signal, a set terminal S of the RS trigger RSFF receives a lower tube control signal Low side, and an output terminal Q of the RS trigger RSFF is connected to an input terminal of the overcurrent trigger module 120 to output an overcurrent flag signal OCL to the overcurrent trigger module 120.

[0063] The first comparison signal is used to characterize the comparison result between the switch node voltage Vsw and the overcurrent threshold voltage Vth, wherein when the switch node voltage Vsw is greater than or equal to the overcurrent threshold voltage Vth, the first comparison signal is a high level, and when the switch node voltage Vsw is less than the overcurrent threshold voltage Vth, the first comparison signal is a low level.

[0064] Whenever the lower tube control signal Low side is an on signal, that is, a high level, the RS trigger RSFF first pulls up the overcurrent flag signal OCL. At this time, the lower tube LQ is turned on, and the inductor current continues to flow through the lower tube LQ. The switch node voltage Vsw is the drain-source voltage of the lower tube LQ, and the switch node voltage Vsw is the product of the drain-source voltage of the lower tube LQ and the on-resistance of the lower tube. The overcurrent threshold is set to x, and the overcurrent threshold voltage Vth is the product of the overcurrent threshold x and the on-resistance of the lower tube. The RS trigger RSFF then determines the overcurrent flag signal OCL through the comparison result of the switch node voltage Vsw and the overcurrent threshold voltage Vth.

[0065] Specifically, if the switch node voltage Vsw is less than the overcurrent threshold voltage Vth, the first comparison signal is at a low level, and the RS trigger RSFF continuously pulls up the overcurrent marking signal OCL; if the switch node voltage Vsw is greater than or equal to the overcurrent threshold voltage Vth, the first comparison signal is at a high level, and the RS trigger RSFF pulls down the overcurrent marking signal OCL.

[0066] In this way, whenever the lower tube control signal Low side of the RS trigger RSFF is an on signal, if the switch node voltage Vsw is less than the overcurrent threshold voltage Vth, the overcurrent flag signal OCL is pulled high according to the first comparison signal; if the switch node voltage Vsw is greater than or equal to the overcurrent threshold voltage Vth, the overcurrent flag signal OCL is pulled low according to the first comparison signal.

[0067] Continue to see Figure 5 The overcurrent trigger module 120 includes a logic unit 121, a first input end of the logic unit 121 is connected to the output end of the overcurrent detection module 120, a second input end of the logic unit 121 receives a second comparison signal Loop, and an output end of the logic unit 121 is connected to the inverting input end of the second logic unit LG2 and the inverting input end of the third logic unit LG3.

[0068] For example, Figure 5As shown, the logic unit 121 includes an AND gate AND, a first input end of the AND gate AND is connected to the output end of the overcurrent detection module 110, a second input end of the AND gate AND is used to receive the second comparison signal Loop, and an output end of the AND gate AND is connected to the inverting input end of the second logic LG2 and the inverting input end of the third logic LG3.

[0069] The AND gate AND can perform an AND operation on the overcurrent flag signal OCL and the second comparison signal Loop to obtain the overcurrent trigger signal OC Trigger, wherein when the overcurrent flag signal OCL is at a high level and the second comparison signal Loop is at a high level, the overcurrent trigger signal OC Trigger is at a high level; when the overcurrent flag signal OCL is at a high level and the second comparison signal Loop is at a low level, the overcurrent trigger signal OC Trigger is at a low level.

[0070] Whenever the lower tube control signal Low side is an on signal and the switch node voltage Vsw is less than the overcurrent threshold voltage Vth, the overcurrent flag signal OCL maintains a high level. At this time, the feedback voltage Vfb is less than the reference voltage Vref, the second comparison signal Loop is high, and the overcurrent trigger signal OC Trigger is high, so that the upper tube HQ and the lower tube LQ of the Buck power chip are turned off, until the inductor current drops to the overcurrent threshold, the switch node voltage Vsw is greater than or equal to the overcurrent threshold voltage Vth, the overcurrent flag signal OCL is low, and the overcurrent trigger signal OC Trigger is low, so that the upper tube HQ of the Buck power chip is turned on.

[0071] In summary, the overcurrent protection circuit 100 includes an overcurrent detection module 110 and an overcurrent trigger module 120. When the lower tube LQ is turned on, the overcurrent detection module 110 determines the overcurrent marking signal OCL according to the comparison result of the switch node voltage Vsw and the overcurrent threshold voltage Vth. The overcurrent trigger module 120 determines the overcurrent trigger signal OC Trigger according to the comparison result of the reference voltage Vref and the feedback voltage Vfb of the Buck power chip and the overcurrent marking signal OCL to determine whether the Buck power chip is overcurrent, so that the Buck power chip can be turned off when overcurrent occurs, thereby reducing the risk of damage to the Buck power chip.

[0072] In some embodiments, see Figure 5 The overcurrent detection module 110 also includes a first comparator CP1, a non-inverting input terminal of the first comparator CP1 is connected to the switch node SW, an inverting input terminal of the first comparator CP1 receives the overcurrent threshold voltage Vth, and an output terminal of the first comparator CP1 is connected to the reset terminal R of the RS trigger RSFF.

[0073] Exemplarily, the non-inverting input terminal of the first comparator CP1 receives the switch node voltage Vsw, and the first comparator CP1 can compare the switch node voltage Vsw and the overcurrent threshold voltage Vth, and generate a first comparison signal according to the comparison result of the switch node voltage Vsw and the overcurrent threshold voltage Vth.

[0074] When the switch node voltage Vsw is greater than or equal to the overcurrent threshold voltage Vth, the first comparison signal generated by the first comparator CP1 is high level, and when the switch node voltage Vsw is less than the overcurrent threshold voltage Vth, the first comparison signal generated by the first comparator CP1 is low level.

[0075] In some embodiments, Figure 6 A circuit diagram of another overcurrent protection circuit provided by an embodiment of the present disclosure is shown in FIG. Figure 6 As shown, the overcurrent trigger module 120 includes a logic unit 121 and an adder counter 122, the first input end of the logic unit 121 is connected to the output end of the overcurrent detection module 110, the second input end of the logic unit 121 receives the second comparison signal Loop, the output end of the logic unit 111 is connected to the input end of the adder counter 122, and the output end of the adder counter 122 is connected to the inverting input end of the second logic LG2 and the inverting input end of the third logic LG3.

[0076] The logic unit 121 is configured to pull up the overcurrent verification signal Trigger when the overcurrent flag signal OCL is at a high level if the reference voltage Vref is greater than or equal to the feedback voltage Vfb, and pull down the overcurrent verification signal Trigger if the reference voltage Vref is less than the feedback voltage Vfb.

[0077] The adder counter 122 is configured to, when the number of consecutive target edges of the overcurrent verification signal Trigger is equal to a preset value, pull up the overcurrent trigger signal OC Trigger to turn off the upper tube HQ and the lower tube LQ; when the number of consecutive target edges of the overcurrent verification signal Trigger is less than the preset value, pull down the overcurrent trigger signal OC Trigger; wherein the target edge is a rising edge or a falling edge.

[0078] For example, Figure 6 As shown, the logic unit 121 includes an AND gate AND, a first input end of the AND gate AND is connected to the output end of the overcurrent detection module 110 , a second input end of the AND gate AND receives the second comparison signal Loop, and an output end of the AND gate AND is connected to the input end of the adder counter 122 .

[0079] The AND gate AND can perform an AND operation on the overcurrent mark signal OCL and the second comparison signal Loop to obtain the overcurrent verification signal Trigger to verify whether the detection result of the inductor current overcurrent is accurate. When the overcurrent mark signal OCL is at a high level and the second comparison signal Loop is at a high level, the overcurrent verification signal Trigger is at a high level, and the detection result of the inductor current overcurrent is accurate; when the overcurrent mark signal OCL is at a high level and the second comparison signal Loop is at a low level, the overcurrent verification signal Trigger is at a low level, and the detection result of the inductor current overcurrent is inaccurate.

[0080] Exemplarily, the adder counter 122 is a rising edge trigger, and can count the continuous rising edges of the overcurrent verification signal Trigger. When the number of continuous rising edges of the overcurrent verification signal Trigger is equal to a preset value, for example, the preset value can be 15, the overcurrent trigger signal OC Trigger output by the adder counter 122 is a high level to turn off the upper tube HQ and the lower tube LQ, thereby achieving the purpose of turning off the Buck power chip. When the number of continuous rising edges of the overcurrent verification signal Trigger is less than the preset value, the overcurrent trigger signal OC Trigger output by the adder counter 122 is a low level.

[0081] Figure 7 A working timing diagram of an overcurrent protection circuit provided by an embodiment of the present disclosure is shown in FIG. Figure 7 As shown, the overcurrent threshold is 9A, the preset value is 15, and between time T1 and time T2, the number of consecutive rising edges of the overcurrent verification signal Trigger is 9. The number of consecutive rising edges of the overcurrent verification signal Trigger is less than the preset value, and the overcurrent trigger signal OC Trigger continues to be at a low level.

[0082] Between time T3 and time T4, the number of consecutive rising edges of the overcurrent verification signal Trigger is 15. Then, at time T4, the number of consecutive rising edges of the overcurrent verification signal Trigger is equal to the preset value, and the overcurrent trigger signal OC Trigger is pulled up to a high level.

[0083] In other embodiments, the adder counter 122 is triggered by a falling edge, and can count the continuous falling edges of the overcurrent verification signal Trigger. When the number of continuous falling edges of the overcurrent verification signal Trigger is equal to a preset value, the overcurrent trigger signal OC Trigger is at a high level to turn off the upper tube HQ and the lower tube LQ. When the number of continuous falling edges of the overcurrent verification signal Trigger is less than the preset value, the overcurrent trigger signal OC Trigger is at a low level.

[0084] In this way, when the number of consecutive overcurrents of the inductor current reaches a preset value, it is determined that the Buck power chip is overcurrent, which can avoid the problem of misjudgment of overcurrent of the Buck power chip, improve the accuracy of overcurrent protection of the Buck power chip, and thus improve the stability of the Buck power chip.

[0085] In some embodiments, see Figure 6 The overcurrent trigger module 120 also includes a reset unit 123, a first input end of the reset unit 123 is connected to the output end of the overcurrent detection module 110, a second input end of the reset unit 123 receives the second comparison signal Loop, and an output end of the reset unit 123 is connected to the reset end of the adder counter 122.

[0086] The reset unit 123 is configured to sample the over-current flag signal OCL at a rising edge of the second comparison signal Loop to obtain a counting reset signal Rese_c.

[0087] The adder counter 122 is further configured to pull down the over-current trigger signal OC Trigger according to the count reset signal Rese_c to reset when the over-current flag signal OCL at the rising edge of the second comparison signal Loop is at a low level.

[0088] Exemplarily, the reset unit 123 includes a D flip-flop DFF, the input end of the D flip-flop DFF is connected to the output end of the overcurrent detection module 110, and the clock end CK of the D flip-flop DFF receives the second ratio

[0089] ——Compared with the signal Loop, the inverting output terminal Q of the D flip-flop DFF is connected to the reset terminal of the adder counter 122.

[0090] Whenever the overcurrent flag signal OCL at the rising edge of the second comparison signal Loop is at a low level, the count reset signal Reset_c output by the D flip-flop is at a high level. At this time, the adder counter 122 is reset according to the count reset signal Reset_c, that is, the overcurrent trigger signal OC Trigger is pulled low. Whenever the overcurrent flag signal OCL at the rising edge of the second comparison signal Loop is at a high level, the count reset signal Reset_c output by the D flip-flop is at a low level. At this time, the adder counter 122 is not reset, and the adder counter 122 maintains the counting state.

[0091] Specifically, when the number of consecutive target edges of the overcurrent verification signal Trigger has not reached a preset value, the overcurrent flag signal OCL is detected to be at a low level, and the D flip-flop DFF pulls up the count reset signal Reset_c to reset the adder counter 122 to ensure that the adder counter 122 can accurately re-count. When the inductor current is not overcurrent, the count reset signal Reset_c is continuously pulled high to continuously reset the adder counter 122, and the adder counter 122 does not count.

[0092] For example, Figure 7 As shown, at time T1, the overcurrent verification signal Trigger has the first rising edge, the overcurrent mark signal OCL is at a high level, the count reset signal Reset_c turns to a low level, and the adder counter 122 starts counting. At time T2, the number of consecutive rising edges of the overcurrent verification signal Trigger does not reach the preset value, but at this time the overcurrent mark signal OCL turns to a low level, the count reset signal Reset_c turns to a high level, and the adder counter 122 is reset.

[0093] At time T3, the overcurrent verification signal Trigger has the first rising edge again, the overcurrent flag signal OCL is at a high level, the count reset signal Reset_c flips to a low level, and the adder counter 122 starts counting. At time T4, the number of consecutive rising edges of the overcurrent verification signal Trigger reaches a preset value, and the count reset signal Reset_c maintains a low level.

[0094] In this way, when the number of consecutive target edges of the overcurrent verification signal Trigger does not reach the preset value, the adder counter 122 is reset; when the inductor current is not overcurrent, the adder counter 122 is reset; the adder counter 122 only counts when the inductor current is overcurrent, and resets the adder counter 122 when the number of consecutive target edges of the overcurrent verification signal Trigger is less than the preset value, thereby ensuring the accurate counting of the adder counter 122 and improving the accuracy of the overcurrent protection of the Buck power chip, thereby improving the stability of the Buck power chip.

[0095] In some embodiments, see Figure 5 and Figure 6 The overcurrent trigger module 120 also includes a second comparator CP2, a non-phase input terminal of the second comparator CP2 receives a reference voltage Vref, an inverting input terminal of the second comparator CP2 is connected to a feedback terminal of the Buck power chip, and an output terminal of the second comparator CP2 is connected to a second input terminal of the logic unit 121.

[0096] Exemplarily, the inverting input terminal of the second comparator CP2 receives the feedback voltage Vfb. The second comparator CP2 can compare the reference voltage Vref with the feedback voltage Vfb, and generate a second comparison signal Loop according to the comparison result of the reference voltage Vref and the feedback voltage Vfb.

[0097] When the reference voltage Vref is greater than or equal to the feedback voltage Vfb, the second comparison signal Loop generated by the second comparator CP2 is at a high level, and when the reference voltage Vref is less than the feedback voltage Vfb, the second comparison signal Loop generated by the second comparator CP2 is at a low level.

[0098] Unless the context clearly indicates otherwise, the singular form of the words used herein and in the appended claims includes the plural and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the words "comprise" and "include" are to be interpreted as inclusive rather than exclusive. Likewise, the terms "include" and "or" should be interpreted as inclusive unless such interpretation is expressly prohibited herein. Where the term "example" is used herein, particularly when it is located after a group of terms, the "example" is merely exemplary and illustrative and should not be considered exclusive or comprehensive.

[0099] Further aspects and scopes of adaptability become apparent from the description provided herein. It should be understood that various aspects of the present application can be implemented individually or in combination with one or more other aspects. It should also be understood that the description and specific embodiments herein are intended for purposes of illustration only and are not intended to limit the scope of the present application.

[0100] Several embodiments of the present disclosure are described in detail above, but it is obvious that those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. The protection scope of the present disclosure is defined by the attached claims.

Claims

1. An overcurrent protection circuit for a Buck power chip, characterized in that: The Buck power chip includes an upper tube and a lower tube, the connection point between the upper tube and the lower tube is a switch node, and the overcurrent protection circuit includes: an overcurrent detection module and an overcurrent trigger module; The overcurrent detection module is configured to determine an overcurrent flag signal according to a comparison result between the switch node voltage and the overcurrent threshold voltage when the lower tube is turned on; The overcurrent trigger module is configured to determine an overcurrent trigger signal based on a comparison result between a reference voltage and a feedback voltage of the Buck power chip and the overcurrent flag signal, so that the Buck power chip is shut down when there is an overcurrent. The overcurrent trigger signal is used to indicate whether the Buck power chip is overcurrent.

2. The overcurrent protection circuit according to claim 1, characterized in that: The overcurrent detection module includes an RS trigger; The reset end of the RS trigger is used to receive the first comparison signal, the set end of the RS trigger is used to receive the lower tube control signal, and the output end of the RS trigger is connected to the input end of the overcurrent trigger module.

3. The overcurrent protection circuit according to claim 2, characterized in that: The overcurrent detection module also includes a first comparator; The non-inverting input terminal of the first comparator is connected to the switch node, the inverting input terminal of the first comparator is used to receive the over-current threshold voltage, and the output terminal of the first comparator is connected to the reset terminal of the RS trigger.

4. The overcurrent protection circuit according to claim 1, characterized in that: The overcurrent trigger module includes a logic unit and an adder counter; The first input end of the logic unit is connected to the output end of the overcurrent detection module, the second input end of the logic unit is used to receive the second comparison signal, the output end of the logic unit is connected to the input end of the adder counter, and the output end of the adder counter is used to output the overcurrent trigger signal; The logic unit is configured to, when the overcurrent flag signal is at a high level, pull up the overcurrent verification signal if the reference voltage is greater than or equal to the feedback voltage, and pull down the overcurrent verification signal if the reference voltage is less than the feedback voltage; The adder counter is configured to, when the number of consecutive target edges of the overcurrent verification signal is equal to a preset value, pull up the overcurrent trigger signal to turn off the upper tube and the lower tube; when the number of consecutive target edges is less than the preset value, pull down the overcurrent trigger signal; wherein the target edge is a rising edge or a falling edge.

5. The overcurrent protection circuit according to claim 4, characterized in that: The logic unit includes an AND gate; The first input end of the AND gate is connected to the output end of the overcurrent detection module, the second input end of the AND gate is used to receive the second comparison signal, and the output end of the AND gate is connected to the input end of the counter.

6. The overcurrent protection circuit according to claim 4, characterized in that: The overcurrent trigger module also includes a reset unit; The first input end of the reset unit is connected to the output end of the overcurrent detection module, the second input end of the reset unit is used to receive the second comparison signal, and the output end of the reset unit is connected to the reset end of the adder counter; The reset unit is configured to, at a rising edge of the second comparison signal, sample the overcurrent flag signal to obtain a counting reset signal; The adder counter is further configured to pull down the overcurrent trigger signal according to the count reset signal to reset the overcurrent trigger signal when the overcurrent flag signal at the rising edge of the second comparison signal is at a low level.

7. The overcurrent protection circuit according to claim 6, characterized in that: The reset unit includes a D flip-flop; The input end of the D flip-flop is connected to the output end of the overcurrent detection module, the clock end of the D flip-flop is used to receive the second comparison signal, and the inverting output end of the D flip-flop is connected to the reset end of the adder counter; The D flip-flop is configured to pull up the count reset signal whenever the overcurrent flag signal at a rising edge of the second comparison signal is at a low level.

8. The overcurrent protection circuit according to any one of claims 4 to 7, characterized in that: The overcurrent trigger module also includes a second comparator; The non-inverting input terminal of the second comparator is used to receive the reference voltage, the inverting input terminal of the second comparator is connected to the feedback terminal of the Buck power chip, and the output terminal of the second comparator is connected to the second input terminal of the logic unit.

9. A control circuit of a Buck power chip, characterized in that: It comprises a driving module and the overcurrent protection circuit according to any one of claims 1 to 8.

10. A Buck power chip, characterized in that: The invention comprises an upper tube, a lower tube and the control circuit as claimed in claim 9.

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