Fabricating a gap structure in a three-dimensional semiconductor device

Abstract

Systems, apparatuses, and methods for fabricating a gap structure in a three-dimensional (3D) semiconductor device are provided. In one aspect, a method includes providing a semiconductor structure including a first region and a second region, the first region including a first trench structure, the second region including a second trench structure, wherein the semiconductor structure includes a first sacrificial film covering the first trench structure, and a second sacrificial film formed on a surface of the second trench structure along a first direction from an opening of the second trench structure to a bottom of the second trench structure. At least one portion of the second sacrificial film is etched while at least one portion of the first sacrificial film remains to cover the first trench structure.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices and manufacturing processes for semiconductor devices. Background Technology

[0002] Semiconductor devices (e.g., memory devices) can have various structures to increase the density of memory cells and lines on a chip. For example, three-dimensional (3D) memory devices have attracted attention because they can increase array density by stacking more layers within a similar footprint. 3D memory devices typically include a memory array of memory cells and peripheral circuitry for facilitating the operation of the memory array. Memory cells may include a vertical structure. Summary of the Invention

[0003] This disclosure describes methods, apparatus, systems, and techniques for managing vertical structures in three-dimensional (3D) semiconductor devices.

[0004] One aspect of this disclosure features a method comprising: providing a semiconductor structure including a first region and a second region, the first region including a first trench structure, and the second region including a second trench structure, wherein the semiconductor structure includes: a first sacrificial film covering the first trench structure, and a second sacrificial film formed on a surface of the second trench structure along a first direction from an opening of the second trench structure to a bottom of the second trench structure. At least one portion of the second sacrificial film is etched, while at least one portion of the first sacrificial film remains to cover the first trench structure.

[0005] In some embodiments, the first trench structure is coupled to the second trench structure, and wherein the first sacrificial membrane is coupled to the second sacrificial membrane.

[0006] In some embodiments, the first trench structure has a width smaller than that of the second trench structure along a second direction perpendicular to the first direction.

[0007] In some embodiments, the method includes depositing a sacrificial material over the first trench structure and the second trench structure to fill the sacrificial material in the first trench structure and form a first sacrificial film covering the filled sacrificial material in the first trench structure, and forming a second sacrificial film having a first portion on the top surface of the second region and a second portion on the inner surface of the second trench structure.

[0008] In some embodiments, the second sacrificial film includes a first portion located on the top surface of the second region and a second portion located on the inner surface of the second trench structure, wherein etching at least one portion of the second sacrificial film includes etching away the second portion of the second sacrificial film from the inner surface of the second trench structure.

[0009] In some embodiments, the method includes altering at least one characteristic of a region of the sacrificial material, wherein the region of the sacrificial material includes the first portion of the second sacrificial membrane or at least one of the first sacrificial membranes.

[0010] In some embodiments, altering at least one characteristic of the region of the sacrificial material includes implanting ions into the region of the sacrificial material to change the etching rate of the region of the sacrificial material.

[0011] In some embodiments, implanting the ions into the region of the sacrificial material includes controlling at least one of ion implantation power, ion implantation angle, or ion implantation density to implant the ions into the region of the sacrificial material.

[0012] In some embodiments, the sacrificial material includes at least one of polycrystalline silicon or alumina, and wherein the ion includes at least one of nitrogen, argon, carbon, or boron.

[0013] In some embodiments, the sacrificial material comprises polycrystalline silicon, and the method further includes implanting ions into a region of the sacrificial material to convert the polycrystalline silicon in the region of the sacrificial material into non-polycrystalline silicon, thereby altering the etch rate of the region of the sacrificial material, wherein the region of the sacrificial material includes a first portion of a second sacrificial film located on the top surface of a second region.

[0014] In some embodiments, the second region includes a plurality of alternating sacrificial layers and insulating layers, and wherein the method further includes removing the sacrificial layers in the second region through openings in the second trench structure after etching at least one portion of the second sacrificial film.

[0015] Another aspect of this disclosure features a semiconductor device comprising: an array region including a first slit structure extending along a first direction; and a connection region adjacent to the array region along a second direction perpendicular to the first direction, wherein the connection region includes a second slit structure extending along the first direction through an insulating layer extending along the second direction, and wherein the insulating layer includes an insulating material and ions distributed in the insulating material within the insulating layer.

[0016] In some embodiments, the semiconductor device includes a stack of conductive and insulating layers alternating with each other along the first direction, wherein each of the first and second slot structures extends through the stack of conductive and insulating layers, and wherein the insulating layer is closer to the end of the second slot structure along the first direction than the stack of conductive and insulating layers.

[0017] In some embodiments, the connection region includes a plurality of contact structures extending through a stack of the conductive layer and the insulating layer, and at least one of the conductive layers is coupled to a corresponding contact structure among the plurality of contact structures.

[0018] In some embodiments, the connection region includes a first end and a second end opposite each other along the first direction, and each of the plurality of contact structures is outwardly coupled to a conductive contact at the first end or the second end.

[0019] In some implementations, the array region includes a plurality of channel structures extending through a stack of the conductive layer and the insulating layer.

[0020] In some embodiments, the first slit structure is connected to the second slit structure along the second direction, and along a third direction perpendicular to the first and second directions, the width of the first slit structure is smaller than the width of the second slit structure.

[0021] In some embodiments, the insulating layer includes a first surface and a second surface along the first direction, the first surface being closer to the end of the second slit structure along the first direction than the second surface, and wherein a first concentration of the ions adjacent to the first surface is higher than a second concentration of the ions adjacent to the second surface of the insulating layer.

[0022] Another aspect of this disclosure features a method comprising: providing a semiconductor structure including a first region and a second region, the first region including a first trench structure, the second region including a second trench structure, wherein the semiconductor structure includes: a first sacrificial film covering the first trench structure, and a second sacrificial film formed on a surface of the second trench structure from an opening of the second trench structure to a bottom of the second trench structure, and wherein the second sacrificial film includes a first portion located on a top surface of the second region and a second portion located on an inner surface of the second trench structure. At least one characteristic of a region of sacrificial material is modified, wherein the region of the sacrificial material includes the first portion of the second sacrificial film or at least one of the first sacrificial film. The second portion of the second sacrificial film is etched away from the inner surface of the second trench structure, while at least one portion of the first sacrificial film remains to cover the first trench structure.

[0023] In some embodiments, altering at least one characteristic of the region of the sacrificial material includes implanting ions into the region of the sacrificial material to change the etching rate of the region of the sacrificial material.

[0024] Embodiments of this disclosure may provide one or more of the following technical advantages and / or benefits. For example, in some cases, during the etching process, the sacrificial material of the second trench structure can be etched, while the sacrificial material of the first trench structure may be retained or etched at a slower or lesser rate than the sacrificial material of the second trench structure. In some embodiments, this technique may use a protective layer to cover the sacrificial material of the first trench structure while exposing the sacrificial material of the second trench structure. In some embodiments, the techniques described herein can implant ions into the sacrificial material of the first trench structure, thereby reducing the etching rate of the sacrificial material of the first trench structure. Therefore, the sacrificial material of the first trench structure can be largely retained, while the sacrificial material of the second trench structure is etched in the same etching process. Ion implantation-based techniques can simplify the manufacturing process (e.g., the technique can eliminate the steps of depositing and removing a dedicated protective layer). Therefore, this technique can reduce the manufacturing cost of semiconductor structures. This technique can also mitigate oxide residue problems, which are typical problems in sacrificial material etching processes. In some embodiments, this technique can extend the time window for etching the sacrificial material, thereby simplifying the manufacturing process of semiconductor structures.

[0025] This technology can be applied to various types of semiconductor devices, volatile memory devices (e.g., DRAM memory devices), or non-volatile memory (NVM) devices, such as NAND flash memory, NOR flash memory, resistive random access memory (RRAM), phase-change memory (PCM) such as phase-change random access memory (PCRAM), spin-transfer torque (STT)-magnetoresistive random access memory (MRAM), and so on. This technology can also be applied to charge-trapping based memory devices, such as silicon-oxide-nitride-oxide-silicon (SONOS) memory devices, and to floating-gate based memory devices. This technology can also be applied to three-dimensional (3D) memory devices. This technology can be applied to various memory types, such as SCL (single-level cell) devices, MLC (multi-level cell) devices like 2-level cell devices, TLC (three-level cell) devices, QLC (four-level cell) devices, or PLC (five-level cell) devices. Additionally or alternatively, this technology can be applied to various types of devices and systems, such as secure digital (SD) cards, embedded multimedia cards (eMMC) or solid-state drives (SSDs), embedded systems, and so on.

[0026] Details of one or more embodiments of the subject matter of this disclosure are set forth in the accompanying drawings and the following description. Other features, aspects, and advantages of the subject matter will become apparent from this description, the drawings, and the claims. Attached Figure Description

[0027] The accompanying drawings, which are incorporated herein and form a part of this disclosure, illustrate various aspects of this disclosure and, together with the description, further serve to explain the principles of this disclosure and enable those skilled in the art to make and use this disclosure.

[0028] Figure 1A This is a top view of an exemplary 3D semiconductor structure.

[0029] Figure 1B Depicting along Figure 1A The cross-sectional view of the exemplary 3D semiconductor structure with cut lines AA' and BB' shown is shown.

[0030] Figures 2A-2E The diagram shows a cross-sectional view of an exemplary semiconductor structure after each stage of the manufacturing process.

[0031] Figures 3A-3D The diagram shows a cross-sectional view of an exemplary semiconductor structure after each stage of the manufacturing process.

[0032] Figure 4 This is a flowchart of an exemplary process for forming a semiconductor structure.

[0033] Figure 5A block diagram of an exemplary system having one or more semiconductor devices is shown.

[0034] Similar reference numerals and names in the accompanying figures denote similar elements. It should also be understood that the various exemplary embodiments shown in the figures are merely illustrative and not necessarily drawn to scale. Detailed Implementation

[0035] Figure 1A-1B An exemplary 3D semiconductor structure 100 is shown, wherein Figure 1A This is a top view of an exemplary 3D semiconductor structure 100, and Figure 1B Depicting along Figure 1A The diagram shows a cross-sectional view of an exemplary 3D semiconductor structure 100 with cut lines AA' and BB'. The 3D semiconductor structure 100 can be used to manufacture memory devices, such as 3D NAND memory devices.

[0036] In some implementations, such as Figure 1A As shown, the semiconductor structure 100 includes one or more array regions (e.g., array region 100A, array region 100C) and a connection region 100B configured to provide conductive connections to the one or more array regions, for example, coupling the array regions to control circuitry. In some examples, the semiconductor structure 100 includes two array regions 100A, 100C, wherein the connection region 100B is located between the two array regions along a first horizontal direction (e.g., the X direction). Each array region 100A, 100C includes an array of channel structures 140. The channel structures 140 can be used to form a string of memory cells, which can be coupled in series along a vertical direction (e.g., the Z direction) perpendicular to the first horizontal direction. Each memory cell can include at least one vertical transistor. The vertical transistors of the memory cells can be stacked together along a second direction.

[0037] In some implementations, such as Figure 1B As shown, the semiconductor structure 100 includes a substrate 110 and a stack 130 of alternating conductive layers 130A and insulating layers 130B provided over the substrate 110. The substrate 110 can be any suitable semiconductor substrate having any suitable semiconductor material such as a single-crystal semiconductor, polycrystalline semiconductor, or monocrystalline semiconductor. For example, the substrate 110 can include silicon, silicon-germanium (SiGe), germanium (Ge), gallium arsenide (GaAs), silicon-on-insulator (SOI), germanium-on-insulator (GOI), gallium nitride, silicon carbide, III-V compounds, or any combination thereof. A contact structure 160 can be formed within the connection region 100B. The contact structure 160 can be configured to connect a corresponding conductive layer from the conductive layers within the array region 100A and / or array region 100C to, for example, a control circuit.

[0038] The stack 130 can extend in a second horizontal direction (e.g., the Y direction) parallel to the top surface of the substrate 110 and perpendicular to the first horizontal direction. The conductive layer 130A and the insulating layer 130B can alternate in a vertical direction (e.g., the Z direction) perpendicular to the second horizontal direction. The conductive layers 130A can be the same or different in thickness, for example, their thickness is in the range of 10-500 nm, such as about 35 nm. The insulating layers 130B can also be the same or different in thickness, for example, their thickness is in the range of 10-500 nm, such as about 25 nm. It should be noted that... Figure 1B The number of conductive layers 130A and isolation layers 130B shown is for illustrative purposes only, and any suitable number of conductive layers 130A and isolation layers 130B may be included in the stack 130 of the semiconductor structure 100. Conductive layer 130A may comprise any suitable conductive material, such as tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), titanium nitride (TiN), polysilicon, doped silicon, silicide, or any combination thereof. Isolation layer 130B may comprise a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In some embodiments, isolation layer 130B may also comprise a high-k dielectric material, such as hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, lanthanum oxide, or any combination thereof.

[0039] One or more channel structures can be formed in the stack 130, extending through the conductive layer 130A and the insulating layer 130B into the substrate 110. For example, such as Figure 1BAs shown, a first channel structure 140 is formed within an array region 100A, and a second channel structure 141 is formed within a connection region 100B. In some examples, each of the first channel structure 140 and the second channel structure 141 may have a cylindrical or columnar shape and may include a high-k layer extending through the conductive layer 130A and the insulating layer 130B of the stack 130, a barrier layer surrounded by the high-k layer, a charge trapping layer (or storage layer) surrounded by the barrier layer, a tunneling layer surrounded by the charge trapping layer, a channel layer surrounded by the tunneling layer, and a core filler layer surrounded by the channel layer, and also includes a channel contact portion (not shown) formed on the core filler layer and in contact with the channel layer. In some embodiments, the channel layer may include silicon, such as amorphous silicon, polycrystalline silicon, or monocrystalline silicon; the tunneling layer may include silicon oxide, silicon nitride, or any combination thereof; the barrier layer may include silicon oxide, silicon nitride, a high-k dielectric, or any combination thereof; and the charge trapping layer may include silicon nitride, silicon oxynitride, silicon, or any combination thereof. In some embodiments, the tunneling layer, charge trapping layer, and barrier layer, collectively referred to as the storage film, may include an ONO dielectric (silicon oxide-silicon nitride-silicon oxide).

[0040] Each of the first channel structure 140 and the second channel structure 141 can be formed as follows: a sacrificial layer through the stack 130 and an isolation layer 130B of the stack 130 are then formed down to one or more channel openings (not shown) in the substrate 110 by a combination of photolithography and etching processes; and a high-k layer, a barrier layer, a charge trapping layer, a tunneling layer, a channel layer, a core filler layer, and a channel contact can then be formed within the channel openings. In some embodiments, the sacrificial layer of the stack 130 within the array region 100A can be replaced with a conductive material (e.g., tungsten (W)) to form a conductive layer 130A of the 3D semiconductor structure 100. The conductive layer 130A can be used to form a stack of transistors for memory cells, which can form vertical strings of memory cells along the first channel structure 140. The first channel structure 140 can be connected to one or more metal layers (not shown) formed on the stack 130. In some embodiments, the second channel structure 141 is a dummy channel structure and is used to support the conductive layer 130A and the insulating layer 130B of the stack 130 within the connection region 100B, and therefore no metal layer is connected to the second channel structure 141.

[0041] One or more first slot structures 150A may be formed along a first horizontal direction (e.g., the X direction) within the stack 130 of the array region 100A to divide the semiconductor structure 100 into multiple semiconductor blocks. Similarly, one or more second slot structures 150B may be formed along the first horizontal direction in the connection region 100B to divide the semiconductor structure 100 into multiple semiconductor blocks. The corresponding first slot structures 150A and second slot structures 150B may be coupled to each other along the first horizontal direction, for example, as shown in the figure. Figure 1A As shown. In some embodiments, along the second horizontal direction (e.g., Figure 1A (As shown in the Y direction), the width of the first slot structure 150A is smaller than the width of the second slot structure 150B. For example, the width of the second slot structure 150B can be approximately 1.5 to 2 times the width of the first slot structure 150A. Each of one or more first slot structures 150A and / or one or more second slot structures 150B can extend through the stack 130 in a vertical direction (e.g., the Z direction) perpendicular to the first and second horizontal directions, for example, as shown in the Y direction. Figure 1B As shown.

[0042] In some embodiments, a tetraethyl orthosilicate (TEOS) hard mask (not shown) can be deposited over the stack 130 in a deposition process (e.g., chemical vapor deposition (CVD) process). A photoresist layer (not shown) can be applied over the TEOS hard mask and patterned corresponding to the trench locations within the stack 130. The stack 130 along with the TEOS hard mask formed thereon can then be etched, thereby forming trench structures within the stack 130 to expose the substrate 110, and exposing the lateral sides of the sacrificial layer and the isolation layer 130B of the stack 130. The trench structures can then be filled with a trench filler material 151 (e.g., polysilicon) to form a first slot structure 150A and / or a second slot structure 150B.

[0043] One or more contact structures 160 may be formed within the connection region 100B to connect the conductive layer 130A of the 3D semiconductor structure 100. In some embodiments, the connection region 100B includes a top end and a bottom end opposite each other in the Z direction, and each of the one or more contact structures 160 is outwardly coupled to a conductive contact at the top or bottom end. In some embodiments, a contact structure opening 161 may be formed extending from the uppermost isolation layer 130B of the isolation layers 130B into a portion of the stack 130 (which may include one or more conductive layers 130A and / or one or more isolation layers 130B) to reach a corresponding (or target) conductive layer 130A of the conductive layers 130A, thereby exposing the lateral side of that portion of the stack 130. Spacers 162 may be formed to cover the lateral side of that portion of the stack 130 and the top surface of the corresponding conductive layer 130A. The spacers 162 covering the top surface of the desired conductive layer 130A may then be removed, for example, by etching. A filler material (e.g., oxide) 160a and a conductive material 160b (e.g., metal) can be sequentially deposited through the contact structure opening 161 to form the contact structure 160.

[0044] The 3D semiconductor structure 100 may include an insulating layer 163 deposited on top of a stack 130. The insulating layer 163 is closer to the end of the second slot structure 150B along the Z-direction than the stack 130. The insulating layer 163 may include a top surface 163A and a bottom surface 163B along the Z-direction. The top surface 163A is closer to the end of the second slot structure 150B along the Z-direction than the bottom surface 163B. In some cases, ions (e.g., such as bonding elements) may be implanted from the top surface 163A of the insulating layer 163 during the fabrication process of the second slot structure 150B. Figures 3A-3D (As described in more detail). As a result, insulating layer 163 may include ions distributed in the insulating material of insulating layer 163. In some cases, the ions include at least one of nitrogen, argon, carbon, or boron. In some examples, the ion concentration in the insulating material of insulating layer 163 is about 10. -14 cm 3 In some embodiments, since the ions are injected from the top surface 163A of the insulating layer 163, the ion concentration may decrease along the Z direction from the top surface 163A to the bottom surface 163B. In other words, the concentration of ions adjacent to the top surface 163A may be higher than the concentration of ions adjacent to the bottom surface 163B.

[0045] In some embodiments, the semiconductor structure 100 includes one or more top selected gates (TSGs) 164. The semiconductor structure 100 can be formed using the following steps: A stack of alternating dielectric layers 130C and isolation layers 130B is formed. After forming the stack of alternating dielectric layers 130C and isolation layers 130B, an insulating layer (e.g., polysilicon) 163 can be formed over the stack. A first portion of the insulating layer 163 in the connection region 100B is etched away, while a second portion of the insulating layer 163 in the array region 100A is retained. Then, one or more TSGs 164 are formed in the array region 100A based on the second portion of the insulating layer 163 in the array region 100A. Subsequently, a dielectric material 165 is deposited on top of the etched insulating layer 163. Figure 1B As shown, since the first part of the insulating layer 163 is etched away, the layer thickness of the dielectric material 165 in the connection region 100B is greater than the layer thickness of the dielectric material 165 above the TSG 164 in the array region 100A.

[0046] In some embodiments, the semiconductor structure 100 can be used to form a memory device through one or more additional processing steps. For example, on a first side of the semiconductor structure 100, the substrate 110 can be thinned or removed to expose, for example, conductive material (e.g., polysilicon or metal) in a channel structure (e.g., channel structure 140) and / or a slot structure (e.g., slot structures 150A and 150B). A conductive material (e.g., metal) can be deposited on the exposed conductive material to form a common source layer, wherein the memory cell string and / or the slot structure can be electrically coupled to the common source layer. On a second side of the semiconductor structure 100 opposite to the first side, the semiconductor structure 100 can be integrated with a control structure (e.g., a CMOS wafer or die) including control circuitry. For example, the surface of the second side of the semiconductor structure 100 can be bonded to the surface of the control circuitry of the control structure.

[0047] Figures 2A-2E The diagram shows a cross-sectional view of an exemplary semiconductor structure after each stage of the manufacturing process. This semiconductor structure can be used with... Figure 1A-1B The 3D semiconductor structure 100 or a portion thereof is similar to or identical to the 3D semiconductor structure 100. Figures 2A-2E Is with Figure 1B Having similar or identical perspectives (e.g., along) Figure 1A The cross-sectional view of the cutting lines AA′ and BB′ shown.

[0048] Figure 2AThe diagram illustrates a structure 200a following the first stage of forming the semiconductor structure. The first stage includes, for example, providing a semiconductor structure including a first region 201 and a second region 202, and depositing a protective layer 207 on the semiconductor structure. In some embodiments, the first region 201 includes a first trench structure 203, and the second region includes a second trench structure 204. In some cases, the first region 201 includes an array region (e.g., corresponding to...). Figure 1A-1B The array region 100A or 100C), and the first trench structure 203 is in the array region. In some cases, the second region 202 includes a connection region (e.g., corresponding to...). Figure 1A-1B The first groove structure 203 can be used to form a slot structure in the first region 201 (e.g., the connection region 100B), and the second groove structure 204 is in the connection region. Figure 1A-1B The first slot structure 150A). The second groove structure 204 can be used to form the slot structure in the second region 202 (e.g., the first slot structure 150A). Figure 1A-1B The second gap structure 150B).

[0049] In some examples, the second region 202 is adjacent to the first region 201 along a first horizontal direction perpendicular to the vertical direction (e.g., the X direction). In some cases, the first trench structure 203 is coupled (e.g., contacted, connected, etc.) to the second trench structure 204. In some cases, along a second horizontal direction (e.g., the Y direction), the first trench structure 203 has a width smaller than that of the second trench structure 204. In some examples, the width of the second trench structure 204 is 1.5 to 2 times larger than the width of the first trench structure.

[0050] In some embodiments, sacrificial material is deposited over the first trench structure 203 before the protective layer 207 is deposited to fill the first trench structure 203 with sacrificial material, thereby forming a first sacrificial film 205A and filled sacrificial material 205B in the first trench structure 203. The first sacrificial film 205A may cover the filled sacrificial material 205B, and thereby cover the first trench structure 203. Air gaps 205c may be formed in the filled sacrificial material 205B inside the first trench structure 203. Furthermore, sacrificial material is deposited over the second trench structure 204 to form a second sacrificial film 206, the second sacrificial film 206 having a first portion 206A located on the top surface of the second region 202, a second portion 206B located on the inner surface of the second trench structure 204, and a third portion 206C located at the bottom of the second trench structure 204. From the opening of the second trench structure 204 to the bottom of the second trench structure 204 along the vertical direction (e.g., Figure 1BA second sacrificial film 206 is formed on the surface of the second trench structure 204 (shown in the Z direction). The sacrificial material may include any suitable sacrificial material, such as oxide, carbon, polysilicon, or combinations thereof. The first sacrificial film 205A may be coupled (e.g., contact, connect, etc.) to the second sacrificial film 206. It should be noted that the widths of the second trench structure 204 and the first trench structure 203 are configured such that the sacrificial material can fill the openings of the first trench structure 203 to form the filled sacrificial material 205B, but cannot cover the openings of the second trench structure 204.

[0051] As described above, a protective layer 207 can be deposited on structure 200a. The protective layer 207 can be formed on the first sacrificial membrane 205A. Furthermore, the protective layer 207 can be formed on a first portion 206A of the second sacrificial membrane 206, while the opening of the second trench structure 204 remains open. For example, in some cases, the protective layer 207 does not cover the second portion 206B and / or the third portion 206C of the second sacrificial membrane 206. The protective layer 207 may comprise one or more materials, such as organotitanium.

[0052] Structure 200a may include a stack 208 of alternating sacrificial layers 208A and insulating layers 208B. As described below, the stack 208 can be used to form a stack of alternating conductive and insulating layers, for example... Figure 1B The stack 130. The sacrificial layer 208A may include a sacrificial material. The sacrificial material may include an insulating material (e.g., silicon dioxide, silicon nitride, carbon), a semiconductor material (e.g., silicon, gallium arsenide) or other materials.

[0053] In some embodiments, one or more first channel structures 220 penetrating the stack 208 are formed in the first region 201 (e.g., Figure 1A-1B The first channel structure 140). One or more second channel structures 222 penetrating the stack 208 are formed in the second region 202 (e.g., Figure 1A-1B The second channel structure 141). An insulating layer 213 may be formed on the top of the stack 208 (e.g., Figure 1B Insulation layer 163).

[0054] Figure 2BStructure 200b following the second stage of semiconductor structure formation is shown. The second stage includes, for example, etching away a second portion 206B of the second sacrificial film 206 from the inner surface of the second trench structure 204, while at least a portion of the first sacrificial film 205A remains to cover the first trench structure 203. A protective layer 207 can be configured to prevent material beneath the protective layer 207 from being etched (e.g., by preventing the material beneath the protective layer 207 from contacting the etchant). Therefore, depositing the protective layer 207 over a selective region allows for selective material removal, i.e., removal of material not covered by the protective layer 207, while largely retaining the material beneath the protective layer 207. In this case, the protective layer 207 covers the first sacrificial film 205A and the first portion 206A of the second sacrificial film 206, while the protective layer 207 does not cover the second portion 206B and the third portion 206C of the second sacrificial film 206. As a result, the second portion 206B of the second sacrificial film 206 can be etched away, while the first sacrificial film 205A can remain to cover the first trench structure 203. In some cases, for example, tetramethylammonium hydroxide (TMAH) can be used to etch the second portion 206B of the second sacrificial film 206.

[0055] Figure 2C The structure 200c after the third stage of forming the semiconductor structure is shown. The third stage includes, for example, removing the protective layer 207. For example, the protective layer 207 can be removed using an ashing method or other suitable material removal process.

[0056] Figure 2D The structure 200d after the fourth stage of forming the semiconductor structure is shown. The fourth stage includes, for example, removing a third portion 206C of the second sacrificial film 206 located at the bottom of the second trench structure 204. The third portion 206C of the second sacrificial film 206 can be etched away using, for example, TMAH.

[0057] Figure 2E Structure 200e is shown after the fifth stage of forming the semiconductor structure. The fifth stage includes, for example, removing the sacrificial material of the sacrificial layer 208A of the stack 208 in the second region 202. In some cases, the sacrificial material can be removed using a material removal process (e.g., wet processing, ashing, or other suitable methods). For example, the sacrificial material in the sacrificial layer 208A can be removed through an opening in the second trench structure 204 (e.g., by dripping etchant into the second trench structure 204 through an opening in the second trench structure 204). Removing the sacrificial material can create cavities (or recesses) in the sacrificial layer 208A. The cavities can then be filled with a conductive material (e.g., tungsten) to form a conductive layer (e.g., Figure 1BThe conductive layer 130A shown herein generates a stack of alternating conductive and insulating layers (e.g., Figure 1B (The stack 130). In some examples, portions of the sacrificial material are not removed to provide support for the structure 200e during one or more subsequent manufacturing process steps.

[0058] Figures 3A-3D The diagram shows a cross-sectional view of an exemplary semiconductor structure after each stage of the manufacturing process. This semiconductor structure can be used with... Figure 1A-1B The 3D semiconductor structure 100 or a portion thereof is similar to or identical to the 3D semiconductor structure 100. Figures 3A-3D Is with Figure 1B Having similar or identical perspectives (e.g., along) Figure 1A The cross-sectional view of cutting lines AA' and BB' is shown. In some cases, combined with... Figures 3A-3D The manufacturing process and combination described Figure 2A-2B The manufacturing processes described are two different manufacturing processes used to create similar semiconductor structures.

[0059] Figure 3A Structure 300a is shown after the first stage of forming the semiconductor structure. In some cases, structure 300a does not include... Figure 2A The structure 200a includes a protective layer 207. The first stage includes, for example, providing a semiconductor structure including a first region 301 and a second region 302. In some embodiments, the first region 301 includes a first trench structure 303 (e.g., Figure 2A The first trench structure 203), and the second region 302 includes a second trench structure 304 (e.g., Figure 2A The second trench structure 204). In some cases, the first region 301 includes an array region (e.g., corresponding to the array region). Figure 1A-1B The array region 100A or 100C is included, and the first trench structure 303 is located within the array region. In some cases, the second region 302 includes a connection region (e.g., corresponding to...). Figure 1A-1B The first groove structure 303 can be used to form a slot structure in the first region 301 (e.g., the connection region 100B), and the second groove structure 304 is in the connection region. Figure 1A-1B The first slot structure 150A). The second groove structure 304 can be used to form the slot structure in the second region 302 (e.g., Figure 1A-1B The second gap structure 150B).

[0060] In some examples, the second region 302 is adjacent to the first region 301 along a first horizontal direction perpendicular to the vertical direction (e.g., the X direction). In some cases, the first trench structure 303 is coupled (e.g., contacted, connected, etc.) to the second trench structure 304. In some cases, along a second horizontal direction (e.g., the Y direction), the first trench structure 303 has a width smaller than that of the second trench structure 304. In some examples, the width of the second trench structure 304 is 1.5 to 2 times larger than the width of the first trench structure.

[0061] In some embodiments, a sacrificial material is deposited over the first trench structure 303 to fill the first trench structure 303 with sacrificial material, thereby forming a first sacrificial film 305A and filled sacrificial material 305B in the first trench structure 303. The first sacrificial film 305A may cover the filled sacrificial material 305B, and thereby cover the first trench structure 303. An air gap 305c may be formed in the filled sacrificial material 305B inside the first trench structure 303. Furthermore, sacrificial material is deposited over the second trench structure 304 to form a second sacrificial film 306, the second sacrificial film 306 having a first portion 306A located on the top surface of the second region 302, and a second portion 306B located on the inner surface (including the bottom) of the second trench structure 304. From the opening of the second trench structure 304 to the bottom of the second trench structure 304 along the vertical direction (e.g., Figure 1B A second sacrificial film 306 is formed on the surface of the second trench structure 304 (shown in the Z direction). The sacrificial material may include any suitable sacrificial material, such as oxide, carbon, polysilicon, or combinations thereof. The first sacrificial film 305A may be coupled (e.g., contact, connect, etc.) to the second sacrificial film 306. It should be noted that the widths of the second trench structure 304 and the first trench structure 303 are configured such that the sacrificial material can fill the openings of the first trench structure 303 to form the filled sacrificial material 305B, but cannot cover the openings of the second trench structure 304.

[0062] Structure 300a may include a stack 308 of alternating sacrificial layers 308A and insulating layers 308B. As described below, the stack 308 can be used to form a stack of alternating conductive and insulating layers, for example... Figure 1B The stack 130. The sacrificial layer 308A may include a sacrificial material. The sacrificial material may include an insulating material (e.g., silicon dioxide, silicon nitride, or carbon), a semiconductor material (e.g., silicon or gallium arsenide), or other materials. In some embodiments, an insulating layer 313 may be formed on top of the stack 308 (e.g., ...). Figure 1B Insulation layer 163).

[0063] Figure 3BStructure 300b is shown after the second stage of forming the semiconductor structure. The second stage includes, for example, altering at least one characteristic of a sacrificial material region. The sacrificial material region may include at least one of, for example, a first portion 306A of a first sacrificial film 305A or a first portion 306A of a second sacrificial film 306. In some cases, altering at least one characteristic of the region of the sacrificial material includes implanting ions into the region of the sacrificial material to change the etch rate of the region of the sacrificial material. In some embodiments, the first etch rate of the sacrificial material with implanted ions is less than the second etch rate of the sacrificial material without implanted ions. In some examples, the ratio of the first etch rate to the second etch rate is approximately 1 / 8. The etch rate can determine the rate at which material is removed during the etching process. For example, a higher etch rate can correspond to a higher etch speed, and a lower etch rate can correspond to a lower etch speed. Therefore, implanted ions in a selective region can be used to selectively remove material, i.e., remove material without implanted ions while largely retaining material with implanted ions.

[0064] In some embodiments, implanting ions into the region of the sacrificial material includes controlling at least one of ion implantation power, ion implantation angle, or ion implantation density to implant ions into the region of the sacrificial material. In some examples, controlling at least one of ion implantation power, ion implantation angle, or ion implantation density to implant ions into the region of the sacrificial material includes controlling the implantation of ions into the region of the sacrificial material without implanting ions into the filled sacrificial material 305B or the second portion 306B of the second sacrificial film. By doing so, the etching rate of the region of the sacrificial material with implanted ions can be different from (e.g., lower than) the etching rate of the sacrificial material in the filled sacrificial material 305B or the second portion 306B of the second sacrificial film 306. By controlling the etching rate in different regions, one or more materials can be removed while other materials are protected from removal. For example, if the etching rate of the region of the sacrificial material with implanted ions is lower than the etching rate of the sacrificial material in the second portion 306B of the second sacrificial film 306, then at least a portion of the region of the sacrificial material with implanted ions can be retained during the etching process, while the sacrificial material in the second portion 306B of the second sacrificial film 306 can be (e.g., completely) removed.

[0065] The sacrificial material and ions can include any suitable material and / or element. In some examples, the sacrificial material includes at least one of polycrystalline silicon or alumina, and the ions include at least one of nitrogen, argon, carbon, or boron. For example, if the sacrificial material includes polycrystalline silicon, ions can be implanted into a region of the sacrificial material to convert the polycrystalline silicon in that region of the sacrificial material into non-polycrystalline silicon, thereby altering the etch rate of that region of the sacrificial material, wherein the region of the sacrificial material includes a first portion 306A of the second sacrificial film 306 located on the top surface of the second region 302. In some other examples, the sacrificial material includes silicon nitride, and the ions can include nitrogen.

[0066] Figure 3C The structure 300c after the third stage of forming the semiconductor structure is shown. The third stage includes, for example, etching away a second portion 306B of the second sacrificial film 306 from the inner surface of the second trench structure 304, while at least a portion of the first sacrificial film 305A remains to cover the first trench structure 303. As described above, this can be achieved because the second portion 306B of the second sacrificial film 306 has a higher etching rate than the first sacrificial film 305A. In some cases, the first portion 306A of the second sacrificial film 306 can be implanted with ions, thereby allowing at least a portion of the first portion 306A of the second sacrificial film 306 to remain when the second portion 306B of the second sacrificial film 306 is etched away.

[0067] Figure 3D The structure 300d after the fourth stage of forming the semiconductor structure is shown. The fourth stage includes, for example, removing the sacrificial material of the sacrificial layer 308A in the second region 302, for example, similar to... Figure 2E The fifth stage. In some cases, the sacrificial material can be removed using a material removal process (e.g., wet process, ashing method, or other suitable method). For example, the sacrificial material in the sacrificial layer 308A can be removed through the openings in the second trench structure 304 (e.g., etchant can be dropped into the second trench structure 304 through the openings in the second trench structure 304). Removing the sacrificial material can create a cavity in the sacrificial layer 308A. The cavity can then be filled with a conductive material (e.g., tungsten) to form a conductive layer (e.g., tungsten). Figure 1B The conductive layer 130A shown herein generates a stack of alternating conductive and insulating layers (e.g., Figure 1B (The stack 130). In some examples, a portion of the sacrificial material is not removed to provide support for the semiconductor structure 300d during the manufacturing process.

[0068] Figure 4 This is a flowchart of an exemplary process 400 for forming a semiconductor structure. This semiconductor structure can be used with… Figure 1A-1B The semiconductor structure 100 or a portion thereof is similar to or identical to the semiconductor structure 100. This can be considered. Figure 1A-1B To describe process 400. Process 400 may include Figures 2A-2E or Figures 3A-3D The manufacturing process that forms a semiconductor structure. Process 400 includes steps that can be performed in any suitable order and / or any combination.

[0069] In step 410, a semiconductor structure including a first region and a second region is provided. The first region (e.g., Figure 2A First area 201 or Figure 3A The first region 301) may include a first trench structure (e.g., Figure 2A The first trench structure 203 or Figure 3A The first trench structure 303), and the second region (e.g., Figure 2A Second area 202 or Figure 3A The second region 302) may include a second trench structure (e.g., Figure 2A The second trench structure 204 or Figure 3A The second trench structure 304). The semiconductor structure may include a first sacrificial film covering the first trench structure (e.g., Figure 2A Sacrificial membrane 205A or Figure 3A 305A), and a second sacrificial film (e.g., formed on the surface of the second trench structure along a first direction (e.g., the Z direction) from the opening of the second trench structure to the bottom of the second trench structure. Figure 2A The sacrificial membrane 206 or Figure 3A (306). In some cases, the first region includes an array region and the second region includes a connection region. The first trench structure is in the array region and the second trench structure is in the connection region. In some embodiments, the first trench structure is coupled to the second trench structure, and the first sacrificial membrane is coupled to the second sacrificial membrane. In some examples, the first trench structure has a width smaller than that of the second trench structure along a second direction perpendicular to the first direction (e.g., the Y direction).

[0070] In some implementations, exemplary process 400 includes depositing sacrificial material over a first trench structure and a second trench structure to fill the sacrificial material in the first trench structure and form a cover over the filled sacrificial material in the first trench structure (e.g., Figure 2A 205B or Figure 3A The first sacrificial film (of type 305B) is formed, and a second sacrificial film is formed, the second sacrificial film having a first portion (e.g., on the top surface of the second region) located thereon. Figure 2A 206A or Figure 3A 306A) and the second portion (e.g., located on the inner surface of the second trench structure) Figure 2A 206B or Figure 3A (306B), for example, such as Figure 2A or Figure 3A As shown.

[0071] In some embodiments, exemplary process 400 includes altering at least one characteristic of a region of the sacrificial material, wherein said region of the sacrificial material includes a first sacrificial membrane (e.g., Figure 3A 305A) or the first part of the second sacrificial membrane (e.g., Figure 3A At least one of (306A), for example, such as Figure 3A As shown. In some examples, altering at least one characteristic of the region of the sacrificial material includes implanting ions into the region of the sacrificial material to change the etching rate of the region of the sacrificial material. In some examples, implanting ions into the region of the sacrificial material includes controlling at least one of ion implantation power, ion implantation angle, or ion implantation density to implant ions into the region of the sacrificial material. In some cases, controlling at least one of ion implantation power, ion implantation angle, or ion implantation density to implant ions into the region of the sacrificial material includes controlling the implantation of ions into the region of the sacrificial material without implanting ions into the first trench structure and the second portion of the second sacrificial film.

[0072] In some examples, the ratio of the etching rate of the region of the sacrificial material with implanted ions to the etching rate of the second portion of the second sacrificial film is approximately 1 / 8. In some embodiments, the sacrificial material comprises at least one of polycrystalline silicon or alumina, and wherein the ions comprise at least one of nitrogen, argon, carbon, or boron. In some embodiments, the sacrificial material comprises polycrystalline silicon, and the method further comprises implanting ions into the region of the sacrificial material to convert the polycrystalline silicon in the region of the sacrificial material into non-polycrystalline silicon, thereby altering the etching rate of the region of the sacrificial material, wherein the region of the sacrificial material includes a first portion of the second sacrificial film located on the top surface of the second region. In some embodiments, the sacrificial material comprises silicon nitride, and wherein the ions comprise nitrogen.

[0073] In some cases, prior to etching the second portion of the second sacrificial film, process 400 includes depositing a protective layer on the semiconductor structure, wherein the protective layer is formed on the first sacrificial film, and the opening of the second trench structure remains open, wherein the protective layer is located on the first portion of the second sacrificial film, for example, as... Figure 2A As shown. In some embodiments, the protective layer comprises organic titanium. In some examples, exemplary process 400 includes removing the protective layer from the semiconductor structure after etching a second portion of the second sacrificial film.

[0074] In step 420, at least a portion of the second sacrificial film is etched, while at least a portion of the first sacrificial film remains to cover the first trench structure. In some cases, the second sacrificial film includes a first portion located on the top surface of the second region and a second portion located on the inner surface of the second trench structure, and etching at least a portion of the second sacrificial film includes etching away the second portion of the second sacrificial film from the inner surface of the second trench structure, for example, as... Figure 2B or Figure 3B As shown. In some cases, the second region includes multiple alternating sacrificial layers and insulating layers, and the exemplary process 400 may further include: after etching at least a portion of the second sacrificial film, removing the sacrificial layers in the second region through openings in the second trench structure, for example, as Figure 2E or Figure 3D As shown.

[0075] Figure 5 A block diagram of a system 500 having one or more semiconductor devices (e.g., memory devices) according to one or more embodiments of the present disclosure is shown. System 500 may be a mobile phone, desktop computer, laptop computer, tablet computer, in-vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage components located therein. Figure 5 As shown, system 500 may include a host device 508 and a memory system 502, the memory system 502 having one or more 3D memory devices 504 and a memory controller 506. The host device 508 may include a processor of an electronic device, such as a central processing unit (CPU), or may include a system-on-a-chip (SoC), such as an application processor (AP). The host device 508 may be configured to send data to or receive data from the one or more 3D memory devices 504.

[0076] 3D memory device 504 can be any 3D memory device disclosed herein, for example, Figure 1A-1B The 3D memory device shown is based on Figures 2A-2E 3D memory devices based on semiconductor structures 200a-200e, or... Figures 3A-3DA 3D memory device with semiconductor structures 300a-300d is described. In some embodiments, the 3D memory device 504 includes NAND flash memory. A memory controller 506 (also known as controller circuitry) is coupled to the 3D memory device 504 and a host device 508. According to embodiments of this disclosure, the 3D memory device 504 may include a plurality of conductive interconnects passing through a cover layer, the conductive interconnects contacting conductive pads in a conductive pad layer, and the memory controller 506 may be coupled to the 3D memory device 504 through at least one of the plurality of conductive interconnects. The memory controller 506 is configured to control the 3D memory device 504. For example, the memory controller 506 may be configured to operate a plurality of channel structures via word lines. The memory controller 506 may manage data stored in the 3D memory device 504 and communicate with the host device 508.

[0077] In some embodiments, the memory controller 506 is designed / configured to operate in a low duty cycle environment, such as a Secure Digital (SD) card, Compact Flash (CF) card, Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, and mobile phones. In some embodiments, the memory controller 506 is designed / configured to operate in a high duty cycle environment, such as an enterprise storage array, and an SSD or embedded multimedia card (eMMC) used as a data storage component in mobile devices such as smartphones, tablets, and laptops. The memory controller 506 may be configured to control the operation of the 3D memory device 504, such as read, erase, and program (or write) operations. The memory controller 506 may also be configured to manage various functions related to data stored in or to be stored in the 3D memory device 504, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 506 is further configured to process error correction codes (ECCs) relating to data read from or written to the 3D memory device 504. The memory controller 506 may also perform any other suitable functions, such as formatting the 3D memory device 504.

[0078] The memory controller 506 can communicate with external devices (e.g., host device 508) according to a specific communication protocol. For example, the memory controller 506 can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, High Speed ​​PCI (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, Firewire protocol, etc.

[0079] The memory controller 506 and one or more 3D memory devices 504 can be integrated into various types of memory devices, for example, contained within the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 502 can be implemented and packaged into different types of end electronic products. Figure 5 In one example shown, the memory controller 506 and the 3D memory device 504 can be integrated into the memory system 502. The memory system 502 may include PC cards (PCMCIA, Personal Computer Memory Card International Association), CF cards, Smart Media (SM) cards, memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), UFS, etc.

[0080] The embodiments, actions, and operations of the subject matter described in this disclosure can be implemented in digital electronic circuit systems, in computer software or firmware tangibly embodied, in computer hardware (including the structures disclosed in this disclosure and their equivalents), or in one or more combinations of the foregoing options. Embodiments of the subject matter described in this disclosure can be implemented as one or more computer programs, for example, one or more modules of computer program instructions encoded on a computer program carrier, for execution by a data processing device or to control the operation of the data processing device. The carrier can be a tangible, non-transitory computer storage medium. Alternatively or additionally, the carrier can be an artificially generated propagation signal, such as a machine-generated electrical signal, optical signal, or electromagnetic signal, generated to encode information for transmission to a suitable receiving device for execution by the data processing device. The computer storage medium can be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, or a combination thereof, or can be part of a combination of a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, or a combination thereof. The computer storage medium is not a propagation signal.

[0081] It should be noted that in this disclosure, references to "an embodiment," "an embodiment," "an exemplary embodiment," "some implementations," and "implementation" indicate that the described embodiment may include a specific feature, structure, or characteristic, but not every embodiment may include that specific feature, structure, or characteristic. Furthermore, such wording does not necessarily refer to the same embodiment. Moreover, when describing a specific feature, structure, or characteristic in conjunction with embodiments, implementing such a feature, structure, or characteristic in conjunction with other implementations, whether explicitly described or not, will be within the knowledge scope of those skilled in the art.

[0082] Generally, terms can be understood at least partly from their usage in context. For example, at least partly depending on the context, the word "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or a combination of features, structures, or characteristics in a plural sense. Similarly, at least partly depending on the context, words such as "a," "a kind," or "described" can also be understood to express either a singular or a plural usage. Furthermore, the word "based on" can be understood not necessarily to express an exclusive set of factors, and instead, may allow for additional factors that are not necessarily explicitly described, again at least partly depending on the context.

[0083] It should be readily understood that the meanings of "on," "above," and "above" in this disclosure should be interpreted in the broadest possible sense, such that "on" means not only directly situated on something, but also includes the meaning of being situated on something with an intermediate feature or layer in between. Furthermore, "above" or "above" means not only situated on or above something, but also includes the meaning of being situated on or above something without any intermediate feature or layer in between (i.e., directly situated on something).

[0084] Furthermore, for ease of explanation, spatially relative terms (e.g., "below," "under," "down," "above," "up," etc.) may be used herein to describe the relationship of an element or feature to one or more other elements or features as shown in the figures. Spatially relative terms are intended to cover different orientations of the apparatus during use or process steps, other than those shown in the figures. The apparatus can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0085] As used herein, the term "substrate" refers to the material on which subsequent layers of material are added. The substrate includes a "top" surface and a "bottom" surface. The top surface of the substrate is typically where semiconductor devices are formed, and therefore, unless otherwise specified, semiconductor devices are formed on the top side of the substrate. The bottom surface is opposite to the top surface, and therefore the bottom side of the substrate is opposite to the top side. The substrate itself can be patterned. The material added on top of the substrate can be patterned or can remain unpatterned. Furthermore, the substrate can comprise a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0086] As used herein, the term "layer" refers to a portion of material comprising a region of thickness. A layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate, while the top side is relatively distant from the substrate. A layer may extend over the entire lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure, with a thickness less than that of the continuous structure. For example, a layer may be located between any set of horizontal planes between, or at, the top and bottom surfaces of the continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, may contain one or more layers therein, and / or may have one or more layers located on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductive and contact layers (where contacts, interconnects, and / or vertical interconnect pathways (VIAs) are formed) and one or more dielectric layers.

[0087] As used herein, the term "nominal / nominally" refers to an expected or target value of a characteristic or parameter of a component or process step set during the design phase of a product or process, together with a range of values ​​higher and / or lower than that expected value. As used herein, this range of values ​​may be attributable to slight variations in manufacturing processes or tolerances. As used herein, the term "approximately" indicates that the value of a given quantity may vary based on a specific technology node associated with the semiconductor device in question. Based on a specific technology node, the term "approximately" may indicate that the value of a given quantity varies within, for example, 10-30% of that value (e.g., ±10%, ±20%, or ±30% of that value).

[0088] In this disclosure, the terms "horizontal / horizontally / laterally" refer to a lateral surface that is nominally parallel to the substrate, and the terms "vertical" or "perpendicularly" refer to a lateral surface that is nominally perpendicular to the substrate.

[0089] As used herein, the term “3D memory” refers to a three-dimensional (3D) semiconductor device having vertically oriented strings of memory cell transistors (referred to herein as “memory strings,” e.g., NAND strings) located on a laterally oriented substrate, such that the memory strings extend vertically relative to the substrate.

[0090] This disclosure provides numerous different implementations or examples of various features for carrying out the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. These are, of course, merely examples and are not intended to constitute limitation. For example, the following description of forming a first feature above or on a second feature may include an implementation where the first and second features are in direct contact, and may also include an implementation where an additional feature may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. Such repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various implementations and / or configurations discussed.

[0091] The descriptions of the specific embodiments described above can be easily modified and / or adjusted for various applications. Therefore, based on the teachings and guidance provided herein, it is intended that such adjustments and modifications fall within the meaning and scope of equivalents of the disclosed embodiments.

[0092] Although this disclosure contains many specific implementation details, these details should not be construed as limiting the scope of the claimed protection, which is defined by the claims themselves. Rather, these details should be understood only as descriptions of features specific to particular embodiments of the invention. Certain features described in the context of multiple individual embodiments in this disclosure may also be implemented in combination in a single embodiment. Conversely, individual features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. Furthermore, while multiple features may be described above as functioning in certain combinations and even initially claimed accordingly, one or more features from the claimed combination may be removed from that combination in certain circumstances, and the claims may relate to sub-combinations or variations thereof.

[0093] Similarly, although multiple operations are depicted in a specific order in the accompanying drawings and are recited in a specific order in the claims, this should not be construed as requiring the execution of such multiple operations in the indicated specific order or sequential order, or as requiring the execution of all illustrated operations, in order to obtain the desired result. In some cases, multitasking and parallel processing may be advantageous. Furthermore, the division of various system modules and components in the embodiments described above should not be construed as requiring such division in all embodiments, and it should be understood that the described program components and systems can generally be integrated together into a single software product or packaged into multiple software products.

[0094] Specific embodiments of the subject matter have been described. Other embodiments are also within the scope of the appended claims. For example, the actions described in the claims can be performed in different orders and still achieve the desired result. As an example, the processes shown in the figures do not necessarily require a specific order or sequential sequence to achieve the desired result. In some cases, multitasking and parallel processing may be advantageous.

[0095] The breadth and scope of this disclosure should not be limited by any of the exemplary embodiments described above, but only by the appended claims and their equivalents.

Claims

1. A method for use in a semiconductor device, comprising: A semiconductor structure including a first region and a second region is provided, the first region including a first trench structure, the second region including a second trench structure, wherein the semiconductor structure includes: a first sacrificial film covering the first trench structure, and a second sacrificial film formed on the surface of the second trench structure along a first direction from the opening of the second trench structure to the bottom of the second trench structure; Modifying at least one characteristic of a region of the sacrificial material, wherein the region of the sacrificial material includes a first portion of the second sacrificial film located on the top surface of the second region or at least one of the first sacrificial films; and At least a portion of the second sacrificial film is etched, while at least a portion of the first sacrificial film remains to cover the first trench structure, such that the entire sidewall of the first trench structure is not exposed. Wherein, altering at least one characteristic of the region of the sacrificial material includes: Ions are injected into the region of the sacrificial material to change the etching rate of the region of the sacrificial material.

2. The method according to claim 1, wherein, The first trench structure is coupled to the second trench structure, and wherein the first sacrificial membrane is coupled to the second sacrificial membrane.

3. The method according to claim 1, wherein, Along a second direction perpendicular to the first direction, the first trench structure has a width smaller than that of the second trench structure.

4. The method according to claim 3, further comprising: The sacrificial material is deposited over the first trench structure and the second trench structure to fill the first trench structure with the sacrificial material and form a first sacrificial film covering the filled sacrificial material in the first trench structure, and to form a second sacrificial film, the second sacrificial film further having a second portion located on the inner surface of the second trench structure.

5. The method according to claim 1, wherein, The second sacrificial membrane further includes a second portion located on the inner surface of the second trench structure, and Etching at least one portion of the second sacrificial film includes etching away the second portion of the second sacrificial film from the inner surface of the second trench structure.

6. The method according to claim 1, wherein, Implanting the ions into the region of the sacrificial material includes: Controlling at least one of ion implantation power, ion implantation angle, or ion implantation density to implant the ions into the region of the sacrificial material.

7. The method according to claim 1, wherein, The sacrificial material includes at least one of polycrystalline silicon or alumina, and the ion includes at least one of nitrogen, argon, carbon or boron.

8. The method according to any one of claims 1 to 7, wherein, The sacrificial material includes polycrystalline silicon, and the method further includes: Ions are implanted into the region of the sacrificial material to convert the polycrystalline silicon in the region of the sacrificial material into non-polycrystalline silicon, thereby changing the etching rate of the region of the sacrificial material.

9. The method according to any one of claims 1 to 7, wherein, The second region comprises multiple alternating sacrificial layers and insulating layers, and The method further includes removing the sacrificial layer in the second region through the opening of the second trench structure after etching at least one portion of the second sacrificial film.

10. A semiconductor device, comprising: An array region, the array region including a first slot structure extending along a first direction; as well as A connecting region, which is adjacent to the array region along a second direction perpendicular to the first direction. The connection region includes a second slot structure that extends along the first direction through an insulating layer extending along the second direction. The insulating layer includes an insulating material and ions distributed in the insulating material within the insulating layer, wherein the ions distributed in the insulating material are configured to reduce the etching rate of the insulating material.

11. The semiconductor device of claim 10, comprising a stack of conductive layers and insulating layers alternating with each other along the first direction. in, Each of the first and second slot structures extends through the stack of the conductive and insulating layers, and Wherein, the insulating layer is closer to the end of the second slot structure than the stack of the conductive layer and the insulating layer along the first direction.

12. The semiconductor device according to claim 11, wherein, The connection region includes multiple contact structures extending through the stack of the conductive layer and the insulating layer, and Wherein, at least one of the conductive layers is coupled to a corresponding contact structure in the plurality of contact structures.

13. The semiconductor device according to claim 12, wherein, The connection region includes a first end and a second end that are opposite each other along the first direction, and Each of the plurality of contact structures is outwardly coupled to a conductive contact portion at either the first end or the second end.

14. The semiconductor device according to any one of claims 11 to 13, wherein, The array region includes multiple channel structures extending through the stack of the conductive layer and the insulating layer.

15. The semiconductor device according to any one of claims 11 to 13, wherein, The first gap structure is connected to the second gap structure along the second direction, and Wherein, along a third direction perpendicular to the first direction and the second direction, the width of the first slit structure is smaller than the width of the second slit structure.

16. The semiconductor device according to any one of claims 11 to 13, wherein, The insulating layer includes a first surface and a second surface along the first direction, the first surface being closer to the end of the second slit structure along the first direction than the second surface, and wherein a first concentration of the ions adjacent to the first surface is higher than a second concentration of the ions adjacent to the second surface of the insulating layer.

17. A method for use in a semiconductor device, comprising: A semiconductor structure is provided, comprising a first region and a second region, the first region including a first trench structure, and the second region including a second trench structure. The semiconductor structure includes: a first sacrificial film covering the first trench structure; and a second sacrificial film formed on a surface of the second trench structure from an opening to a bottom of the second trench structure. The second sacrificial film includes a first portion located on a top surface of the second region and a second portion located on an inner surface of the second trench structure. Modifying at least one characteristic of a region of the sacrificial material, wherein the region of the sacrificial material includes the first portion of the second sacrificial membrane or at least one of the first sacrificial membranes; and The second portion of the second sacrificial film is etched away from the inner surface of the second trench structure, while at least a portion of the first sacrificial film remains to cover the first trench structure, such that the entire sidewall of the first trench structure is not exposed, wherein altering at least one characteristic of the region of the sacrificial material includes: Ions are injected into the region of the sacrificial material to change the etching rate of the region of the sacrificial material.

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