Multi-step and v-groove gate-all-around gallium nitride p-channel field effect transistor and preparation method thereof

Abstract

The application provides a multi-step and V-shaped groove gate gallium nitride P-channel field effect tube and a preparation method thereof, and relates to the technical field of semiconductor devices. The application comprises, from bottom to top, a substrate layer, a buffer layer, a barrier layer, a channel layer and a cap layer; a groove extends downward from the middle region of the upper surface of the cap layer and penetrates through the cap layer into the channel layer, the shape of the groove is a multi-step groove, a V-shaped groove or an inverted trapezoidal groove; a source electrode is formed on the cap layer on one side of the groove; a drain electrode is formed on the cap layer on the other side of the groove; and a gate electrode is formed in the groove and is in contact with the channel layer. The multi-step groove gate, the V-shaped groove gate and the inverted trapezoidal groove gate can optimize the electric field distribution between the gate and the drain, relieve the local high electric field, and widen the application of the device in the high-voltage and high-power application field; on the basis of realizing the enhanced P-channel field effect tube, the output current is increased, and the performance and reliability of the P-channel field effect tube in the high-frequency and high-power application are improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and in particular to a multi-step and V-groove gate gallium nitride P-channel field-effect transistor and its fabrication method. Background Technology

[0002] Gallium nitride (GaN) possesses unique advantages such as a large bandgap, high electron drift velocity, high thermal conductivity, and resistance to high temperatures and pressures. This allows GaN-based integrated electronic devices to be radiation-resistant, heat-resistant, and characterized by high frequency, high power, and high density. GaN-based integrated electronic devices can be used to fabricate radio frequency and power devices. However, compared to GaN enhancement-mode N-channel high electron mobility transistors (HEMTs), the research and development of GaN enhancement-mode P-channel devices has been slower. This has limited the widespread application of all-gaN complementary metal-oxide-semiconductor (CMOS) technology, and the advantages of GaN devices, such as high breakdown voltage, stronger radiation resistance, and low switching losses, cannot be fully realized.

[0003] In critical fields such as power electronics and energy conversion, GaN materials, due to their excellent high breakdown voltage characteristics, have become key materials for solving device reliability issues in high-voltage, high-frequency, and high-power applications. High breakdown voltage effectively prevents premature breakdown during operation, extending device lifespan. However, traditional gallium nitride P-channel field-effect transistors (PFETs), due to their short gate-drain spacing, cause the peak electric field to concentrate near the gate region during high-voltage operation, increasing the risk of device breakdown. Furthermore, enhancement-mode devices with a single dielectric recessed gate structure have a deep recess, resulting in significant on-resistance and substantial power loss during conduction. Additionally, increased operating temperature negatively impacts performance and reliability in high-frequency, high-power applications. Summary of the Invention

[0004] The purpose of this invention is to provide a stepped and V-groove gate gallium nitride P-channel field-effect transistor and its fabrication method, which solves the problems of peak electric field concentration in the region near the gate, increasing the risk of device breakdown, and the impact of increased device operating temperature on its performance and reliability in high-frequency and high-power applications.

[0005] To address the aforementioned technical problems, the embodiments of the present invention provide the following technical solutions:

[0006] The first aspect of the present invention provides a multi-step and V-groove gate gallium nitride P-channel field-effect transistor, comprising a substrate layer, a buffer layer, a barrier layer, a channel layer and a cap layer arranged sequentially from bottom to top;

[0007] The groove extends downward from the middle area of ​​the upper surface of the cap layer and penetrates the cap layer into the channel layer. The groove can be a multi-step groove, a V-shaped groove, or an inverted trapezoidal groove.

[0008] The source electrode is formed on the cap layer on one side of the groove;

[0009] The drain electrode is formed on the cap layer on the other side of the groove;

[0010] The gate electrode is formed in the groove and contacts the channel layer. The horizontal plane of the upper surface of the gate electrode is lower than the horizontal plane of the upper surface of the channel layer.

[0011] In some modified embodiments of the first aspect of the invention, each step of the multi-step groove has the same width, and the inclination angles of the V-shaped groove and the inverted trapezoidal groove are both greater than 0° and less than 90°.

[0012] In some modified embodiments of the first aspect of the present invention, the buffer layer is made of GaN material and has a thickness of 1 to 10 μm.

[0013] In some modified embodiments of the first aspect of the present invention, the material of the barrier layer is AlGaN material, wherein the Al component in the AlGaN material is 5% to 30%, and the thickness of the barrier layer is 5 to 30 nm.

[0014] In some modified embodiments of the first aspect of the present invention, the channel layer is a p-type GaN channel layer, the doping ions of the p-type GaN channel layer are Mg ions, and the doping concentration of Mg ions in the p-type GaN channel layer is 5 × 10⁻⁶. 18 ~5×10 19 cm -3 The thickness of the p-type GaN channel layer is 50nm to 100nm.

[0015] In some modified embodiments of the first aspect of the present invention, the cap layer is a p-type heavily doped GaN channel layer, the dopant ions in the p-type heavily doped GaN channel layer are Mg ions, and the doping concentration of Mg ions in the p-type heavily doped GaN channel layer is 1×10⁻⁶. 19 ~1×10 20 cm -3 The thickness is 5nm to 30nm.

[0016] In some modified embodiments of the first aspect of the present invention, both the source electrode and the drain electrode are made of Ni / Au metal.

[0017] In some modified embodiments of the first aspect of the present invention, the material of the gate electrode is W / Au or Ti / Au metal.

[0018] A second aspect of the present invention provides a method for fabricating a multi-step, V-groove gate gallium nitride P-channel field-effect transistor, comprising:

[0019] Obtain an epitaxial wafer, which includes a substrate layer, a buffer layer, a barrier layer, a channel layer and a cap layer stacked sequentially from bottom to top;

[0020] Metal is deposited on the upper surface of the cap layer to form a source electrode and a drain electrode. The source electrode is located in one edge region of the upper surface of the cap layer, and the drain electrode is located in the other edge region of the upper surface of the cap layer.

[0021] Etch downwards from the upper surface of the cap layer outside the source and drain electrode regions, until the upper surface of the channel layer is reached;

[0022] Multiple etchings are performed from the upper surface of the channel layer downwards to form multi-step grooves, with each etching having the same width.

[0023] Metal is deposited at the bottom of a multi-step groove to form a gate electrode.

[0024] A third aspect of the present invention provides a method for fabricating a multi-step, V-groove gate gallium nitride P-channel field-effect transistor, comprising:

[0025] Obtain an epitaxial wafer, which includes a substrate layer, a buffer layer, a barrier layer, a channel layer and a cap layer stacked sequentially from bottom to top;

[0026] An SOG film is coated on the upper surface of the cap layer to form a hard mask layer, and photoresist layers are coated on both sides of the edge region of the hard mask layer.

[0027] Part of the hard mask layer is removed to form a sloped hard mask layer, and the photoresist layer is removed. The sloped hard mask layer has an angle greater than 0° and less than 90°.

[0028] Part of the hard mask layer and cap layer are etched away until they reach the channel layer, forming a V-shaped groove or an inverted trapezoidal groove.

[0029] Metal is deposited on the upper surface of the cap layer to form a source electrode and a drain electrode. The source electrode is located in one edge region of the upper surface of the cap layer, and the drain electrode is located in the other edge region of the upper surface of the cap layer.

[0030] Metal is deposited at the bottom of a V-shaped groove or an inverted trapezoidal groove to form a gate electrode.

[0031] Compared to existing technologies, the multi-step and V-groove gate gallium nitride P-channel field-effect transistor and its fabrication method provided by the present invention include a substrate layer, a buffer layer, a barrier layer, a channel layer, and a cap layer arranged sequentially from bottom to top; a groove extending downward from the middle region of the upper surface of the cap layer and penetrating the cap layer into the channel layer, the groove being a multi-step groove, a V-shaped groove, or an inverted trapezoidal groove; a source electrode formed on the cap layer on one side of the groove; a drain electrode formed on the cap layer on the other side of the groove; and a gate electrode formed in the groove and in contact with the channel layer, the horizontal plane of the upper surface of the gate electrode being lower than the horizontal plane of the upper surface of the channel layer. Thus, employing multi-step grooved gates, V-shaped grooved gates, and inverted trapezoidal grooved gates can optimize the electric field distribution between the gate and drain, alleviate local high electric fields, and broaden the application of the device in high-voltage and high-power applications. By using multi-step grooved gates, V-shaped grooved gates, and inverted trapezoidal grooved gates, the output current is increased and the on-resistance is reduced while realizing enhancement-mode P-channel MOSFETs, thereby reducing the power loss of P-channel MOSFETs in the on-state and improving the performance and reliability of P-channel MOSFETs in high-frequency and high-power applications. Attached Figure Description

[0032] The above and other objects, features, and advantages of exemplary embodiments of the present invention will become readily apparent upon reading the following detailed description with reference to the accompanying drawings. In the drawings, several embodiments of the invention are illustrated by way of example and not limitation, with the same or corresponding reference numerals denoteing the same or corresponding parts, wherein:

[0033] Figure 1 A schematic diagram of a multi-step, V-groove gate gallium nitride P-channel field-effect transistor is shown.

[0034] Figure 2 The fabrication process of a multi-step, V-groove gate gallium nitride P-channel field-effect transistor is schematically illustrated. Figure 1 .

[0035] Figure 3 The schematic diagram illustrates the fabrication process of a multi-step, V-groove gate gallium nitride P-channel field-effect transistor. Figure 1 ;

[0036] Figure 4 The fabrication process of a multi-step, V-groove gate gallium nitride P-channel field-effect transistor is schematically illustrated. Figure 2 ;

[0037] Figure 5 The schematic diagram illustrates the fabrication process of a multi-step, V-groove gate gallium nitride P-channel field-effect transistor. Figure 2 .

[0038] Explanation of reference numerals in the attached figures

[0039] 1. Substrate layer; 2. Buffer layer; 3. Barrier layer; 4. Channel layer; 5. Cap layer; 6. Groove; 61. Multi-step groove; 62. V-groove; 63. Inverted trapezoidal groove; 7. Source electrode; 8. Drain electrode; 9. Gate electrode; 10. Hard mask layer; 11. Photoresist layer. Detailed Implementation

[0040] Exemplary embodiments of the invention will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the invention are shown in the drawings, it should be understood that the invention can be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the invention and to fully convey the scope of the invention to those skilled in the art.

[0041] It should be noted that, unless otherwise stated, the technical or scientific terms used in this invention should have the ordinary meaning as understood by one of ordinary skill in the art.

[0042] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0043] Example 1:

[0044] Figure 1 A schematic diagram of a multi-step, V-groove gate gallium nitride P-channel field-effect transistor is shown, in which... Figure 1 (a) is a multi-step grooved gate gallium nitride P-channel field-effect transistor. Figure 1 (b) is a V-groove gate gallium nitride P-channel field-effect transistor. Figure 1 (c) is a 63-gate gallium nitride P-channel field-effect transistor with an inverted trapezoidal groove. Specifically, the multi-step and V-groove gate gallium nitride P-channel field-effect transistor includes: a substrate layer 1, a buffer layer 2, a barrier layer 3, a channel layer 4 and a cap layer 5 arranged sequentially from bottom to top.

[0045] The groove 6 extends downward from the middle area of ​​the upper surface of the cap layer 5 and penetrates the cap layer 5 into the channel layer 4. The groove is in the shape of a multi-step groove 61, a V-shaped groove 62 or an inverted trapezoidal groove 63.

[0046] The source electrode 7 is formed on the cap layer 5 on one side of the groove 6;

[0047] The drain electrode 8 is formed on the cap layer 5 on the other side of the groove 6;

[0048] The gate electrode 9 is formed in the groove 6 and contacts the channel layer 4. The horizontal plane of the upper surface of the gate electrode 9 is lower than the horizontal plane of the upper surface of the channel layer 4.

[0049] Specifically, the epitaxial wafer has a structure consisting of a substrate layer 1, a buffer layer 2, a barrier layer 3, a channel layer 4, and a cap layer 5 stacked sequentially. A source electrode 7 and a drain electrode 8 are deposited on the cap layer 5, with ohmic contacts. The cap layer 5 without deposited metal and a portion of the channel layer 4 are etched away to form a groove. The groove shape is a multi-step groove 61, a V-shaped groove 62, or an inverted trapezoidal groove 63. Metal is deposited at the bottom of the exposed channel layer 4 after etching to form a gate electrode 9, with Schottky contacts. This creates an enhanced grooved gate structure, which includes a multi-step grooved gate and gate electrode 9, a V-shaped grooved gate and gate electrode 9, or an inverted trapezoidal grooved gate and gate electrode 9.

[0050] A multi-step groove gate formed by a multi-step groove and a gate electrode 9, a V-shaped groove gate formed by a V-shaped groove 62 and a gate electrode 9, and an inverted trapezoidal groove 63 gate formed by an inverted trapezoidal groove 63 and a gate electrode 9.

[0051] The fabrication process of the multi-step groove grid differs from that of the V-shaped groove grid and the inverted trapezoidal groove grid, while the fabrication processes of the V-shaped groove grid and the inverted trapezoidal groove grid are the same. The number of steps in the multi-step groove 61 can be changed according to requirements; no specific limit is made here.

[0052] The substrate layer 1 is made of Si, Al2O3 or SiC.

[0053] As an optional implementation, each step of the multi-step groove 61 has the same width, and the inclination angles of the V-shaped groove 62 and the inverted trapezoidal groove 63 are both greater than 0° and less than 90°.

[0054] Specifically, the tilt angles of the V-shaped groove 62 and the inverted trapezoidal groove 63 can be changed according to requirements, as long as the tilt angles of the V-shaped groove 62 and the inverted trapezoidal groove 63 are greater than 0° and less than 90°.

[0055] As an optional implementation, the buffer layer 2 is made of GaN material and has a thickness of 1 to 10 μm.

[0056] As an optional implementation, the barrier layer 3 is made of AlGaN material, in which the Al content is 5% to 30%, and the thickness of the barrier layer 3 is 5 to 30 nm.

[0057] As an optional implementation, the channel layer 4 is a p-type GaN channel layer 4, and the doping ions of the p-type GaN channel layer 4 are Mg ions, with a doping concentration of 5 × 10⁻⁶ Mg ions in the p-type GaN channel layer 4. 18 ~5×10 19 cm -3 The thickness of the p-type GaN channel layer 4 is 50nm to 100nm.

[0058] As an optional implementation, the cap layer 5 is a p-type heavily doped GaN channel layer 4, and the dopant ion in the p-type heavily doped GaN channel layer 4 is Mg ions, with a doping concentration of 1×10⁻⁶ Mg ions in the p-type heavily doped GaN channel layer 4. 19 ~1×10 20 cm -3 The thickness is 5nm to 30nm.

[0059] As an optional implementation, both the source electrode 7 and the drain electrode 8 are made of Ni / Au metal.

[0060] Specifically, Ni metal has a high work function, which can form an ohmic contact with the surface of the cap layer 5, reducing the contact resistance between the metal and the semiconductor, reducing heat accumulation and power consumption. Au metal has good stability and conductivity, preventing oxidation of the underlying Ni metal.

[0061] As an optional implementation, the gate electrode 9 is made of W / Au or Ti / Au metal.

[0062] Specifically, the gate electrode 9 is a low work function metal, which can be W / Au or Ti / Au metal, to ensure that a Schottky contact is formed with the channel layer 4, thereby depleting the two-site holes at the heterojunction interface under the gate and forming an enhancement-mode device.

[0063] In summary, the multi-step and V-groove gate gallium nitride enhancement-mode P-channel MOSFET has a lateral structure. This multi-step and V-groove gate gallium nitride enhancement-mode P-channel MOSFET effectively solves the problem of low breakdown voltage caused by the short distance between the gate and drain and the high electric field shifting towards the gate in traditional gallium nitride enhancement-mode P-channel MOSFETs. At the same time, it avoids the defects of low output current and high on-resistance of traditional single dielectric trench devices.

[0064] Based on the above Figure 1As can be seen from the implementation, the multi-step and V-groove gate gallium nitride P-channel field-effect transistor of the present invention includes a substrate layer 1, a buffer layer 2, a barrier layer 3, a channel layer 4, and a cap layer 5 arranged sequentially from bottom to top; a groove extends downward from the middle region of the upper surface of the cap layer 5 and penetrates the cap layer 5 into the channel layer 4, and the shape of the groove is a multi-step groove 61, a V-shaped groove, or an inverted trapezoidal groove 63; a source electrode 7 is formed on the cap layer 5 on one side of the groove; a drain electrode 8 is formed on the cap layer 5 on the other side of the groove; and a gate electrode 9 is formed in the groove and contacts the channel layer 4, and the horizontal plane of the upper surface of the gate electrode 9 is lower than the horizontal plane of the upper surface of the channel layer 4. By employing multi-step grooved gates, V-shaped grooved gates, and inverted trapezoidal grooved gates, the electric field distribution between the gate and drain can be optimized, local high electric fields can be alleviated, and the application of the device in high-voltage and high-power applications can be broadened. Through multi-step grooved gates, V-shaped grooved gates, and inverted trapezoidal grooved gates, the output current is increased and the on-resistance is reduced while realizing enhancement-mode P-channel MOSFETs, thereby reducing the power loss of P-channel MOSFETs in the on-state and improving the performance and reliability of P-channel MOSFETs in high-frequency and high-power applications.

[0065] Example 2:

[0066] Figure 2 The schematic diagram illustrates the fabrication process of a multi-step and V-groove gate gallium nitride P-channel field-effect transistor according to an embodiment of the present invention. Figure 1 See Figure 2 As shown, the fabrication method of this multi-step and V-groove gate gallium nitride P-channel field-effect transistor may include:

[0067] S201. Obtain the epitaxial wafer.

[0068] The epitaxial wafer comprises, from bottom to top, a substrate layer 1, a buffer layer 2, a barrier layer 3, a channel layer 4, and a cap layer 5.

[0069] The epitaxial wafer can be obtained by metal-organic chemical vapor deposition (MOCVD). The substrate layer 1 is made of Si, Al2O3, or SiC.

[0070] Specifically, Figure 3 The schematic diagram illustrates the fabrication process of a multi-step, V-groove gate gallium nitride P-channel field-effect transistor. Figure 1 ,in, Figure 3 (a) shows the structure of the epitaxial wafer. Organic cleaning and surface oxide removal are performed on the epitaxial wafer. See [link to epitaxial wafer structure] for details. Figure 3(a) Cleaning the epitaxial wafer can reduce the interference of oxidation and contamination on subsequent device processes and the impact on device performance. First, organic cleaning of the epitaxial wafer is performed by immersing the epitaxial material in an acetone solution and ultrasonically cleaning for 5 minutes to remove organic contaminants from the material surface. Next, it is immersed in an isopropanol solution for ultrasonic cleaning for 5 minutes to effectively remove residual acetone. Then, the epitaxial wafer is rinsed in deionized water to remove any remaining isopropanol. Finally, the surface of the material is dried with high-purity nitrogen to ensure no residual liquid remains. Then, the epitaxial wafer is placed in a 1:7 BOE solution for 30 seconds to remove the surface oxide layer. It is then rinsed with a large amount of deionized water, and finally dried with high-purity nitrogen to complete the entire cleaning process.

[0071] S202. Deposit metal on the upper surface of the cap layer 5 to form the source electrode 7 and the drain electrode 8.

[0072] The source electrode 7 is located on one side edge region of the upper surface of the cap layer 5, and the drain electrode 8 is located on the other side edge region of the upper surface of the cap layer 5.

[0073] Specifically, Figure 3 The schematic diagram illustrates the fabrication process of a multi-step, V-groove gate gallium nitride P-channel field-effect transistor. Figure 1 ,in, Figure 3 (b) Schematic diagram of the formation of source electrode 7 and drain electrode 8. The surface of cap layer 5 is subjected to homogenization, baking, exposure, and development. The regions of source electrode 7 and drain electrode 8 are defined using photolithography. Ni / Au metal is then sputtered onto the developed epitaxial wafer surface using magnetron sputtering. Residual resist and metal from other areas are removed using a stripping solution. A rapid thermal annealing process is used, annealing the epitaxial wafer at 450°C for 5 minutes in a nitrogen atmosphere. This treatment reduces the influence of the gold-semiconductor interface states, ensuring good ohmic contact between source electrode 7 and drain electrode 8 and the surface of cap layer 5, thus reducing the contact resistance between the metal and semiconductor.

[0074] S203. Etch downwards from the upper surface of the cap layer 5 outside the source electrode 7 and drain electrode 8 regions, until the upper surface of the channel layer 4 is reached.

[0075] Specifically, Figure 3 The schematic diagram illustrates the fabrication process of a multi-step, V-groove gate gallium nitride P-channel field-effect transistor. Figure 1 ,in, Figure 3 (c) is a schematic diagram of the device structure after etching the cap layer 5. The source and drain electrode 8 area is etched to remove the cap layer 5, so that the channel layer 4 is fully exposed. The device is then cleaned with stripping solution to remove residual adhesive.

[0076] S204. Multiple etchings are performed from the upper surface of the channel layer 4 downwards to form a multi-step groove 61, and the width of each etching is the same.

[0077] Specifically, Figure 3 The schematic diagram illustrates the fabrication process of a multi-step, V-groove gate gallium nitride P-channel field-effect transistor. Figure 1 ,in, Figure 3 (d) is a schematic diagram of forming a multi-step groove 61. The trench layer 4 is etched by multiple photolithography processes and multiple ICP dry etching techniques. The etching width is shortened at equal intervals according to the number of steps and the length of steps, and the etching depth is increased at equal intervals according to the number of steps and the height of steps, thus forming a multi-step groove 61.

[0078] S205. Deposit metal in the bottom of the multi-step groove 61 to form the gate electrode 9.

[0079] Specifically, Figure 3 The schematic diagram illustrates the fabrication process of a multi-step, V-groove gate gallium nitride P-channel field-effect transistor. Figure 1 ,in, Figure 3 (e) is a schematic diagram of the formation of the gate electrode 9. First, the epitaxial wafer is annealed in a nitrogen atmosphere at 450°C for 5 minutes. Then, it is preheated in a tetramethylammonium hydroxide (TMAH) solution at 80°C for 10 minutes to repair the interface damage of the etched area. Then, metal, which can be W or Ti metal, is sputtered on the bottom surface of the gate area of ​​the multi-step groove 61 using a magnetron sputtering process to form the gate electrode 9.

[0080] Example 3:

[0081] Based on Example 2, combined with Figure 3 This embodiment illustrates the fabrication method of a multi-step and V-groove gate gallium nitride P-channel field-effect transistor using the fabrication of a Si substrate layer 1, a 5μm GaN buffer layer 2, a 15nm AlGaN barrier layer 3, a 70nm GaN channel layer 4, and a 10nm GaN cap layer 5 as an example. The fabrication method of this multi-step and V-groove gate gallium nitride P-channel field-effect transistor includes:

[0082] Step A1: Obtain the epitaxial wafer.

[0083] The epitaxial wafer comprises, from bottom to top, a substrate layer 1, a buffer layer 2, a barrier layer 3, a channel layer 4, and a cap layer 5.

[0084] In Example 3, the epitaxial wafer can be obtained by MOCVD epitaxial growth. The substrate layer 1 is made of Si.

[0085] Specifically, Figure 3The schematic diagram illustrates the fabrication process of a multi-step, V-groove gate gallium nitride P-channel field-effect transistor. Figure 1 ,in, Figure 3 (a) shows the structure of the epitaxial wafer. Organic cleaning and surface oxide removal are performed on the epitaxial wafer. See [link to epitaxial wafer structure] for details. Figure 3 (a) Cleaning the epitaxial wafer can reduce the interference of oxidation and contamination on subsequent device processes and the impact on device performance. First, organic cleaning of the epitaxial wafer is performed by immersing the epitaxial material in an acetone solution and ultrasonically cleaning for 5 minutes to remove organic contaminants from the material surface. Next, it is immersed in an isopropanol solution for ultrasonic cleaning for 5 minutes to effectively remove residual acetone. Then, the epitaxial wafer is rinsed in deionized water to remove any remaining isopropanol. Finally, the surface of the material is dried with high-purity nitrogen to ensure no residual liquid remains. Then, the epitaxial wafer is placed in a 1:7 BOE solution for 30 seconds to remove the surface oxide layer. It is then rinsed with a large amount of deionized water, and finally dried with high-purity nitrogen to complete the entire cleaning process.

[0086] Step A2: Deposit metal on the upper surface of the cap layer 5 to form the source electrode 7 and the drain electrode 8.

[0087] The source electrode 7 is located on one side edge region of the upper surface of the cap layer 5, and the drain electrode 8 is located on the other side edge region of the upper surface of the cap layer 5.

[0088] Specifically, Figure 3 The schematic diagram illustrates the fabrication process of a multi-step, V-groove gate gallium nitride P-channel field-effect transistor. Figure 1 ,in, Figure 3 (b) Schematic diagram of the formation of source electrode 7 and drain electrode 8. The surface of cap layer 5 is subjected to homogenization, baking, exposure, and development. The regions of source electrode 7 and drain electrode 8 are defined using photolithography. Ni / Au metal is then sputtered onto the developed epitaxial wafer surface using magnetron sputtering. Residual resist and metal from other areas are removed using a stripping solution. A rapid thermal annealing process is used, annealing the epitaxial wafer at 450°C for 5 minutes in a nitrogen atmosphere. This treatment reduces the influence of the gold-semiconductor interface states, ensuring good ohmic contact between source electrode 7 and drain electrode 8 and the surface of cap layer 5, thus reducing the contact resistance between the metal and semiconductor.

[0089] Step A3: Etch downwards from the upper surface of the cap layer 5 outside the regions of the source electrode 7 and the drain electrode 8, until the upper surface of the channel layer 4 is reached.

[0090] Specifically, Figure 3 The schematic diagram illustrates the fabrication process of a multi-step, V-groove gate gallium nitride P-channel field-effect transistor. Figure 1 ,in, Figure 3(c) is a schematic diagram of the device structure after etching the cap layer 5. The non-source / drain electrode 8 region is etched using ICP dry etching technology to remove the cap layer 5, so that the channel layer 4 is fully exposed to form a grooved gate structure. The device is then cleaned with stripping solution to remove residual adhesive.

[0091] Step A4: Etch multiple times from the upper surface of the channel layer 4 downwards to form a multi-step groove 61, with the width of each etching being the same.

[0092] Specifically, Figure 3 The schematic diagram illustrates the fabrication process of a multi-step, V-groove gate gallium nitride P-channel field-effect transistor. Figure 1 ,in, Figure 3 (d) is a schematic diagram of forming a multi-step groove 61. The channel layer 4 is etched by multiple photolithography processes and multiple ICP dry etching techniques. The etching width is shortened at equal intervals according to the number of steps and the step length, and the etching depth is increased at equal intervals according to the number of steps and the step height, thus forming a multi-step groove 61 gate structure.

[0093] Step A5: Deposit metal in the bottom of the multi-step groove 61 to form the gate electrode 9.

[0094] Specifically, Figure 3 The schematic diagram illustrates the fabrication process of a multi-step, V-groove gate gallium nitride P-channel field-effect transistor. Figure 1 ,in, Figure 3 (e) is a schematic diagram of the formation of the gate electrode 9. First, the epitaxial wafer is placed in a nitrogen atmosphere at 450°C for 5 min to anneal the gate trench. Then, it is heated in a TMAH solution at 80°C for 10 min to repair the interface damage of the etched area. Then, metal, which can be W or Ti metal, is sputtered on the bottom surface of the gate area of ​​the multi-step trench 61 using a magnetron sputtering process to form the gate electrode 9.

[0095] Example 4:

[0096] Figure 4 The fabrication process of a multi-step, V-groove gate gallium nitride P-channel field-effect transistor is schematically illustrated. Figure 2 See Figure 4 As shown, the fabrication method of this multi-step and V-groove gate gallium nitride P-channel field-effect transistor may include:

[0097] S401, Obtain the epitaxial wafer.

[0098] The epitaxial wafer comprises, from bottom to top, a substrate layer 1, a buffer layer 2, a barrier layer 3, a channel layer 4, and a cap layer 5.

[0099] Specifically, the epitaxial wafer can be obtained through MOCVD epitaxial growth. The substrate layer 1 is made of Si, Al2O3, or SiC.

[0100] Specifically, Figure 5 The schematic diagram illustrates the fabrication process of a multi-step, V-groove gate gallium nitride P-channel field-effect transistor. Figure 2 ,in, Figure 5 (a) is a schematic diagram of the epitaxial wafer structure. Organic cleaning and surface oxide layer removal are performed on the epitaxial wafer. For the structure of the epitaxial wafer, please refer to [link to diagram]. Figure 5 (a) Cleaning the epitaxial wafer can reduce the interference of oxidation and contamination on subsequent device processes and the impact on device performance. First, organic cleaning of the epitaxial wafer is performed by immersing the epitaxial material in an acetone solution and ultrasonically cleaning for 5 minutes to remove organic contaminants from the material surface. Next, it is immersed in an isopropanol solution for ultrasonic cleaning for 5 minutes to effectively remove residual acetone. Then, the epitaxial wafer is rinsed in deionized water to remove any remaining isopropanol. Finally, the surface of the material is dried with high-purity nitrogen to ensure no residual liquid remains. Then, the epitaxial wafer is placed in a 1:7 BOE solution for 30 seconds to remove the surface oxide layer. It is then rinsed with a large amount of deionized water, and finally dried with high-purity nitrogen to complete the entire cleaning process.

[0101] S402. A SOG film is coated on the upper surface of the cap layer 5 to form a hard mask layer 10, and a photoresist layer 11 is coated on both sides of the edge region of the hard mask layer 10.

[0102] Specifically, Figure 5 The schematic diagram illustrates the fabrication process of a multi-step, V-groove gate gallium nitride P-channel field-effect transistor. Figure 2 ,in, Figure 5 (b) is a schematic diagram of the device after the photoresist layer 11 is coated. A silicon-on-glass (SOG) bonding structure solution is dropped onto the center of the epitaxial wafer surface. The epitaxial wafer is then rotated rapidly to uniformly coat the solution onto the surface of the epitaxial wafer, forming a uniform liquid film. The solvent is then removed by soft baking, making the SOG film semi-solid. Further heating is used to completely solidify the SOG film, forming a hard mask layer 10. Photoresist is then coated on the surface of the hard mask layer 10, followed by homogenization, baking, exposure, and development, resulting in the formation of photoresist layers 11 on both sides.

[0103] S403. Remove part of the hard mask layer 10 to form a hard mask layer 10 with an angle, and remove the photoresist layer 11.

[0104] The tilt angle of the hard mask layer 10 with a slope is greater than 0° and less than 90°.

[0105] Specifically, Figure 5 The schematic diagram illustrates the fabrication process of a multi-step, V-groove gate gallium nitride P-channel field-effect transistor. Figure 2,in, Figure 5 (c) is a schematic diagram of the device after removing the photoresist layer 11. The hard mask layer 10 is etched with a diluted HF solution with a concentration of 2%. The gap between the hard mask layer 10 and the photoresist layer 11 causes the upper part of the hard mask layer 10 to be etched faster than the lower part, forming a hard mask layer 10 with an angle. The photoresist layer 11 is then removed using a stripping solution.

[0106] S404. Part of the hard mask layer 10 and the cap layer 5 are etched away until they reach the channel layer 4, forming a V-shaped groove 62 or an inverted trapezoidal groove 63.

[0107] Specifically, Figure 5 The schematic diagram illustrates the fabrication process of a multi-step, V-groove gate gallium nitride P-channel field-effect transistor. Figure 2 ,in, Figure 5 (d) is a schematic diagram of the formation of the inverted trapezoidal groove 63. Figure 5 (e) For the formation of V-shaped groove 62, ICP dry etching technology is used to etch away the hard mask layer 10 and the cap layer 5 of the non-source drain electrode 8 region, and part of the channel layer 4 is etched to form V-shaped groove 62 or inverted trapezoidal groove 63; ideally, V-shaped groove 62 is formed.

[0108] S405. Deposit metal on the upper surface of the cap layer 5 to form the source electrode 7 and the drain electrode 8.

[0109] The source electrode 7 is located on one side edge region of the upper surface of the cap layer 5, and the drain electrode 8 is located on the other side edge region of the upper surface of the cap layer 5.

[0110] Specifically, Figure 5 The schematic diagram illustrates the fabrication process of a multi-step, V-groove gate gallium nitride P-channel field-effect transistor. Figure 2 ,in, Figure 5 (f) is a schematic diagram showing the formation of source electrode 7 and drain electrode 8 on the upper surface of cap layer 5 in inverted trapezoidal groove 63. Spin coating, baking, exposure, and development are performed on the upper surface of cap layer 5 in inverted trapezoidal groove 63 or on the upper surface of cap layer 5 in V-shaped groove 62. Ni / Au metal is then sputtered onto the developed cap layer 5 surface using magnetron sputtering. Residual resist and metal from other areas are removed using a stripping solution. A rapid thermal annealing process is used, annealing the epitaxial wafer at 450°C for 5 minutes in a nitrogen atmosphere.

[0111] S406. Deposit metal at the bottom of the V-shaped groove 62 or the inverted trapezoidal groove 63 to form the gate electrode 9.

[0112] Specifically, Figure 5 The schematic diagram illustrates the fabrication process of a multi-step, V-groove gate gallium nitride P-channel field-effect transistor. Figure 2 ,in, Figure 5(g) is a schematic diagram of the gate electrode 9 formed at the bottom of the inverted trapezoidal groove 63. Figure 5 (h) is a schematic diagram of forming the gate electrode 9 at the bottom of the V-groove 62. The epitaxial wafer is annealed in a nitrogen atmosphere at 450°C for 5 minutes, followed by water bath heating in a TMAH solution at 80°C for 10 minutes to repair interface damage in the etched area. Then, metal, which can be W or Ti, is sputtered onto the bottom surface of the V-groove 62 or the inverted trapezoidal groove 63 region using magnetron sputtering to form the gate electrode 9. Ideally, a V-groove gate is formed.

[0113] Example 5:

[0114] Based on Example 4, combined with Figure 5 This fifth embodiment illustrates the fabrication method of a multi-step and V-groove gate gallium nitride P-channel field-effect transistor, using the fabrication of a Si substrate layer 1, a 5μm GaN buffer layer 2, a 15nm AlGaN barrier layer 3, a 70nm GaN channel layer 4, and a 10nm GaN cap layer 5 as an example. The fabrication method of this multi-step and V-groove gate gallium nitride P-channel field-effect transistor includes:

[0115] Step B1: Obtain the epitaxial wafer.

[0116] The epitaxial wafer comprises, from bottom to top, a substrate layer 1, a buffer layer 2, a barrier layer 3, a channel layer 4, and a cap layer 5.

[0117] In this fifth embodiment, the epitaxial wafer can be obtained by MOCVD epitaxial growth. The substrate layer 1 is made of Si.

[0118] Specifically, Figure 5 The schematic diagram illustrates the fabrication process of a multi-step, V-groove gate gallium nitride P-channel field-effect transistor. Figure 2 ,in, Figure 5 (a) is a schematic diagram of the epitaxial wafer structure. Organic cleaning and surface oxide layer removal are performed on the epitaxial wafer. For the structure of the epitaxial wafer, please refer to [link to diagram]. Figure 5 (a) Cleaning the epitaxial wafer can reduce the interference of oxidation and contamination on subsequent device processes and the impact on device performance. First, organic cleaning of the epitaxial wafer is performed by immersing the epitaxial material in an acetone solution and ultrasonically cleaning for 5 minutes to remove organic contaminants from the material surface. Next, it is immersed in an isopropanol solution for ultrasonic cleaning for 5 minutes to effectively remove residual acetone. Then, the epitaxial wafer is rinsed in deionized water to remove any remaining isopropanol. Finally, the surface of the material is dried with high-purity nitrogen to ensure no residual liquid remains. Then, the epitaxial wafer is placed in a 1:7 BOE solution for 30 seconds to remove the surface oxide layer. It is then rinsed with a large amount of deionized water, and finally dried with high-purity nitrogen to complete the entire cleaning process.

[0119] Step B2: Coat an SOG film on the upper surface of the cap layer 5 to form a hard mask layer 10, and coat photoresist layers 11 on both sides of the edge region of the hard mask layer 10.

[0120] Specifically, Figure 5 The schematic diagram illustrates the fabrication process of a multi-step, V-groove gate gallium nitride P-channel field-effect transistor. Figure 2 ,in, Figure 5 (b) is a schematic diagram of the device after the photoresist layer 11 is coated. The SOG solution is dropped onto the center of the epitaxial wafer surface, and then the epitaxial wafer is rotated rapidly to uniformly coat the solution on the surface of the epitaxial wafer, forming a uniform liquid film. The solvent is then removed by soft baking, making the SOG film semi-solid. Further heating is used to completely solidify the SOG film to form a hard mask layer 10. Photoresist is then coated on the surface of the hard mask layer 10, and the photoresist is homogenized, baked, exposed, and developed to form photoresist layers 11 on both sides.

[0121] Step B3: Remove part of the hard mask layer 10 to form a hard mask layer 10 with an angle, and remove the photoresist layer 11.

[0122] The tilt angle of the hard mask layer 10 with a slope is greater than 0° and less than 90°.

[0123] Specifically, Figure 5 The schematic diagram illustrates the fabrication process of a multi-step, V-groove gate gallium nitride P-channel field-effect transistor. Figure 2 ,in, Figure 5 (c) is a schematic diagram of the device after removing the photoresist layer 11. The hard mask layer 10 is etched with a diluted HF solution with a concentration of 2%. The gap between the hard mask layer 10 and the photoresist layer 11 causes the upper part of the hard mask layer 10 to be etched faster than the lower part, forming a hard mask layer 10 with an angle. The photoresist layer 11 is then removed using a stripping solution.

[0124] Step B4: Etch away part of the hard mask layer 10 and the cap layer 5 until it reaches the channel layer 4, forming a V-shaped groove 62 or an inverted trapezoidal groove 63.

[0125] Specifically, Figure 5 The schematic diagram illustrates the fabrication process of a multi-step, V-groove gate gallium nitride P-channel field-effect transistor. Figure 2 ,in, Figure 5 (d) For the formation of V-shaped groove 62 or inverted trapezoidal groove 63, ICP dry etching technology is used to etch away the hard mask layer 10 and the cap layer 5 in the non-source drain electrode 8 region, and part of the channel layer 4 is etched to form V-shaped groove 62. Ideally, the gap in the middle of the photoresist layer 11 formed in step B2 can be small enough to form a complete V-shaped groove 62 after etching the hard mask layer 10, cap layer 5 and channel layer 4.

[0126] Step B5: Deposit metal on the upper surface of the cap layer 5 to form the source electrode 7 and the drain electrode 8.

[0127] The source electrode 7 is located on one side edge region of the upper surface of the cap layer 5, and the drain electrode 8 is located on the other side edge region of the upper surface of the cap layer 5.

[0128] Specifically, Figure 5 The schematic diagram illustrates the fabrication process of a multi-step, V-groove gate gallium nitride P-channel field-effect transistor. Figure 2 ,in, Figure 5 (e) is a schematic diagram of the formation of source electrode 7 and drain electrode 8. The cap layer 5 is subjected to homogenization, baking, exposure, and development. Ni / Au metal is then sputtered onto the developed cap layer 5 using magnetron sputtering. Residual resist and metal from other areas are removed using a stripping solution. The epitaxial wafer is then annealed at 450°C for 5 minutes in a nitrogen atmosphere using a rapid thermal annealing process.

[0129] Step B6: Deposit metal at the bottom of the V-shaped groove 62 or the inverted trapezoidal groove 63 to form the gate electrode 9.

[0130] Specifically, Figure 5 The schematic diagram illustrates the fabrication process of a multi-step, V-groove gate gallium nitride P-channel field-effect transistor. Figure 2 , among which, among which, Figure 5 (f) is a schematic diagram of the gate electrode 9 formed at the bottom of the V-shaped groove 62. Figure 5 (g) is a schematic diagram of forming the gate electrode 9 at the bottom of the inverted trapezoidal groove 63. The epitaxial wafer is annealed in a nitrogen atmosphere at 450°C for 5 minutes, followed by water bath heating in a TMAH solution at 80°C for 10 minutes to repair interface damage in the etched area. Then, metal, which can be W or Ti, is sputtered onto the bottom surface of the V-groove 62 or the inverted trapezoidal groove 63 area using magnetron sputtering to form the gate electrode 9. Ideally, a V-groove gate is formed.

[0131] It should be noted that the description of the above embodiments of the fabrication method for multi-step and V-groove gate gallium nitride (GaN) P-channel field-effect transistors is similar to the description of the above embodiments of multi-step and V-groove gate GaN P-channel field-effect transistors, and has similar beneficial effects. For technical details not disclosed in the embodiments of the fabrication method for multi-step and V-groove gate GaN P-channel field-effect transistors of the present invention, please refer to the description of the embodiments of the present invention for understanding.

[0132] The above are merely specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A multi-step, V-groove gate gallium nitride P-channel field-effect transistor, characterized in that, It includes, from bottom to top, a substrate layer, a buffer layer, a barrier layer, a channel layer, and a cap layer; The groove extends downward from the middle area of ​​the upper surface of the cap layer and penetrates the cap layer into the channel layer. The groove is in the shape of a multi-step groove, a V-shaped groove, or an inverted trapezoidal groove. A source electrode is formed on the cap layer on one side of the groove; A drain electrode is formed on the cap layer on the other side of the groove, and the contact type between the source electrode and the drain electrode and the cap layer is ohmic contact; A gate electrode is formed in the groove and contacts the channel layer. The horizontal plane of the upper surface of the gate electrode is lower than the horizontal plane of the upper surface of the channel layer. The contact type between the gate electrode and the channel layer is a Schottky contact. Each step of the multi-step groove has the same width, and the inclination angles of the V-shaped groove and the inverted trapezoidal groove are both greater than 0° and less than 90°.

2. The multi-step and V-groove gate gallium nitride P-channel field-effect transistor according to claim 1, characterized in that, The buffer layer is made of GaN material and has a thickness of 1–10 µm.

3. The multi-step and V-groove gate gallium nitride P-channel field-effect transistor according to claim 1, characterized in that, The barrier layer is made of AlGaN material, wherein the Al content in the AlGaN material is 5% to 30%, and the thickness of the barrier layer is 5 to 30 nm.

4. The multi-step and V-groove gate gallium nitride P-channel field-effect transistor according to claim 1, characterized in that, The channel layer is a p-type GaN channel layer, and the doping ions in the p-type GaN channel layer are Mg ions. The doping concentration of Mg ions in the p-type GaN channel layer is 5 × 10⁻⁶. 18 ~5×10 19 cm -3 The thickness of the p-type GaN channel layer is 50nm~100nm.

5. The multi-step and V-groove gate gallium nitride P-channel field-effect transistor according to claim 1, characterized in that, The cap layer is a p-type heavily doped GaN layer, and the dopant ions in the p-type heavily doped GaN layer are Mg ions. The doping concentration of Mg ions in the p-type heavily doped GaN layer is 1 × 10⁻⁶. 19 ~1×10 20 cm -3 The thickness is 5nm~30nm.

6. The multi-step and V-groove gate gallium nitride P-channel field-effect transistor according to claim 1, characterized in that, Both the source electrode and the drain electrode are made of Ni / Au metal.

7. The multi-step and V-groove gate gallium nitride P-channel field-effect transistor according to claim 1, characterized in that, The gate electrode is made of W / Au or Ti / Au metal.

8. A method for fabricating a multi-step, V-groove gate gallium nitride P-channel field-effect transistor, characterized in that, The multi-step and V-groove gate gallium nitride P-channel field-effect transistor according to any one of claims 1-7 comprises: Obtain an epitaxial wafer, the epitaxial wafer comprising a substrate layer, a buffer layer, a barrier layer, a channel layer and a cap layer stacked sequentially from bottom to top; Metal is deposited on the upper surface of the cap layer to form a source electrode and a drain electrode. The source electrode is located in one edge region of the upper surface of the cap layer, and the drain electrode is located in the other edge region of the upper surface of the cap layer. The contact type between the source electrode and the drain electrode and the cap layer is ohmic contact. Etch downwards from the upper surface of the cap layer, outside the source electrode and drain electrode regions, to the upper surface of the channel layer; Multiple etchings are performed from the upper surface of the channel layer downwards to form a multi-step groove, with each etching having the same width. The metal is deposited in the bottom of the multi-step groove to form a gate electrode, and the contact type between the gate electrode and the channel layer is a Schottky contact.

9. A method for fabricating a multi-step, V-groove gate gallium nitride P-channel field-effect transistor, characterized in that, The multi-step and V-groove gate gallium nitride P-channel field-effect transistor according to any one of claims 1-7 comprises: Obtain an epitaxial wafer, the epitaxial wafer comprising a substrate layer, a buffer layer, a barrier layer, a channel layer and a cap layer stacked sequentially from bottom to top; An SOG film is coated on the upper surface of the cap layer to form a hard mask layer, and a photoresist layer is coated on both sides of the hard mask layer edge region; A portion of the hard mask layer is removed to form a sloped hard mask layer, and the photoresist layer is removed. The sloped hard mask layer has an angle greater than 0° and less than 90°. Etch away part of the hard mask layer and the cap layer until the channel layer is formed, creating a V-shaped groove or an inverted trapezoidal groove; Metal is deposited on the upper surface of the cap layer to form a source electrode and a drain electrode. The source electrode is located in one edge region of the upper surface of the cap layer, and the drain electrode is located in the other edge region of the upper surface of the cap layer. The contact type between the source electrode and the drain electrode and the cap layer is ohmic contact. The metal is deposited at the bottom of the V-shaped groove or the inverted trapezoidal groove to form a gate electrode, and the contact type between the gate electrode and the channel layer is a Schottky contact.

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