A gain amplifier and packaging method thereof

Abstract

The present invention discloses a gain amplifier, comprising a gain amplifier body and a packaging structure. The gain amplifier body includes an input-stage chip, a gain-stage chip, an output-stage chip, and a control-stage chip. The packaging structure comprises a multi-layer embedded substrate, the embedded substrate having grooves and through-holes formed therein, and the grooves and through-holes are surrounded by an absorbing material. The input-stage chip is disposed on one side of the upper surface of the embedded substrate and is surrounded by a metal shield. The gain-stage chip is stacked on the input-stage chip and is coated with a radiation-proof coating. The output-stage chip is located above the gain-stage chip and is surrounded by an electromagnetic shield. The control-stage chip is disposed on the output-stage chip and is surrounded by an isolation zone. The embedded substrate also has redistribution lines formed on its upper surface, and a radiation-proof protection ring is provided around the redistribution lines. The present invention not only has a high degree of integration but also reduces signal interference.

Description

Technical Field

[0001] The present invention relates to the technical field of gain amplifiers, and in particular to a gain amplifier and a packaging method thereof. Background Art

[0002] With the rapid development of modern electronic technology, various electronic devices are placing increasingly higher demands on the performance, integration, and reliability of semiconductor devices. Among numerous semiconductor devices, gain amplifiers, as key components in signal processing, are widely used in fields such as communications, radar, and electronic measurement. To meet the high-quality signal amplification and processing requirements of these applications, the various components of the gain amplifier must be highly integrated and achieve even higher performance targets.

[0003] Traditional packaging methods often struggle to meet the demands of this high level of integration and high performance. For example, in some simple packaging structures, individual circuit modules may be dispersed, resulting in long signal transmission paths, which can introduce significant signal delays and losses, impacting the amplifier's overall performance. Furthermore, with increasing integration, electromagnetic interference (EMI) between chips is becoming increasingly prominent. Effectively suppressing EMI within limited space has become a critical issue in the semiconductor packaging field. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a gain amplifier and a packaging method thereof, which not only has a high degree of integration but also can effectively suppress electromagnetic interference.

[0005] In order to solve the above technical problems, the technical solutions adopted by the present invention are as follows.

[0006] A gain amplifier, comprising a gain amplifier body and a packaging structure for packaging the gain amplifier body; the gain amplifier body comprises an input stage chip, a gain stage chip, an output stage chip and a control stage chip; the packaging structure comprises a multi-layer embedded substrate, the bottom layer of the embedded substrate is provided with a power plane and a ground plane, the interior of the embedded substrate is formed with grooves and through-holes for wiring to connect signal lines between different layers, and the grooves and through-holes are filled with absorbing materials for absorbing external radiation interference signals; the input stage chip is arranged on one side of the upper surface of the embedded substrate and is electrically connected to the embedded substrate through bumps, and the input stage chip is electrically connected to the embedded substrate through bumps. A metal shielding cover is set around the chip; the gain stage chip is stacked on the input stage chip and transmits signals to the input stage chip through silicon vias, and the surface of the gain stage chip is coated with a layer of radiation protection coating; the output stage chip is located on the gain stage chip and connected to the gain stage chip through silicon vias, and an electromagnetic shielding layer is set around the output stage chip; the control stage chip is arranged on the output stage chip and is connected to the gain stage chip through metal connections or silicon vias, and an isolation belt is set around the control stage chip; the upper surface of the embedded substrate is also formed with redistribution lines connected to the input and output pins of each chip, and a radiation protection ring is set around the redistribution lines.

[0007] Preferably, the surface of the redistribution line is coated with a passivation layer, on which solder balls or metal columns serving as external connection pins of the package structure are made, and a radiation shielding cover is provided around the solder balls or metal columns.

[0008] Preferably, the interior of the through silicon via is filled with a highly conductive metal material, both ends of the through silicon via are connected to the circuit inside the corresponding chip through metal wires, and the area around the through silicon via is filled with radiation protection material.

[0009] Preferably, the input stage chip includes an input stage circuit, the gain stage chip includes a reconfigurable capacitor array dynamic impedance matching network, and the output stage chip includes an output stage circuit;

[0010] The input stage circuit is used to receive an input signal and output the input signal to the reconfigurable capacitor array dynamic impedance matching network after processing;

[0011] The reconfigurable capacitor array dynamic impedance matching network includes a transformer and a reconfigurable capacitor array integrated in the transformer; the reconfigurable capacitor array is used to change its capacitance value according to a control signal to change the impedance characteristics of the matching network to affect the gain of the gain amplifier;

[0012] The output stage circuit is used to receive the output signal processed by the reconfigurable capacitor array dynamic impedance matching network and amplify and output it.

[0013] Preferably, the capacitor unit in the reconfigurable capacitor array is implemented by cascading a MOS tube and a capacitor, and the structure of the capacitor unit is: the source and drain of the MOS tube are connected together, and the connection point is node A, node A is connected to the control signal input end, the common end connected to the source and drain of the MOS tube is grounded through a capacitor in series, and the control signal changes the equivalent capacitance value of the capacitor array by controlling the conduction and disconnection of the MOS tube; the gate of the MOS tube is connected to the control signal output end, and the gate voltage of the MOS tube is controlled by a digital signal to realize the on-off of the capacitor to change the impedance characteristics of the matching network.

[0014] Preferably, the control signal is generated by an external digital signal processing unit; the digital signal processing unit is connected to the input stage circuit, and the digital signal processing unit is used to generate a control signal according to the characteristics of the input signal; the control stage chip includes a matching network controller, and the matching network controller is connected to the external digital signal processing unit and the reconfigurable capacitor array, and the matching network controller is used to convert the control signal generated by the digital signal processing unit into a level signal suitable for the reconfigurable capacitor array, and drive the reconfigurable capacitor array to realize the control of the capacitor on and off.

[0015] Preferably, the transformer adopts a multi-winding transformer structure; the reconfigurable capacitor array is integrated between the primary winding and the secondary winding of the transformer.

[0016] Preferably, the input stage circuit includes a low noise amplifier for performing low noise amplification processing on the input signal to reduce noise introduced into the signal during the amplification process.

[0017] Preferably, the output stage circuit includes a power amplifier for power amplifying the signal processed by the reconfigurable capacitor array dynamic impedance matching network to meet the signal power requirements of the subsequent circuit, and an output matching network for matching the signal output by the power amplifier with the subsequent circuit to reduce signal reflection and improve signal transmission efficiency.

[0018] A packaging method for a gain amplifier, characterized in that it includes the following steps:

[0019] S1. Chip preparation, including the following steps:

[0020] S11. Perform wafer-level testing on the input-stage chip, gain-stage chip, output-stage chip, and control-stage chip of the gain amplifier body to screen out chips with qualified performance;

[0021] S12. Making gold bumps or solder bumps on the active surface of each chip;

[0022] S2. Chip stacking and bonding, specifically including the following steps:

[0023] S21. Place the input-stage chip at a predetermined position on the upper surface of the embedded substrate. Electrically connect the bumps on the input-stage chip to the connection points on the embedded substrate by thermocompression bonding or reflow soldering. During the bonding process, ensure that the metal shield surrounding the input-stage chip is well connected to the ground pins of the embedded substrate.

[0024] S22. Align the gain stage chip with the input stage chip, using through-silicon via (TSV) alignment technology to ensure vertical alignment of the TSVs. Bond the two chips together using thermocompression bonding or eutectic bonding. After bonding, cure the radiation protection coating on the gain stage chip.

[0025] S23. Stack the output-level chip and the control-level chip sequentially according to the method of S22, and pay attention to the setting of the electromagnetic shielding layer and the isolation belt between the chips;

[0026] S3. Wafer-level packaging, specifically including the following steps:

[0027] S31. The entire structure is subjected to photolithography to define the pattern of the redistribution line. Metal is then deposited in the photolithographically defined area by electroplating to form the redistribution line. During the formation of the redistribution line, a radiation protection ring is simultaneously formed around it and connected to the ground pin.

[0028] S32. After the redistribution line is formed, a passivation layer is coated;

[0029] S33. Form solder balls or metal pillars on the passivation layer, and after forming the solder balls or metal pillars, install a radiation shield around them.

[0030] Due to the adoption of the above technical solution, the technical progress achieved by the present invention is as follows.

[0031] This invention achieves a high degree of integration and reduces signal delay and loss. By integrating the individual chips using SIP packaging technology, it not only achieves a high degree of system integration but also significantly shortens the signal transmission path. For example, vertical signal transmission between the input-stage chip and the gain-stage chip is achieved through silicon vias (TSVs). This avoids the significant delays and losses caused by the multiple signal transitions between wiring layers in traditional planar interconnects. This allows for faster and more efficient signal transmission between chips, thereby improving the overall operating frequency and bandwidth performance of the gain amplifier.

[0032] The present invention can reduce signal interference: filling the wiring grooves and through-holes inside the embedded substrate with absorbing materials, and providing various radiation shielding structures (such as metal shielding covers, electromagnetic shielding layers, radiation protection coatings, etc.) around the chip can effectively absorb and shield external electromagnetic radiation interference signals, thereby helping to maintain signal purity, reduce signal distortion and crosstalk during transmission, and further improve the quality and reliability of signal transmission.

[0033] This invention improves gain adjustment accuracy: by employing a reconfigurable capacitor array based on MOS transistors and capacitor cascades, it achieves high-precision gain adjustment of the amplifier. This high-precision adjustment capability meets the demand for precise signal gain control in modern radio frequency systems. For example, in receivers, it can more accurately amplify weak signals, avoid signal distortion and noise amplification, and improve receiver sensitivity and signal-to-noise ratio.

[0034] This invention enhances the reconfigurability of the matching network: a reconfigurable capacitor array is integrated into the transformer, enabling dynamic reconfiguration of the matching network. This allows the gain amplifier to adapt to varying operating conditions and signal characteristics, such as varying frequency bands and signal strengths. In multi-band communication systems or frequency-agile systems, this reconfigurability can significantly improve system flexibility and adaptability, mitigating performance degradation caused by frequency or signal strength variations.

[0035] This invention optimizes the overall performance of the gain amplifier: Because the reconfigurable capacitor array dynamic impedance matching network can adjust matching performance in real time, it not only increases gain but also reduces noise figure and improves linearity. Adopting this technical solution in preamplifiers or intermediate frequency amplifiers throughout a radio frequency system can enhance the system's signal processing capabilities, reduce power consumption, and improve communication quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 This is a principle block diagram of the gain amplifier body of the present invention. DETAILED DESCRIPTION

[0037] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0038] A gain amplifier comprises a gain amplifier body and a packaging structure, wherein the gain amplifier body comprises an input stage chip, a gain stage chip, an output stage chip, a control stage chip and an external digital signal processing unit; and the packaging structure is used to encapsulate the input stage chip, the gain stage chip, the output stage chip and the control stage chip of the gain amplifier body.

[0039] like Figure 1As shown, the input stage chip includes an input stage circuit, the gain stage chip includes a reconfigurable capacitor array dynamic impedance matching network, the output stage chip includes an output stage circuit, and the control stage chip includes a matching network controller.

[0040] The input stage receives the input signal, processes it, and then outputs it to the reconfigurable capacitor array dynamic impedance matching network. The input stage includes a low-noise amplifier (LNA), which amplifies the input signal with low noise, thereby reducing noise introduced during the amplification process. The LNA can be designed using CMOS technology. For example, a common-source amplifier structure can be used to achieve the desired gain and noise performance by properly selecting parameters such as transistor size, bias voltage, and load resistance.

[0041] Specifically, a CMOS transistor suitable for RF applications is selected. Based on design requirements, the transistor's width-to-length ratio is adjusted to control its transconductance. An appropriate bias voltage is set to ensure the transistor operates at a suitable quiescent operating point. Active loads, such as current source loads, can be used as load resistors to increase the amplifier's output resistance and gain. Furthermore, to reduce noise, noise suppression techniques such as source degeneracy inductors can be employed at the input.

[0042] The reconfigurable capacitor array dynamic impedance matching network includes a transformer and a reconfigurable capacitor array integrated in the transformer. The reconfigurable capacitor array is used to change its capacitance value according to a control signal, thereby changing the impedance characteristics of the matching network to affect the gain of the gain amplifier.

[0043] Specifically, the capacitor units in the reconfigurable capacitor array are implemented using a cascade connection of MOS transistors and capacitors. The capacitor unit structure is as follows: the source and drain of the MOS transistor are connected together, with the connection point being node A, which is connected to the control signal input terminal. The common terminal where the source and drain of the MOS transistor are connected is connected to ground via a series capacitor. The control signal controls the conduction and disconnection of the MOS transistor, thereby changing the equivalent capacitance value of the capacitor array. Simultaneously, the gate of the MOS transistor is connected to the control signal output terminal. The gate voltage of the MOS transistor is controlled by a digital signal, thereby switching the capacitor on and off, thereby changing the impedance characteristics of the matching network.

[0044] Select a suitable MOS transistor using a CMOS process, whose parameters such as threshold voltage must meet the circuit design requirements. The capacitance value of the series capacitor is determined by factors such as the required resolution of the circuit. For example, if higher resolution is required, a smaller capacitor value can be selected, but the impact on the overall capacitance value and circuit performance must also be considered.

[0045] The transformer uses a multi-winding transformer structure, combining multiple capacitor units described above into a reconfigurable capacitor array, which is integrated between the transformer's primary and secondary windings. During the integration process, layout and routing must be carefully considered to minimize parasitic effects. For example, a symmetrical layout is employed, with capacitor units evenly distributed around the transformer, and routing is kept as short and straight as possible to minimize parasitic effects such as wiring capacitance and inductance.

[0046] For easier control, the reconfigurable capacitor array can be grouped according to a specific pattern, with each group of capacitor units controlled by a single control signal. For example, if the reconfigurable capacitor array is divided into n groups, each containing m capacitor units, then the capacitance of the entire reconfigurable capacitor array can be effectively controlled using n control signals.

[0047] The digital signal processing unit is used to generate a control signal. The digital signal processing unit is connected to the input stage circuit. The digital signal processing unit is used to generate a control signal according to the frequency, amplitude and other characteristics of the input signal, thereby controlling the on and off of the capacitors in the reconfigurable capacitor array and realizing precise adjustment of the gain of the gain amplifier.

[0048] The matching network controller is connected between the external digital signal processing unit and the reconfigurable capacitor array. The matching network controller is used to convert the control signal generated by the digital signal processing unit into a level signal suitable for the reconfigurable capacitor array, and drive the reconfigurable capacitor array to realize the control of the capacitor on and off.

[0049] Specifically, the matching network controller includes a level conversion circuit and a control driving circuit.

[0050] The level conversion circuit is used to convert the control signal generated by the digital signal processing unit into a level signal suitable for the reconfigurable capacitor array. If the control signal generated by the digital signal processing unit is a digital logic level (such as a CMOS level), and the MOS transistors in the reconfigurable capacitor array require a higher drive level, a level conversion circuit is required to achieve the level conversion.

[0051] The level conversion circuit can use a charge pump circuit or a dedicated level conversion chip. For example, if the control signal generated by the digital signal processing unit is a 3.3V CMOS level, but the MOS transistors in the reconfigurable capacitor array require a 12V drive level to reliably turn on and off, a multi-stage charge pump circuit can be used to achieve the level conversion. The charge pump circuit achieves level increase by charging and discharging capacitors, which is highly efficient and has a simple circuit structure.

[0052] The control drive circuit is used to drive the MOS transistors in the reconfigurable capacitor array, controlling the capacitors' on and off states. Because a reconfigurable capacitor array may contain a large number of capacitor units, a circuit with strong drive capability is required to ensure that each MOS transistor accurately changes state according to the control signal.

[0053] This can be achieved using a multi-stage buffer or dedicated driver chip. For example, when there are a large number of MOS transistors in a capacitor array, the level conversion circuit at the first stage may not be able to drive the signal. In this case, a multi-stage buffer circuit can be used to gradually increase the driving capability to ensure that the MOS transistors in each capacitor unit can function properly.

[0054] The output stage circuit receives and amplifies the output signal processed by the reconfigurable capacitor array dynamic impedance matching network. The output stage circuit includes a power amplifier and an output matching network. The power amplifier amplifies the signal processed by the reconfigurable capacitor array dynamic impedance matching network to meet the signal power requirements of subsequent circuits. The output matching network matches the output signal of the power amplifier with the subsequent circuits, thereby reducing signal reflections and improving signal transmission efficiency.

[0055] Specifically, the power amplifier may adopt various topological structures based on CMOS technology, such as Class-AB or Class-E power amplifier structures.

[0056] The output matching network can be designed using classic π-type or T-type LC matching network methods. Based on the output impedance of the power amplifier and the input impedance of the subsequent circuitry, combined with the signal's operating frequency range, the inductance and capacitance values ​​of the LC matching network are determined through calculation and simulation. During layout design, consideration should also be given to minimizing the impact of parasitic effects, rationally placing the inductors and capacitors, and optimizing the wiring combinations across multiple layers using a multilayer PCB process.

[0057] When the gain amplifier is in use, the working principle is as follows:

[0058] (1) Signal input and preprocessing

[0059] When the input signal enters the input stage, the low-noise amplifier (LNA) amplifies it while minimizing the noise it introduces. The LNA's gain and other performance parameters are determined based on design requirements. At this stage, it primarily performs preliminary power amplification on the input signal, providing a sufficiently strong and low-noise input signal for subsequent circuits.

[0060] (2) Control signal generation and conversion

[0061] Externally, the digital signal processing unit generates a control signal based on the frequency, amplitude, and other characteristics of the received input signal. For example, if the input signal's frequency is high, the digital signal processing unit can use an algorithm to calculate the capacitance range that needs to be adjusted and generate the corresponding control signal. The control signal is typically a digital logic level signal and needs to be converted and adjusted by the level conversion circuit in the matching network controller to meet the control requirements of the reconfigurable capacitor array.

[0062] (3) Matching network adjustment

[0063] The converted control signal drives the MOS transistors in the reconfigurable capacitor array through a control drive circuit, changing their on and off states, thereby varying the capacitance of the reconfigurable capacitor array. Because the reconfigurable capacitor array is integrated between the primary and secondary windings of a transformer, changes in capacitance alter the transformer's matching performance. Transformer matching performance includes the relationship between input and output impedances, as well as the transmission characteristics of different frequency components. By changing this matching performance, the gain of the gain amplifier can be dynamically adjusted.

[0064] (4) Signal amplification output

[0065] After being adjusted by the reconfigurable capacitor array dynamic impedance matching network, the signal enters the output stage circuit. The power amplifier in the output stage automatically adjusts its operating state (such as adjusting the bias voltage or bias current) based on the signal strength and frequency characteristics processed by the reconfigurable capacitor array dynamic impedance matching network to ensure the output signal has appropriate gain and power. If the input signal strength after passing through the reconfigurable capacitor array dynamic impedance matching network is weak, the power amplifier can adjust its operating state to provide a higher amplification factor. If the input signal strength is strong, the operating state can be adjusted to avoid saturation distortion, thereby ensuring the quality of the output signal.

[0066] The package structure utilizes a multi-layer buried substrate as its foundation. The bottom layer of the buried substrate houses the power and ground planes, providing a stable power supply and excellent electromagnetic shielding. An isolation layer is added between the power and ground planes to reduce the impact of power supply noise on the signal.

[0067] The buried substrate is internally formed through processes like photolithography and etching to create trenches and vias for wiring, connecting signal lines between different layers. To enhance radiation protection, the trenches and vias are surrounded by absorbing materials, such as carbonyl iron powder composites, to absorb external radiation interference signals.

[0068] The input-stage chip is mounted on the top surface of the embedded substrate and is electrically connected to the embedded substrate via gold bumps or solder bumps. A metal shield is placed around the input-stage chip, which is grounded to prevent external radiation from interfering with the internal circuitry of the input-stage chip.

[0069] The gain stage chip is stacked on top of the input stage chip. To achieve precise capacitance adjustment and dynamic matching, signals are transmitted between the gain stage chip and the input stage chip via through-silicon vias (TSVs). The TSVs run vertically through the gain stage chip, and metal traces connect the TSVs to the corresponding capacitor array circuits within the gain stage chip. The surface of the gain stage chip is coated with a radiation shielding coating, such as an organic coating containing metal particles, to reduce the impact of radiation on the gain stage chip.

[0070] The output-stage chip sits above the gain-stage chip and also uses through-silicon via technology to connect to the underlying gain-stage chip, ensuring efficient signal transmission and matching. An electromagnetic shielding layer, constructed from high-permeability materials such as Permalloy, surrounds the output-stage chip to further reduce external radiation interference.

[0071] The control-stage chip is located above the output-stage chip. Communication between the control-stage chip and the gain-stage chip occurs via metal interconnects or short-distance through-silicon vias (TSVs). This allows for dynamic control of the capacitance of the capacitor array, thereby adjusting impedance matching. An isolation zone, filled with radiation-resistant material, is placed between the control-stage chip and the surrounding circuitry to reduce radiation coupling.

[0072] After the individual chips are stacked, the entire stack is packaged using wafer-level packaging technology. Redistribution lines (RDLs) are formed on the top surface of the embedded substrate through photolithography and electroplating processes. These redistribute the input and output pins of each chip to a layout that is more convenient for external connections. A grounded radiation shielding ring is placed around the RDLs to effectively shield against external radiation.

[0073] After the redistribution lines are formed, a passivation layer, such as silicon nitride (Si3N4) or silicon oxide (SiO2), is applied to their surface to protect the circuitry from the external environment. Solder balls or metal pillars are fabricated on the passivation layer to serve as external connection pins for the package structure. These solder balls can be traditional tin-lead solder balls or lead-free solder balls, such as tin-silver-copper (SAC) solder balls. A radiation shield is placed around the solder balls or metal pillars to prevent radiation from entering the package through the solder ball or metal pillar interface.

[0074] In the gain stage chip and the output stage chip, the diameter of the through silicon via can be designed according to the requirements of signal transmission, generally ranging from tens of microns to hundreds of microns.

[0075] TSVs are filled with highly conductive metal materials, such as copper (Cu). Electroplating and other methods can be used to ensure complete metal filling and good conductivity within the TSV. Metal traces connect the two ends of the TSV to the corresponding chip's internal circuitry, enabling vertical signal transmission and reducing signal transmission delays and losses. Radiation shielding materials, such as lead glass, are placed around the TSV to further enhance radiation protection.

[0076] A packaging method for a gain amplifier comprises the following steps:

[0077] S1. Chip preparation, including the following steps:

[0078] S11. Perform wafer-level testing on the input-stage chip, gain-stage chip, output-stage chip, and control-stage chip of the gain amplifier body to screen out chips with qualified performance.

[0079] S12. Fabricate gold bumps or solder bumps on the active surface of each chip. Gold bumps can be formed using chemical gold plating and photolithography; solder bumps can be prepared by screen printing solder paste followed by reflow soldering.

[0080] S2. Chip stacking and bonding, specifically including the following steps:

[0081] S21. Place the input-level chip at a predetermined position on the upper surface of the embedded substrate, and electrically connect the bumps on the input-level chip to the connection points on the embedded substrate through hot compression bonding or reflow soldering. During the bonding process, ensure that the metal shielding cover around the input-level chip is well connected to the ground pins of the embedded substrate.

[0082] S22. Align the gain stage chip with the input stage chip, use through-silicon via alignment technology to ensure the vertical alignment of the through-silicon vias, and then bond the two chips together through thermocompression bonding or eutectic bonding (if eutectic material is used). After bonding, cure the anti-radiation coating on the surface of the gain stage chip to ensure good adhesion and anti-radiation performance.

[0083] S23. Stack the output-level chips and the control-level chips in sequence according to the method of S22. During the stacking process, pay attention to the setting of the electromagnetic shielding layer and isolation belt between the chips to ensure the radiation protection effect.

[0084] S3. Wafer-level packaging, specifically including the following steps:

[0085] S31. The entire structure is photolithographically processed to define the pattern of the redistribution line, and then metal is deposited in the photolithographically defined area through an electroplating process to form the redistribution line. In the process of forming the redistribution line, an anti-radiation protection ring is synchronously produced around it and connected to the ground pin.

[0086] S32. After the redistribution lines are formed, apply a passivation layer. Chemical vapor deposition (CVD) or spin coating can be used to deposit the passivation layer. Then, photolithography and etching processes are used to pattern the passivation layer, exposing the pad locations for external pin connections. Before applying the passivation layer, inspect the chip and redistribution lines to ensure that the radiation protection coating and shielding layer are intact.

[0087] S33. Fabricate solder balls or metal pillars on the passivation layer. For solder ball fabrication, a ball placement process can be used to place pre-prepared solder balls on the pads via reflow soldering. For metal pillar fabrication, electroplating or chemical plating can be used to grow metal pillars on the pads. After fabricating the solder balls or metal pillars, install a radiation shield around them.

Claims

1. A gain amplifier, characterized in that: It includes a gain amplifier body and a packaging structure for packaging the gain amplifier body; the gain amplifier body includes an input stage chip, a gain stage chip, an output stage chip and a control stage chip; The input stage chip includes an input stage circuit, the gain stage chip includes a reconfigurable capacitor array dynamic impedance matching network, and the output stage chip includes an output stage circuit; The input stage circuit is used to receive an input signal and output the input signal to the reconfigurable capacitor array dynamic impedance matching network after processing; The reconfigurable capacitor array dynamic impedance matching network includes a transformer and a reconfigurable capacitor array integrated in the transformer; the reconfigurable capacitor array is used to change its capacitance value according to a control signal to change the impedance characteristics of the matching network to affect the gain of the gain amplifier; The output stage circuit is used to receive the output signal processed by the reconfigurable capacitor array dynamic impedance matching network and amplify and output it; The control signal is generated by an external digital signal processing unit; the digital signal processing unit is connected to the input stage circuit, and the digital signal processing unit is used to generate a control signal according to the characteristics of the input signal; the control stage chip includes a matching network controller, which is connected to the external digital signal processing unit and the reconfigurable capacitor array, and is used to convert the control signal generated by the digital signal processing unit into a level signal suitable for the reconfigurable capacitor array, and drive the reconfigurable capacitor array to realize the control of the capacitor on and off; The packaging structure includes a multi-layer embedded substrate, wherein the bottom layer of the embedded substrate is provided with a power plane and a ground plane, and the interior of the embedded substrate is formed with grooves and through-holes for wiring to connect signal lines between different layers, and the grooves and through-holes are filled with absorbing material for absorbing external radiation interference signals; the input-stage chip is arranged on one side of the upper surface of the embedded substrate and is electrically connected to the embedded substrate through bumps, and a metal shielding cover is arranged around the input-stage chip; the gain-stage chip is stacked on the input-stage chip and transmits signals to the input-stage chip through silicon vias, and the surface of the gain-stage chip is coated with a layer of radiation protection coating; the output-stage chip is located on the gain-stage chip and is connected to the gain-stage chip through silicon vias, and an electromagnetic shielding layer is arranged around the output-stage chip; the control-stage chip is arranged on the output-stage chip and is communicatively connected to the gain-stage chip through metal connections or silicon vias, and an isolation belt is arranged around the control-stage chip; the upper surface of the embedded substrate is also formed with redistribution lines connected to the input and output pins of each chip, and a radiation protection ring is arranged around the redistribution lines.

2. A gain amplifier according to claim 1, characterized in that: The surface of the redistribution line is coated with a passivation layer, on which solder balls or metal columns serving as external connection pins of the packaging structure are made, and a radiation shielding cover is provided around the solder balls or metal columns.

3. The gain amplifier according to claim 1, wherein: The through silicon via is filled with a highly conductive metal material, both ends of the through silicon via are connected to the circuit inside the corresponding chip through metal wires, and the area around the through silicon via is filled with radiation protection material.

4. The gain amplifier according to claim 1, wherein: The capacitor unit in the reconfigurable capacitor array is implemented by cascading a MOS transistor and a capacitor. The structure of the capacitor unit is as follows: the source and drain of the MOS transistor are connected together, and the connection point is node A, which is connected to the control signal input terminal. The common terminal connected to the source and drain of the MOS transistor is grounded via a capacitor connected in series. The control signal changes the equivalent capacitance value of the capacitor array by controlling the conduction and disconnection of the MOS transistor. The gate of the MOS transistor is connected to the control signal output terminal, and the gate voltage of the MOS transistor is controlled by a digital signal to realize the switching of the capacitor to change the impedance characteristics of the matching network.

5. The gain amplifier according to claim 1, wherein: The transformer adopts a multi-winding transformer structure; the reconfigurable capacitor array is integrated between the primary winding and the secondary winding of the transformer.

6. The gain amplifier according to claim 1, wherein: The input stage circuit includes a low noise amplifier for performing low noise amplification processing on the input signal to reduce noise introduced into the signal during the amplification process.

7. The gain amplifier according to claim 1, wherein: The output stage circuit includes a power amplifier for amplifying the power of the signal processed by the reconfigurable capacitor array dynamic impedance matching network to meet the signal power requirements of the subsequent circuit, and an output matching network for matching the signal output by the power amplifier with the subsequent circuit to reduce signal reflection and improve signal transmission efficiency.

8. The packaging method of a gain amplifier according to claim 1, wherein: The following steps are involved: S1. Chip preparation, including the following steps: S11. Perform wafer-level testing on the input-stage chip, gain-stage chip, output-stage chip, and control-stage chip of the gain amplifier body to screen out chips with qualified performance; S12. Making gold bumps or solder bumps on the active surface of each chip; S2. Chip stacking and bonding, specifically including the following steps: S21. Place the input-stage chip at a predetermined position on the upper surface of the embedded substrate. Electrically connect the bumps on the input-stage chip to the connection points on the embedded substrate by thermocompression bonding or reflow soldering. During the bonding process, ensure that the metal shield surrounding the input-stage chip is well connected to the ground pins of the embedded substrate. S22. Align the gain stage chip with the input stage chip, using through-silicon via (TSV) alignment technology to ensure vertical alignment of the TSVs. Bond the two chips together using thermocompression bonding or eutectic bonding. After bonding, cure the radiation protection coating on the gain stage chip. S23. Stack the output-level chip and the control-level chip sequentially according to the method of S22, and pay attention to the setting of the electromagnetic shielding layer and the isolation belt between the chips; S3. Wafer-level packaging, specifically including the following steps: S31. The entire structure is subjected to photolithography to define the pattern of the redistribution line. Metal is then deposited in the photolithographically defined area by electroplating to form the redistribution line. During the formation of the redistribution line, a radiation protection ring is simultaneously formed around it and connected to the ground pin. S32. After the redistribution line is formed, a passivation layer is coated; S33. Form solder balls or metal pillars on the passivation layer, and after forming the solder balls or metal pillars, install a radiation shield around them.

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