Light-emitting structure and preparation method thereof

Abstract

The invention relates to a light-emitting structure and a preparation method thereof. The preparation method comprises the steps of providing a substrate; forming a first sub-pixel unit, a second sub-pixel unit and a third sub-pixel unit which are arranged at intervals on the chip area; the chip area is etched, a first pixel groove, a second pixel groove and a third pixel groove which expose the pixel units and are arranged at intervals are formed, and the first pixel groove, the second pixel groove and the third pixel groove correspond to the first sub-pixel unit, the second sub-pixel unit and the third sub-pixel unit respectively; the part, which is not removed, of the chip area forms an isolation retaining wall, the first isolation retaining wall is located between any two of the first pixel groove, the second pixel groove and the third pixel groove, and the second isolation retaining wall is located in the edge area of the chip area; a filter layer covering the pixel grooves is formed on the second surface, the first filter layer covers the first pixel grooves, and the second filter layer covers the second pixel grooves; and forming an extinction layer on the isolation retaining wall. Therefore, the display contrast of the light-emitting structure is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a light-emitting structure and a method for preparing the same. Background Art

[0002] Micro LED (Micro Light Emitting Diode) display is the next generation display technology emerging after liquid crystal display and OLED (Organic Light Emitting Diode) display. Micro LED display has many advantages such as self-luminescence, high efficiency, long life, and ultra-high resolution. It can be widely used in AR / VR near-eye display devices, wearable devices and other fields.

[0003] At present, the art realizes color conversion by setting different colors of color conversion materials on the blue light LED of the Micro LED chip, where the red color conversion material can convert blue light into red light, and the green color conversion material can convert blue light into green light, thereby realizing full-color display. In order to prevent light crosstalk, isolation walls are further set between different color conversion materials during actual preparation. However, when the Micro LED is exposed to external light, both its luminous area (the area where the LED is located) and the non-luminous area (the area where the isolation wall is located) reflect light, greatly reducing the display contrast. Summary of the invention

[0004] In view of this, the embodiments of the present application provide a light-emitting structure and a method for preparing the same in order to solve at least one problem existing in the background technology.

[0005] In a first aspect, an embodiment of the present application provides a method for preparing a light-emitting structure, comprising:

[0006] Providing a substrate, the substrate comprising a chip region and a scribe line region located at the periphery of the chip region, the substrate comprising a first surface and a second surface opposite to each other in a thickness direction;

[0007] forming a pixel unit on the chip region from the first surface side, the pixel unit comprising a first sub-pixel unit, a second sub-pixel unit and a third sub-pixel unit which are spaced apart from each other;

[0008] The chip region is etched from the second surface side to form a pixel groove exposing the pixel unit, the pixel groove includes a first pixel groove, a second pixel groove and a third pixel groove which are spaced apart from each other, the first pixel groove, the second pixel groove and the third pixel groove respectively correspond to the first sub-pixel unit, the second sub-pixel unit and the third sub-pixel unit; the unremoved portion of the chip region is formed as an isolation barrier wall, the isolation barrier wall includes a first isolation barrier wall and a second isolation barrier wall, the first isolation barrier wall is located between any two of the first pixel groove, the second pixel groove and the third pixel groove, the second isolation barrier wall is located at an edge area of ​​the chip region, and along the thickness direction of the substrate, the projection of the second isolation barrier wall surrounds the projection of the first isolation barrier wall;

[0009] forming a first color conversion layer and a second color conversion layer in the first pixel groove and the second pixel groove respectively;

[0010] forming a filter layer covering the pixel groove on the second surface, the filter layer comprising a first filter layer and a second filter layer, the first filter layer covering the first pixel groove, and the second filter layer covering the second pixel groove;

[0011] A matte layer is formed on the isolation retaining wall.

[0012] In combination with the first aspect of the present application, in an optional implementation, the substrate includes a plurality of the chip regions; the matte layer on the adjacent second isolation barrier wall defines a cutting path window, and the cutting path window exposes the cutting path region.

[0013] In conjunction with the first aspect of the present application, in an optional implementation,

[0014] The step of forming a filter layer covering the pixel groove on the second surface and forming a matte layer on the isolation retaining wall comprises:

[0015] forming a first filter material layer covering the pixel groove and the substrate on the second surface;

[0016] Performing a first patterning process on the first filter material layer to expose the second pixel groove, the third pixel groove and the cutting track area, and the first filter material layer on the first pixel groove is formed into the first filter layer;

[0017] forming a second filter material layer covering the pixel groove and the substrate on the second surface;

[0018] A second patterning process is performed on the second filter material layer to expose the first pixel groove, the third pixel groove and the cutting path area, and the second filter material layer on the second pixel groove is formed as the second filter layer; the stacked structure composed of the first filter material layer and the second filter material layer on the isolation retaining wall is formed as the extinction layer, and the first filter material layer and the second filter material layer filter light of different colors.

[0019] In combination with the first aspect of the present application, in an optional implementation manner, the filter layer also covers a portion of the isolation retaining wall.

[0020] In combination with the first aspect of the present application, in an optional implementation manner, the line width of the portion of the filter layer covering the isolation retaining wall is in a range of 0 μm-30 μm.

[0021] In a second aspect, an embodiment of the present application provides a light-emitting structure, including:

[0022] A substrate, comprising a chip region and a scribe line region located at the periphery of the chip region, the substrate comprising a first surface and a second surface opposite to each other in a thickness direction;

[0023] A pixel unit, located on the first surface side of the chip region, the pixel unit comprising a first sub-pixel unit, a second sub-pixel unit and a third sub-pixel unit that are spaced apart from each other;

[0024] a pixel groove located in the chip area and extending from the second surface side until the pixel unit is exposed, the pixel groove comprising a first pixel groove, a second pixel groove and a third pixel groove arranged at intervals from each other, the first pixel groove, the second pixel groove and the third pixel groove respectively corresponding to the first sub-pixel unit, the second sub-pixel unit and the third sub-pixel unit;

[0025] An isolation barrier wall, comprising a first isolation barrier wall and a second isolation barrier wall, wherein the first isolation barrier wall is formed by a portion of the chip region located between any two of the first pixel groove, the second pixel groove and the third pixel groove, and the second isolation barrier wall is formed by an edge region of the chip region, and in a thickness direction of the substrate, a projection of the second isolation barrier wall surrounds a projection of the first isolation barrier wall;

[0026] A first color conversion layer and a second color conversion layer are respectively located in the first pixel groove and the second pixel groove;

[0027] a filter layer, located on the second surface side and covering the pixel groove, the filter layer comprising a first filter layer and a second filter layer, the first filter layer covering the first pixel groove, and the second filter layer covering the second pixel groove;

[0028] The matting layer is located on the isolation retaining wall.

[0029] In conjunction with the second aspect of the present application, in an optional implementation, the substrate includes a plurality of the chip regions; the matte layer on the adjacent second isolation barrier wall defines a cutting path window, and the cutting path window exposes the cutting path region.

[0030] In combination with the second aspect of the present application, in an optional embodiment, the extinction layer includes a first filter material layer and a second filter material layer stacked in sequence, the first filter material layer and the second filter material layer filter light of different colors; the first filter material layer and the first filter layer are the same material layer, and the second filter material layer and the second filter layer are the same material layer.

[0031] In conjunction with the second aspect of the present application, in an optional implementation, the filter layer also covers a portion of the isolation retaining wall.

[0032] In conjunction with the second aspect of the present application, in an optional implementation manner, the line width of the portion of the filter layer covering the isolation retaining wall is in a range of 0 μm-30 μm.

[0033] The light-emitting structure and preparation method thereof provided in the embodiments of the present application provide an extinction layer on the isolation retaining wall, and utilize the extinction layer to absorb all light, thereby preventing the light irradiated on the isolation retaining wall from being reflected, thereby improving the display contrast of the light-emitting structure.

[0034] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0036] Figure 1 A schematic diagram of a process for preparing a light-emitting structure provided in an embodiment of the present application;

[0037] Figure 2 A schematic diagram of a cross-sectional structure of a pixel unit provided in an embodiment of the present application;

[0038] Figure 3 for Figure 2 Global layout of the structure shown;

[0039] Figure 4 for Figure 2 A schematic diagram of the arrangement of each sub-pixel unit in FIG.

[0040] Figure 5 A schematic diagram of the cross-sectional structure of a pixel groove provided in an embodiment of the present application;

[0041] Figure 6 for Figure 5 A layout of the structure shown;

[0042] Figure 7 A schematic diagram of the cross-sectional structure of a color conversion layer provided in an embodiment of the present application;

[0043] Figures 8 to 11 A schematic diagram of a cross-sectional structure of a light-emitting structure during the preparation process provided by an optional specific implementation manner;

[0044] Fig.12 is a schematic diagram of an exposure pattern on a first filter material layer;

[0045] Fig.13 is a schematic diagram of an exposure pattern on the second filter material layer;

[0046] Figures 14 to 18 A schematic diagram of a cross-sectional structure of a light-emitting structure during the preparation process provided in another optional specific implementation manner;

[0047] Fig.19 for Fig.10 and Fig.17 Global layout of the shown structure. DETAILED DESCRIPTION

[0048] The exemplary embodiments disclosed in the present application will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present application and to fully convey the scope disclosed in the present application to those skilled in the art. In the following description, a large number of specific details are given in order to provide a more thorough understanding of the present application. However, it is obvious to those skilled in the art that the present application can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present application, some technical features known in the art are not described; that is, all features of the actual embodiments are not described here, and the known functions and structures are not described in detail. In the accompanying drawings, for clarity, the sizes of layers, regions, elements and their relative sizes may be exaggerated. The same reference numerals represent the same elements throughout.

[0049] When an element or layer is referred to as "on ...", "adjacent to ..." other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. Although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, the first element, component, region, layer or part discussed below may be represented as the second element, component, region, layer or part. When the second element, component, region, layer or part discussed, it does not indicate that the application necessarily has the first element, component, region, layer or part.

[0050] Spatially relative terms such as "under", "below", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. In addition to the orientation shown in the figure, the spatially relative terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0051] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present application. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0052] In order to thoroughly understand the present application, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present application. The preferred embodiments of the present application are described in detail below, but in addition to these detailed descriptions, the present application may also have other implementation methods.

[0053] Figure 1 A schematic flow chart of a method for preparing a light-emitting structure provided in an embodiment of the present application is shown in the figure. The preparation method includes:

[0054] Step S101: providing a substrate, the substrate comprising a chip region and a scribe line region located outside the chip region, and the substrate comprising a first surface and a second surface opposite to each other in a thickness direction;

[0055] Step S102: forming a pixel unit on the chip region from the first surface side, the pixel unit comprising a first sub-pixel unit, a second sub-pixel unit and a third sub-pixel unit which are spaced apart from each other;

[0056] Step S103: etching the chip area from the second surface side to form a pixel groove exposing the pixel unit, the pixel groove includes a first pixel groove, a second pixel groove and a third pixel groove spaced apart from each other, the first pixel groove, the second pixel groove and the third pixel groove respectively corresponding to the first sub-pixel unit, the second sub-pixel unit and the third sub-pixel unit; the unremoved portion of the chip area is formed into an isolation barrier wall, the isolation barrier wall includes a first isolation barrier wall and a second isolation barrier wall, the first isolation barrier wall is located between any two of the first pixel groove, the second pixel groove and the third pixel groove, the second isolation barrier wall is located at the edge area of ​​the chip area, and the projection of the second isolation barrier wall surrounds the projection of the first isolation barrier wall along the thickness direction of the substrate;

[0057] Step S104: forming a first color conversion layer and a second color conversion layer in the first pixel groove and the second pixel groove respectively;

[0058] Step S105: forming a filter layer covering the pixel groove on the second surface, the filter layer comprising a first filter layer and a second filter layer, the first filter layer covers the first pixel groove, and the second filter layer covers the second pixel groove;

[0059] Step S106: forming a matte layer on the isolation retaining wall.

[0060] Therefore, by arranging a matt layer on the isolation retaining wall, the matt layer is used to absorb all light, thereby preventing the light irradiated on the isolation retaining wall from being reflected, thereby improving the display contrast of the light-emitting structure.

[0061] It should be noted that although Figure 1 The steps in the embodiment are shown in sequence according to the arrows, but these steps are not necessarily performed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be performed in other orders.

[0062] First, please refer to Figure 2 and Figure 3 , performing step S101: providing a substrate 100, the substrate 100 includes a chip area 110 and a cutting road area 120 located at the periphery of the chip area 110, and the substrate 100 includes a first surface 101 and a second surface 102 opposite to each other in the thickness direction.

[0063] The substrate 100 may be a sapphire substrate, a silicon carbide substrate, a gallium nitride substrate, a gallium arsenide substrate, a silicon substrate, or other semiconductor material substrates known in the art. In the embodiment of the present application, the substrate 100 may be a silicon substrate.

[0064] It should be noted that the plane where the first surface 101 and the second surface 102 of the substrate 100 are located, or strictly speaking, the center plane in the thickness direction of the substrate 100, is determined to be the plane where the substrate 100 is located, and the direction perpendicular to the plane where the substrate 100 is located is along the thickness direction of the substrate 100.

[0065] In the thickness direction of the substrate 100 , the projection of the scribe line region 120 surrounds the projection of the chip region 110 .

[0066] like Figure 3 As shown, in some embodiments, the substrate 100 includes a plurality of chip regions 110. In this embodiment, the substrate 100 can be understood as a wafer.

[0067] Next, please refer to Figures 2 to 4 , executing step S102: forming a pixel unit 200 on the chip area 110 from the first surface 101 side, the pixel unit 200 includes a first sub-pixel unit 210, a second sub-pixel unit 220 and a third sub-pixel unit 230 which are spaced apart from each other.

[0068] It should be noted that Figure 2 A schematic cross-sectional structure diagram of a pixel unit provided in an embodiment of the present application, Figure 3 for Figure 2 The global layout of the structure shown, Figure 2 Figures (a), (b) and (c) are respectively along Figure 3 Schematic diagram of the cross-sectional structure along the A-A' line, the B-B' line and the C-C' line; Figure 4 for Figure 2 The arrangement diagram of each sub-pixel unit in is also Figure 3 An enlarged schematic diagram of a pixel unit in FIG.

[0069] In some embodiments, the substrate 100 may be a growth substrate, and an epitaxial layer (not shown) is formed on the substrate 100 through an epitaxial growth process; a patterning process (such as photolithography, etching, etc.) is performed on the epitaxial layer to form a pixel unit 200.

[0070] Forming an epitaxial layer on the substrate 100 may include: sequentially growing a first conductive semiconductor layer (not shown in the figure), an active layer (not shown in the figure), and a second conductive semiconductor layer (not shown in the figure) on the epitaxial layer. The first conductive semiconductor layer may be an N-type conductive semiconductor layer, and the second conductive semiconductor layer may be a P-type conductive semiconductor layer; the active layer may be a multi-quantum well layer. Here, the first conductive semiconductor layer may also be referred to as a "first semiconductor layer", the second conductive semiconductor layer may also be referred to as a "second semiconductor layer", and the active layer may also be referred to as a "semiconductor light-emitting layer". The materials of the first conductive semiconductor layer and the second conductive semiconductor layer may include at least one of gallium nitride (GaN), gallium nitrogen arsenide (GaNAs), gallium phosphide (GaP), aluminum gallium arsenide (AlGaAs), and indium phosphide (InP).

[0071] It should be understood that Figure 4 It is only illustrated that the projection shape of the pixel unit 200 on the plane where the substrate 100 is located is a rectangle, and each pixel unit 200 includes three sub-pixel units. The present application does not exclude that the projection shape of the pixel unit on the plane where the substrate 100 is located is a triangle, a trapezoid, a pentagon or other suitable shapes. The present application also does not exclude the situation where the pixel unit 200 includes four, five or more sub-pixel units. Of course, in some specific embodiments, on the plane where the substrate 100 is located, the projection shapes of the first sub-pixel unit 210, the second sub-pixel unit 220, and the third sub-pixel unit 230 can be a rectangle, a trapezoid, a circle, a triangle or other suitable shapes; the projection shapes of the first sub-pixel unit 210, the second sub-pixel unit 220, and the third sub-pixel unit 230 can be the same or different. The present application does not specifically limit this.

[0072] In some embodiments, please refer to Figure 4 An isolation channel is formed between each sub-pixel unit, and the isolation channel includes a first sub-channel 201, a second sub-channel 202 and a third sub-channel 203; wherein the first sub-channel 201 is located between the first sub-pixel unit 210 and the second sub-pixel unit 220; the second sub-channel 202 is located between the first sub-pixel unit 210 and the third sub-pixel unit 230; the third sub-channel 203 is located between the second sub-pixel unit 220 and the third sub-pixel unit 230; one end of the first sub-channel 201 is connected to the second sub-channel 202 and the third sub-channel 203.

[0073] In this way, through the isolation effect of each sub-channel in the isolation channel, while ensuring that each sub-pixel unit is isolated from each other, each sub-pixel unit obtains a more reasonable distribution method and a suitable area contour, which is beneficial to adjust the arrangement method and light-emitting area size of multiple sub-pixel units of different colors.

[0074] In some embodiments, before executing step S103, the preparation method may further include: bonding a temporary carrier (not shown in the figure) on the first surface 101 side; flipping the substrate 100. Thus, the substrate 100 that has completed the preparation process of the pixel unit 200 is bonded to a temporary carrier, so as to perform the subsequent step S103; specifically, through the support of the temporary carrier, the steps of preparing the first pixel groove 131, the second pixel groove 132 and the third pixel groove 133 on the second surface 102 of the substrate 100 by photolithography, etching and other processes are implemented.

[0075] Next, please refer to Figure 5 , executing step S103: etching the chip area 110 from the second surface 102 side to form a pixel groove 130 exposing the pixel unit 200, the pixel groove 130 includes a first pixel groove 131, a second pixel groove 132 and a third pixel groove 133 arranged at intervals from each other, the first pixel groove 131, the second pixel groove 132 and the third pixel groove 133 respectively correspond to the first sub-pixel unit 210, the second sub-pixel unit 220 and the third sub-pixel unit 230; the unremoved portion of the chip area 110 is formed as an isolation barrier wall, the isolation barrier wall includes a first isolation barrier wall 111 and a second isolation barrier wall 112, the first isolation barrier wall 111 is located between any two of the first pixel groove 131, the second pixel groove 132 and the third pixel groove 133, the second isolation barrier wall 112 is located at the edge area of ​​the chip area 110, and along the thickness direction of the substrate 100, the projection of the second isolation barrier wall 112 surrounds the projection of the first isolation barrier wall 111.

[0076] It should be noted that Figure 5 Figures (a), (b) and (c) are respectively Figure 2 The (a), (b) and (c) in the figure correspond to each other. Figure 2 Schematic diagram of a structure formed by further executing the preparation method based on (a), (b) and (c) in FIG.

[0077] It can be understood that the first pixel groove 131 extends from the second surface 102 to the first surface 101 through the substrate 100, and the first pixel groove 131 corresponds to the first sub-pixel unit 210; the second pixel groove 132 extends from the second surface 102 to the first surface 101 through the substrate 100, and the second pixel groove 132 corresponds to the second sub-pixel unit 220; the third pixel groove 133 extends from the second surface 102 to the first surface 101 through the substrate 100, and the third pixel groove 133 corresponds to the third sub-pixel unit 230. In the thickness direction of the substrate 100, the depths of the first pixel groove 131, the second pixel groove 132, and the third pixel groove 133 are equal to the thickness of the substrate 100.

[0078] like Figure 6As shown, in the unremoved portion of the chip region 110, the portion of the first pixel groove 131 close to the second pixel groove 132 and the third pixel groove 133 is the first isolation retaining wall 111, and the portion of the first pixel groove 131 away from the second pixel groove 132 and the third pixel groove 133 is the second isolation retaining wall 112; the portion of the second pixel groove 132 close to the first pixel groove 131 and the third pixel groove 133 is the first isolation retaining wall 111, and the portion of the second pixel groove 132 away from the first pixel groove 131 and the third pixel groove 133 is the second isolation retaining wall 112; the portion of the third pixel groove 133 close to the first pixel groove 131 and the second pixel groove 132 is the first isolation retaining wall 111, and the portion of the third pixel groove 133 away from the first pixel groove 131 and the second pixel groove 132 is the second isolation retaining wall 112. The projection of the second isolation retaining wall 112 on the plane where the substrate 100 is located is specifically annular. The outer boundary of the second isolation barrier 112 can be understood as the boundary between the chip region 110 and the scribe line region 120 .

[0079] It is understandable that in the related art, after forming the pixel unit 200, it is usually chosen to additionally prepare an isolation retaining wall between each sub-pixel unit through a deposition process and an etching process; or, it is chosen to prepare an isolation retaining wall, a color conversion layer and other structural layers on a carrier substrate, and prepare the pixel unit 200 on another carrier substrate, and then bond and remove the carrier substrate. The preparation process is complicated, has high process requirements, high production costs, and the support of the isolation retaining wall is poor. Therefore, the present application adopts a substrate 100 that carries the pixel unit to prepare the isolation retaining wall, which is beneficial to improve the support strength of the isolation retaining wall, improve the structural stability of the light-emitting element, and reduce the difficulty and cost of production. In the embodiment of the present application, the substrate 100 is a silicon substrate, the material of the isolation retaining wall is silicon, and the isolation retaining wall is also called a "silicon wall".

[0080] In some embodiments, on the plane where the substrate 100 is located, the projection shapes of the first pixel groove 131, the second pixel groove 132 and the third pixel groove 133 may be rectangular, trapezoidal, circular, triangular or other suitable shapes; the projection shapes of the first pixel groove 131, the second pixel groove 132 and the third pixel groove 133 may be the same or different.

[0081] In some specific embodiments, please refer to Figure 4 and Figure 6, in the thickness direction of the substrate 100, the projection shapes of the first pixel groove 131, the second pixel groove 132 and the third pixel groove 133 are respectively the same as the projection shapes of the corresponding first sub-pixel unit 210, the second sub-pixel unit 220 and the third sub-pixel unit 230. Of course, in some other embodiments, the projection shapes of the first pixel groove 131, the second pixel groove 132 and the third pixel groove 133 may also be different from the projection shapes of the corresponding first sub-pixel unit 210, the second sub-pixel unit 220 and the third sub-pixel unit 230. This application does not make specific limitations on this.

[0082] In some embodiments, the line width of the isolation barrier wall is greater than the line width of the isolation channel, which is beneficial to further improve the structural strength and light-emitting effect of the light-emitting element.

[0083] Next, please refer to Figure 7 , executing step S104: forming a first color conversion layer 410 and a second color conversion layer 420 in the first pixel groove 131 and the second pixel groove 132 respectively.

[0084] It should be noted that Figure 7 Figures (a), (b) and (c) are respectively Figure 5 The (a), (b) and (c) in the figure correspond to each other. Figure 5 Schematic diagram of a structure formed by further executing the preparation method based on (a), (b) and (c) in FIG.

[0085] Optionally, the materials of the first color conversion layer 410 and the second color conversion layer 420 may include phosphors or quantum dots. When phosphors and quantum dots are excited by external energy, electronic transitions occur and energy is released in the form of light; and by adjusting the composition and size of phosphors and quantum dots, the luminescent color can be adjusted, so that each pixel slot emits light of different colors. Furthermore, the materials of the first color conversion layer 410 and the second color conversion layer 420 are both quantum dots.

[0086] The first sub-pixel unit 210 and the first color conversion layer 410 can constitute a first sub-pixel, the second sub-pixel unit 220 and the second color conversion layer 420 can constitute a second sub-pixel, and the third sub-pixel unit 230 constitutes a third sub-pixel. In this embodiment, the first sub-pixel is a red sub-pixel, the second sub-pixel is a green sub-pixel, and the third sub-pixel is a blue sub-pixel. The red sub-pixel, the green sub-pixel, and the blue sub-pixel can constitute a light-emitting pixel unit (full-color LED chip) to emit red, green, and blue light. Therefore, the first color conversion layer 410 can be a red color conversion layer, and the second color conversion layer 420 can be a green color conversion layer.

[0087] It should be noted that the pixel unit can be understood as a "light-emitting chip", the sub-pixel unit can be understood as a "light-emitting core particle", the light-emitting chip can be a blue light chip or an ultraviolet light chip; the light-emitting chip can be a Micro LED chip. The red, green and blue sub-pixels use the same light-emitting chip, and the materials and light-emitting characteristics of the light-emitting areas of each sub-pixel are highly consistent, which is conducive to improving the display effect and long-term stability of the light-emitting structure (full-color LED wafer).

[0088] In some embodiments, on the plane where the substrate 100 is located, the projection area of ​​the third pixel groove 133 is smaller than the projection area of ​​the first pixel groove 131 and smaller than the projection area of ​​the second pixel groove 132. In this way, it is beneficial to expand the filling area of ​​the first color conversion layer 410 and the second color conversion layer 420, reduce the difficulty of filling the first color conversion layer 410 and the second color conversion layer 420, and reduce the blue light radiation intensity per unit area of ​​the first color conversion layer 410 and the second color conversion layer 420, thereby increasing the service life of the first color conversion layer 410 and the second color conversion layer 420.

[0089] Optionally, the preparation method may further include: forming an optical material layer 300 in the third pixel groove 133 , and the optical material layer 300 may include a third color conversion layer (not shown in the figure) and / or a light diffusion layer (not shown in the figure).

[0090] In some embodiments, the light emitted by the pixel unit 200 is blue light, and the optical material layer 300 may be a light diffusion layer. It is understandable that the material of the light diffusion layer includes diffusion particles, and the diffusion particles include organic materials, inorganic materials, and organic-inorganic composite materials, such as polystyrene, silicon dioxide, titanium dioxide, etc. The light diffusion performance is achieved by mixing the light diffusion particles into the interior or surface of the matrix and utilizing the reflection and refraction of light between the diffusion particles.

[0091] In other embodiments, the light emitted by the pixel unit 200 is ultraviolet light, the optical material layer 300 may include a third color conversion layer, or the optical material layer may include a third color conversion layer and a light diffusion layer, and the light diffusion layer is located between the third color conversion layer and the third sub-pixel unit 230; wherein the third color conversion layer is a blue color conversion layer.

[0092] Optionally, before executing step S104, the preparation method may include: forming a light diffusion layer (not shown in the figure) in the first pixel groove 131 and the second pixel groove 132; in the thickness direction of the substrate 100, the thickness of the light diffusion layer is less than the depth of the first pixel groove 131 and the second pixel groove 132. Providing the light diffusion layer is conducive to the quantum dots receiving uniform light irradiation, thereby effectively reducing the light intensity at the center of the quantum dots, greatly improving the light stability of the quantum dots, and improving the situation where the local quantum dots are prone to light quenching due to excessive central light intensity, effectively extending the luminescence life.

[0093] It can be understood that, in actual preparation, the light diffusion layers in the first pixel groove 131 , the second pixel groove 132 , and the third pixel groove 133 can be prepared in the same process.

[0094] Next, please refer to Fig. 9 and Fig.15 , step S105 is performed: forming a filter layer covering the pixel groove on the second surface 102, the filter layer comprising a first filter layer 511 and a second filter layer 521, the first filter layer 511 covers the first pixel groove 131, and the second filter layer 521 covers the second pixel groove 132. It can be understood that it is difficult for the color conversion material to absorb all the light incident on the pixel unit. Adding a corresponding filter layer on the color conversion layer to absorb the residual light is conducive to further improving the color purity of the light emitted by each sub-pixel, so as to more accurately control the display color; and it is conducive to improving the blackness of the light-emitting structure, which can reduce the reflection of the light-emitting element to the ambient light, thereby improving the contrast.

[0095] Optionally, the filter layer further includes a third filter layer (not shown in the figure), and the third filter layer covers the third pixel groove 133 .

[0096] In some specific embodiments, the filter layer may be a color filter (CF) that can only pass light within a specific wavelength range, and the type of the filter can be set according to the color of the light to be emitted. In this embodiment, the first filter layer 511 may be a red filter layer (CF-R), the second filter layer 521 may be a green filter layer (CF-G), and the third filter layer may be a blue filter layer (CF-B). When the light emitted by each sub-pixel area is blue light, the red filter layer and the green filter layer may be filter materials for filtering out the blue light that is not absorbed by the light conversion material, and the blue filter layer may be a transparent layer or a filter material for filtering wavelengths other than blue light.

[0097] Please refer to Fig. 9 and Fig.16 , execute step S106: form a matte layer 600 on the isolation retaining wall. It can be understood that in this embodiment, the isolation retaining wall is prepared by the substrate 100. The material of the conventional substrate has a certain reflectivity. Under the irradiation of ambient light, the top surface of the isolation retaining wall will reflect the ambient light, so that the non-luminous area of ​​the light-emitting structure (the area where the isolation retaining wall is located) can also emit light, which greatly affects the display contrast of the light-emitting structure. Therefore, the present application sets a matte layer 600 on the isolation retaining wall, uses the matte layer 600 to absorb the incident ambient light, improves the blackness of the light-emitting structure, reduces the reflection of the ambient light by the light-emitting element, and thus improves the contrast.

[0098] In some embodiments, please refer to Fig. 9 , Fig.16 and Fig.19 , the substrate 100 includes a plurality of chip regions 110; the matt layer 600 on the adjacent second isolation barrier wall 112 defines a cutting path window 121, and the cutting path window 121 exposes the cutting path region 120. In the present application, the matt layer 600 includes a first portion and a second portion, the first portion is a portion of the matt layer 600 located on the first isolation barrier wall 111, and the second portion is a portion of the matt layer 600 located on the second isolation barrier wall 112, and the first portion and the second portion are connected to each other.

[0099] It can be understood that the second isolation barrier 112 is located at the edge area of ​​the chip area 110, and the outer boundary of the second isolation barrier 112 can be understood as the boundary of the chip area 110, and is also the boundary of the cutting road area 120. The outer side wall of the second part of the matt layer 600 corresponds to the boundary of the second isolation barrier 112. In other words, the outer side wall of the second part of the matt layer 600 corresponds to the boundary of the cutting road area 120. Therefore, for two adjacent chip areas 110 and the cutting road area 120 therebetween, the window formed between the outer side walls of the two adjacent second parts exposes the cutting road area 120.

[0100] It is understandable that the art generally chooses to form a mark on the cutting road area 120 during the preparation process, and before the wafer is diced, the wafer surface morphology image is obtained by the device to find the mark and determine the position of the cutting road area 120. In this process, the device emits light to the surface of the wafer, and generates a wafer surface morphology image based on the light reflected by the wafer. Among them, the isolation retaining wall and the cutting road area 120 will both reflect the incident light of the device, resulting in a low contrast of the wafer surface morphology image, making it difficult to accurately find the mark position, thereby affecting the dicing and causing waste. Therefore, the present application sets a matte layer 600 on the isolation retaining wall, and exposes the cutting road area 120 through the cutting road window 121 defined by the pattern of the matte layer 600. When the device irradiates the wafer surface, the isolation retaining wall will not reflect light, while the cutting road area 120 will reflect light. The display contrast of the light-emitting structure is high, and the contrast of the image obtained by the device is strong, so the position of the cutting road can be obtained relatively easily and accurately.

[0101] On the plane where the substrate 100 is located, the projection of the second isolation barrier 112 is annular, the projection of the scribe area 120 is annular, the side of the second isolation barrier 112 away from the pixel groove is the scribe area 120, and the projection of the scribe area 120 surrounds the projection of the second isolation barrier 112. In some embodiments, on the plane where the substrate 100 is located, the projection shape of the second portion is the same as the projection shape of the second isolation barrier 112, and the projection area of ​​the second portion is smaller than the projection area of ​​the second isolation barrier 112. In this embodiment, the line width of the scribe window 121 is greater than the line width of the scribe area 120. More space is reserved for dicing, and it is easier to identify the position of the scribe area 120 before dicing.

[0102] In other embodiments, on the plane where the substrate 100 is located, the projection of the second portion overlaps with the projection of the second isolation barrier 112. In this embodiment, the line width of the cutting street window 121 is equal to the line width of the cutting street area 120. It is avoided that the matte layer 600 is not formed in a part of the chip area 110, thereby affecting the contrast of the light-emitting structure.

[0103] In an optional specific implementation, please refer to Figure 8 and Fig. 9 , step S105 and step S106 include:

[0104] A first filter material layer 510 is formed on the second surface 102 to cover the pixel groove 130 and the substrate 100;

[0105] Performing a first patterning process on the first filter material layer 510 to expose the second pixel groove 132 , the third pixel groove 133 and the cutting lane area 120 , and the first filter material layer 510 on the first pixel groove 131 is formed into a first filter layer 511 ;

[0106] A second filter material layer 520 is formed on the second surface 102 to cover the pixel groove 130 and the substrate 100;

[0107] A second patterning process is performed on the second filter material layer 520 to expose the first pixel groove 131, the third pixel groove 133 and the cutting path area 120, and the second filter material layer 520 on the second pixel groove 132 is formed as a second filter layer 521; the stacked structure composed of the first filter material layer 510 and the second filter material layer 520 on the isolation retaining wall is formed into an extinction layer 600, and the first filter material layer 510 and the second filter material layer 520 filter light of different colors.

[0108] Therefore, step S105 and step S106 are performed in the same process, and when the first filter layer 511 and the second filter layer 521 are prepared, the extinction layer 600 is formed simultaneously, thereby reducing the number of processes and improving production efficiency.

[0109] It should be noted that Figure 8 and Fig. 9 In each figure, (a), (b) and (c) are respectively Figure 7 The (a), (b) and (c) in the figure correspond to each other. Figure 7 A schematic diagram of a structure formed by sequentially executing the preparation method based on (a), (b) and (c) in FIG.

[0110] Optionally, the materials of the first filter material layer 510 and the second filter material layer 520 include color photoresist; and the first patterning process and the second patterning process include photolithography processes.

[0111] Specifically, please refer to Fig.12 During the first photolithography, the first exposure area 5101 includes the portion of the first filter material layer 510 corresponding to the first pixel groove 131 and the portion corresponding to the isolation barrier wall; the first non-exposure area 5102 includes the portion of the first filter material layer 510 corresponding to the second pixel groove 132, the portion corresponding to the third pixel groove 133, and the portion corresponding to the cutting track area 120. The first filter material layer 510 is a negative photoresist. The first filter material layer 510 in the first exposure area 5101 is retained, and the first filter material layer 510 in the first non-exposure area 5102 is removed. Please refer to Fig.13 During the second photolithography, the second exposure area 5201 includes the portion of the second filter material layer 520 corresponding to the second pixel groove 132 and the portion corresponding to the isolation barrier wall; the second non-exposure area 5202 includes the portion of the second filter material layer 520 corresponding to the first pixel groove 131, the portion corresponding to the third pixel groove 133, and the portion corresponding to the cutting track area 120. The second filter material layer 520 is a negative photoresist. The second filter material layer 520 in the second exposure area 5201 is retained, and the second filter material layer 520 in the second non-exposure area 5202 is removed. It can be understood that in the related art, the first filter layer 511 and the second filter layer 521 are usually obtained by two photolithography processes. In the present application, the extinction layer 600 is formed synchronously without increasing the number of exposures, and the improvement to the production process is small.

[0112] Since the first filter material layer 510 and the second filter material layer 520 only allow the corresponding color spectrum to pass through, after the two filter material layers are stacked, the outgoing light after passing through the second filter material layer 520 can no longer pass through the first filter material layer 510, and vice versa, achieving an extinction effect. As a result, all visible light maintains a low transmittance, and the isolation retaining wall achieves a low reflectivity effect. In this embodiment, the stacked structure composed of the first filter material layer 510 and the second filter material layer 520 can also be referred to as a "CF stacked structure". The first filter material layer 510 is specifically a red filter material layer, such as a red photoresist layer, and the second filter material layer 520 is specifically a green filter material layer, such as a green photoresist layer.

[0113] It should be noted that Figure 8 and Fig. 9 The preparation sequence of first forming the first filter material layer 510 and then forming the second filter material layer 520 is only schematically shown, but the present application does not exclude the preparation sequence of first forming the second filter material layer 520 and then forming the first filter material layer 510, and the present application does not limit this.

[0114] In some embodiments, the preparation method further includes: forming a third filter material layer (not shown in the figure) covering the pixel groove 130 and the substrate 100 on the second surface 102; performing a third patterning process on the third filter material layer to expose the first pixel groove 131, the second pixel groove 132 and the cutting road area 120, and the third filter material layer on the third pixel groove 133 is formed as a third filter layer; the stacked structure consisting of the first filter material layer 510, the second filter material layer 520 and the third filter material layer on the isolation retaining wall is formed into an extinction layer 600, and the first filter material layer 510, the second filter material layer 520 and the third filter material layer filter different colors of light. The third filter material layer is specifically a blue filter material layer, such as a blue photoresist layer. It can be understood that the present application does not limit the order of forming the first filter material layer 510, the second filter material layer 520 and the third filter material layer.

[0115] In another optional specific implementation, please refer to Figures 14 to 16 , step S105 and step S106 include:

[0116] A first filter material layer 510 is formed on the second surface 102 to cover the pixel groove 130 and the substrate 100;

[0117] Performing a first patterning process on the first filter material layer 510 to expose the second pixel groove 132 , the third pixel groove 133 , the isolation barrier wall and the cutting road area 120 , and forming a first filter layer 511 covering the first pixel groove 131 ;

[0118] A second filter material layer 520 is formed on the second surface 102 to cover the pixel groove 130 and the substrate 100;

[0119] Performing a second patterning process on the second filter material layer 520 to expose the first pixel groove 131 , the third pixel groove 133 , the isolation barrier wall and the cutting road area 120 , and forming a second filter layer 521 covering the second pixel groove 132 ;

[0120] A matte material layer (not shown) is formed on the second surface 102 to cover the pixel groove 130 and the substrate 100 ;

[0121] A third patterning process is performed on the matte material layer to expose the pixel groove 130 and the cutting street area 120 to form a matte layer 600 on the isolation barrier wall.

[0122] In this specific implementation, after step S105 is completed, step S106 is performed through a photolithography process. In actual preparation, the photomask required for the two photolithography processes in step S105 can be a photomask currently in production, and only an additional photomask for performing the photolithography process in step S106 needs to be made, which makes minor changes to the photomask and is easier to adapt to existing production processes.

[0123] It should be noted that Figures 14 to 16 In each figure, (a), (b) and (c) are respectively Figure 7 The (a), (b) and (c) in the figure correspond to each other. Figure 7 A schematic diagram of a structure formed by sequentially executing the preparation method based on (a), (b) and (c) in FIG.

[0124] Optionally, the material of the matte layer 600 includes black photoresist. Black photoresist can absorb most of the light, effectively achieve a blackening effect, and improve the contrast of the light-emitting structure.

[0125] Please refer to Fig. 9 and Fig.15 Optionally, the filter layer also covers part of the isolation barrier wall. Thus, the requirement for overlay accuracy during actual preparation is reduced, a margin is reserved for the patterning process, and each filter layer is prevented from being formed on other pixel grooves to affect the luminescence of the sub-pixel.

[0126] In some embodiments, the line width of the portion of the filter layer covering the isolation retaining wall is in the range of 0 μm-30 μm. Thus, by controlling the line width in the range of 0 μm-30 μm, it is possible to moderately reduce the overlay accuracy requirements while ensuring that the light-emitting area of ​​the light-emitting structure does not change significantly. Furthermore, the line width of the portion of the filter layer covering the isolation retaining wall is in the range of 1 μm-5 μm, which is more conducive to balancing the overlay accuracy and the light-emitting effect.

[0127] Please refer to Fig.10 , Fig.17 and Fig.19 After executing step S106, the preparation method further includes: forming a protective cover layer 700, wherein the protective cover layer 700 covers the second surface 102, the filter layer and the extinction layer 600. It can be understood that by providing the protective cover layer 700, on the one hand, the structural strength of the light-emitting structure can be improved; on the other hand, the color conversion layer, the filter layer and other structures can be effectively isolated from the contact with the outside air. For example, when the material of the color conversion layer includes quantum dots, the problem of quantum dots fading or even deactivation due to water vapor and oxygen in the air can be reduced, thereby improving the service life of the quantum dots.

[0128] It should be noted that Fig.19 for Fig.10The layout of the structure shown is also Fig.17 The layout of the structure shown, Fig.10 A schematic diagram of a cross-sectional structure of a light-emitting structure during the preparation process provided in an optional specific implementation manner, Fig.17 A schematic diagram of a cross-sectional structure of a light-emitting structure during the preparation process provided in another optional specific implementation manner; Fig.10 and Fig.17 Figures (a), (b) and (c) are all along the Fig.19 Schematic diagram of the cross-sectional structure of the DD line, EE line and FF line.

[0129] The protective cover layer 700 can be formed by sputtering or evaporation. The material of the protective cover layer 700 can be an insulating material with high light transmittance to avoid affecting the color display of the light-emitting structure. For example, the material of the protective cover layer 700 includes inorganic materials such as silicon oxide (SiO2), silicon nitride (SiN), aluminum oxide (Al2O3), glass, sapphire, or transparent polymers such as silica gel and resin.

[0130] Please refer to Fig.10 and Fig.11 as well as Fig.17 and Fig.18 After step S106 , the preparation method may further include: scribing along the saw road window 121 to obtain a chip structure.

[0131] It should be noted that Fig.10 and Fig.11 In each figure, (a), (b) and (c) are respectively Fig. 9 The (a), (b) and (c) in the figure correspond to each other. Fig. 9 A schematic diagram of a structure formed by sequentially executing the preparation method based on (a), (b) and (c) in FIG. Fig.17 and Fig.18 In each figure, (a), (b) and (c) are respectively Fig.16 The (a), (b) and (c) in the figure correspond to each other. Fig.16 A schematic diagram of a structure formed by sequentially executing the preparation method based on (a), (b) and (c) in FIG.

[0132] The present application also provides a light emitting structure. Fig.11 and Fig.17 , the light emitting structure comprises:

[0133] The substrate 100 includes a chip region 110 and a scribe line region 120 located at the periphery of the chip region 110 , and the substrate 100 includes a first surface 101 and a second surface 102 opposite to each other in a thickness direction;

[0134] The pixel unit 200 is located on the first surface 101 side of the chip region 110, and the pixel unit 200 includes a first sub-pixel unit 210, a second sub-pixel unit 220 and a third sub-pixel unit 230 which are spaced apart from each other;

[0135] The pixel groove 130 is located in the chip area 110 and extends from the second surface 102 side until the pixel unit 200 is exposed. The pixel groove 130 includes a first pixel groove 131, a second pixel groove 132 and a third pixel groove 133 that are spaced apart from each other. The first pixel groove 131, the second pixel groove 132 and the third pixel groove 133 correspond to the first sub-pixel unit 210, the second sub-pixel unit 220 and the third sub-pixel unit 230 respectively.

[0136] The isolation barrier wall includes a first isolation barrier wall 111 and a second isolation barrier wall 112. The first isolation barrier wall 111 is formed by a portion of the chip region 110 located between any two of the first pixel groove 131, the second pixel groove 132 and the third pixel groove 133. The second isolation barrier wall 112 is formed by an edge region of the chip region 110. In the thickness direction of the substrate 100, the projection of the second isolation barrier wall 112 surrounds the projection of the first isolation barrier wall 111.

[0137] The first color conversion layer 410 and the second color conversion layer 420 are respectively located in the first pixel groove 131 and the second pixel groove 132;

[0138] A filter layer, located on the second surface 102 side and covering the pixel groove 130 , the filter layer includes a first filter layer 511 and a second filter layer 521 , the first filter layer 511 covers the first pixel groove 131 , and the second filter layer 521 covers the second pixel groove 132 ;

[0139] The matt layer 600 is located on the isolation retaining wall.

[0140] Therefore, by arranging the matt layer 600 on the isolation retaining wall, the matt layer 600 absorbs all light and prevents the light irradiated on the isolation retaining wall from being reflected, thereby improving the display contrast of the light emitting structure.

[0141] It can be understood that the first pixel groove 131 extends from the second surface 102 to the first surface 101 through the substrate 100, and the first pixel groove 131 corresponds to the first sub-pixel unit 210; the second pixel groove 132 extends from the second surface 102 to the first surface 101 through the substrate 100, and the second pixel groove 132 corresponds to the second sub-pixel unit 220; the third pixel groove 133 extends from the second surface 102 to the first surface 101 through the substrate 100, and the third pixel groove 133 corresponds to the third sub-pixel unit 230. In the thickness direction of the substrate 100, the depths of the first pixel groove 131, the second pixel groove 132, and the third pixel groove 133 are equal to the thickness of the substrate 100.

[0142] In the chip area 110, the portion of the first pixel groove 131 close to the second pixel groove 132 and the third pixel groove 133 is the first isolation barrier wall 111, and the portion of the first pixel groove 131 away from the second pixel groove 132 and the third pixel groove 133 is the second isolation barrier wall 112; the portion of the second pixel groove 132 close to the first pixel groove 131 and the third pixel groove 133 is the first isolation barrier wall 111, and the portion of the second pixel groove 132 away from the first pixel groove 131 and the third pixel groove 133 is the second isolation barrier wall 112; the portion of the third pixel groove 133 close to the first pixel groove 131 and the second pixel groove 132 is the first isolation barrier wall 111, and the portion of the third pixel groove 133 away from the first pixel groove 131 and the second pixel groove 132 is the second isolation barrier wall 112. The projection of the second isolation barrier wall 112 on the plane where the substrate 100 is located is specifically annular. Since the second isolation barrier 112 is formed by the edge region of the chip region 110 , the outer boundary of the second isolation barrier 112 can be understood as the boundary of the chip region 110 , and can also be understood as the boundary between the scribe line regions 120 .

[0143] Optionally, the materials of the first color conversion layer 410 and the second color conversion layer 420 may include phosphor or quantum dots. Further, the materials of the first color conversion layer 410 and the second color conversion layer 420 are both quantum dots.

[0144] The first sub-pixel unit 210 and the first color conversion layer 410 can constitute a first sub-pixel, the first sub-pixel unit 210 and the second color conversion layer 420 can constitute a second sub-pixel, and the third sub-pixel unit 230 constitutes a third sub-pixel. In this embodiment, the first sub-pixel is a red sub-pixel, the second sub-pixel is a green sub-pixel, and the third sub-pixel is a blue sub-pixel. The red sub-pixel, the green sub-pixel, and the blue sub-pixel can constitute a light-emitting pixel unit (full-color LED chip) to emit red, green, and blue light. Therefore, the first color conversion layer 410 can be a red color conversion layer, and the second color conversion layer 420 can be a green color conversion layer.

[0145] It should be noted that the pixel unit can be understood as a "light-emitting chip", the sub-pixel unit can be understood as a "light-emitting core particle", the light-emitting chip can be a blue light chip or an ultraviolet light chip; the light-emitting chip can be a Micro LED chip. The red, green and blue sub-pixels use the same light-emitting chip, and the materials and light-emitting characteristics of the light-emitting areas of each sub-pixel are highly consistent, which is conducive to improving the display effect and long-term stability of the light-emitting structure (full-color LED wafer).

[0146] Optionally, an optical material layer 300 is formed in the third pixel groove 133, and the optical material layer 300 may include a third color conversion layer (not shown in the figure) and / or a light diffusion layer (not shown in the figure). In some embodiments, the light emitted by the pixel unit 200 is blue light, and the optical material layer 300 may be a light diffusion layer. In other embodiments, the light emitted by the pixel unit 200 is ultraviolet light, and the optical material layer 300 may include a third color conversion layer, or the optical material layer may include a third color conversion layer and a light diffusion layer, and the light diffusion layer is located between the third color conversion layer and the third sub-pixel unit 230; wherein the third color conversion layer is a blue color conversion layer.

[0147] Optionally, a light diffusion layer (not shown) is formed between the first color conversion layer 410 and the first sub-pixel unit 210, and a light diffusion layer (not shown) is formed between the second color conversion layer 420 and the second sub-pixel unit 220. This is beneficial to prolonging the luminous life.

[0148] Optionally, the substrate 100 includes a plurality of chip regions 110; the matte layer 600 on the adjacent second isolation barrier walls 112 defines a scribe window 121, and the scribe window 121 exposes the scribe region 120. Thus, the position of the scribe region 120 can be obtained relatively easily and accurately.

[0149] As an optional specific implementation, please refer to Fig.11 The extinction layer 600 includes a first filter material layer 510 and a second filter material layer 520 stacked in sequence, and the first filter material layer 510 and the second filter material layer 520 filter light of different colors; the first filter material layer 510 and the first filter layer 511 are the same material layer, and the second filter material layer 520 and the second filter layer 521 are the same material layer. Since the first filter material layer 510 and the second filter material layer 520 only allow the corresponding color spectrum to pass through, after the two filter material layers are stacked, the outgoing light after passing through the second filter material layer 520 can no longer pass through the first filter material layer 510, and vice versa, achieving an extinction effect. As a result, all visible light maintains a low transmittance, and the isolation retaining wall achieves a low reflectance effect. In this embodiment, the stacked structure composed of the first filter material layer 510 and the second filter material layer 520 can also be called a "CF stacked structure".

[0150] Optionally, the materials of the first filter material layer 510 and the second filter material layer 520 include color photoresist. In this embodiment, the first filter material layer 510 is specifically a red filter material layer, such as a red photoresist layer, and the second filter material layer 520 is specifically a green filter material layer, such as a green photoresist layer.

[0151] Furthermore, the first filter material layer 510 and the first filter layer 511 are made of the same material layer, and the second filter material layer 520 and the second filter layer 521 are made of the same material layer. In actual preparation, the first filter material layer 510 and the second filter material layer 520 can be formed while preparing the first filter layer 511 and the second filter layer 521 to obtain a stacked structure. Thus, the production process is reduced and the production efficiency is improved.

[0152] Optionally, the filter layer includes a color filter (CF). The color filter can only pass light within a specific wavelength range. Further, the material of the filter layer includes color photoresist.

[0153] As another optional specific implementation, please refer to Fig.17 The material of the matt layer 600 includes black photoresist. Black photoresist can absorb most of the light, effectively achieve a blackening effect, and improve the contrast of the light-emitting structure.

[0154] Optionally, the filter layer also covers part of the isolation barrier wall, thereby reducing the requirement for overlay accuracy during actual preparation, leaving a margin for the photolithography process, and preventing each filter layer from being formed on other pixel grooves to affect the light-emitting area of ​​the sub-pixel.

[0155] Optionally, the line width of the portion of the filter layer covering the isolation barrier wall is in the range of 1 μm-5 μm. Thus, by controlling the line width in the range of 1 μm-5 μm, the requirements for overlay accuracy can be appropriately reduced while ensuring that the light emitting area of ​​the light emitting structure does not change significantly.

[0156] Please refer to Fig.10 and Fig.17 The light emitting structure further includes: a protective cover layer 700, covering the second surface 102, the filter layer and the extinction layer 600. This can improve the structural strength of the light emitting structure and effectively isolate the color conversion layer, the filter layer and other structures from the outside air.

[0157] It should be noted that the light-emitting structure embodiments and the light-emitting structure preparation method embodiments provided in the present application belong to the same concept; the technical features in the technical solutions recorded in the embodiments can be arbitrarily combined without conflict. However, it should be further noted that the light-emitting structure provided in the embodiments of the present application, the combination of its various technical features can already solve the technical problem to be solved by the present application; therefore, the light-emitting structure provided in the embodiments of the present application may not be limited by the light-emitting structure preparation method provided in the embodiments of the present application, and any light-emitting structure prepared by the preparation method that can form the light-emitting structure provided in the embodiments of the present application is within the scope of protection of the present application.

[0158] It should be understood that the above embodiments are exemplary and are not intended to include all possible implementations. Various modifications and changes may also be made on the basis of the above embodiments without departing from the scope of the present disclosure. Similarly, the various technical features of the above embodiments may also be combined arbitrarily to form other embodiments of the present application that may not be clearly described. Therefore, the above embodiments only express several implementations of the present application and do not limit the scope of protection of the patent of this application.

Claims

1. A method for preparing a light-emitting structure, characterized in that: include: Providing a substrate, the substrate comprising a chip region and a scribe line region located at the periphery of the chip region, the substrate comprising a first surface and a second surface opposite to each other in a thickness direction; forming a pixel unit on the chip region from the first surface side, the pixel unit comprising a first sub-pixel unit, a second sub-pixel unit and a third sub-pixel unit which are spaced apart from each other; The chip region is etched from the second surface side to form a pixel groove exposing the pixel unit, the pixel groove includes a first pixel groove, a second pixel groove and a third pixel groove which are spaced apart from each other, the first pixel groove, the second pixel groove and the third pixel groove respectively correspond to the first sub-pixel unit, the second sub-pixel unit and the third sub-pixel unit; the unremoved portion of the chip region is formed as an isolation barrier wall, the isolation barrier wall includes a first isolation barrier wall and a second isolation barrier wall, the first isolation barrier wall is located between any two of the first pixel groove, the second pixel groove and the third pixel groove, the second isolation barrier wall is located at an edge area of ​​the chip region, and along the thickness direction of the substrate, the projection of the second isolation barrier wall surrounds the projection of the first isolation barrier wall; forming a first color conversion layer and a second color conversion layer in the first pixel groove and the second pixel groove respectively; forming a filter layer covering the pixel groove on the second surface, the filter layer comprising a first filter layer and a second filter layer, the first filter layer covering the first pixel groove, and the second filter layer covering the second pixel groove; A matte layer is formed on the isolation retaining wall.

2. The method for preparing a light emitting structure according to claim 1, characterized in that: The substrate includes a plurality of chip regions; the matte layer adjacent to the second isolation barrier wall defines a cutting path window, and the cutting path window exposes the cutting path region.

3. The method for preparing a light emitting structure according to claim 2, characterized in that: forming a filter layer covering the pixel groove on the second surface; Forming a matte layer on the isolation retaining wall comprises: forming a first filter material layer covering the pixel groove and the substrate on the second surface; Performing a first patterning process on the first filter material layer to expose the second pixel groove, the third pixel groove and the cutting track area, and the first filter material layer on the first pixel groove is formed into the first filter layer; forming a second filter material layer covering the pixel groove and the substrate on the second surface; A second patterning process is performed on the second filter material layer to expose the first pixel groove, the third pixel groove and the cutting path area, and the second filter material layer on the second pixel groove is formed as the second filter layer; the stacked structure composed of the first filter material layer and the second filter material layer on the isolation retaining wall is formed as the extinction layer, and the first filter material layer and the second filter material layer filter light of different colors.

4. The method for preparing a light emitting structure according to claim 1, characterized in that: The filter layer also covers a portion of the isolation barrier wall.

5. The method for preparing a light emitting structure according to claim 4, characterized in that: The line width of the portion of the filter layer covering the isolation barrier wall is in a range of 0 μm to 30 μm.

6. A light emitting structure, characterized in that: include: A substrate, comprising a chip region and a scribe line region located at the periphery of the chip region, the substrate comprising a first surface and a second surface opposite to each other in a thickness direction; A pixel unit, located on the first surface side of the chip region, the pixel unit comprising a first sub-pixel unit, a second sub-pixel unit and a third sub-pixel unit that are spaced apart from each other; a pixel groove located in the chip area and extending from the second surface side until the pixel unit is exposed, the pixel groove comprising a first pixel groove, a second pixel groove and a third pixel groove arranged at intervals from each other, the first pixel groove, the second pixel groove and the third pixel groove respectively corresponding to the first sub-pixel unit, the second sub-pixel unit and the third sub-pixel unit; An isolation barrier wall, comprising a first isolation barrier wall and a second isolation barrier wall, wherein the first isolation barrier wall is formed by a portion of the chip region located between any two of the first pixel groove, the second pixel groove and the third pixel groove, and the second isolation barrier wall is formed by an edge region of the chip region, and in a thickness direction of the substrate, a projection of the second isolation barrier wall surrounds a projection of the first isolation barrier wall; A first color conversion layer and a second color conversion layer are respectively located in the first pixel groove and the second pixel groove; a filter layer, located on the second surface side and covering the pixel groove, the filter layer comprising a first filter layer and a second filter layer, the first filter layer covering the first pixel groove, and the second filter layer covering the second pixel groove; The matting layer is located on the isolation retaining wall.

7. The light emitting structure according to claim 6, characterized in that: The substrate includes a plurality of chip regions; the matte layer adjacent to the second isolation barrier wall defines a cutting path window, and the cutting path window exposes the cutting path region.

8. The light emitting structure according to claim 6 or 7, characterized in that: The extinction layer includes a first filter material layer and a second filter material layer stacked in sequence, the first filter material layer and the second filter material layer filter light of different colors; the first filter material layer and the first filter layer are the same material layer, and the second filter material layer and the second filter layer are the same material layer.

9. The light emitting structure according to claim 6, characterized in that: The filter layer also covers a portion of the isolation barrier wall.

10. The light emitting structure according to claim 9, characterized in that: The line width of the portion of the filter layer covering the isolation barrier wall is in a range of 0 μm to 30 μm.

Images