Circuit and control method thereof, aging machine and aging equipment

Abstract

The invention provides a circuit and a control method thereof, an aging machine and aging equipment, relates to the technical field of electronics, and can output excitation signals in different states and adjust the current driving capability of the excitation signals. The circuit comprises a driving circuit and a main control circuit. The driving circuit comprises a plurality of driving units, each driving unit comprises a first adjustable voltage source, a first switch, a second switch, a grounding end and an output end, the first switch and the second switch are connected to the input side of the output end in parallel, and the main control circuit comprises a plurality of switch control circuits. The first adjustable voltage source outputs a first high level. The switch control circuit is used for controlling the first switch and the second switch to be switched off in a first mode; in the second mode, the control grounding end is electrically connected with the output end through the first switch and the second switch; in the third mode, the first adjustable voltage source is controlled to be electrically connected with the output end through the first switch, or the first adjustable voltage source is controlled to be electrically connected with the output end through the first switch and the second switch.

Description

Technical Field

[0001] The present application relates to the field of electronic technology, and in particular to a circuit and a control method thereof, an aging machine, and an aging device. Background Art

[0002] As the scale of chips continues to expand, the modules integrated in the chips become more numerous and more complex. In order to ensure the delivery quality of chips, the existing technology uses a burn-in platform with the function of screening out early failed chips to perform aging tests on the device under test (DUT). The principle of the aging platform is to simulate the long-term use of the chip under test, accelerate the aging of the chip by artificially creating high temperature, constant current, constant voltage and other environments, to screen good chips, and obtain data such as the life, safety, and ability to resist harsh environments of the chip under test.

[0003] As a universal test platform, the aging machine needs to deal with various types of chips under test, and it is necessary to provide the chips under test with excitation signals of different states (high / low / high impedance, H / L / Z). At the same time, in the scenario where a single excitation signal output by the aging machine is used to drive multiple chips under test, the excitation signal should also have a large current driving capability, otherwise, the signal quality transmitted to the chip under test is poor and the test effect cannot be achieved. Summary of the invention

[0004] In order to solve the above technical problems, the present application provides a circuit and its control method, an aging machine, and an aging device, which uses a driving circuit 20 to provide excitation signals of different states (H / L / Z) to the chip under test, and adjusts the current driving capability of the excitation signal input to the chip under test through a parallel branch.

[0005] In the first aspect, the present application provides a circuit, including a driving circuit and a main control circuit. The driving circuit has multiple driving units, and the driving units include a first adjustable voltage source, a first switch, a second switch, a ground terminal, and an output terminal. The first switch and the second switch are connected in parallel to the input side of the output terminal. The main control circuit includes multiple switch control circuits, each of which is used to control at least one driving unit. The first adjustable voltage source: configured to output a first high level. The switch control circuit: configured to control the first switch and the second switch to be disconnected in the first mode; in the second mode, the ground terminal is controlled to be electrically connected to the output terminal through the first switch and the second switch to output a low level through the output terminal; in the third mode, the first adjustable voltage source is controlled to be electrically connected to the output terminal through the first switch, or the first adjustable voltage source is controlled to be electrically connected to the output terminal through the first switch and the second switch respectively to output the first high level through the output terminal.

[0006] In the present application, in the first mode, the switch control circuit is used to control the first switch and the second switch to be disconnected, so that the driving unit is in a high impedance state. In the second mode, the switch control circuit is used to control the first switch and the second switch to be electrically connected to the ground terminal, so that the driving unit outputs a low level. In the third mode, the switch control circuit is used to control the first switch to be electrically connected to the first adjustable voltage source, or the switch control circuit is used to control the first switch and the second switch to be electrically connected to the first adjustable voltage source, so that the driving unit outputs the first high level provided by the first adjustable voltage source.

[0007] On this basis, in the third mode, the switch control circuit can also control the first switch to be electrically connected to the first adjustable voltage source according to the current driving capability required by the excitation signal output by the driving unit, or control the first switch and the second switch to be electrically connected to the first adjustable voltage source, thereby adjusting the current driving energy of the excitation signal. For example, if the current driving capability required by the excitation signal output by the driving unit is relatively small, the switch control circuit controls the first switch to be electrically connected to the first adjustable voltage source; if the current driving capability required by the excitation signal output by the driving unit is relatively large, the switch control circuit controls the first switch and the second switch to be electrically connected to the first adjustable voltage source, so as to prevent the signal quality received by the chip under test from being too poor and failing to achieve the test effect.

[0008] In some possible implementations, the driving unit may include multiple adjustable voltage sources, and the voltage values ​​output by the multiple adjustable voltage sources are different, so as to use the same driving unit to input test voltages of different voltage values ​​to multiple chips under test. For example, the driving unit also includes a second adjustable voltage source, a third switch and a fourth switch, and the third switch and the fourth switch are connected in parallel to the input side of the output terminal. The second adjustable voltage source: configured to output a second high level, and the second high level is different from the first high level. The switch control circuit: configured to control the third switch and the fourth switch to be disconnected in the first mode and the third mode; in the second mode, the ground terminal is electrically connected to the ground terminal through the third switch and the fourth switch. The switch control circuit: is also configured to control the first switch and the second switch to be disconnected in the fourth mode, and control the second adjustable voltage source to be electrically connected to the output terminal through the third switch, or control the second adjustable voltage source to be electrically connected to the output terminal through the third switch and the fourth switch, respectively, so as to output the second high level through the output terminal.

[0009] In the present application, in the first mode, the switch control circuit is used to control the first switch, the second switch, the third switch, and the fourth switch to be disconnected, so that the drive unit is in a high impedance state. In the second mode, the switch control circuit is used to control the first switch, the second switch, the third switch, and the fourth switch to be electrically connected to the ground terminal, so that the drive unit outputs a low level. In the third mode, the switch control circuit is used to control the third switch and the fourth switch to be disconnected; the switch control circuit is used to control the first switch to be electrically connected to the first adjustable voltage source, or the switch control circuit is used to control the first switch and the second switch to be electrically connected to the first adjustable voltage source, so that the drive unit outputs the first high level provided by the first adjustable voltage source. In the third mode, the switch control circuit is used to control the first switch and the second switch to be disconnected; the switch control circuit is used to control the third switch to be electrically connected to the second adjustable voltage source, or the switch control circuit is used to control the third switch and the fourth switch to be electrically connected to the second adjustable voltage source, so that the drive unit outputs the second high level provided by the second adjustable voltage source.

[0010] On this basis, in the fourth mode, the switch control circuit can also control the third switch to be electrically connected to the second adjustable voltage source according to the current driving capability required by the excitation signal output by the driving unit, or control both the third switch and the fourth switch to be electrically connected to the second adjustable voltage source, thereby playing a role in adjusting the current driving energy of the excitation signal. For example, if the current driving capability required by the excitation signal output by the driving unit is relatively small, the switch control circuit controls the third switch to be electrically connected to the second adjustable voltage source; if the current driving capability required by the excitation signal output by the driving unit is relatively large, the switch control circuit controls both the third switch and the fourth switch to be electrically connected to the second adjustable voltage source, so as to prevent the signal quality received by the chip under test from being too poor and failing to achieve the test effect.

[0011] In some possible implementations, the second switch includes a first sub-switch and a first resistor, and the first switch and the first sub-switch constitute a first bipolar double-pole switch; and / or the fourth switch includes a second sub-switch and a second resistor, and the third switch and the second sub-switch constitute a second bipolar double-pole switch. Those skilled in the art should know that the first switch in the first bipolar double-pole switch is turned on or off at the same time as the first sub-switch. The third switch in the second bipolar double-pole switch is turned on or off at the same time as the second sub-switch.

[0012] In some possible implementations, the circuit further includes a receiving circuit, the receiving circuit includes a first comparator, a second comparator, a third adjustable voltage source, and a fourth adjustable voltage source, and the main control circuit further includes a detection circuit. The first comparator includes a first input terminal, a second input terminal, and a first output terminal, and the second comparator includes a third input terminal, a fourth input terminal, and a second output terminal; the first output terminal is electrically connected to the detection circuit, and the second output terminal is electrically connected to the detection circuit. The main control circuit is configured to control the first input terminal to be electrically connected to the third adjustable voltage source, and to control the third input terminal to be electrically connected to the fourth adjustable voltage source. The third adjustable voltage source is configured to input a first reference high level to the first comparator; the fourth adjustable voltage source is configured to input a first reference low level to the second comparator.

[0013] On this basis, the main control circuit is configured to control the external circuit to input the first voltage to the first comparator through the second input terminal, and to control the external circuit to input the first voltage to the second comparator through the fourth input terminal. The first comparator is configured to compare the received first voltage with the first reference high level, and input the first comparison result to the detection circuit. The second comparator is configured to compare the received first voltage with the first reference low level, and input the second comparison result to the detection circuit. The detection circuit is configured to identify the first voltage according to the first comparison result and the second comparison result.

[0014] The receiving circuit is used to receive the signal output by the chip under test, and compare the signal output by the chip under test with the expected value to identify the signal output by the chip under test, so as to test the chip under test.

[0015] Alternatively, the main control circuit is configured to, in the third mode, control the driving unit to input the first high level to the first comparator through the output terminal and the second input terminal, and control the driving unit to input the first high level to the second comparator through the output terminal and the fourth input terminal. The first comparator is configured to compare the received first high level with the first reference high level, and input the third comparison result to the detection circuit. The second comparator is configured to compare the received first high level with the first reference low level, and input the fourth comparison result to the detection circuit. The detection circuit is configured to confirm whether the first adjustable voltage source is qualified according to the third comparison result and the fourth comparison result.

[0016] The receiving circuit is used to receive the first high level sent by the driving circuit to determine whether the first adjustable voltage source is qualified; or the receiving circuit is used to receive the second high level sent by the driving circuit to determine whether the second adjustable voltage source is qualified.

[0017] In some possible implementations, the receiving circuit further includes a fifth adjustable voltage source, a sixth adjustable voltage source, a fifth switch, and a sixth switch. The main control circuit is configured to control the first input terminal to be disconnected from the third adjustable voltage source through the fifth switch and electrically connected to the fifth adjustable voltage source through the fifth switch, and to control the third input terminal to be disconnected from the fourth adjustable voltage source through the sixth switch and electrically connected to the sixth adjustable voltage source through the sixth switch; or, configured to control the first input terminal to be electrically connected to the third adjustable voltage source through the fifth switch and disconnected from the fifth adjustable voltage source through the fifth switch, and to control the third input terminal to be electrically connected to the fourth adjustable voltage source through the sixth switch and disconnected from the sixth adjustable voltage source through the sixth switch. The fifth adjustable voltage source is configured to input a second reference high level to the first comparator, and the second reference high level is different from the first reference high level. The sixth adjustable voltage source is configured to input a second reference low level to the second comparator, and the second reference low level is different from the first reference low level.

[0018] On this basis, the main control circuit is configured to control the external circuit to input a second voltage to the first comparator through the second input terminal, and to control the external circuit to input a second voltage to the second comparator through the fourth input terminal, wherein the second voltage is different from the first voltage. The first comparator is configured to compare the received second voltage with the second reference high level, and input a fifth comparison result to the detection circuit. The second comparator is configured to compare the received second voltage with the second reference low level, and input a sixth comparison result to the detection circuit. The detection circuit is configured to identify the second voltage according to the fifth comparison result and the sixth comparison result.

[0019] If the signals output by the chip under test are voltage values ​​of two different standards, the third and fourth adjustable voltage sources can be used to identify the voltage value of one standard, and the fifth and sixth adjustable voltage sources can be used to identify the voltage value of the other standard.

[0020] Alternatively, in the case where the driving unit further includes a second adjustable voltage source, a third switch, and a fourth switch, in the fourth mode, the driving unit is controlled to input the second high level to the first comparator through the output terminal and the second input terminal, and the driving unit is controlled to input the second high level to the second comparator through the output terminal and the fourth input terminal. The first comparator is configured to compare the received second high level with the second reference high level, and input the seventh comparison result to the detection circuit. The second comparator is configured to compare the received second high level with the second reference low level, and input the eighth comparison result to the detection circuit. The detection circuit is configured to confirm whether the second adjustable voltage source is qualified according to the seventh comparison result and the eighth comparison result.

[0021] When the driving unit includes a second adjustable voltage source, the receiving circuit may further include a fifth adjustable voltage source and a sixth adjustable voltage source, and the third adjustable voltage source and the fourth adjustable voltage source may be used to detect whether the second adjustable voltage source is qualified, and the fifth adjustable voltage source and the sixth adjustable voltage source may be used to detect whether the second adjustable voltage source is qualified.

[0022] In some possible implementations, the fifth switch and the sixth switch are both single-pole double-throw switches.

[0023] In some possible implementations, the main control circuit also includes a power supply regulating circuit. The power supply regulating circuit is configured to adjust the first high level output by the first adjustable voltage source, adjust the second high level output by the second adjustable voltage source, adjust the first reference high level output by the third adjustable voltage source, adjust the first reference low level output by the fourth adjustable voltage source, adjust the second reference high level output by the fifth adjustable voltage source, and adjust the second reference low level output by the sixth adjustable voltage source. In this way, according to the test requirements of the chip under test, the driving unit can input the first high level and the second high level of various voltage values ​​to the chip under test. At the same time, according to the voltage value of the signal output by the chip under test, the first reference high level, the first reference low level, the second reference high point level, and the second reference low level can be adjusted to use the receiving circuit to identify the signal output by the chip under test, and to detect whether the first adjustable voltage source and the second adjustable voltage source are qualified.

[0024] In a second aspect, the present application provides a burn-in machine, comprising the circuit described in the first aspect.

[0025] The second aspect and any implementation of the second aspect correspond to the first aspect and any implementation of the first aspect respectively. The technical effects corresponding to the second aspect and any implementation of the second aspect can refer to the technical effects corresponding to the above-mentioned first aspect and any implementation of the first aspect, which will not be repeated here.

[0026] In a third aspect, the present application provides an aging device, including an aging board and the aging machine described in the second aspect, the aging board is used to carry multiple chips under test, and the aging machine is used to perform aging tests on the multiple chips under test through the aging board.

[0027] The third aspect and any implementation of the third aspect correspond to the first aspect and any implementation of the first aspect, respectively. The technical effects corresponding to the third aspect and any implementation of the third aspect can refer to the technical effects corresponding to the first aspect and any implementation of the first aspect, which will not be repeated here.

[0028] In some possible implementations, in order to improve production test efficiency and reduce the test cost of a single chip under test, the number of chips under test on the burn-in board should be as large as possible. This application does not limit the arrangement of multiple chips under test on the burn-in board. Figure 1b As shown, the connection lines on the aging board and the chips under test adopt a daisy chain structure of one-drive-multiple topology. Specifically, the aging board includes connection lines, the connection lines include a first line and a plurality of second lines, the first line is electrically connected between the aging machine and the plurality of second lines; each second line is electrically connected to a plurality of chips under test.

[0029] In some possible implementations, the aging board further includes a third resistor, a first capacitor, a second capacitor, a first ground terminal, and a second ground terminal. The third resistor is connected to the first wiring, the first capacitor is electrically connected between one end of the third resistor and the first ground terminal, and the second capacitor is electrically connected between the other end of the third resistor and the second ground terminal; and / or, the aging board further includes a fourth resistor, which is electrically connected between the second wiring and the chip under test; the aging board further includes a transient suppression diode and a third ground terminal, the input end of the transient suppression diode is electrically connected between the aging machine and the fourth resistor, and the output end of the transient suppression diode is electrically connected to the third ground terminal.

[0030] By adjusting the resistance value of the third resistor, and the capacitance values ​​of the first capacitor and the second capacitor, the driving current strength and the waveform edge slope of the excitation signal input from the aging machine to the aging board can be controlled. In addition, the π-type circuit composed of the third resistor, the first capacitor, and the second capacitor can be used to absorb the signal clutter reflection on the far-end chip under test, thereby improving the waveform quality of the excitation signal received by the chip under test.

[0031] Transient suppression diodes can act as voltage clamps to protect the back-end chip under test from damage or failure due to electrical overstress caused by abnormal voltage or glitches.

[0032] The fourth resistor can effectively suppress the signal reflection at the end of the chip under test, control the rising edge of the signal at the chip under test, and improve the signal quality received by the chip under test.

[0033] In a fourth aspect, the present application provides a control method for a circuit, the circuit includes a driving circuit and a main control circuit; the driving circuit includes multiple driving units, the driving unit includes a first adjustable voltage source, a first switch, a second switch, a ground terminal, and an output terminal, and the first switch and the second switch are connected in parallel to the input side of the output terminal; the main control circuit includes multiple switch control circuits, each switch control circuit is used to control a driving unit. The control method of the circuit includes: in a first mode, the first switch and the second switch are both controlled to be disconnected by the switch control circuit. In a second mode, the ground terminal is controlled to be electrically connected to the output terminal through the first switch and the second switch by the switch control circuit, so as to output a low level through the output terminal. In a third mode, a first high level is output through the first adjustable voltage source; the first adjustable voltage source is controlled to be electrically connected to the output terminal through the first switch by the switch control circuit, or the first adjustable voltage source is controlled to be electrically connected to the output terminal through the first switch and the second switch, respectively, so as to output a first high level through the output terminal.

[0034] In some possible implementations, the driving unit further includes a second adjustable voltage source, a third switch and a fourth switch, and the third switch and the fourth switch are connected in parallel to the input side of the output terminal. The circuit control method also includes: in the first mode, controlling the third switch and the fourth switch to be disconnected; in the second mode, controlling the ground terminal to be electrically connected to the ground terminal through the third switch and the fourth switch; in the third mode, controlling the third switch and the fourth switch to be disconnected. In the fourth mode, the second high level is output through the second adjustable voltage source, and the second high level is different from the first high level; controlling the first switch and the second switch to be disconnected, and controlling the second adjustable voltage source to be electrically connected to the output terminal through the third switch, or controlling the second adjustable voltage source to be electrically connected to the output terminal through the third switch and the fourth switch, respectively, so as to output the second high level through the output terminal.

[0035] In some possible implementations, the circuit further includes a receiving circuit, the receiving circuit includes a first comparator, a second comparator, a third adjustable voltage source, and a fourth adjustable voltage source, and the main control circuit further includes a detection circuit. The first comparator includes a first input terminal, a second input terminal, and a first output terminal, and the second comparator includes a third input terminal, a fourth input terminal, and a second output terminal; the first output terminal is electrically connected to the detection circuit, and the second output terminal is electrically connected to the detection circuit. The control method of the circuit also includes: using the main control circuit to control the first input terminal to be electrically connected to the third adjustable voltage source, and controlling the third input terminal to be electrically connected to the fourth adjustable voltage source; using the third adjustable voltage source to input a first reference high level to the first comparator; using the fourth adjustable voltage source to input a first reference low level to the second comparator.

[0036] In some possible implementations, the circuit control method further includes: using the main control circuit to control the external circuit to input the first voltage to the first comparator through the second input terminal, and controlling the external circuit to input the first voltage to the second comparator through the fourth input terminal. Using the first comparator to compare the received first voltage with the first reference high level, and input the first comparison result to the detection circuit; using the second comparator to compare the received first voltage with the first reference low level, and input the second comparison result to the detection circuit. Using the detection circuit to identify the first voltage according to the first comparison result and the second comparison result.

[0037] In some possible implementations, in the third mode, the main control circuit is used to control the driving unit to input the first high level to the first comparator through the output terminal and the second input terminal, and the driving unit is controlled to input the first high level to the second comparator through the output terminal and the fourth input terminal. The first comparator is used to compare the received first high level with the first reference high level, and the third comparison result is input to the detection circuit; the second comparator is used to compare the received first high level with the first reference low level, and the fourth comparison result is input to the detection circuit. The detection circuit is used to confirm whether the first adjustable voltage source is qualified according to the third comparison result and the fourth comparison result.

[0038] In some possible implementations, the receiving circuit further includes a fifth adjustable voltage source, a sixth adjustable voltage source, a fifth switch, and a sixth switch. The circuit control method further includes: using the main control circuit to control the first input terminal to be disconnected from the third adjustable voltage source through the fifth switch and electrically connected to the fifth adjustable voltage source through the fifth switch, controlling the third input terminal to be disconnected from the fourth adjustable voltage source through the sixth switch and electrically connected to the sixth adjustable voltage source through the sixth switch; using the fifth adjustable voltage source to input a second reference high level to the first comparator; using the sixth adjustable voltage source to input a second reference low level to the second comparator; or using the main control circuit to control the first input terminal to be electrically connected to the third adjustable voltage source through the fifth switch and disconnected from the fifth adjustable voltage source through the fifth switch, controlling the third input terminal to be electrically connected to the fourth adjustable voltage source through the sixth switch and disconnected from the sixth adjustable voltage source through the sixth switch; using the third adjustable voltage source to input a first reference high level to the first comparator; using the fourth adjustable voltage source to input a first reference low level to the second comparator; wherein the second reference high level is different from the first reference high level, and the second reference low level is different from the first reference low level.

[0039] In some possible implementations, the circuit control method further includes: using the main control circuit to control the external circuit to input a second voltage to the first comparator through the second input terminal, and controlling the external circuit to input a second voltage to the second comparator through the fourth input terminal, wherein the second voltage is different from the first voltage. Using the first comparator to compare the received second voltage with the second reference high level, and inputting a fifth comparison result to the detection circuit; using the second comparator to compare the received second voltage with the second reference low level, and inputting a sixth comparison result to the detection circuit. Using the detection circuit to identify the second voltage according to the fifth comparison result and the sixth comparison result.

[0040] In some possible implementations, the circuit control method further includes: when the driving unit further includes a second adjustable voltage source, a third switch, and a fourth switch, in the fourth mode, the driving unit is controlled to input a second high level to the first comparator through the output terminal and the second input terminal, and the driving unit is controlled to input a second high level to the second comparator through the output terminal and the fourth input terminal. The first comparator is used to compare the received second high level with the second reference high level, and a seventh comparison result is input to the detection circuit; the second comparator is used to compare the received second high level with the second reference low level, and an eighth comparison result is input to the detection circuit. The detection circuit is used to confirm whether the second adjustable voltage source is qualified according to the seventh comparison result and the eighth comparison result.

[0041] The fourth aspect and any implementation of the fourth aspect correspond to the first aspect and any implementation of the first aspect, respectively. The technical effects corresponding to the fourth aspect and any implementation of the fourth aspect can refer to the technical effects corresponding to the above-mentioned first aspect and any implementation of the first aspect, which will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1a A schematic diagram of the structure of the aging device provided in the embodiment of the present application;

[0043] Figure 1b A circuit connection diagram of the aging machine, aging board and chip under test provided in the embodiment of the present application;

[0044] Figure 2 A diagram showing the corresponding relationship between the switch control circuit and the drive unit provided in the embodiment of the present application;

[0045] Figure 3 A corresponding relationship diagram of the main control circuit, the driving circuit and the chip under test provided in the embodiment of the present application;

[0046] Figure 4 A circuit diagram of a circuit provided in an embodiment of the present application;

[0047] Figure 5A flowchart of the circuit provided in the embodiment of the present application;

[0048] Figure 6 A circuit diagram of a circuit provided in an embodiment of the present application;

[0049] Figure 7 A flowchart of the circuit provided in the embodiment of the present application;

[0050] Figure 8 A diagram showing the corresponding relationship between the main control circuit and the driving circuit, the receiving circuit and the chip under test provided in the embodiment of the present application;

[0051] Fig. 9 A circuit diagram of a circuit provided in an embodiment of the present application;

[0052] Fig.10 A circuit diagram of a circuit provided in an embodiment of the present application;

[0053] Fig.11 A circuit diagram of a circuit provided in an embodiment of the present application;

[0054] Fig.12 A circuit diagram of a circuit provided in an embodiment of the present application;

[0055] Fig.13 A circuit diagram of a circuit provided in an embodiment of the present application;

[0056] Fig.14 A circuit diagram of a circuit provided in an embodiment of the present application;

[0057] Fig.15 A circuit control flow chart provided for an embodiment of the present application.

[0058] Reference numerals:

[0059] 10-main control circuit; 11-switch control circuit; 12-power supply regulation circuit; 13-detection circuit; 20-drive circuit; 21-drive unit; 211-first adjustable voltage source; 212-second switch; 213-second adjustable voltage source; 214-fourth switch; 30-receiving circuit; 31-first comparator; 32-second comparator; 33-third adjustable voltage source; 34-fourth adjustable voltage source; 35-fifth adjustable voltage source; 36-sixth adjustable voltage source. DETAILED DESCRIPTION

[0060] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0061] The term "and / or" in this article is merely a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone.

[0062] The terms "first" and "second" in the description and claims of the embodiments of the present application are used to distinguish different objects rather than to describe a specific order of objects. For example, a first target object and a second target object are used to distinguish different target objects rather than to describe a specific order of target objects.

[0063] In the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0064] In the description of the embodiments of the present application, unless otherwise specified, the meaning of "multiple" refers to two or more than two. For example, multiple processing units refer to two or more processing units; multiple systems refer to two or more systems.

[0065] The embodiment of the present application provides an aging device. The principle of the aging device is to simulate the long-term use of the chip under test, accelerate the aging of the chip by artificially creating a high temperature, constant current, constant voltage and other environments, so as to screen good chips and obtain data such as the life, safety, and resistance to harsh environments of the chip under test. Figure 1a As shown, the aging equipment includes an aging machine and a burn-in board (BIB). The aging machine includes a power board, a temperature control board, a main control board, a duct control board, etc. Among them, the power board is used to provide power for the chip under test; the temperature control board is used to control the temperature of the chip under test; the main control board is used to control other sub-boards, run algorithms, and generate excitation signals.

[0066] The aging board usually includes a socket for the chip under test and the basic peripheral circuit of the chip under test, and needs to be inserted into the aging furnace during operation. During the aging test, the chip under test can be installed on the aging equipment through the aging board, and the aging machine is electrically connected to the aging board through multiple interfaces (or multiple channels, which can include IO channels) to create heating / cooling, constant current, constant pressure and other environments for the chip under test through the aging board.

[0067] In the aging test, the chip under test needs to work in a specific state. In addition to providing the necessary external power supply, clock, high temperature / low temperature environment, it is also necessary to input a specific digital signal waveform (design for testability scan chain, DFT SCAN) into the test interface of the chip under test. We call the digital signal waveform sender the aging vector or excitation signal source. The aging vector is used to configure the chip under test so that the chip under test works in a specific working state and transfers the chip under test from the idle state to the target working state.

[0068] For example, under high temperature and high pressure conditions, the aging machine inputs an excitation signal to the chip under test, compares the signal output by the chip under test with the expected value, and determines whether the signal output by the chip under test is within the tolerance range. If it is not within the tolerance range, the faulty chip under test is identified, which can improve the service life and reliability of the chip under test after it leaves the factory.

[0069] In some embodiments, the embodiments of the present application do not limit the number of chips under test that the aging board can carry. Optionally, the aging board can carry one or more chips under test.

[0070] In order to improve production test efficiency and reduce the test cost of a single chip under test, the number of chips under test on the aging board needs to be as large as possible, that is, the number of chips under test that the aging board can carry is multiple.

[0071] In some possible implementations, the present application does not limit the arrangement of multiple chips under test on the aging board. Optionally, Figure 1b As shown in FIG. 1 , the connection lines on the aging board and the chip under test adopt a daisy chain structure (fly-by) with one drive multiple topology. Specifically, Figure 1b As shown, the connection wiring on the aging board includes a first wiring and multiple second wirings, the first wiring is electrically connected between the aging machine and the multiple second wirings, and each second wiring is electrically connected to multiple chips under test.

[0072] The embodiments of the present application do not limit the specific number of chips under test on the aging board. For example, the number of chips under test on the aging board may be 6, 12, 24, etc.

[0073] On this basis, if Figure 1b As shown, the aging board also includes a third resistor R3, a first capacitor C1, a second capacitor C2, a first ground terminal, and a second ground terminal. The third resistor R3 is connected to the first trace, the first capacitor C1 is electrically connected between one end of the third resistor R3 and the first ground terminal, and the second capacitor C2 is electrically connected between the other end of the third resistor R3 and the second ground terminal.

[0074] By adjusting the resistance value of the third resistor R3, and the capacitance values ​​of the first capacitor C1 and the second capacitor C2, the driving current strength and the waveform edge slope of the excitation signal input by the aging machine to the aging board can be controlled. In addition, the π-type circuit composed of the third resistor R3, the first capacitor C1, and the second capacitor C2 can also be used to absorb the signal clutter reflection on the far-end chip under test, thereby improving the waveform quality of the excitation signal received by the chip under test.

[0075] like Figure 1b As shown, the aging board may further include a fourth resistor R4, which is electrically connected between the second wiring and the chip under test. The aging board also includes a transient voltage suppressor (TVS) and a third ground terminal, the aging machine and the third resistor R3 are adjacent to node a, and the transient voltage suppressor is electrically connected between node a and the third ground terminal. For example, the input end of the transient voltage suppressor is electrically connected to node a, and the output end of the transient voltage suppressor is electrically connected to the third ground terminal.

[0076] The transient suppression diode can play the role of voltage clamping, protecting the back-end chip under test from damage or failure due to electrical over stress (EOS) caused by abnormal voltage or glitches.

[0077] The fourth resistor R4 can effectively suppress the signal reflection at the end chip under test, control the rising edge of the signal at the chip under test, and improve the signal quality received by the chip under test.

[0078] However, as a universal test platform, the aging machine needs to deal with various types of chips under test, and it is necessary to provide the chips under test with excitation signals of different states (H / L / Z). At the same time, in the scenario where a single excitation signal output by the aging machine is used to drive multiple chips under test, the excitation signal should also have a large current driving capability, otherwise, the signal quality transmitted to the chip under test is poor and the test effect cannot be achieved. Among them, H means that the aging machine provides a high-level excitation signal to the chip under test, L means that the aging machine provides a low-level excitation signal to the chip under test, and Z means that the aging machine provides a high-impedance state to the chip under test.

[0079] Based on this, Figure 2 As shown, an embodiment of the present application provides a circuit, which includes a main control circuit 10 and a drive circuit 20. The main control circuit 10 includes a plurality of switch control circuits 11, and the drive circuit 20 includes a plurality of drive units 21, each of which is used to control at least one drive unit 21.

[0080] For example, the driving circuit includes 256 driving units 21 , the main control circuit 10 includes 256 switch control circuits 11 , and the switch control circuits 11 correspond to the driving units 21 one by one.

[0081] Of course, in some other possible implementations, the driving circuit includes 256 driving units 21 , the main control circuit 10 includes 128 switch control circuits 11 , and each switch control circuit 11 is used to control two driving units 21 .

[0082] It should be noted that the embodiments of the present application do not limit the application scenarios of the circuit. The circuit of the present application is applicable to any application scenario that requires outputting excitation signals of different states (H / L / Z). For the convenience of explanation, the following description takes the circuit as a part of the main control board in the aging machine as an example. Figure 3 As shown, during the aging test, the driving circuit 20 is electrically connected to the input side of the chip under test, and the main control circuit 10 controls the driving circuit 20 to provide the chip under test with excitation signals of multiple different states (H / L / Z).

[0083] On the basis of the above, if Figure 4 As shown, the driving unit 21 includes a first adjustable voltage source 211, a first switch K1, a second switch K2, a ground terminal, and an output terminal Out. The first switch K1 and the second switch K2 are connected in parallel to the input side of the output terminal Out.

[0084] In some possible implementations, the embodiment of the present application does not limit the first switch K1 and the second switch 212. Optionally, the first switch K1 and the second switch 212 may both be transistors; or the second switch 212 includes a first sub-switch K2 and a first resistor R1, and the first switch K1 and the first sub-switch K2 form a first bipolar double-pole switch. For the convenience of description, the following description is based on an example in which the second switch 212 includes a first sub-switch K2 and a first resistor R1, and the first switch K1 and the first sub-switch K2 form a first bipolar double-pole switch.

[0085] Those skilled in the art should know that the first switch K1 and the first sub-switch K2 in the first double-pole double-pole switch are turned on or off at the same time.

[0086] Combine the following Figure 5 The flowchart shown in FIG. 1 details the working principle of any driving unit 21 under the control of the main control circuit 10 .

[0087] The main control circuit 10 parses the vector configuration file to determine the first high level to be configured to the first adjustable voltage source 211 , or in other words, to determine the first high level that the first adjustable voltage source 211 can output.

[0088] In some possible implementations, the main control circuit 10 further includes a power regulation circuit 12. In different application scenarios, the power regulation circuit 12 can be used to parse a configuration file and adjust the first high level voltage value output by the first adjustable voltage source 211 according to the configuration file.

[0089] For example, at the 1st μs, the power supply regulating circuit 12 controls the first adjustable voltage source 211 to output a first high level of 3.3 V. At the 10th μs, the power supply regulating circuit 12 controls the first adjustable voltage source 211 to output a first high level of 1.8 V.

[0090] The switch control circuit 11 may also parse the vector configuration file and decode the waveform and timing of the output of the driving unit 21 to determine the waveform and timing of the excitation signal to be output by the driving unit 21 .

[0091] The switch control circuit 11 determines the current working mode of the driving unit 21 according to the waveform and timing of the excitation signal to be output by the driving unit 21, and sends the OE1 signal and the S signal to the first switch K1 and the second switch 212. Under the control of the OE1 signal and the S signal, the driving unit 21 works in the first mode, the second mode, or the third mode.

[0092] For example, referring to Table 1, assuming that when the OE1 signal is a digital signal 0, the first switch K1 and the first sub-switch K2 are both disconnected; when the OE1 signal is a digital signal 1, the first switch K1 and the first sub-switch K2 are both turned on. When the S signal is 1, the first switch K1 and the first sub-switch K2 are both electrically connected to the first adjustable voltage source 211; when the S signal is 0, the first switch K1 and the first sub-switch K2 are both electrically connected to the ground terminal. In addition, the priority of the OE1 signal is higher than the priority of the S signal.

[0093] Of course, it can also be set that when the OE1 signal is a digital signal 1, the first switch K1 and the first sub-switch K2 are both disconnected; when the OE1 signal is a digital signal 0, the first switch K1 and the first sub-switch K2 are both turned on; when the S signal is 0, the first switch K1 and the first sub-switch K2 are both electrically connected to the first adjustable voltage source 211; when the S signal is 1, the first switch K1 and the first sub-switch K2 are both electrically connected to the ground terminal, and the embodiment of the present application is not limited to this.

[0094] Table 1

[0095] OE1 S Working status 0 1 First Mode 0 0 First Mode 1 0 Second Mode 1 1 Third Mode

[0096] Referring to Table 1, the switch control circuit 11 determines whether the current working mode of the driving unit 21 is the first mode according to the waveform and timing of the excitation signal output by the driving unit 21. If so, the switch control circuit 11 inputs an OE1 signal with a digital signal of 0 to the first switch K1 and the first sub-switch K2. Under the control of the OE1 signal, the internal resistance of the first switch K1 and the first sub-switch K2 increases, the first switch K1 and the first sub-switch K2 are both in the disconnected state, and the driving unit 21 is in a high impedance state.

[0097] If not, the excitation signal level amplitude selection mode is entered to determine whether the driving unit 21 operates in the second mode or the third mode.

[0098] Optionally, if the driving unit 21 operates in the second mode, the switch control circuit 11 inputs an S signal and an OE1 signal whose digital signal is 1 to the first switch K1 and the first sub-switch K2. Under the control of the OE1 signal, the first switch K1 and the first sub-switch K2 are both turned on. On this basis, the S signal is a digital signal of 0, and the first switch K1 and the first sub-switch K2 are both electrically connected to the ground terminal. Since the first switch K1 and the first sub-switch K2 are also connected in parallel to the input side of the output terminal Out, the first switch K1 is electrically connected between the ground terminal and the output terminal Out, and the excitation signal output by the output terminal Out is a low level. The driving unit 21 can input the low level to the chip under test on the aging board through the output terminal Out to perform an aging test on the chip under test.

[0099] For the second switch 212, if in the branch where the ground terminal, the first sub-switch K2, the first resistor R1, and the output terminal Out are located, the two ends of the first resistor R1 are electrically connected to the first sub-switch K2 and the output terminal Out respectively, then the excitation signal outputted from the ground terminal through the second switch 212 and the output terminal Out is also low level. If in the branch where the ground terminal, the first sub-switch K2, the first resistor R1, and the output terminal Out are located, the two ends of the first resistor R1 are not electrically connected to the first sub-switch K2 and / or the output terminal Out, then the branch where the ground terminal, the first sub-switch K2, the first resistor R1, and the output terminal Out are located is disconnected, but this situation does not affect the excitation signal outputted from the ground terminal through the first switch K1 and the output terminal Out is low level.

[0100] In some possible implementations, if the first resistor R1 is coupled to a circuit board where the circuit of the present application is located, the two ends of the first resistor R1 are electrically connected to the first sub-switch K2 and the output end Out, respectively; otherwise, the two ends of the first resistor R1 are not electrically connected to the first sub-switch K2 and / or the output end Out.

[0101] Optionally, if the driving unit 21 operates in the third mode, the switch control circuit 11 inputs an S signal and an OE1 signal whose digital signal is 1 to the first switch K1 and the first sub-switch K2. Under the control of the OE1 signal, the first switch K1 and the first sub-switch K2 are both turned on. On this basis, the S signal is a digital signal 1, and the first switch K1 and the first sub-switch K2 are both electrically connected to the first adjustable voltage source 211. Since the first switch K1 and the first sub-switch K2 are also connected in parallel to the input side of the output terminal Out, the first switch K1 is electrically connected between the first adjustable voltage source 211 and the output terminal Out.

[0102] For the second switch 212, if in the branch where the ground terminal, the first sub-switch K2, the first resistor R1, and the output terminal Out are located, the two ends of the first resistor R1 are electrically connected to the first sub-switch K2 and the output terminal Out respectively, then the first adjustable voltage source 211 is electrically connected to the output terminal Out through the second switch 212. The branch where the first switch K1 is located and the branch where the second switch 212 is located are connected in parallel between the first adjustable voltage source 211 and the output terminal Out, and the excitation signal output by the output terminal Out is a first high level. The driving unit 21 can input the first high level to the chip under test on the aging board through the output terminal Out to perform an aging test on the chip under test.

[0103] Furthermore, since the branch where the first switch K1 is located and the branch where the second switch 212 is located are connected in parallel between the first adjustable voltage source 211 and the output terminal Out, the driving current of the excitation signal output by the output terminal Out is doubled, thereby improving the current driving capability of the excitation signal and avoiding the failure to achieve the test effect due to the poor quality of the signal transmitted to the chip under test.

[0104] For example, assuming that the upper limit of the current flow of the first switch K1 and the first sub-switch K2 are both 100mA, the current of the excitation signal output by the branch where the first switch K1 is located through the output terminal Out is 100mA, and when the branch where the second switch 212 is located is turned on, the current of the excitation signal output by the branch where the second switch 212 is located through the output terminal Out is also 100mA, and the two are added together, and the total current of the excitation signal output by the output terminal Out is 200mA. In addition, when the second switch 212 is turned off, the total current of the excitation signal output by the output terminal Out is 100mA. Therefore, the embodiment of the present application can also adjust the current size of the excitation signal output by the output terminal Out by controlling the second switch 212 to be turned on or off.

[0105] That is, the driving circuit 20 provided in the embodiment of the present application can also increase the current driving capability of the excitation signal input to the chip under test through a parallel branch when providing excitation signals of different states (H / L / Z) to the chip under test, thereby preventing the signal quality received by the chip under test from being too poor and failing to achieve the test effect.

[0106] Of course, the upper limit of the current flow of the first switch K1 and the first sub-switch K2 can also be other values, which is not limited in the embodiment of the present application. In addition, in order to make the excitation signal output by the drive unit 21 reach the set current value, the embodiment of the present application is not limited to the drive unit 21 including the first switch K1 and the second switch 212 in parallel. In some other possible implementations, the drive unit 21 may also include more switches connected in parallel with the first switch K1 and the second switch 212. Three or more parallel switches made by ordinary technicians in this field under the inspiration of this application are all within the protection of this application.

[0107] For the second switch 212, if in the branch where the ground terminal, the first sub-switch K2, the first resistor R1, and the output terminal Out are located, the two ends of the first resistor R1 are not electrically connected to the first sub-switch K2 and / or the output terminal Out, then the branch where the first adjustable voltage source 211, the first sub-switch K2, the first resistor R1, and the output terminal Out are located is disconnected, but this situation does not affect the first adjustable voltage source 211 outputting the first high level through the first switch K1 and the output terminal Out.

[0108] In some possible implementations, in order to prevent the excitation signal reaching the chip under test from being significantly attenuated, the solution of the embodiment of the present application can also make the internal resistance of the first bipolar double-pole switch as small as possible (for example, 4.5Ω~8.5Ω) to reduce the signal voltage drop inside the first bipolar double-pole switch when driven by large current.

[0109] The above describes the case where the driving unit 21 includes an adjustable voltage source (a first adjustable voltage source). In other embodiments, the driving unit 21 may include multiple adjustable voltage sources, and the voltage values ​​output by the multiple adjustable voltage sources are different, so that the same driving unit 21 can be used to input test voltages of different voltage values ​​to multiple chips under test.

[0110] The following description will be made by taking the example that the driving unit 21 includes the second adjustable voltage source 213 in addition to the first adjustable voltage source 211. Figure 6 As shown, the driving unit 21 further includes a third switch K3 and a fourth switch 214. The third switch K3 and the fourth switch 214 are connected in parallel to the input side of the output terminal Out.

[0111] In some possible implementations, the embodiment of the present application does not limit the third switch K3 and the fourth switch 214. Optionally, the third switch K3 and the fourth switch 214 may both be transistors; or the fourth switch 214 includes a second sub-switch K4 and a second resistor R2, and the third switch K3 and the second sub-switch K4 form a second bipolar double-pole switch. For the convenience of description, the following description is based on an example in which the fourth switch 214 includes a second sub-switch K4 and a second resistor R2, and the third switch K3 and the second sub-switch K4 form a second bipolar double-pole switch.

[0112] Those skilled in the art should know that the third switch K3 and the second sub-switch K4 in the second double-pole double-pole switch are turned on or off at the same time.

[0113] Figure 7 2 shows a flow chart when the driving unit 21 includes a first adjustable voltage source 211 and a second adjustable voltage source 213. Figure 7 It shows that the drive unit 21 works in the first mode, the third mode, and the fourth mode. Figure 7 The flowchart shown in FIG. 1 details the working principle of any driving unit 21 under the control of the main control circuit 10 .

[0114] The main control circuit 10 parses the vector configuration file to determine the first high level configured to the first adjustable voltage source 211 and the second high level configured to the second adjustable voltage source 213. In other words, the main control circuit 10 parses the vector configuration file to determine the first high level that the first adjustable voltage source 211 can output and the second high level that the second adjustable voltage source 213 can output.

[0115] In some possible implementations, the main control circuit 10 further includes a power supply regulating circuit 12. In different application scenarios, the power supply regulating circuit 12 can be used to parse the configuration file, and adjust the voltage value of the first high level output by the first adjustable voltage source 211 and the voltage value of the second high level output by the second adjustable voltage source 213 according to the configuration file.

[0116] For example, the power regulation circuit 12 controls the first high level output by the first adjustable voltage source 211 to be 3.3V, and controls the first high level output by the second adjustable voltage source 213 to be 2.5V.

[0117] The switch control circuit 11 may also parse the vector configuration file and decode the waveform and timing of the output of the driving unit 21 to determine the waveform and timing of the excitation signal to be output by the driving unit 21 .

[0118] The switch control circuit 11 determines the current working mode of the driving unit 21 according to the waveform and timing of the excitation signal to be output by the driving unit 21, and sends the OE1 signal and the S signal to the first switch K1 and the second switch 212, and sends the OE2 signal and the S signal to the third switch K3 and the fourth switch 214. Under the control of the OE1 signal, the OE2 signal and the S signal, the driving unit 21 works in the first mode, the second mode, the third mode, or the fourth mode.

[0119] For example, referring to Table 2, assuming that when the OE1 signal is a digital signal 0, the first switch K1 and the first sub-switch K2 are both turned off; when the OE1 signal is a digital signal 1, the first switch K1 and the first sub-switch K2 are both turned on. When the OE2 signal is a digital signal 0, the third switch K3 and the second sub-switch K4 are both turned off; when the OE2 signal is a digital signal 1, the third switch K3 and the second sub-switch K4 are both turned on.

[0120] When the S signal is 1, the first switch K1 and the first sub-switch K2 are both electrically connected to the first adjustable voltage source 211, and the third switch K3 and the second sub-switch K4 are both electrically connected to the second adjustable voltage source 213; when the S signal is 0, the first switch K1 and the first sub-switch K2 are both electrically connected to the ground terminal, and the third switch K3 and the second sub-switch K4 are both electrically connected to the ground terminal. In addition, the priority of the OE1 signal and the OE2 signal is higher than the priority of the S signal.

[0121] Of course, it can also be set that when the OE1 signal is a digital signal 1, the first switch K1 and the first sub-switch K2 are both disconnected; when the OE1 signal is a digital signal 0, the first switch K1 and the first sub-switch K2 are both turned on. When the OE2 signal is a digital signal 1, the third switch K3 and the second sub-switch K4 are both disconnected; when the OE2 signal is a digital signal 0, the third switch K3 and the second sub-switch K4 are both turned on; when the S signal is 0, the first switch K1 and the first sub-switch K2 are both electrically connected to the first adjustable voltage source 211, and the third switch K3 and the second sub-switch K4 are both electrically connected to the second adjustable voltage source 213; when the S signal is 1, the first switch K1 and the first sub-switch K2 are both electrically connected to the ground terminal, and the third switch K3 and the second sub-switch K4 are both electrically connected to the ground terminal, which is not limited in the embodiment of the present application.

[0122] Table 2

[0123] OE1 OE2 S Working status 0 0 1 First Mode 0 0 0 First Mode 1 1 0 Second Mode 1 0 1 Third Mode 0 1 1 Fourth Mode

[0124] Referring to Table 2, the switch control circuit 11 determines whether the current working mode of the driving unit 21 is the first mode according to the waveform and timing of the excitation signal output by the driving unit 21. If so, the switch control circuit 11 inputs the OE1 signal with a digital signal of 0 to the first switch K1 and the first sub-switch K2, and inputs the OE2 signal with a digital signal of 0 to the third switch K3 and the second sub-switch K4. Under the control of the OE1 signal, the internal resistance of the first switch K1 and the first sub-switch K2 increases, and the first switch K1 and the first sub-switch K2 are both in the disconnected state; under the control of the OE2 signal, the internal resistance of the third switch K3 and the second sub-switch K4 increases, and the third switch K3 and the second sub-switch K4 are both in the disconnected state, and the driving unit 21 is in a high impedance state.

[0125] If not, the excitation signal level amplitude selection mode is entered to determine whether the driving unit 21 operates in the second mode, the third mode, or the fourth mode.

[0126] Optionally, if the driving unit 21 operates in the second mode, the switch control circuit 11 inputs an S signal and an OE1 signal whose digital signal is 1 to the first switch K1 and the first sub-switch K2, and the switch control circuit 11 inputs an S signal and an OE2 signal whose digital signal is 1 to the third switch K3 and the second sub-switch K4. Under the control of the OE1 signal, the first switch K1 and the first sub-switch K2 are both turned on; under the control of the OE2 signal, the third switch K3 and the second sub-switch K4 are both turned on.

[0127] On this basis, the S signal is a digital signal 0, the first switch K1 and the first sub-switch K2 are both electrically connected to the ground terminal, and the third switch K3 and the second sub-switch K4 are both electrically connected to the ground terminal. Since the first switch K1 and the first sub-switch K2 are also connected in parallel to the input side of the output terminal Out, the first switch K1 is electrically connected between the ground terminal and the output terminal Out, the third switch K3 is electrically connected between the ground terminal and the output terminal Out, and the excitation signal output by the output terminal Out is a low level.

[0128] For the second switch 212, if in the branch where the ground terminal, the first sub-switch K2, the first resistor R1, and the output terminal Out are located, the two ends of the resistor are electrically connected to the first sub-switch K2 and the output terminal Out respectively, then the excitation signal outputted from the ground terminal through the second switch 212 and the output terminal Out is also low level. If in the branch where the ground terminal, the first sub-switch K2, the first resistor R1, and the output terminal Out are located, the two ends of the resistor are not electrically connected to the first sub-switch K2 and / or the output terminal Out, then the branch where the ground terminal, the first sub-switch K2, the first resistor R1, and the output terminal Out are located is disconnected, but this situation does not affect the excitation signal outputted from the ground terminal through the first switch K1 and the output terminal Out is low level.

[0129] For the fourth switch 214, if in the branch where the ground terminal, the second sub-switch K4, the second resistor R2, and the output terminal Out are located, the two ends of the second resistor R2 are electrically connected to the second sub-switch K4 and the output terminal Out respectively, then the excitation signal outputted from the ground terminal through the fourth switch 214 and the output terminal Out is also low level. If in the branch where the ground terminal, the second sub-switch K4, the second resistor R2, and the output terminal Out are located, the two ends of the resistor are not electrically connected to the second sub-switch K4 and / or the output terminal Out, then the branch where the ground terminal, the second sub-switch K4, the second resistor R2, and the output terminal Out are located is disconnected, but this situation does not affect the excitation signal outputted from the ground terminal through the third switch K2 and the output terminal Out is low level.

[0130] Optionally, if the driving unit 21 operates in the third mode, the switch control circuit 11 inputs an S signal and an OE1 signal whose digital signal is 1 to the first switch K1 and the first sub-switch K2, and the switch control circuit 11 inputs an S signal and an OE1 signal whose digital signal is 0 to the third switch K3 and the second sub-switch K4. Under the control of the OE1 signal, the first switch K1 and the first sub-switch K2 are both turned on; under the control of the OE2 signal, the third switch K3 and the second sub-switch K4 are both turned off.

[0131] On this basis, the S signal is a digital signal 1, and the first switch K1 and the first sub-switch K2 are both electrically connected to the first adjustable voltage source 211. Since the first switch K1 and the first sub-switch K2 are also connected in parallel to the input side of the output terminal Out, the first switch K1 is electrically connected between the first adjustable voltage source 211 and the output terminal Out.

[0132] For the second switch 212, if in the branch where the ground terminal, the first sub-switch K2, the first resistor R1, and the output terminal Out are located, the two ends of the first resistor R1 are electrically connected to the first sub-switch K2 and the output terminal Out respectively, then the first adjustable voltage source 211 is electrically connected to the output terminal Out through the second switch 212. The branch where the first switch K1 is located and the branch where the second switch 212 is located are connected in parallel between the first adjustable voltage source 211 and the output terminal Out, and the excitation signal output by the output terminal Out is the first high level 3.3V.

[0133] Furthermore, since the branch where the first switch K1 is located and the branch where the second switch 212 is located are connected in parallel between the first adjustable voltage source 211 and the output terminal Out, the driving current of the excitation signal output by the output terminal Out is doubled, thereby improving the current driving capability of the excitation signal and avoiding the failure to achieve the test effect due to the poor quality of the signal transmitted to the chip under test.

[0134] For example, assuming that the upper limit of the current flow of the first switch K1 and the first sub-switch K2 are both 100mA, the current of the excitation signal output by the branch where the first switch K1 is located through the output terminal Out is 100mA, and when the branch where the second switch 212 is located is turned on, the current of the excitation signal output by the branch where the second switch 212 is located through the output terminal Out is also 100mA, and the two are added together, and the total current of the excitation signal output by the output terminal Out is 200mA. In addition, when the second switch 212 is turned off, the total current of the excitation signal output by the output terminal Out is 100mA. Therefore, the embodiment of the present application can also adjust the current size of the excitation signal output by the output terminal Out by controlling the second switch 212 to be turned on or off.

[0135] That is, the driving circuit 20 provided in the embodiment of the present application can also increase the current driving capability of the excitation signal input to the chip under test through a parallel branch when providing excitation signals of different states (H / L / Z) to the chip under test, thereby preventing the signal quality received by the chip under test from being too poor and failing to achieve the test effect.

[0136] Of course, the upper limit of the current flow of the first switch K1 and the first sub-switch K2 can also be other values, which is not limited in the embodiment of the present application. In addition, in order to make the excitation signal output by the drive unit 21 reach the set current value, the embodiment of the present application is not limited to the drive unit 21 including the first switch K1 and the second switch 212 in parallel. In some other possible implementations, the drive unit 21 may also include more switches connected in parallel with the first switch K1 and the second switch 212. Three or more parallel switches made by ordinary technicians in this field under the inspiration of this application are all within the protection of this application.

[0137] For the second switch 212, if in the branch where the ground terminal, the first sub-switch K2, the first resistor R1, and the output terminal Out are located, the two ends of the first resistor R1 are not electrically connected to the first sub-switch K2 and / or the output terminal Out, then the branch where the ground terminal, the first sub-switch K2, the first resistor R1, and the output terminal Out are located is disconnected, but this situation does not affect the first adjustable voltage source 211 outputting the first high level 3.3V through the first switch K1 and the output terminal Out.

[0138] In some possible implementations, in order to prevent the excitation signal reaching the chip under test from being significantly attenuated, the solution of the embodiment of the present application can also make the internal resistance of the first bipolar double-pole switch as small as possible (for example, 4.5Ω~8.5Ω) to reduce the signal voltage drop inside the first bipolar double-pole switch when driven by large current.

[0139] Optionally, if the driving unit 21 operates in the fourth mode, the switch control circuit 11 inputs an S signal and an OE1 signal whose digital signal is 0 to the third switch K3 and the second sub-switch K4, and the switch control circuit 11 inputs an S signal and an OE1 signal whose digital signal is 1 to the third switch K3 and the second sub-switch K4. Under the control of the OE1 signal, the third switch K3 and the second sub-switch K4 are both disconnected; under the control of the OE2 signal, the third switch K3 and the second sub-switch K4 are both turned on.

[0140] On this basis, the S signal is a digital signal 1, and the third switch K3 and the second sub-switch K4 are both electrically connected to the second adjustable voltage source 213. Since the third switch K3 and the second sub-switch K4 are also connected in parallel to the input side of the output terminal Out, the third switch K3 is electrically connected between the second adjustable voltage source 213 and the output terminal Out.

[0141] For the fourth switch 214, if in the branch where the ground terminal, the second sub-switch K4, the second resistor R2, and the output terminal Out are located, the two ends of the second resistor R2 are electrically connected to the second sub-switch K4 and the output terminal Out respectively, then the second adjustable voltage source 213 is electrically connected to the output terminal Out through the fourth switch 214. The branch where the third switch K3 is located and the branch where the fourth switch 214 is located are connected in parallel between the second adjustable voltage source 213 and the output terminal Out, and the excitation signal output by the output terminal Out is the second high level 2.5V.

[0142] Furthermore, since the branch where the third switch K3 is located and the branch where the fourth switch 214 is located are connected in parallel between the second adjustable voltage source 213 and the output terminal Out, the driving current of the excitation signal output by the output terminal Out is doubled, thereby improving the current driving capability of the excitation signal and avoiding the failure to achieve the test effect due to the poor quality of the signal transmitted to the chip under test.

[0143] For example, assuming that the upper limit of the current flow of the third switch K3 and the second sub-switch K4 are both 100mA, the current of the excitation signal output by the branch where the third switch K3 is located through the output terminal Out is 100mA, and when the branch where the fourth switch 214 is located is turned on, the current of the excitation signal output by the branch where the fourth switch 214 is located through the output terminal Out is also 100mA, and the two are added together, and the total current of the excitation signal output by the output terminal Out is 200mA. In addition, when the fourth switch 214 is turned off, the total current of the excitation signal output by the output terminal Out is 100mA. Therefore, the embodiment of the present application can also adjust the current size of the excitation signal output by the output terminal Out by controlling the fourth switch 214 to be turned on or off.

[0144] That is, the driving circuit 20 provided in the embodiment of the present application can also increase the current driving capability of the excitation signal input to the chip under test through a parallel branch when providing excitation signals of different states (H / L / Z) to the chip under test, thereby preventing the signal quality received by the chip under test from being too poor and failing to achieve the test effect.

[0145] Of course, the upper limit of the current flow of the third switch K3 and the second sub-switch K4 can also be other values, which is not limited in the embodiment of the present application. In addition, in order to make the excitation signal output by the driving unit 21 reach the set current value, the embodiment of the present application is not limited to the driving unit 21 including the third switch K3 and the fourth switch 214 in parallel. In some other possible implementations, the driving unit 21 can also include more switches connected in parallel with the third switch K3 and the fourth switch 214. Under the guidance of this application, three or more parallel switches made by ordinary technicians in this field are all within the protection of this application.

[0146] For the fourth switch 214, if in the branch where the ground terminal, the second sub-switch K4, the second resistor R2, and the output terminal Out are located, the two ends of the second resistor R2 are not electrically connected to the second sub-switch K4 and / or the output terminal Out, then the branch where the second adjustable voltage source 213, the second sub-switch K4, the second resistor R2, and the output terminal Out are located is disconnected, but this situation does not affect the second adjustable voltage source 213 outputting the second high level 2.5V through the third switch K3 and the output terminal Out.

[0147] In some possible implementations, in order to prevent the excitation signal reaching the chip under test from being significantly attenuated, the solution of the embodiment of the present application can also make the internal resistance of the second bipolar double-pole switch as small as possible (for example, 4.5Ω~8.5Ω) to reduce the signal voltage drop inside the second bipolar double-pole switch when driven by large current.

[0148] In some embodiments, Figure 8 As shown, the circuit further includes a receiving circuit 30. Fig. 9 As shown, the receiving circuit 30 is electrically connected to the output side of the chip under test and the output side of the driving circuit 20. The receiving circuit 30 includes a first comparator 31, a second comparator 32, a third adjustable voltage source 33, and a fourth adjustable voltage source 34. The main control circuit also includes a detection circuit 13.

[0149] The first comparator 31 includes a first input terminal, a second input terminal, and a first output terminal, and the second comparator 32 includes a third input terminal, a fourth input terminal, and a second output terminal. The first output terminal is electrically connected to the detection circuit 13, and the second output terminal is electrically connected to the detection circuit 13.

[0150] The main control circuit 10 controls the first input terminal to be electrically connected to the third adjustable voltage source 33, so as to input the first reference high level to the first comparator 31 by using the third adjustable voltage source 33. The main control circuit 10 controls the third input terminal to be electrically connected to the fourth adjustable voltage source 34, so as to input the first reference low level to the second comparator 32 by using the fourth adjustable voltage source 34.

[0151] In the first application scenario, the receiving circuit 20 is used to receive a signal output by the chip under test, and compare the signal output by the chip under test with an expected value to identify the signal output by the chip under test, so as to test the chip under test.

[0152] In the second application scenario, the receiving circuit 20 is used to receive the first high level sent by the driving circuit 20 to determine whether the first adjustable voltage source 211 is qualified; or, the receiving circuit 20 is used to receive the second high level sent by the driving circuit 20 to determine whether the second adjustable voltage source 213 is qualified.

[0153] Specifically, Fig.10 The working principle of the receiving circuit 30 and the detection circuit 13 in the first application scenario is shown. Fig.10 The bold line with an arrow in the middle indicates the source of the signal received by the receiving circuit 30 . It can be seen that the receiving circuit 30 receives the signal output by the chip under test.

[0154] like Fig.10 As shown, the main control circuit 10 controls the chip under test (ie, the external circuit) to input the first voltage to the first comparator 31 through the second input terminal, and controls the chip under test to input the first voltage to the second comparator 32 through the fourth input terminal.

[0155] The first comparator 31 compares the received first voltage with the first reference high level, and inputs the first comparison result to the detection circuit 13. The second comparator is configured to compare the received first voltage with the first reference low level, and input the second comparison result to the detection circuit 13. The detection circuit 13 identifies the first voltage according to the first comparison result and the second comparison result.

[0156] For example, ideally, the first voltage output by the chip under test should be 3.3 V. According to the voltage value of 3.3 V, the first reference high level can be set to 2.6 V and the first reference low level can be set to 0.7 V. During the aging test, the first voltage actually output by the chip under test may have an error. In order to identify the first voltage actually output by the chip under test, the second input terminal of the first comparator 31 and the fourth input terminal of the second comparator 32 are used to receive the first voltage.

[0157] For example, the first voltage actually output by the chip under test is 2.9V. After receiving the first voltage of 2.9V, the first comparator 31 compares the first reference high level of 2.6V with the first voltage of 2.9V. Since 2.9V>2.6V, the first comparator 31 inputs the first comparison result of the digital signal of 1 to the detection circuit 13. After receiving the first voltage of 2.9V, the second comparator 32 compares the first reference low level of 0.7V with the first voltage of 2.9V. Since 2.9V>0.7V, the second comparator 32 inputs the second comparison result of the digital signal of 1 to the detection circuit 13.

[0158] The detection circuit 13 confirms that the first voltage (2.9V) actually output by the chip under test is a high level according to the received first comparison result (digital signal 1) and the second comparison result (digital signal 1).

[0159] For another example, the first voltage actually output by the chip under test is 0.3V. After receiving the first voltage of 0.3V, the first comparator 31 compares the first reference high level of 2.6V with the first voltage of 0.3V. Since 2.6V>0.3V, the first comparator 31 inputs the first comparison result of the digital signal being 0 to the detection circuit 13. After receiving the first voltage of 0.3V, the second comparator 32 compares the first reference low level of 0.7V with the first voltage of 0.3V. Since 0.7V>0.3V, the second comparator 32 inputs the second comparison result of the digital signal being 0 to the detection circuit 13.

[0160] The detection circuit 13 confirms that the first voltage (0.3V) actually output by the chip under test is a low level according to the received first comparison result (digital signal 0) and the second comparison result (digital signal 0).

[0161] In some possible implementations, the signal quality of the first voltage output by the chip under test is poor, and the first voltage falls between 0.7V and 2.6V. In order to use the receiving circuit 30 and the detection circuit 13 to identify the first voltage, the first reference high level and the first reference low level can be adjusted. For example, the first reference high level is adjusted from 2.6V to 1.5V, and the first reference low level is adjusted from 0.7V to 1.2V.

[0162] Of course, according to actual needs, the first reference high level and the first reference low level may also be adjusted to other values, which is not limited in the embodiments of the present application.

[0163] For example, the first voltage actually output by the chip under test is 2V. After receiving the first voltage of 2V, the first comparator 31 compares the first reference high level of 1.5V with the first voltage of 2V. Since 2V>1.5V, the first comparator 31 inputs the first comparison result of the digital signal 1 to the detection circuit 13. After receiving the first voltage of 2V, the second comparator 32 compares the first reference low level of 1.2V with the first voltage of 2V. Since 2V>1.2V, the second comparator 32 inputs the second comparison result of the digital signal 1 to the detection circuit 13.

[0164] The detection circuit 13 confirms that the first voltage (2V) actually output by the chip under test is a high level according to the received first comparison result (digital signal 1) and the second comparison result (digital signal 1).

[0165] For another example, the first voltage actually output by the chip under test is 0.9V. After receiving the first voltage of 0.9V, the first comparator 31 compares the first reference high level of 1.5V with the first voltage of 0.9V. Since 1.5V>0.9V, the first comparator 31 inputs the first comparison result of the digital signal being 0 to the detection circuit 13. After receiving the first voltage of 0.9V, the second comparator 32 compares the first reference low level of 1.2V with the first voltage of 0.9V. Since 1.2V>0.9V, the second comparator 32 inputs the second comparison result of the digital signal being 0 to the detection circuit 13.

[0166] The detection circuit 13 confirms that the first voltage (0.9V) actually output by the chip under test is a low level according to the received first comparison result (digital signal 0) and the second comparison result (digital signal 0).

[0167] Fig.11 The working principle of the receiving circuit 30 and the detection circuit 13 in the second application scenario is shown. Fig.11 The bold line with an arrow indicates the source of the signal received by the receiving circuit 30 . It can be seen that the driving unit 21 works in the third mode, and the first high level or low level output by the driving unit 21 is input to the chip under test and the receiving circuit 30 respectively.

[0168] like Fig.11 As shown, the main control circuit is configured to: in the third mode, the control driving unit 21 inputs the first high level to the first comparator through the output terminal and the second input terminal, and the control driving unit 21 inputs the first high level to the second comparator 32 through the output terminal Out and the fourth input terminal.

[0169] The first comparator 31 compares the received first high level with the first reference high level, and inputs a third comparison result to the detection circuit. The second comparator 32 compares the received first high level with the first reference low level, and inputs a fourth comparison result to the detection circuit. The detection circuit 13 determines whether the first adjustable voltage source 211 is qualified according to the third comparison result and the fourth comparison result.

[0170] For example, ideally, the first high level output by the first adjustable voltage source 211 is 3.3V, and the first high level output by the driving unit 21 is also 3.3V. According to the voltage value of 3.3V, the first reference high level can be set to 2.6V and the first reference low level to 0.7V. During the aging test, the first high level output by the first adjustable voltage source 211 may have an error. In order to confirm whether the first adjustable voltage source 211 is qualified, the first high level output by the driving unit 21 is received by the second input terminal of the first comparator 31 and the fourth input terminal of the second comparator 32, respectively.

[0171] For example, the first high level actually output by the driving unit 21 is 3V. After receiving the first high level of 3V, the first comparator 31 compares the first reference high level of 2.6V with the first high level of 3V. Since 3V>2.6V, the first comparator 31 inputs the third comparison result of the digital signal 1 to the detection circuit 13. After receiving the first high level of 3V, the second comparator 32 compares the first reference low level of 0.7V with the first high level of 3V. Since 3V>0.7V, the second comparator 32 inputs the fourth comparison result of the digital signal 1 to the detection circuit 13.

[0172] The detection circuit 13 confirms that the first adjustable voltage source 211 is qualified according to the received third comparison result (digital signal 1) and the fourth comparison result (digital signal 1).

[0173] For another example, the first high level actually output by the driving unit 21 is 1V. After receiving the first high level of 1V, the first comparator 31 compares the first reference high level of 2.6V with the first high level of 1V. Since 2.6V>1V, the first comparator 31 inputs the third comparison result of the digital signal 0 to the detection circuit 13. After receiving the first high level of 1V, the second comparator 32 compares the first reference low level of 0.7V with the first high level of 1V. Since 0.7V<1V, the second comparator 32 inputs the fourth comparison result of the digital signal 1 to the detection circuit 13.

[0174] The detection circuit 13 determines that the first adjustable voltage source 211 is unqualified according to the received third comparison result (digital signal 0) and the fourth comparison result (digital signal 1).

[0175] The first application scenario and the second application scenario described above introduce the case where the receiving circuit 30 includes a third adjustable voltage source 33 and a fourth adjustable voltage source 34. In other embodiments, the receiving circuit 30 may further include other more adjustable voltage sources.

[0176] For example, in the third application scenario, the signal output by the chip under test is two voltage values ​​of different standards. The third adjustable voltage source 33 and the fourth adjustable voltage source 34 can be used to identify the voltage value of one standard, and the fifth adjustable voltage source 35 and the sixth adjustable voltage source 36 can be used to identify the voltage value of the other standard.

[0177] For another example, in the fourth application scenario, when the driving unit 21 includes a second adjustable voltage source, the receiving circuit 30 may further include a fifth adjustable voltage source 35 and a sixth adjustable voltage source 36, and the third adjustable voltage source 33 and the fourth adjustable voltage source 34 are used to detect whether the second adjustable voltage source 213 is qualified, and the fifth adjustable voltage source 35 and the sixth adjustable voltage source 36 are used to detect whether the second adjustable voltage source 213 is qualified.

[0178] Fig.13 The working principle of the receiving circuit 30 and the detection circuit 13 in the third application scenario is shown. Fig.13 The bold line with an arrow in the middle indicates the source of the signal received by the receiving circuit 30 . It can be seen that the receiving circuit 30 receives the signal output by the chip under test.

[0179] exist Fig. 9 On the basis of the receiving circuit 30 shown, the receiving circuit 30 may further include a fifth switch K5 and a sixth switch K6. The main control circuit 10 controls the fifth switch K5 and the sixth switch K6 to enable the third adjustable voltage source 33 and the fourth adjustable voltage source 34 to work simultaneously, and the fifth adjustable voltage source 35 and the sixth adjustable voltage source 36 to work simultaneously. The fifth switch K5 and the sixth switch K6 may both be single-pole double-throw switches.

[0180] For example, assuming that the signal output by the chip under test is a first voltage, the main control circuit 10 controls the first input terminal to be electrically connected to the third adjustable voltage source 33 through the fifth switch K5, and to be disconnected from the fifth adjustable voltage source 35 through the fifth switch K5, and the third adjustable voltage source 33 inputs a first reference high level to the first comparator 31; the main control circuit 10 also controls the third input terminal to be electrically connected to the fourth adjustable voltage source 34 through the sixth switch K6, and to be disconnected from the sixth adjustable voltage source 36 through the sixth switch K6, and the fourth adjustable voltage source 34 inputs a first reference low level to the second comparator 32.

[0181] The first comparator 31 compares the received first voltage with the first reference high level, and inputs the first comparison result to the detection circuit 13. The second comparator is configured to compare the received first voltage with the first reference low level, and input the second comparison result to the detection circuit 13. The detection circuit 13 identifies the first voltage according to the first comparison result and the second comparison result.

[0182] Assuming that ideally, the first voltage output by the chip under test should be 3.3 V. According to the voltage value of 3.3 V, the first reference high level can be set to 2.6 V and the first reference low level can be set to 0.7 V. During the aging test, the first voltage actually output by the chip under test may have errors. In order to identify the first voltage actually output by the chip under test, the second input terminal of the first comparator 31 and the fourth input terminal of the second comparator 32 are used to receive the first voltage respectively.

[0183] For example, the first voltage actually output by the chip under test is 2.9V. After receiving the first voltage of 2.9V, the first comparator 31 compares the first reference high level of 2.6V with the first voltage of 2.9V. Since 2.9V>2.6V, the first comparator 31 inputs the first comparison result of the digital signal of 1 to the detection circuit 13. After receiving the first voltage of 2.9V, the second comparator 32 compares the first reference low level of 0.7V with the first voltage of 2.9V. Since 2.9V>0.7V, the second comparator 32 inputs the second comparison result of the digital signal of 1 to the detection circuit 13.

[0184] The detection circuit 13 confirms that the first voltage (2.9V) actually output by the chip under test is a high level according to the received first comparison result (digital signal 1) and the second comparison result (digital signal 1).

[0185] For another example, the first voltage actually output by the chip under test is 0.3V. After receiving the first voltage of 0.3V, the first comparator 31 compares the first reference high level of 2.6V with the first voltage of 0.3V. Since 2.6V>0.3V, the first comparator 31 inputs the first comparison result of the digital signal being 0 to the detection circuit 13. After receiving the first voltage of 0.3V, the second comparator 32 compares the first reference low level of 0.7V with the first voltage of 0.3V. Since 0.7V>0.3V, the second comparator 32 inputs the second comparison result of the digital signal being 0 to the detection circuit 13.

[0186] The detection circuit 13 confirms that the first voltage (0.3V) actually output by the chip under test is a low level according to the received first comparison result (digital signal 0) and the second comparison result (digital signal 0).

[0187] For example, assuming that the signal output by the chip under test is a second voltage (the second voltage is different from the first voltage), the main control circuit 10 controls the first input terminal to be disconnected from the third adjustable voltage source 33 through the fifth switch K5, and to be electrically connected to the fifth adjustable voltage source 35 through the fifth switch K5, and the fifth adjustable voltage source 35 inputs a second reference high level to the first comparator 31; the main control circuit 10 also controls the third input terminal to be disconnected from the fourth adjustable voltage source 34 through the sixth switch K6, and to be electrically connected to the sixth adjustable voltage source 36 through the sixth switch K6, and the sixth adjustable voltage source 36 inputs a second reference low level to the second comparator 32. Among them, the first reference low level is different from the second reference low level, and the first reference high level is different from the second reference high level.

[0188] The first comparator 31 compares the received second voltage with the second reference high level, and inputs a fifth comparison result to the detection circuit 13. The second comparator is configured to compare the received second voltage with the second reference low level, and input a sixth comparison result to the detection circuit 13. The detection circuit 13 identifies the second voltage according to the fifth comparison result and the sixth comparison result.

[0189] Assuming that ideally, the second voltage output by the chip under test should be 2.5 V. According to the voltage value of 2.5 V, the second reference high level can be set to 2 V and the second reference low level can be set to 0.5 V. During the aging test, the second voltage actually output by the chip under test may have errors. In order to identify the second voltage actually output by the chip under test, the second input terminal of the first comparator 31 and the fourth input terminal of the second comparator 32 are used to receive the second voltage.

[0190] For example, the second voltage actually output by the chip under test is 2.1V. After receiving the second voltage of 2.1V, the first comparator 31 compares the second reference high level of 2V with the second voltage of 2.1V. Since 2.1V>2V, the first comparator 31 inputs the fifth comparison result of the digital signal 1 to the detection circuit 13. After receiving the second voltage of 2.1V, the second comparator 32 compares the second reference low level of 0.5V with the second voltage of 2.1V. Since 2.1V>0.5V, the second comparator 32 inputs the sixth comparison result of the digital signal 1 to the detection circuit 13.

[0191] The detection circuit 13 confirms that the second voltage (2.1V) actually output by the chip under test is a high level according to the received fifth comparison result (digital signal 1) and the sixth comparison result (digital signal 1).

[0192] For another example, the second voltage actually output by the chip under test is 0.3V. After receiving the second voltage of 0.3V, the first comparator 31 compares the second reference high level of 2V with the second voltage of 0.3V. Since 2V>0.3V, the first comparator 31 inputs the fifth comparison result of the digital signal being 0 to the detection circuit 13. After receiving the second voltage of 0.3V, the second comparator 32 compares the second reference low level of 0.5V with the second voltage of 0.3V. Since 0.5V>0.3V, the second comparator 32 inputs the sixth comparison result of the digital signal being 0 to the detection circuit 13.

[0193] The detection circuit 13 confirms that the second voltage (0.3V) actually output by the chip under test is a low level according to the received fifth comparison result (digital signal 0) and the sixth comparison result (digital signal 0).

[0194] In some possible implementations, the signal quality of the first voltage output by the chip under test is poor, and the first voltage falls between 0.7V and 2.6V. In order to use the receiving circuit 30 and the detection circuit 13 to identify the first voltage, the first reference high level and the first reference low level can be adjusted. For example, the first reference high level is adjusted from 2.6V to 1.5V, and the first reference low level is adjusted from 0.7V to 1.2V.

[0195] In some possible implementations, the signal quality of the second voltage output by the chip under test is poor, and the second voltage falls between 0.5V and 2V. In order to identify the second voltage using the receiving circuit 30 and the detection circuit 13, the second reference high level and the second reference low level can be optionally adjusted. For example, the second reference high level is adjusted from 2V to 1.5V, and the second reference low level is adjusted from 0.5V to 1V.

[0196] Of course, according to actual needs, the first reference high level, the first reference low level, the second reference high level, and the second reference low level can also be adjusted to other values, and the embodiment of the present application is not limited to this. In different application scenarios, the power supply regulation circuit 12 can be used to parse the configuration file, and adjust the first reference high level output by the third adjustable voltage source 33, adjust the first reference low level output by the fourth adjustable voltage source 34, adjust the second reference high level output by the fifth adjustable voltage source 35, and adjust the second reference low level output by the sixth adjustable voltage source 36 according to the configuration file.

[0197] Fig.14 The working principle of the receiving circuit 30 and the detection circuit 13 in the fourth application scenario is shown. Fig.14The bold line with an arrow indicates the source of the signal received by the receiving circuit 30 . It can be seen that the driving unit 21 works in the third mode, and the second high level or low level output by the driving unit 21 is input to the chip under test and the receiving circuit 30 respectively.

[0198] For example, assuming that the first high level output by the first adjustable voltage source 211 is 3.3V, and the signal output by the chip under test is the first voltage, the main control circuit 10 controls the first input terminal to be electrically connected to the third adjustable voltage source 33 through the fifth switch K5, and to be disconnected from the fifth adjustable voltage source 35 through the fifth switch K5, and the third adjustable voltage source 33 inputs a first reference high level to the first comparator 31; the main control circuit 10 also controls the third input terminal to be electrically connected to the fourth adjustable voltage source 34 through the sixth switch K6, and to be disconnected from the sixth adjustable voltage source 36 through the sixth switch K6, and the fourth adjustable voltage source 34 inputs a first reference low level to the second comparator 32.

[0199] The first comparator 31 compares the received first high level with the first reference high level, and inputs a third comparison result to the detection circuit 13. The second comparator compares the received first high level with the first reference low level, and inputs a fourth comparison result to the detection circuit 13. The detection circuit 13 determines whether the first adjustable voltage source 211 is qualified according to the third comparison result and the fourth comparison result.

[0200] For example, the first high level actually output by the driving unit 21 is 3V. After receiving the first high level of 3V, the first comparator 31 compares the first reference high level of 2.6V with the first high level of 3V. Since 3V>2.6V, the first comparator 31 inputs the third comparison result of the digital signal 1 to the detection circuit 13. After receiving the first high level of 3V, the second comparator 32 compares the first reference low level of 0.7V with the first high level of 3V. Since 3V>0.7V, the second comparator 32 inputs the fourth comparison result of the digital signal 1 to the detection circuit 13.

[0201] The detection circuit 13 confirms that the first adjustable voltage source 211 is qualified according to the received third comparison result (digital signal 1) and the fourth comparison result (digital signal 1).

[0202] For another example, the first high level actually output by the driving unit 21 is 1V. After receiving the first high level of 1V, the first comparator 31 compares the first reference high level of 2.6V with the first high level of 1V. Since 2.6V>1V, the first comparator 31 inputs the third comparison result of the digital signal 0 to the detection circuit 13. After receiving the first high level of 1V, the second comparator 32 compares the first reference low level of 0.7V with the first high level of 1V. Since 0.7V<1V, the second comparator 32 inputs the fourth comparison result of the digital signal 1 to the detection circuit 13.

[0203] The detection circuit 13 determines that the first adjustable voltage source 211 is unqualified according to the received third comparison result (digital signal 0) and the fourth comparison result (digital signal 1).

[0204] For example, assuming that the second high level input by the driving unit 21 to the first comparator 31 and the second comparator 32 is 2.5V, the main control circuit 10 controls the first input terminal to be disconnected from the third adjustable voltage source 33 through the fifth switch K5, and to be electrically connected to the fifth adjustable voltage source 35 through the fifth switch K5, and the fifth adjustable voltage source 35 inputs a second reference high level to the first comparator 31; the main control circuit 10 also controls the third input terminal to be disconnected from the fourth adjustable voltage source 34 through the sixth switch K6, and to be electrically connected to the sixth adjustable voltage source 36 through the sixth switch K6, and the sixth adjustable voltage source 36 inputs a second reference low level to the second comparator 32.

[0205] The first comparator 31 compares the received second high level with the second reference high level, and inputs a seventh comparison result to the detection circuit 13. The second comparator 32 compares the received second high level with the second reference low level, and inputs an eighth comparison result to the detection circuit 13. The detection circuit 13 determines whether the second adjustable voltage source 213 is qualified according to the seventh comparison result and the eighth comparison result.

[0206] For example, the second high level actually output by the driving unit 21 is 2.2V. After receiving the second high level of 2.2V, the first comparator 31 compares the second reference high level of 2V with the second high level of 2.2V. Since 2.2V>2V, the first comparator 31 inputs the seventh comparison result of the digital signal 1 to the detection circuit 13. After receiving the second high level of 2.2V, the second comparator 32 compares the second reference low level of 0.5V with the second high level of 2.2V. Since 2.2V>0.5V, the second comparator 32 inputs the eighth comparison result of the digital signal 1 to the detection circuit 13.

[0207] The detection circuit 13 confirms that the second adjustable voltage source 213 is qualified according to the received seventh comparison result (digital signal 1) and the eighth comparison result (digital signal 1).

[0208] For another example, the second high level actually output by the driving unit 21 is 1V. After receiving the second high level of 1V, the first comparator 31 compares the second reference high level of 2V with the second high level of 1V. Since 2V>1V, the first comparator 31 inputs the seventh comparison result of the digital signal 0 to the detection circuit 13. After receiving the second high level of 1V, the second comparator 32 compares the second reference low level of 0.5V with the second high level of 1V. Since 0.5V<1V, the second comparator 32 inputs the eighth comparison result of the digital signal 1 to the detection circuit 13.

[0209] The detection circuit 13 determines that the second adjustable voltage source 213 is unqualified according to the received seventh comparison result (digital signal 0) and the eighth comparison result (digital signal 1).

[0210] In another embodiment, the present application also provides a circuit control method, such as Figure 4 As shown, the circuit includes a driving circuit 10 and a main control circuit 20. The driving circuit 20 includes a plurality of driving units 21, and the driving unit 21 includes a first adjustable voltage source 211, a first switch K1, a second switch 212, a ground terminal, and an output terminal Out. The first switch K1 and the second switch 212 are connected in parallel to the input side of the output terminal Out. The main control circuit 10 includes a plurality of switch control circuits 11, and each switch control circuit 11 is used to control one driving unit 21.

[0211] like Fig.15 As shown, this can be achieved through the following steps:

[0212] S110 , in the first mode, the switch control circuit 11 is used to control the first switch K1 and the second switch 212 to be turned off.

[0213] Before step S110 , step S120 , and step S130 , the main control circuit 10 may parse the vector configuration file to determine the first high level configured for the first adjustable voltage source 211 , or in other words, to determine the first high level that the first adjustable voltage source 211 can output.

[0214] In some possible implementations, the main control circuit 10 further includes a power regulation circuit 12. In different application scenarios, the power regulation circuit 12 can be used to parse a configuration file and adjust the first high level voltage value output by the first adjustable voltage source 211 according to the configuration file.

[0215] For example, at the 1st μs, the power supply regulating circuit 12 controls the first adjustable voltage source 211 to output a first high level of 3.3 V. At the 10th μs, the power supply regulating circuit 12 controls the first adjustable voltage source 211 to output a first high level of 1.8 V.

[0216] The switch control circuit 11 may also parse the vector configuration file and decode the waveform and timing of the output of the driving unit 21 to determine the waveform and timing of the excitation signal to be output by the driving unit 21 .

[0217] Next, step S110 is executed, the switch control circuit 11 determines the current working mode of the driving unit 21 according to the waveform and timing of the excitation signal to be output by the driving unit 21, and sends the OE1 signal and the S signal to the first switch K1 and the second switch 212. Under the control of the OE1 signal and the S signal, the driving unit 21 works in the first mode, the second mode, or the third mode.

[0218] For example, referring to Table 1, assuming that when the OE1 signal is a digital signal 0, the first switch K1 and the first sub-switch K2 are both disconnected; when the OE1 signal is a digital signal 1, the first switch K1 and the first sub-switch K2 are both turned on. When the S signal is 1, the first switch K1 and the first sub-switch K2 are both electrically connected to the first adjustable voltage source 211; when the S signal is 0, the first switch K1 and the first sub-switch K2 are both electrically connected to the ground terminal. In addition, the priority of the OE1 signal is higher than the priority of the S signal.

[0219] Of course, it can also be set that when the OE1 signal is a digital signal 1, the first switch K1 and the first sub-switch K2 are both disconnected; when the OE1 signal is a digital signal 0, the first switch K1 and the first sub-switch K2 are both turned on; when the S signal is 0, the first switch K1 and the first sub-switch K2 are both electrically connected to the first adjustable voltage source 211; when the S signal is 1, the first switch K1 and the first sub-switch K2 are both electrically connected to the ground terminal, and the embodiment of the present application is not limited to this.

[0220] Table 1

[0221] OE1 S Working status 0 1 First Mode 0 0 First Mode 1 0 Second Mode 1 1 Third Mode

[0222] Referring to Table 1, the switch control circuit 11 determines whether the current working mode of the driving unit 21 is the first mode according to the waveform and timing of the excitation signal output by the driving unit 21. If so, the switch control circuit 11 inputs an OE1 signal with a digital signal of 0 to the first switch K1 and the first sub-switch K2. Under the control of the OE1 signal, the internal resistance of the first switch K1 and the first sub-switch K2 increases, the first switch K1 and the first sub-switch K2 are both in the disconnected state, and the driving unit 21 is in a high impedance state.

[0223] If not, the process enters the excitation signal level amplitude selection mode to determine whether the driving unit 21 operates in the second mode or the third mode, that is, executing step S120 and step S130.

[0224] S120 , in the second mode, the switch control circuit 11 is used to control the ground terminal to be electrically connected to the output terminal through the first switch K1 and the second switch 212 , so as to output a low level through the output terminal Out.

[0225] If the driving unit 21 operates in the second mode, the switch control circuit 11 inputs the S signal and the OE1 signal whose digital signal is 1 to the first switch K1 and the first sub-switch K2. Under the control of the OE1 signal, the first switch K1 and the first sub-switch K2 are both turned on. On this basis, the S signal is the digital signal 0, and the first switch K1 and the first sub-switch K2 are both electrically connected to the ground terminal. Since the first switch K1 and the first sub-switch K2 are also connected in parallel to the input side of the output terminal Out, the first switch K1 is electrically connected between the ground terminal and the output terminal Out, and the excitation signal output by the output terminal Out is a low level. The driving unit 21 can input the low level to the chip under test on the aging board through the output terminal Out to perform an aging test on the chip under test.

[0226] For the second switch 212, if in the branch where the ground terminal, the first sub-switch K2, the first resistor R1, and the output terminal Out are located, the two ends of the first resistor R1 are electrically connected to the first sub-switch K2 and the output terminal Out respectively, then the excitation signal outputted from the ground terminal through the second switch 212 and the output terminal Out is also low level. If in the branch where the ground terminal, the first sub-switch K2, the first resistor R1, and the output terminal Out are located, the two ends of the first resistor R1 are not electrically connected to the first sub-switch K2 and / or the output terminal Out, then the branch where the ground terminal, the first sub-switch K2, the first resistor R1, and the output terminal Out are located is disconnected, but this situation does not affect the excitation signal outputted from the ground terminal through the first switch K1 and the output terminal Out is low level.

[0227] In some possible implementations, if the first resistor R1 is coupled to a circuit board where the circuit of the present application is located, the two ends of the first resistor R1 are electrically connected to the first sub-switch K2 and the output end Out, respectively; otherwise, the two ends of the first resistor R1 are not electrically connected to the first sub-switch K2 and / or the output end Out.

[0228] S130, in the third mode, outputting a first high level through the first adjustable voltage source 211; utilizing the switch control circuit 11 to control the first adjustable voltage source 211 to be electrically connected to the output terminal Out through the first switch K1, or controlling the first adjustable voltage source 211 to be electrically connected to the output terminal Out through the first switch K1 and the second switch 212 respectively, so as to output the first high level through the output terminal Out.

[0229] If the driving unit 21 operates in the third mode, the switch control circuit 11 inputs the S signal and the OE1 signal whose digital signal is 1 to the first switch K1 and the first sub-switch K2. Under the control of the OE1 signal, the first switch K1 and the first sub-switch K2 are both turned on. On this basis, the S signal is the digital signal 1, and the first switch K1 and the first sub-switch K2 are both electrically connected to the first adjustable voltage source 211. Since the first switch K1 and the first sub-switch K2 are also connected in parallel to the input side of the output terminal Out, the first switch K1 is electrically connected between the first adjustable voltage source 211 and the output terminal Out.

[0230] For the second switch 212, if in the branch where the ground terminal, the first sub-switch K2, the first resistor R1, and the output terminal Out are located, the two ends of the first resistor R1 are electrically connected to the first sub-switch K2 and the output terminal Out respectively, then the first adjustable voltage source 211 is electrically connected to the output terminal Out through the second switch 212. The branch where the first switch K1 is located and the branch where the second switch 212 is located are connected in parallel between the first adjustable voltage source 211 and the output terminal Out, and the excitation signal output by the output terminal Out is a first high level. The driving unit 21 can input the first high level to the chip under test on the aging board through the output terminal Out to perform an aging test on the chip under test.

[0231] Furthermore, since the branch where the first switch K1 is located and the branch where the second switch 212 is located are connected in parallel between the first adjustable voltage source 211 and the output terminal Out, the driving current of the excitation signal output by the output terminal Out is doubled, thereby improving the current driving capability of the excitation signal and avoiding the failure to achieve the test effect due to the poor quality of the signal transmitted to the chip under test.

[0232] For example, assuming that the upper limit of the current flow of the first switch K1 and the first sub-switch K2 are both 100mA, the current of the excitation signal output by the branch where the first switch K1 is located through the output terminal Out is 100mA, and when the branch where the second switch 212 is located is turned on, the current of the excitation signal output by the branch where the second switch 212 is located through the output terminal Out is also 100mA, and the two are added together, and the total current of the excitation signal output by the output terminal Out is 200mA. In addition, when the second switch 212 is turned off, the total current of the excitation signal output by the output terminal Out is 100mA. Therefore, the embodiment of the present application can also adjust the current size of the excitation signal output by the output terminal Out by controlling the second switch 212 to be turned on or off.

[0233] That is, the driving circuit 20 provided in the embodiment of the present application can also increase the current driving capability of the excitation signal input to the chip under test through a parallel branch when providing excitation signals of different states (H / L / Z) to the chip under test, thereby preventing the signal quality received by the chip under test from being too poor and failing to achieve the test effect.

[0234] Of course, the upper limit of the current flow of the first switch K1 and the first sub-switch K2 can also be other values, which is not limited in the embodiment of the present application. In addition, in order to make the excitation signal output by the drive unit 21 reach the set current value, the embodiment of the present application is not limited to the drive unit 21 including the first switch K1 and the second switch 212 in parallel. In some other possible implementations, the drive unit 21 may also include more switches connected in parallel with the first switch K1 and the second switch 212. Three or more parallel switches made by ordinary technicians in this field under the inspiration of this application are all within the protection of this application.

[0235] For the second switch 212, if in the branch where the ground terminal, the first sub-switch K2, the first resistor R1, and the output terminal Out are located, the two ends of the first resistor R1 are not electrically connected to the first sub-switch K2 and / or the output terminal Out, then the branch where the first adjustable voltage source 211, the first sub-switch K2, the first resistor R1, and the output terminal Out are located is disconnected, but this situation does not affect the first adjustable voltage source 211 outputting the first high level through the first switch K1 and the output terminal Out.

[0236] In some possible implementations, in order to prevent the excitation signal reaching the chip under test from being significantly attenuated, the solution of the embodiment of the present application can also make the internal resistance of the first bipolar double-pole switch as small as possible (for example, 4.5Ω~8.5Ω) to reduce the signal voltage drop inside the first bipolar double-pole switch when driven by large current.

[0237] Of course, the above steps S110, S120, and S130 can be performed in any order, which is not limited in the present embodiment. That is, the execution order of steps S110, S120, and S130 is based on the waveform and timing of the excitation signal output by the driving unit 21.

[0238] In some embodiments, the driving unit 21 includes, in addition to the first adjustable voltage source 211, a second adjustable voltage source 213 as an example. Figure 6 As shown, the driving unit 21 further includes a third switch K3 and a fourth switch 214. The third switch K3 and the fourth switch 214 are connected in parallel to the input side of the output terminal Out. The circuit control method further includes:

[0239] The main control circuit 10 parses the vector configuration file to determine the first high level configured to the first adjustable voltage source 211 and the second high level configured to the second adjustable voltage source 213. In other words, the main control circuit 10 parses the vector configuration file to determine the first high level that the first adjustable voltage source 211 can output and the second high level that the second adjustable voltage source 213 can output.

[0240] In some possible implementations, the main control circuit 10 further includes a power supply regulating circuit 12. In different application scenarios, the power supply regulating circuit 12 can be used to parse the configuration file, and adjust the voltage value of the first high level output by the first adjustable voltage source 211 and the voltage value of the second high level output by the second adjustable voltage source 213 according to the configuration file.

[0241] For example, the power regulation circuit 12 controls the first high level output by the first adjustable voltage source 211 to be 3.3V, and controls the first high level output by the second adjustable voltage source 213 to be 2.5V.

[0242] The switch control circuit 11 may also parse the vector configuration file and decode the waveform and timing of the output of the driving unit 21 to determine the waveform and timing of the excitation signal to be output by the driving unit 21 .

[0243] The switch control circuit 11 determines the current working mode of the driving unit 21 according to the waveform and timing of the excitation signal to be output by the driving unit 21, and sends the OE1 signal and the S signal to the first switch K1 and the second switch 212, and sends the OE2 signal and the S signal to the third switch K3 and the fourth switch 214. Under the control of the OE1 signal, the OE2 signal and the S signal, the driving unit 21 works in the first mode, the second mode, the third mode, or the fourth mode.

[0244] For example, referring to Table 2, assuming that when the OE1 signal is a digital signal 0, the first switch K1 and the first sub-switch K2 are both turned off; when the OE1 signal is a digital signal 1, the first switch K1 and the first sub-switch K2 are both turned on. When the OE2 signal is a digital signal 0, the third switch K3 and the second sub-switch K4 are both turned off; when the OE2 signal is a digital signal 1, the third switch K3 and the second sub-switch K4 are both turned on.

[0245] When the S signal is 1, the first switch K1 and the first sub-switch K2 are both electrically connected to the first adjustable voltage source 211, and the third switch K3 and the second sub-switch K4 are both electrically connected to the second adjustable voltage source 213; when the S signal is 0, the first switch K1 and the first sub-switch K2 are both electrically connected to the ground terminal, and the third switch K3 and the second sub-switch K4 are both electrically connected to the ground terminal. In addition, the priority of the OE1 signal and the OE2 signal is higher than the priority of the S signal.

[0246] Of course, it can also be set that when the OE1 signal is a digital signal 1, the first switch K1 and the first sub-switch K2 are both disconnected; when the OE1 signal is a digital signal 0, the first switch K1 and the first sub-switch K2 are both turned on. When the OE2 signal is a digital signal 1, the third switch K3 and the second sub-switch K4 are both disconnected; when the OE2 signal is a digital signal 0, the third switch K3 and the second sub-switch K4 are both turned on; when the S signal is 0, the first switch K1 and the first sub-switch K2 are both electrically connected to the first adjustable voltage source 211, and the third switch K3 and the second sub-switch K4 are both electrically connected to the second adjustable voltage source 213; when the S signal is 1, the first switch K1 and the first sub-switch K2 are both electrically connected to the ground terminal, and the third switch K3 and the second sub-switch K4 are both electrically connected to the ground terminal, which is not limited in the embodiment of the present application.

[0247] Table 2

[0248] OE1 OE2 S Working status 0 0 1 First Mode 0 0 0 First Mode 1 1 0 Second Mode 1 0 1 Third Mode 0 1 1 Fourth Mode

[0249] Referring to Table 2, the switch control circuit 11 determines whether the current working mode of the driving unit 21 is the first mode according to the waveform and timing of the excitation signal output by the driving unit 21. If so, the switch control circuit 11 inputs the OE1 signal with a digital signal of 0 to the first switch K1 and the first sub-switch K2, and inputs the OE2 signal with a digital signal of 0 to the third switch K3 and the second sub-switch K4. Under the control of the OE1 signal, the internal resistance of the first switch K1 and the first sub-switch K2 increases, and the first switch K1 and the first sub-switch K2 are both in the disconnected state; under the control of the OE2 signal, the internal resistance of the third switch K3 and the second sub-switch K4 increases, and the third switch K3 and the second sub-switch K4 are both in the disconnected state, and the driving unit 21 is in a high impedance state.

[0250] If not, the excitation signal level amplitude selection mode is entered to determine whether the driving unit 21 operates in the second mode, the third mode, or the fourth mode.

[0251] Optionally, if the driving unit 21 operates in the second mode, the switch control circuit 11 inputs an S signal and an OE1 signal whose digital signal is 1 to the first switch K1 and the first sub-switch K2, and the switch control circuit 11 inputs an S signal and an OE2 signal whose digital signal is 1 to the third switch K3 and the second sub-switch K4. Under the control of the OE1 signal, the first switch K1 and the first sub-switch K2 are both turned on; under the control of the OE2 signal, the third switch K3 and the second sub-switch K4 are both turned on.

[0252] On this basis, the S signal is a digital signal 0, the first switch K1 and the first sub-switch K2 are both electrically connected to the ground terminal, and the third switch K3 and the second sub-switch K4 are both electrically connected to the ground terminal. Since the first switch K1 and the first sub-switch K2 are also connected in parallel to the input side of the output terminal Out, the first switch K1 is electrically connected between the ground terminal and the output terminal Out, the third switch K3 is electrically connected between the ground terminal and the output terminal Out, and the excitation signal output by the output terminal Out is a low level.

[0253] For the second switch 212, if in the branch where the ground terminal, the first sub-switch K2, the first resistor R1, and the output terminal Out are located, the two ends of the resistor are electrically connected to the first sub-switch K2 and the output terminal Out respectively, then the excitation signal outputted from the ground terminal through the second switch 212 and the output terminal Out is also low level. If in the branch where the ground terminal, the first sub-switch K2, the first resistor R1, and the output terminal Out are located, the two ends of the resistor are not electrically connected to the first sub-switch K2 and / or the output terminal Out, then the branch where the ground terminal, the first sub-switch K2, the first resistor R1, and the output terminal Out are located is disconnected, but this situation does not affect the excitation signal outputted from the ground terminal through the first switch K1 and the output terminal Out is low level.

[0254] For the fourth switch 214, if in the branch where the ground terminal, the second sub-switch K4, the second resistor R2, and the output terminal Out are located, the two ends of the second resistor R2 are electrically connected to the second sub-switch K4 and the output terminal Out respectively, then the excitation signal outputted from the ground terminal through the fourth switch 214 and the output terminal Out is also low level. If in the branch where the ground terminal, the second sub-switch K4, the second resistor R2, and the output terminal Out are located, the two ends of the resistor are not electrically connected to the second sub-switch K4 and / or the output terminal Out, then the branch where the ground terminal, the second sub-switch K4, the second resistor R2, and the output terminal Out are located is disconnected, but this situation does not affect the excitation signal outputted from the ground terminal through the third switch K2 and the output terminal Out is low level.

[0255] Optionally, if the driving unit 21 operates in the third mode, the switch control circuit 11 inputs an S signal and an OE1 signal whose digital signal is 1 to the first switch K1 and the first sub-switch K2, and the switch control circuit 11 inputs an S signal and an OE1 signal whose digital signal is 0 to the third switch K3 and the second sub-switch K4. Under the control of the OE1 signal, the first switch K1 and the first sub-switch K2 are both turned on; under the control of the OE2 signal, the third switch K3 and the second sub-switch K4 are both turned off.

[0256] On this basis, the S signal is a digital signal 1, and the first switch K1 and the first sub-switch K2 are both electrically connected to the first adjustable voltage source 211. Since the first switch K1 and the first sub-switch K2 are also connected in parallel to the input side of the output terminal Out, the first switch K1 is electrically connected between the first adjustable voltage source 211 and the output terminal Out.

[0257] For the second switch 212, if in the branch where the ground terminal, the first sub-switch K2, the first resistor R1, and the output terminal Out are located, the two ends of the first resistor R1 are electrically connected to the first sub-switch K2 and the output terminal Out respectively, then the first adjustable voltage source 211 is electrically connected to the output terminal Out through the second switch 212. The branch where the first switch K1 is located and the branch where the second switch 212 is located are connected in parallel between the first adjustable voltage source 211 and the output terminal Out, and the excitation signal output by the output terminal Out is the first high level 3.3V.

[0258] Furthermore, since the branch where the first switch K1 is located and the branch where the second switch 212 is located are connected in parallel between the first adjustable voltage source 211 and the output terminal Out, the driving current of the excitation signal output by the output terminal Out is doubled, thereby improving the current driving capability of the excitation signal and avoiding the failure to achieve the test effect due to the poor quality of the signal transmitted to the chip under test.

[0259] For example, assuming that the upper limit of the current flow of the first switch K1 and the first sub-switch K2 are both 100mA, the current of the excitation signal output by the branch where the first switch K1 is located through the output terminal Out is 100mA, and when the branch where the second switch 212 is located is turned on, the current of the excitation signal output by the branch where the second switch 212 is located through the output terminal Out is also 100mA, and the two are added together, and the total current of the excitation signal output by the output terminal Out is 200mA. In addition, when the second switch 212 is turned off, the total current of the excitation signal output by the output terminal Out is 100mA. Therefore, the embodiment of the present application can also adjust the current size of the excitation signal output by the output terminal Out by controlling the second switch 212 to be turned on or off.

[0260] That is, the driving circuit 20 provided in the embodiment of the present application can also increase the current driving capability of the excitation signal input to the chip under test through a parallel branch when providing excitation signals of different states (H / L / Z) to the chip under test, thereby preventing the signal quality received by the chip under test from being too poor and failing to achieve the test effect.

[0261] Of course, the upper limit of the current flow of the first switch K1 and the first sub-switch K2 can also be other values, which is not limited in the embodiment of the present application. In addition, in order to make the excitation signal output by the drive unit 21 reach the set current value, the embodiment of the present application is not limited to the drive unit 21 including the first switch K1 and the second switch 212 in parallel. In some other possible implementations, the drive unit 21 may also include more switches connected in parallel with the first switch K1 and the second switch 212. Three or more parallel switches made by ordinary technicians in this field under the inspiration of this application are all within the protection of this application.

[0262] For the second switch 212, if in the branch where the ground terminal, the first sub-switch K2, the first resistor R1, and the output terminal Out are located, the two ends of the first resistor R1 are not electrically connected to the first sub-switch K2 and / or the output terminal Out, then the branch where the ground terminal, the first sub-switch K2, the first resistor R1, and the output terminal Out are located is disconnected, but this situation does not affect the first adjustable voltage source 211 outputting the first high level 3.3V through the first switch K1 and the output terminal Out.

[0263] In some possible implementations, in order to prevent the excitation signal reaching the chip under test from being significantly attenuated, the solution of the embodiment of the present application can also make the internal resistance of the first bipolar double-pole switch as small as possible (for example, 4.5Ω~8.5Ω) to reduce the signal voltage drop inside the first bipolar double-pole switch when driven by large current.

[0264] Optionally, if the driving unit 21 operates in the fourth mode, the switch control circuit 11 inputs an S signal and an OE1 signal whose digital signal is 0 to the third switch K3 and the second sub-switch K4, and the switch control circuit 11 inputs an S signal and an OE1 signal whose digital signal is 1 to the third switch K3 and the second sub-switch K4. Under the control of the OE1 signal, the third switch K3 and the second sub-switch K4 are both disconnected; under the control of the OE2 signal, the third switch K3 and the second sub-switch K4 are both turned on.

[0265] On this basis, the S signal is a digital signal 1, and the third switch K3 and the second sub-switch K4 are both electrically connected to the second adjustable voltage source 213. Since the third switch K3 and the second sub-switch K4 are also connected in parallel to the input side of the output terminal Out, the third switch K3 is electrically connected between the second adjustable voltage source 213 and the output terminal Out.

[0266] For the fourth switch 214, if in the branch where the ground terminal, the second sub-switch K4, the second resistor R2, and the output terminal Out are located, the two ends of the second resistor R2 are electrically connected to the second sub-switch K4 and the output terminal Out respectively, then the second adjustable voltage source 213 is electrically connected to the output terminal Out through the fourth switch 214. The branch where the third switch K3 is located and the branch where the fourth switch 214 is located are connected in parallel between the second adjustable voltage source 213 and the output terminal Out, and the excitation signal output by the output terminal Out is the second high level 2.5V.

[0267] Furthermore, since the branch where the third switch K3 is located and the branch where the fourth switch 214 is located are connected in parallel between the second adjustable voltage source 213 and the output terminal Out, the driving current of the excitation signal output by the output terminal Out is doubled, thereby improving the current driving capability of the excitation signal and avoiding the failure to achieve the test effect due to the poor quality of the signal transmitted to the chip under test.

[0268] For example, assuming that the upper limit of the current flow of the third switch K3 and the second sub-switch K4 are both 100mA, the current of the excitation signal output by the branch where the third switch K3 is located through the output terminal Out is 100mA, and when the branch where the fourth switch 214 is located is turned on, the current of the excitation signal output by the branch where the fourth switch 214 is located through the output terminal Out is also 100mA, and the two are added together, and the total current of the excitation signal output by the output terminal Out is 200mA. In addition, when the fourth switch 214 is turned off, the total current of the excitation signal output by the output terminal Out is 100mA. Therefore, the embodiment of the present application can also adjust the current size of the excitation signal output by the output terminal Out by controlling the fourth switch 214 to be turned on or off.

[0269] That is, the driving circuit 20 provided in the embodiment of the present application can also increase the current driving capability of the excitation signal input to the chip under test through a parallel branch when providing excitation signals of different states (H / L / Z) to the chip under test, thereby preventing the signal quality received by the chip under test from being too poor and failing to achieve the test effect.

[0270] Of course, the upper limit of the current flow of the third switch K3 and the second sub-switch K4 can also be other values, which is not limited in the embodiment of the present application. In addition, in order to make the excitation signal output by the driving unit 21 reach the set current value, the embodiment of the present application is not limited to the driving unit 21 including the third switch K3 and the fourth switch 214 in parallel. In some other possible implementations, the driving unit 21 can also include more switches connected in parallel with the third switch K3 and the fourth switch 214. Under the guidance of this application, three or more parallel switches made by ordinary technicians in this field are all within the protection of this application.

[0271] For the fourth switch 214, if in the branch where the ground terminal, the second sub-switch K4, the second resistor R2, and the output terminal Out are located, the two ends of the second resistor R2 are not electrically connected to the second sub-switch K4 and / or the output terminal Out, then the branch where the second adjustable voltage source 213, the second sub-switch K4, the second resistor R2, and the output terminal Out are located is disconnected, but this situation does not affect the second adjustable voltage source 213 outputting the second high level 2.5V through the third switch K3 and the output terminal Out.

[0272] In some possible implementations, in order to prevent the excitation signal reaching the chip under test from being significantly attenuated, the solution of the embodiment of the present application can also make the internal resistance of the second bipolar double-pole switch as small as possible (for example, 4.5Ω~8.5Ω) to reduce the signal voltage drop inside the second bipolar double-pole switch when driven by large current.

[0273] In some embodiments, Figure 8 As shown, the circuit further includes a receiving circuit 30. Fig. 9 As shown, the receiving circuit 30 is electrically connected to the output side of the chip under test and the output side of the driving circuit 20. The receiving circuit 30 includes a first comparator 31, a second comparator 32, a third adjustable voltage source 33, and a fourth adjustable voltage source 34. The main control circuit also includes a detection circuit 13.

[0274] The first comparator 31 includes a first input terminal, a second input terminal, and a first output terminal, and the second comparator 32 includes a third input terminal, a fourth input terminal, and a second output terminal. The first output terminal is electrically connected to the detection circuit 13, and the second output terminal is electrically connected to the detection circuit 13.

[0275] The main control circuit 10 controls the first input terminal to be electrically connected to the third adjustable voltage source 33, so as to input the first reference high level to the first comparator 31 by using the third adjustable voltage source 33. The main control circuit 10 controls the third input terminal to be electrically connected to the fourth adjustable voltage source 34, so as to input the first reference low level to the second comparator 32 by using the fourth adjustable voltage source 34.

[0276] In the first application scenario, the receiving circuit 20 is used to receive a signal output by the chip under test, and compare the signal output by the chip under test with an expected value to identify the signal output by the chip under test, so as to test the chip under test.

[0277] In the second application scenario, the receiving circuit 20 is used to receive the first high level sent by the driving circuit 20 to determine whether the first adjustable voltage source 211 is qualified; or, the receiving circuit 20 is used to receive the second high level sent by the driving circuit 20 to determine whether the second adjustable voltage source 213 is qualified.

[0278] Specifically, the circuit control method further includes:

[0279] Fig.10 The working principle of the receiving circuit 30 and the detection circuit 13 in the first application scenario is shown. Fig.10 The bold line with an arrow in the middle indicates the source of the signal received by the receiving circuit 30 . It can be seen that the receiving circuit 30 receives the signal output by the chip under test.

[0280] like Fig.10 As shown, the main control circuit 10 controls the chip under test (ie, the external circuit) to input the first voltage to the first comparator 31 through the second input terminal, and controls the chip under test to input the first voltage to the second comparator 32 through the fourth input terminal.

[0281] The first comparator 31 compares the received first voltage with the first reference high level, and inputs the first comparison result to the detection circuit 13. The second comparator is configured to compare the received first voltage with the first reference low level, and input the second comparison result to the detection circuit 13. The detection circuit 13 identifies the first voltage according to the first comparison result and the second comparison result.

[0282] For example, ideally, the first voltage output by the chip under test should be 3.3 V. According to the voltage value of 3.3 V, the first reference high level can be set to 2.6 V and the first reference low level can be set to 0.7 V. During the aging test, the first voltage actually output by the chip under test may have an error. In order to identify the first voltage actually output by the chip under test, the second input terminal of the first comparator 31 and the fourth input terminal of the second comparator 32 are used to receive the first voltage.

[0283] For example, the first voltage actually output by the chip under test is 2.9V. After receiving the first voltage of 2.9V, the first comparator 31 compares the first reference high level of 2.6V with the first voltage of 2.9V. Since 2.9V>2.6V, the first comparator 31 inputs the first comparison result of the digital signal of 1 to the detection circuit 13. After receiving the first voltage of 2.9V, the second comparator 32 compares the first reference low level of 0.7V with the first voltage of 2.9V. Since 2.9V>0.7V, the second comparator 32 inputs the second comparison result of the digital signal of 1 to the detection circuit 13.

[0284] The detection circuit 13 confirms that the first voltage (2.9V) actually output by the chip under test is a high level according to the received first comparison result (digital signal 1) and the second comparison result (digital signal 1).

[0285] For another example, the first voltage actually output by the chip under test is 0.3V. After receiving the first voltage of 0.3V, the first comparator 31 compares the first reference high level of 2.6V with the first voltage of 0.3V. Since 2.6V>0.3V, the first comparator 31 inputs the first comparison result of the digital signal being 0 to the detection circuit 13. After receiving the first voltage of 0.3V, the second comparator 32 compares the first reference low level of 0.7V with the first voltage of 0.3V. Since 0.7V>0.3V, the second comparator 32 inputs the second comparison result of the digital signal being 0 to the detection circuit 13.

[0286] The detection circuit 13 confirms that the first voltage (0.3V) actually output by the chip under test is a low level according to the received first comparison result (digital signal 0) and the second comparison result (digital signal 0).

[0287] In some possible implementations, the signal quality of the first voltage output by the chip under test is poor, and the first voltage falls between 0.7V and 2.6V. In order to use the receiving circuit 30 and the detection circuit 13 to identify the first voltage, the first reference high level and the first reference low level can be adjusted. For example, the first reference high level is adjusted from 2.6V to 1.5V, and the first reference low level is adjusted from 0.7V to 1.2V.

[0288] Of course, according to actual needs, the first reference high level and the first reference low level may also be adjusted to other values, which is not limited in the embodiments of the present application.

[0289] For example, the first voltage actually output by the chip under test is 2V. After receiving the first voltage of 2V, the first comparator 31 compares the first reference high level of 1.5V with the first voltage of 2V. Since 2V>1.5V, the first comparator 31 inputs the first comparison result of the digital signal 1 to the detection circuit 13. After receiving the first voltage of 2V, the second comparator 32 compares the first reference low level of 1.2V with the first voltage of 2V. Since 2V>1.2V, the second comparator 32 inputs the second comparison result of the digital signal 1 to the detection circuit 13.

[0290] The detection circuit 13 confirms that the first voltage (2V) actually output by the chip under test is a high level according to the received first comparison result (digital signal 1) and the second comparison result (digital signal 1).

[0291] For another example, the first voltage actually output by the chip under test is 0.9V. After receiving the first voltage of 0.9V, the first comparator 31 compares the first reference high level of 1.5V with the first voltage of 0.9V. Since 1.5V>0.9V, the first comparator 31 inputs the first comparison result of the digital signal being 0 to the detection circuit 13. After receiving the first voltage of 0.9V, the second comparator 32 compares the first reference low level of 1.2V with the first voltage of 0.9V. Since 1.2V>0.9V, the second comparator 32 inputs the second comparison result of the digital signal being 0 to the detection circuit 13.

[0292] The detection circuit 13 confirms that the first voltage (0.9V) actually output by the chip under test is a low level according to the received first comparison result (digital signal 0) and the second comparison result (digital signal 0).

[0293] Fig.11 The working principle of the receiving circuit 30 and the detection circuit 13 in the second application scenario is shown. Fig.11 The bold line with an arrow indicates the source of the signal received by the receiving circuit 30 . It can be seen that the driving unit 21 works in the third mode, and the first high level or low level output by the driving unit 21 is input to the chip under test and the receiving circuit 30 respectively.

[0294] like Fig.11 As shown, the main control circuit is configured to: in the third mode, the control driving unit 21 inputs the first high level to the first comparator through the output terminal and the second input terminal, and the control driving unit 21 inputs the first high level to the second comparator 32 through the output terminal Out and the fourth input terminal.

[0295] The first comparator 31 compares the received first high level with the first reference high level, and inputs a third comparison result to the detection circuit. The second comparator 32 compares the received first high level with the first reference low level, and inputs a fourth comparison result to the detection circuit. The detection circuit 13 determines whether the first adjustable voltage source 211 is qualified according to the third comparison result and the fourth comparison result.

[0296] For example, ideally, the first high level output by the first adjustable voltage source 211 is 3.3V, and the first high level output by the driving unit 21 is also 3.3V. According to the voltage value of 3.3V, the first reference high level can be set to 2.6V and the first reference low level to 0.7V. During the aging test, the first high level output by the first adjustable voltage source 211 may have an error. In order to confirm whether the first adjustable voltage source 211 is qualified, the first high level output by the driving unit 21 is received by the second input terminal of the first comparator 31 and the fourth input terminal of the second comparator 32, respectively.

[0297] For example, the first high level actually output by the driving unit 21 is 3V. After receiving the first high level of 3V, the first comparator 31 compares the first reference high level of 2.6V with the first high level of 3V. Since 3V>2.6V, the first comparator 31 inputs the third comparison result of the digital signal 1 to the detection circuit 13. After receiving the first high level of 3V, the second comparator 32 compares the first reference low level of 0.7V with the first high level of 3V. Since 3V>0.7V, the second comparator 32 inputs the fourth comparison result of the digital signal 1 to the detection circuit 13.

[0298] The detection circuit 13 confirms that the first adjustable voltage source 211 is qualified according to the received third comparison result (digital signal 1) and the fourth comparison result (digital signal 1).

[0299] For another example, the first high level actually output by the driving unit 21 is 1V. After receiving the first high level of 1V, the first comparator 31 compares the first reference high level of 2.6V with the first high level of 1V. Since 2.6V>1V, the first comparator 31 inputs the third comparison result of the digital signal 0 to the detection circuit 13. After receiving the first high level of 1V, the second comparator 32 compares the first reference low level of 0.7V with the first high level of 1V. Since 0.7V<1V, the second comparator 32 inputs the fourth comparison result of the digital signal 1 to the detection circuit 13.

[0300] The detection circuit 13 determines that the first adjustable voltage source 211 is unqualified according to the received third comparison result (digital signal 0) and the fourth comparison result (digital signal 1).

[0301] The first application scenario and the second application scenario described above introduce the case where the receiving circuit 30 includes a third adjustable voltage source 33 and a fourth adjustable voltage source 34. In other embodiments, the receiving circuit 30 may further include other more adjustable voltage sources.

[0302] For example, in the third application scenario, the signal output by the chip under test is two voltage values ​​of different standards. The third adjustable voltage source 33 and the fourth adjustable voltage source 34 can be used to identify the voltage value of one standard, and the fifth adjustable voltage source 35 and the sixth adjustable voltage source 36 can be used to identify the voltage value of the other standard.

[0303] For another example, in the fourth application scenario, when the driving unit 21 includes a second adjustable voltage source, the receiving circuit 30 may further include a fifth adjustable voltage source 35 and a sixth adjustable voltage source 36, and the third adjustable voltage source 33 and the fourth adjustable voltage source 34 are used to detect whether the second adjustable voltage source 213 is qualified, and the fifth adjustable voltage source 35 and the sixth adjustable voltage source 36 are used to detect whether the second adjustable voltage source 213 is qualified.

[0304] Specifically, the circuit control method further includes:

[0305] Fig.13 The working principle of the receiving circuit 30 and the detection circuit 13 in the third application scenario is shown. Fig.13 The bold line with an arrow in the middle indicates the source of the signal received by the receiving circuit 30 . It can be seen that the receiving circuit 30 receives the signal output by the chip under test.

[0306] exist Fig. 9 On the basis of the receiving circuit 30 shown, the receiving circuit 30 may further include a fifth switch K5 and a sixth switch K6. The main control circuit 10 controls the fifth switch K5 and the sixth switch K6 to enable the third adjustable voltage source 33 and the fourth adjustable voltage source 34 to work simultaneously, and the fifth adjustable voltage source 35 and the sixth adjustable voltage source 36 to work simultaneously. The fifth switch K5 and the sixth switch K6 may both be single-pole double-throw switches.

[0307] For example, assuming that the signal output by the chip under test is a first voltage, the main control circuit 10 controls the first input terminal to be electrically connected to the third adjustable voltage source 33 through the fifth switch K5, and to be disconnected from the fifth adjustable voltage source 35 through the fifth switch K5, and the third adjustable voltage source 33 inputs a first reference high level to the first comparator 31; the main control circuit 10 also controls the third input terminal to be electrically connected to the fourth adjustable voltage source 34 through the sixth switch K6, and to be disconnected from the sixth adjustable voltage source 36 through the sixth switch K6, and the fourth adjustable voltage source 34 inputs a first reference low level to the second comparator 32.

[0308] The first comparator 31 compares the received first voltage with the first reference high level, and inputs the first comparison result to the detection circuit 13. The second comparator is configured to compare the received first voltage with the first reference low level, and input the second comparison result to the detection circuit 13. The detection circuit 13 identifies the first voltage according to the first comparison result and the second comparison result.

[0309] Assuming that ideally, the first voltage output by the chip under test should be 3.3 V. According to the voltage value of 3.3 V, the first reference high level can be set to 2.6 V and the first reference low level can be set to 0.7 V. During the aging test, the first voltage actually output by the chip under test may have errors. In order to identify the first voltage actually output by the chip under test, the second input terminal of the first comparator 31 and the fourth input terminal of the second comparator 32 are used to receive the first voltage respectively.

[0310] For example, the first voltage actually output by the chip under test is 2.9V. After receiving the first voltage of 2.9V, the first comparator 31 compares the first reference high level of 2.6V with the first voltage of 2.9V. Since 2.9V>2.6V, the first comparator 31 inputs the first comparison result of the digital signal of 1 to the detection circuit 13. After receiving the first voltage of 2.9V, the second comparator 32 compares the first reference low level of 0.7V with the first voltage of 2.9V. Since 2.9V>0.7V, the second comparator 32 inputs the second comparison result of the digital signal of 1 to the detection circuit 13.

[0311] The detection circuit 13 confirms that the first voltage (2.9V) actually output by the chip under test is a high level according to the received first comparison result (digital signal 1) and the second comparison result (digital signal 1).

[0312] For another example, the first voltage actually output by the chip under test is 0.3V. After receiving the first voltage of 0.3V, the first comparator 31 compares the first reference high level of 2.6V with the first voltage of 0.3V. Since 2.6V>0.3V, the first comparator 31 inputs the first comparison result of the digital signal being 0 to the detection circuit 13. After receiving the first voltage of 0.3V, the second comparator 32 compares the first reference low level of 0.7V with the first voltage of 0.3V. Since 0.7V>0.3V, the second comparator 32 inputs the second comparison result of the digital signal being 0 to the detection circuit 13.

[0313] The detection circuit 13 confirms that the first voltage (0.3V) actually output by the chip under test is a low level according to the received first comparison result (digital signal 0) and the second comparison result (digital signal 0).

[0314] For example, assuming that the signal output by the chip under test is a second voltage (the second voltage is different from the first voltage), the main control circuit 10 controls the first input terminal to be disconnected from the third adjustable voltage source 33 through the fifth switch K5, and to be electrically connected to the fifth adjustable voltage source 35 through the fifth switch K5, and the fifth adjustable voltage source 35 inputs a second reference high level to the first comparator 31; the main control circuit 10 also controls the third input terminal to be disconnected from the fourth adjustable voltage source 34 through the sixth switch K6, and to be electrically connected to the sixth adjustable voltage source 36 through the sixth switch K6, and the sixth adjustable voltage source 36 inputs a second reference low level to the second comparator 32. Among them, the first reference low level is different from the second reference low level, and the first reference high level is different from the second reference high level.

[0315] The first comparator 31 compares the received second voltage with the second reference high level, and inputs a fifth comparison result to the detection circuit 13. The second comparator is configured to compare the received second voltage with the second reference low level, and input a sixth comparison result to the detection circuit 13. The detection circuit 13 identifies the second voltage according to the fifth comparison result and the sixth comparison result.

[0316] Assuming that ideally, the second voltage output by the chip under test should be 2.5 V. According to the voltage value of 2.5 V, the second reference high level can be set to 2 V and the second reference low level can be set to 0.5 V. During the aging test, the second voltage actually output by the chip under test may have errors. In order to identify the second voltage actually output by the chip under test, the second input terminal of the first comparator 31 and the fourth input terminal of the second comparator 32 are used to receive the second voltage.

[0317] For example, the second voltage actually output by the chip under test is 2.1V. After receiving the second voltage of 2.1V, the first comparator 31 compares the second reference high level of 2V with the second voltage of 2.1V. Since 2.1V>2V, the first comparator 31 inputs the fifth comparison result of the digital signal 1 to the detection circuit 13. After receiving the second voltage of 2.1V, the second comparator 32 compares the second reference low level of 0.5V with the second voltage of 2.1V. Since 2.1V>0.5V, the second comparator 32 inputs the sixth comparison result of the digital signal 1 to the detection circuit 13.

[0318] The detection circuit 13 confirms that the second voltage (2.1V) actually output by the chip under test is a high level according to the received fifth comparison result (digital signal 1) and the sixth comparison result (digital signal 1).

[0319] For another example, the second voltage actually output by the chip under test is 0.3V. After receiving the second voltage of 0.3V, the first comparator 31 compares the second reference high level of 2V with the second voltage of 0.3V. Since 2V>0.3V, the first comparator 31 inputs the fifth comparison result of the digital signal being 0 to the detection circuit 13. After receiving the second voltage of 0.3V, the second comparator 32 compares the second reference low level of 0.5V with the second voltage of 0.3V. Since 0.5V>0.3V, the second comparator 32 inputs the sixth comparison result of the digital signal being 0 to the detection circuit 13.

[0320] The detection circuit 13 confirms that the second voltage (0.3V) actually output by the chip under test is a low level according to the received fifth comparison result (digital signal 0) and the sixth comparison result (digital signal 0).

[0321] In some possible implementations, the signal quality of the first voltage output by the chip under test is poor, and the first voltage falls between 0.7V and 2.6V. In order to use the receiving circuit 30 and the detection circuit 13 to identify the first voltage, the first reference high level and the first reference low level can be adjusted. For example, the first reference high level is adjusted from 2.6V to 1.5V, and the first reference low level is adjusted from 0.7V to 1.2V.

[0322] In some possible implementations, the signal quality of the second voltage output by the chip under test is poor, and the second voltage falls between 0.5V and 2V. In order to identify the second voltage using the receiving circuit 30 and the detection circuit 13, the second reference high level and the second reference low level can be optionally adjusted. For example, the second reference high level is adjusted from 2V to 1.5V, and the second reference low level is adjusted from 0.5V to 1V.

[0323] Of course, according to actual needs, the first reference high level, the first reference low level, the second reference high level, and the second reference low level can also be adjusted to other values, and the embodiment of the present application is not limited to this. In different application scenarios, the power supply regulation circuit 12 can be used to parse the configuration file, and adjust the first reference high level output by the third adjustable voltage source 33, adjust the first reference low level output by the fourth adjustable voltage source 34, adjust the second reference high level output by the fifth adjustable voltage source 35, and adjust the second reference low level output by the sixth adjustable voltage source 36 according to the configuration file.

[0324] Fig.14 The working principle of the receiving circuit 30 and the detection circuit 13 in the fourth application scenario is shown. Fig.14 The bold line with an arrow indicates the source of the signal received by the receiving circuit 30 . It can be seen that the driving unit 21 works in the third mode, and the second high level or low level output by the driving unit 21 is input to the chip under test and the receiving circuit 30 respectively.

[0325] For example, assuming that the first high level output by the first adjustable voltage source 211 is 3.3V, and the signal output by the chip under test is the first voltage, the main control circuit 10 controls the first input terminal to be electrically connected to the third adjustable voltage source 33 through the fifth switch K5, and to be disconnected from the fifth adjustable voltage source 35 through the fifth switch K5, and the third adjustable voltage source 33 inputs a first reference high level to the first comparator 31; the main control circuit 10 also controls the third input terminal to be electrically connected to the fourth adjustable voltage source 34 through the sixth switch K6, and to be disconnected from the sixth adjustable voltage source 36 through the sixth switch K6, and the fourth adjustable voltage source 34 inputs a first reference low level to the second comparator 32.

[0326] The first comparator 31 compares the received first high level with the first reference high level, and inputs a third comparison result to the detection circuit 13. The second comparator compares the received first high level with the first reference low level, and inputs a fourth comparison result to the detection circuit 13. The detection circuit 13 determines whether the first adjustable voltage source 211 is qualified according to the third comparison result and the fourth comparison result.

[0327] For example, the first high level actually output by the driving unit 21 is 3V. After receiving the first high level of 3V, the first comparator 31 compares the first reference high level of 2.6V with the first high level of 3V. Since 3V>2.6V, the first comparator 31 inputs the third comparison result of the digital signal 1 to the detection circuit 13. After receiving the first high level of 3V, the second comparator 32 compares the first reference low level of 0.7V with the first high level of 3V. Since 3V>0.7V, the second comparator 32 inputs the fourth comparison result of the digital signal 1 to the detection circuit 13.

[0328] The detection circuit 13 confirms that the first adjustable voltage source 211 is qualified according to the received third comparison result (digital signal 1) and the fourth comparison result (digital signal 1).

[0329] For another example, the first high level actually output by the driving unit 21 is 1V. After receiving the first high level of 1V, the first comparator 31 compares the first reference high level of 2.6V with the first high level of 1V. Since 2.6V>1V, the first comparator 31 inputs the third comparison result of the digital signal 0 to the detection circuit 13. After receiving the first high level of 1V, the second comparator 32 compares the first reference low level of 0.7V with the first high level of 1V. Since 0.7V<1V, the second comparator 32 inputs the fourth comparison result of the digital signal 1 to the detection circuit 13.

[0330] The detection circuit 13 determines that the first adjustable voltage source 211 is unqualified according to the received third comparison result (digital signal 0) and the fourth comparison result (digital signal 1).

[0331] For example, assuming that the second high level input by the driving unit 21 to the first comparator 31 and the second comparator 32 is 2.5V, the main control circuit 10 controls the first input terminal to be disconnected from the third adjustable voltage source 33 through the fifth switch K5, and to be electrically connected to the fifth adjustable voltage source 35 through the fifth switch K5, and the fifth adjustable voltage source 35 inputs a second reference high level to the first comparator 31; the main control circuit 10 also controls the third input terminal to be disconnected from the fourth adjustable voltage source 34 through the sixth switch K6, and to be electrically connected to the sixth adjustable voltage source 36 through the sixth switch K6, and the sixth adjustable voltage source 36 inputs a second reference low level to the second comparator 32.

[0332] The first comparator 31 compares the received second high level with the second reference high level, and inputs a seventh comparison result to the detection circuit 13. The second comparator 32 compares the received second high level with the second reference low level, and inputs an eighth comparison result to the detection circuit 13. The detection circuit 13 determines whether the second adjustable voltage source 213 is qualified according to the seventh comparison result and the eighth comparison result.

[0333] For example, the second high level actually output by the driving unit 21 is 2.2V. After receiving the second high level of 2.2V, the first comparator 31 compares the second reference high level of 2V with the second high level of 2.2V. Since 2.2V>2V, the first comparator 31 inputs the seventh comparison result of the digital signal 1 to the detection circuit 13. After receiving the second high level of 2.2V, the second comparator 32 compares the second reference low level of 0.5V with the second high level of 2.2V. Since 2.2V>0.5V, the second comparator 32 inputs the eighth comparison result of the digital signal 1 to the detection circuit 13.

[0334] The detection circuit 13 confirms that the second adjustable voltage source 213 is qualified according to the received seventh comparison result (digital signal 1) and the eighth comparison result (digital signal 1).

[0335] For another example, the second high level actually output by the driving unit 21 is 1V. After receiving the second high level of 1V, the first comparator 31 compares the second reference high level of 2V with the second high level of 1V. Since 2V>1V, the first comparator 31 inputs the seventh comparison result of the digital signal 0 to the detection circuit 13. After receiving the second high level of 1V, the second comparator 32 compares the second reference low level of 0.5V with the second high level of 1V. Since 0.5V<1V, the second comparator 32 inputs the eighth comparison result of the digital signal 1 to the detection circuit 13.

[0336] The detection circuit 13 determines that the second adjustable voltage source 213 is unqualified according to the received seventh comparison result (digital signal 0) and the eighth comparison result (digital signal 1).

[0337] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the purpose of the present application and the scope of protection of the claims, all of which are within the protection of the present application.

Claims

1. A circuit, characterized in that: Including driving circuit and main control circuit; The driving circuit comprises a plurality of driving units, wherein the driving units comprise a first adjustable voltage source, a first switch, a second switch, a ground terminal, and an output terminal, wherein the first switch and the second switch are connected in parallel to the input side of the output terminal; the main control circuit comprises a plurality of switch control circuits, each of which is used to control at least one of the driving units; The first adjustable voltage source is configured to output a first high level; The switch control circuit is configured to: in a first mode, control the first switch and the second switch to be disconnected; in a second mode, control the ground terminal to be electrically connected to the output terminal through the first switch and the second switch, so as to output a low level through the output terminal; in a third mode, control the first adjustable voltage source to be electrically connected to the output terminal through the first switch, or control the first adjustable voltage source to be electrically connected to the output terminal through the first switch and the second switch, respectively, so as to output a first high level through the output terminal.

2. The circuit according to claim 1, characterized in that The driving unit further includes a second adjustable voltage source, a third switch and a fourth switch, wherein the third switch and the fourth switch are connected in parallel to the input side of the output end; The second adjustable voltage source is configured to output a second high level, where the second high level is different from the first high level; The switch control circuit is configured to control the third switch and the fourth switch to be disconnected in the first mode and the third mode; and to control the ground terminal to be electrically connected to the ground terminal through the third switch and the fourth switch in the second mode; The switch control circuit is further configured to, in a fourth mode, control both the first switch and the second switch to be disconnected, and control the second adjustable voltage source to be electrically connected to the output end through the third switch, or control the second adjustable voltage source to be electrically connected to the output end through the third switch and the fourth switch, respectively, so as to output a second high level through the output end.

3. The circuit according to claim 2, characterized in that The second switch includes a first sub-switch and a first resistor, and the first switch and the first sub-switch form a first bipolar double-pole switch; and / or, The fourth switch includes a second sub-switch and a second resistor, and the third switch and the second sub-switch constitute a second double-pole double-pole switch.

4. The circuit according to any one of claims 1 to 3, characterized in that: The circuit further includes a receiving circuit, the receiving circuit includes a first comparator, a second comparator, a third adjustable voltage source, and a fourth adjustable voltage source, and the main control circuit further includes a detection circuit; The first comparator includes a first input terminal, a second input terminal, and a first output terminal, and the second comparator includes a third input terminal, a fourth input terminal, and a second output terminal; the first output terminal is electrically connected to the detection circuit, and the second output terminal is electrically connected to the detection circuit; The main control circuit is configured to control the first input terminal to be electrically connected to the third adjustable voltage source, and control the third input terminal to be electrically connected to the fourth adjustable voltage source; The third adjustable voltage source is configured to input a first reference high level to the first comparator; The fourth adjustable voltage source is configured to input a first reference low level to the second comparator.

5. The circuit according to claim 4, characterized in that The main control circuit is configured to control the external circuit to input the first voltage to the first comparator through the second input terminal, and control the external circuit to input the first voltage to the second comparator through the fourth input terminal; The first comparator is configured to compare the received first voltage with the first reference high level and input a first comparison result to the detection circuit; The second comparator is configured to compare the received first voltage with the first reference low level and input a second comparison result to the detection circuit; The detection circuit is configured to identify the first voltage according to the first comparison result and the second comparison result.

6. The circuit according to claim 4, characterized in that The main control circuit is configured to, in the third mode, control the driving unit to input the first high level to the first comparator through the output terminal and the second input terminal, and control the driving unit to input the first high level to the second comparator through the output terminal and the fourth input terminal; The first comparator is configured to compare the received first high level with the first reference high level, and input a third comparison result to the detection circuit; The second comparator is configured to compare the received first high level with the first reference low level, and input a fourth comparison result to the detection circuit; The detection circuit is configured to confirm whether the first adjustable voltage source is qualified according to the third comparison result and the fourth comparison result.

7. The circuit according to any one of claims 4 to 6, characterized in that: The receiving circuit further includes a fifth adjustable voltage source, a sixth adjustable voltage source, a fifth switch, and a sixth switch; The main control circuit is configured to control the first input terminal to be disconnected from the third adjustable voltage source through the fifth switch and to be electrically connected to the fifth adjustable voltage source through the fifth switch, and to control the third input terminal to be disconnected from the fourth adjustable voltage source through the sixth switch and to be electrically connected to the sixth adjustable voltage source through the sixth switch; or, configured to control the first input terminal to be electrically connected to the third adjustable voltage source through the fifth switch and to be disconnected from the fifth adjustable voltage source through the fifth switch, and to control the third input terminal to be electrically connected to the fourth adjustable voltage source through the sixth switch and to be disconnected from the sixth adjustable voltage source through the sixth switch; The fifth adjustable voltage source is configured to input a second reference high level to the first comparator, wherein the second reference high level is different from the first reference high level; The sixth adjustable voltage source is configured to input a second reference low level to the second comparator, where the second reference low level is different from the first reference low level.

8. The circuit according to claim 7, characterized in that The main control circuit is configured to control the external circuit to input a second voltage to the first comparator through the second input terminal, and to control the external circuit to input the second voltage to the second comparator through the fourth input terminal, wherein the second voltage is different from the first voltage; The first comparator is configured to compare the received second voltage with the second reference high level, and input a fifth comparison result to the detection circuit; The second comparator is configured to compare the received second voltage with the second reference low level, and input a sixth comparison result to the detection circuit; The detection circuit is configured to identify the second voltage according to the fifth comparison result and the sixth comparison result.

9. The circuit according to claim 7, characterized in that In the case where the driving unit further includes a second adjustable voltage source, a third switch and the fourth switch, in the fourth mode, the driving unit is controlled to input the second high level to the first comparator through the output terminal and the second input terminal, and the driving unit is controlled to input the second high level to the second comparator through the output terminal and the fourth input terminal; The first comparator is configured to compare the received second high level with the second reference high level, and input a seventh comparison result to the detection circuit; The second comparator is configured to compare the received second high level with the second reference low level, and input an eighth comparison result to the detection circuit; The detection circuit is configured to confirm whether the second adjustable voltage source is qualified according to the seventh comparison result and the eighth comparison result.

10. The circuit according to any one of claims 7 to 9, characterized in that: The fifth switch and the sixth switch are both single-pole double-throw switches.

11. The circuit according to any one of claims 7 to 10, characterized in that: The main control circuit also includes a power supply regulation circuit; The power supply regulation circuit is configured to regulate the first high level output by the first adjustable voltage source, regulate the second high level output by the second adjustable voltage source, regulate the first reference high level output by the third adjustable voltage source, regulate the first reference low level output by the fourth adjustable voltage source, regulate the second reference high level output by the fifth adjustable voltage source, and regulate the second reference low level output by the sixth adjustable voltage source.

12. An aging machine, characterized in that: The invention comprises the circuit described in any one of claims 1 to 11.

13. An aging device, characterized in that: It comprises an aging board and the aging machine according to claim 12, wherein the aging board is used to carry a plurality of chips under test, and the aging machine is used to perform aging tests on the plurality of chips under test through the aging board.

14. The aging device according to claim 13, characterized in that: The aging board includes a connecting wire, the connecting wire includes a first wire and a plurality of second wires, and the first wire is electrically connected between the aging machine and the plurality of second wires; Each of the second wirings is electrically connected to a plurality of the chips under test.

15. The aging device according to claim 14, characterized in that: The aging board also includes a third resistor, a first capacitor, a second capacitor, a first ground terminal, and a second ground terminal; The third resistor is connected to the first wiring, the first capacitor is electrically connected between one end of the third resistor and the first ground terminal, and the second capacitor is electrically connected between the other end of the third resistor and the second ground terminal; and / or, The aging board also includes a fourth resistor, which is electrically connected between the second wiring and the chip under test; the aging board also includes a transient suppression diode and a third ground terminal, the input end of the transient suppression diode is electrically connected between the aging machine and the fourth resistor, and the output end of the transient suppression diode is electrically connected to the third ground terminal.

16. A circuit control method, characterized in that: The circuit includes a driving circuit and a main control circuit; the driving circuit includes a plurality of driving units, the driving unit includes a first adjustable voltage source, a first switch, a second switch, a ground terminal, and an output terminal, the first switch and the second switch are connected in parallel to the input side of the output terminal; the main control circuit includes a plurality of switch control circuits, each of which is used to control one of the driving units; The control method of the circuit comprises: In the first mode, the switch control circuit is used to control the first switch and the second switch to be disconnected; In the second mode, the switch control circuit is used to control the ground terminal to be electrically connected to the output terminal through the first switch and the second switch, so as to output a low level through the output terminal; In the third mode, a first high level is output through the first adjustable voltage source; the switch control circuit is used to control the first adjustable voltage source to be electrically connected to the output end through the first switch, or the first adjustable voltage source is controlled to be electrically connected to the output end through the first switch and the second switch respectively, so as to output the first high level through the output end.

17. The circuit control method according to claim 16, characterized in that: The driving unit further includes a second adjustable voltage source, a third switch and a fourth switch, wherein the third switch and the fourth switch are connected in parallel to the input side of the output end; The control method of the circuit further includes: In the first mode, the third switch and the fourth switch are both controlled to be disconnected; In the second mode, controlling the ground terminal to be electrically connected to the ground terminal through the third switch and the fourth switch; In the third mode, controlling the third switch and the fourth switch to be disconnected; In the fourth mode, a second high level is output through the second adjustable voltage source, and the second high level is different from the first high level; the first switch and the second switch are both controlled to be disconnected, and the second adjustable voltage source is controlled to be electrically connected to the output end through the third switch, or the second adjustable voltage source is controlled to be electrically connected to the output end through the third switch and the fourth switch respectively, so as to output the second high level through the output end.

18. The circuit control method according to claim 16 or 17, characterized in that: The circuit further includes a receiving circuit, the receiving circuit includes a first comparator, a second comparator, a third adjustable voltage source, and a fourth adjustable voltage source, and the main control circuit further includes a detection circuit; The first comparator includes a first input terminal, a second input terminal, and a first output terminal, and the second comparator includes a third input terminal, a fourth input terminal, and a second output terminal; the first output terminal is electrically connected to the detection circuit, and the second output terminal is electrically connected to the detection circuit; The control method of the circuit further includes: Using the main control circuit to control the first input terminal to be electrically connected to the third adjustable voltage source, and to control the third input terminal to be electrically connected to the fourth adjustable voltage source; The third adjustable voltage source is used to input a first reference high level into the first comparator; and the fourth adjustable voltage source is used to input a first reference low level into the second comparator.

19. The circuit control method according to claim 18, characterized in that: The control method of the circuit further includes: Using the main control circuit to control the external circuit to input the first voltage to the first comparator through the second input terminal, and controlling the external circuit to input the first voltage to the second comparator through the fourth input terminal; Using the first comparator to compare the received first voltage with the first reference high level, and inputting a first comparison result to the detection circuit; using the second comparator to compare the received first voltage with the first reference low level, and inputting a second comparison result to the detection circuit; The first voltage is identified by the detection circuit according to the first comparison result and the second comparison result.

20. The circuit control method according to claim 18, characterized in that: The control method of the circuit further includes: In the third mode, the main control circuit is used to control the driving unit to input the first high level to the first comparator through the output terminal and the second input terminal, and to control the driving unit to input the first high level to the second comparator through the output terminal and the fourth input terminal; Using the first comparator to compare the received first high level with the first reference high level, and inputting a third comparison result to the detection circuit; using the second comparator to compare the received first high level with the first reference low level, and inputting a fourth comparison result to the detection circuit; The detection circuit is used to confirm whether the first adjustable voltage source is qualified according to the third comparison result and the fourth comparison result.

21. The circuit control method according to any one of claims 18 to 20, characterized in that: The receiving circuit further includes a fifth adjustable voltage source, a sixth adjustable voltage source, a fifth switch, and a sixth switch; The control method of the circuit further includes: The main control circuit is used to control the first input terminal to be disconnected from the third adjustable voltage source through the fifth switch and to be electrically connected to the fifth adjustable voltage source through the fifth switch, and the third input terminal is controlled to be disconnected from the fourth adjustable voltage source through the sixth switch and to be electrically connected to the sixth adjustable voltage source through the sixth switch; the fifth adjustable voltage source is used to input a second reference high level to the first comparator; the sixth adjustable voltage source is used to input a second reference low level to the second comparator; or, The main control circuit is used to control the first input terminal to be electrically connected to the third adjustable voltage source through the fifth switch and to be disconnected from the fifth adjustable voltage source through the fifth switch, and the third input terminal is controlled to be electrically connected to the fourth adjustable voltage source through the sixth switch and to be disconnected from the sixth adjustable voltage source through the sixth switch; the third adjustable voltage source is used to input a first reference high level to the first comparator; the fourth adjustable voltage source is used to input a first reference low level to the second comparator; wherein the second reference high level is different from the first reference high level, and the second reference low level is different from the first reference low level.

22. The circuit control method according to claim 21, characterized in that: The control method of the circuit further includes: Using the main control circuit to control the external circuit to input a second voltage to the first comparator through the second input terminal, and controlling the external circuit to input the second voltage to the second comparator through the fourth input terminal, wherein the second voltage is different from the first voltage; using the first comparator to compare the received second voltage with the second reference high level, and inputting a fifth comparison result to the detection circuit; using the second comparator to compare the received second voltage with the second reference low level, and inputting a sixth comparison result to the detection circuit; The second voltage is identified by the detection circuit according to the fifth comparison result and the sixth comparison result.

23. The circuit control method according to claim 21, characterized in that: The control method of the circuit further includes: In the case where the driving unit further includes a second adjustable voltage source, a third switch and the fourth switch, in the fourth mode, the driving unit is controlled to input the second high level to the first comparator through the output terminal and the second input terminal, and the driving unit is controlled to input the second high level to the second comparator through the output terminal and the fourth input terminal; using the first comparator to compare the received second high level with the second reference high level, and inputting a seventh comparison result to the detection circuit; using the second comparator to compare the received second high level with the second reference low level, and inputting an eighth comparison result to the detection circuit; The detection circuit is used to confirm whether the second adjustable voltage source is qualified according to the seventh comparison result and the eighth comparison result.

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