Fault injection optimization method and device based on FPGA
By extracting the FPGA gate-level netlist and initial fault list from the RTL code, determining predictable fault and equivalent fault groups, and optimizing the initial fault list, solving the problem of the expansion of FPGA circuit scale, resulting in serious increase in fault injection time, and realizing time and resource savings.
Patent Information
- Application Number
- CN202510156172.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-12
- Publication Date
- 2025-05-13
AI Technical Summary
With the expansion of the scale of FPGA circuits, the number of injected faults has increased at an almost exponential rate, which has caused serious time-consuming and inability to meet the actual usage needs.
By extracting the FPGA gate-level netlist and initial fault list from the RTL code to be injected, identify predictable fault and/or equivalent fault groups, and using these fault groups to optimize the initial fault list, build an optimized list for fault injection.
To a certain extent, the time for fault injection is reduced, especially when the verification system is relatively complex and the fault space is particularly large, it greatly saves the time and resources for fault injection and is more in line with actual usage requirements.
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Figure CN119986319A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of fault detection, and in particular to a fault injection optimization method and device based on FPGA (Field Programmable Gate Array). Background Art
[0002] Fault detection coverage is generally obtained through fault injection. Fault injection is a reliability verification technique that intentionally introduces faults into the system through controlled experiments and observes the behavior of the system when the fault exists to calculate the diagnostic coverage. Fault injection is a widely used method to evaluate circuit reliability and the possibility of fault propagation as errors and failures.
[0003] In the related technology, a transmission system model can be established, and the FPGA development platform can be used to analyze the timing logic circuit of the corresponding transmission system model, and then a timing directed graph of the transmission system model can be established, and then the time margin of each timing path in the calculation can be iteratively updated until the time margin of each timing path meets the requirements; it is also possible to perform semantic analysis, hierarchical structure analysis and node extraction on the RTL (Register Transfer Level) code design based on the semantic analysis of the open source library, and then use the simulator for rapid pre-simulation, and classify the corrected nodes according to the automotive chip fault classification standard to facilitate fault simulation.
[0004] However, in the related technology, as the scale of FPGA circuits expands, the fault space, that is, the number of faults that need to be injected, grows at an almost exponential rate, resulting in serious time consumption during fault injection, which cannot meet actual usage needs and is in urgent need of improvement. Summary of the invention
[0005] The present application provides an FPGA-based fault injection optimization method and device to solve the problem in the related art that as the scale of FPGA circuits expands, the number of injected faults increases at a nearly exponential rate, resulting in a serious time consumption during fault injection and failure to meet actual usage requirements.
[0006] The first aspect of the present application provides an FPGA-based fault injection optimization method, comprising the following steps: obtaining the RTL code to be fault injected, and extracting the FPGA gate-level netlist and the initial fault list from the RTL code; determining the predictable faults and / or equivalent fault groups in the initial fault list based on the netlist characteristics of the FPGA gate-level netlist; optimizing the initial nodes in the initial fault list using the predictable faults and / or equivalent fault groups to obtain optimized nodes, and constructing an optimized list corresponding to the initial fault list using the optimized nodes; and injecting faults into the optimized list to obtain the fault injection result of the RTL code.
[0007] Optionally, in one embodiment of the present application, determining the predictable faults in the initial fault list based on the netlist characteristics of the FPGA gate-level netlist includes: determining node information of the nodes to be fault injected in the initial fault list based on the netlist characteristics; and when determining that the node is located in a logic cone using the node information, determining, based on the logic cone, that a fault generated by any node located in the logic cone is a predictable fault.
[0008] Optionally, in one embodiment of the present application, determining the predictable faults in the initial fault list based on the netlist characteristics of the FPGA gate-level netlist further includes: when using the node information to determine that the node is a constant node, determining that the fault generated by the node is a predictable fault based on the constant node.
[0009] Optionally, in one embodiment of the present application, the determining of the equivalent fault group in the initial fault list based on the netlist characteristics of the FPGA gate-level netlist includes: obtaining a truth table of the node to be fault-injected in the initial fault list based on the netlist characteristics; simulating the fault injection behavior of the node using the truth table to obtain a simulated fault injection result of the node; and based on the simulated fault injection result, determining that the faults generated by the nodes corresponding to the same simulated fault injection result are equivalent fault groups.
[0010] Optionally, in one embodiment of the present application, the determining of the equivalent fault group in the initial fault list based on the netlist characteristics of the FPGA gate-level netlist includes: obtaining the circuit connection relationship of the nodes to be fault injected in the initial fault list based on the netlist characteristics; and determining, based on the circuit connection relationship, the fault generated by the node under the one-to-one circuit connection as an equivalent fault group.
[0011] The second aspect of the present application provides a fault injection optimization device based on FPGA, including: an extraction module, used to obtain the RTL code to be fault injected, and extract the FPGA gate-level netlist and the initial fault list from the RTL code; a determination module, used to determine the predictable faults and / or equivalent fault groups in the initial fault list based on the netlist characteristics of the FPGA gate-level netlist; a construction module, used to optimize the initial nodes in the initial fault list using the predictable faults and / or equivalent fault groups to obtain optimized nodes, and use the optimized nodes to construct an optimization list corresponding to the initial fault list; a generation module, used to inject faults into the optimization list to obtain the fault injection result of the RTL code.
[0012] Optionally, in one embodiment of the present application, the determination module includes: a first determination unit, used to determine the node information of the node to be fault injected in the initial fault list based on the netlist characteristics; and a second determination unit, used to determine, based on the logic cone, when using the node information to determine that the node is located in the logic cone, that a fault generated by any node located in the logic cone is a predictable fault.
[0013] Optionally, in one embodiment of the present application, the determination module further includes: a third determination unit, configured to determine, when using the node information to determine that the node is a constant node, that the fault generated by the node is a predictable fault based on the constant node.
[0014] Optionally, in one embodiment of the present application, the determination module includes: a first acquisition unit, used to obtain a truth table of the node to be fault-injected in the initial fault list based on the netlist characteristics; a generation unit, used to simulate the fault injection behavior of the node using the truth table to obtain a simulated fault injection result of the node; and a fourth determination unit, used to determine, based on the simulated fault injection result, that the faults generated by the nodes corresponding to the same simulated fault injection result are equivalent fault groups.
[0015] Optionally, in one embodiment of the present application, the determination module includes: a second acquisition unit, used to acquire the circuit connection relationship of the node to be fault injected in the initial fault list based on the netlist characteristics; a fifth determination unit, used to determine, based on the circuit connection relationship, that the fault generated by the node under the one-to-one circuit connection is an equivalent fault group.
[0016] The third aspect of the present application provides an electronic device, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the FPGA-based fault injection optimization method as described in the above embodiment.
[0017] The fourth aspect of the present application provides a computer-readable storage medium, which stores a computer program. When the program is executed by a processor, it implements the above-mentioned FPGA-based fault injection optimization method.
[0018] The fifth aspect of the present application provides a computer program product, including a computer program, which implements the above-mentioned FPGA-based fault injection optimization method when executed.
[0019] The embodiment of the present application can extract the FPGA gate-level netlist and the initial fault list from the RTL code to be fault-injected, and then determine the predictable faults and / or equivalent fault groups, and use the predictable faults and / or equivalent fault groups to optimize the initial fault list, thereby constructing an optimized list corresponding to the initial fault list, and performing fault injection on the optimized list to obtain a fault injection result, which reduces the time for fault injection to a certain extent, especially when the verification system is relatively complex and the fault space is particularly large, greatly saving the time and resources for fault injection, and more in line with actual use requirements. Thus, the problem in the related art that as the scale of the FPGA circuit expands, the number of injected faults increases at a nearly exponential rate, resulting in serious time consumption during fault injection and failure to meet actual use requirements is solved.
[0020] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:
[0022] Figure 1 A flowchart of a fault injection optimization method based on FPGA provided according to an embodiment of the present application;
[0023] Figure 2 A block diagram of logic cone optimization according to an embodiment of the present application;
[0024] Figure 3 A block diagram of a constant value signal provided according to an embodiment of the present application;
[0025] Figure 4 A flowchart of extracting an equivalent fault group from a truth table according to an embodiment of the present application;
[0026] Figure 5 A schematic block diagram of an extraction sub-truth table provided according to an embodiment of the present application;
[0027] Figure 6 A flowchart of extracting equivalent fault groups from front-to-back connection relationships according to an embodiment of the present application;
[0028] Figure 7 A block diagram of an example FPGA circuit provided according to an embodiment of the present application;
[0029] Figure 8 A block diagram of an optimization process provided according to an embodiment of the present application;
[0030] Fig. 9 A block diagram of an optimization method provided according to an embodiment of the present application;
[0031] Fig.10 A block diagram of a fault injection optimization device based on FPGA provided according to an embodiment of the present application;
[0032] Fig.11 It is a schematic diagram of the structure of an electronic device provided according to an embodiment of the present application. DETAILED DESCRIPTION
[0033] Embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limiting the present application.
[0034] The following describes the FPGA-based fault injection optimization method and device of the embodiment of the present application with reference to the accompanying drawings. In view of the problem mentioned in the above background technology that as the scale of the FPGA circuit expands, the number of injected faults increases at a nearly exponential rate, resulting in serious time consumption during fault injection and failure to meet the actual use requirements, the present application provides a FPGA-based fault injection optimization method, in which the FPGA gate-level netlist and the initial fault list can be extracted from the RTL code to be injected with faults, and then the predictable faults and / or equivalent fault groups are determined, and the initial fault list is optimized using the predictable faults and / or equivalent fault groups, so as to construct an optimized list corresponding to the initial fault list, and the optimized list is injected with faults to obtain the fault injection result, which reduces the time of fault injection to a certain extent, especially when the verification system is relatively complex and the fault space is particularly large, greatly saving the time and resources of fault injection, which is more in line with the actual use requirements. Thus, the problem that as the scale of the FPGA circuit expands, the number of injected faults increases at a nearly exponential rate, resulting in serious time consumption during fault injection and failure to meet the actual use requirements in the related technology is solved.
[0035] Specifically, Figure 1The present invention provides a flowchart of a fault injection optimization method based on FPGA according to an embodiment of the present application.
[0036] like Figure 1 As shown, the FPGA-based fault injection optimization method includes the following steps:
[0037] In step S101 , the RTL code to be subjected to fault injection is obtained, and an FPGA gate-level netlist and an initial fault list are extracted from the RTL code.
[0038] As a possible implementation method, the embodiment of the present application can first obtain the RTL code to be subjected to fault injection, and then use the RTL code to extract the FPGA gate-level netlist and the initial fault list.
[0039] Further, as shown in Table 1, the initial fault list of the embodiment of the present application may include, but is not limited to, three pieces of information: fault sequence number, fault node name position, and fault type, etc., which are not specifically limited in the present application. Among them, in the embodiment of the present application, the fault type can be used to describe how the function of the node changes when a fault occurs. As shown in Table 1, the embodiment of the present application may include, but is not limited to, SA0 fault (Stuck-at-0, fixed "0" fault), that is, the value of the node is stuck at 0; SA1 fault (Stuck-at-1, fixed "1" fault), that is, the value of the node is stuck at 1; SEU fault (Single Event Upset, single event flip), that is, a transient fault, which can also be permanently reversed), etc., which can be specifically set by technicians in this field according to actual conditions, and the present application is not specifically limited. Among them, Table 1 is a block diagram of the initial fault list provided according to an embodiment of the present application.
[0040] Table 1
[0041] Fault number Faulty node name and location Fault type Injection results 1 LUT5-done_sig_tmp_i_1_I0 SA0 - 2 LUT5-done_sig_tmp_i_1_I0 SA1 - 3 LUT5-done_sig_tmp_i_1_I0 SEU - 4 LUT5-done_sig_tmp_i_1_I1 SA0 - ... ... ... ... (gate node type + name + location)
[0042] Exemplarily, the embodiments of the present application can extract an FPGA gate-level netlist and an initial fault list from the RTL code to be subjected to fault injection.
[0043] Among them, in the embodiment of the present application, synthesis can be understood as the process of converting RTL code into a gate-level netlist. The synthesis tool analyzes the logic of the RTL code and maps it to the internal logic unit of the FPGA. Further, the synthesis tool of the embodiment of the present application can include but is not limited to EDA (Electronic Design Automation) tools, third-party synthesis tools, etc., which can be specifically set by a technician in the field according to actual conditions, and this application is not specifically limited.
[0044] In step S102, based on the netlist characteristics of the FPGA gate-level netlist, predictable faults and / or equivalent fault groups in the initial fault list are determined.
[0045] It is understandable that in the embodiments of the present application, a predictable fault can be understood as a fault that directly infers the result of fault injection. In the fault injection activity, the injection result is collected by comparing the values before and after the fault is injected into the observation node to determine whether the fault is converted into a failure. If it can be proved that the fault occurring at a certain node can or cannot affect the value of the observation node, such as the fault that occurs cannot be propagated to the observation node, then the fault injected at this node can be pruned.
[0046] That is to say, the injection result of the predictable fault in the embodiment of the present application can be directly predicted without the need for fault injection, which is equivalent to deleting this row value in the initial fault list (which actually needs to be injected).
[0047] In addition, it should be noted that an equivalent fault group can be understood as a connection between some injected nodes, such as two nodes being the input and output nodes of the same gate, or two nodes being connected by the same line. If mathematical proofs can be used to prove that the injection results of two or more faults are the same or opposite, then these faults can be classified as equivalent fault groups. Equivalent fault groups have the following properties:
[0048] Property 1: If it can be proved that fault A is equivalent to fault B, and fault B is equivalent to fault C, then A and C are also equivalent;
[0049] Property 2: If it can be proved that fault A is equivalent to fault B, and the injection result of B is predictable, then the injection result of A is also predictable.
[0050] Furthermore, according to the two properties of property 1 and property 2, if there are predictable faults in the equivalent fault group, all faults in the group may not be injected. Conversely, only one fault injection is needed to obtain the fault injection results of the entire equivalent fault group.
[0051] That is to say, in the embodiment of the present application, only one fault injection is required in each equivalent fault group, and the others are equivalent to optimized faults. In particular, if there are predictable faults in the group, the fault injection results in the entire group can be predicted.
[0052] In some embodiments, the embodiments of the present application may determine the predictable faults and equivalent fault groups in the initial fault list based on the netlist characteristics of the FPGA gate-level netlist.
[0053] In some embodiments, the embodiments of the present application may determine predictable faults in the initial fault list based on the netlist characteristics of the FPGA gate-level netlist.
[0054] In some embodiments, the embodiments of the present application may determine an equivalent fault group in an initial fault list based on the netlist characteristics of an FPGA gate-level netlist.
[0055] Optionally, in one embodiment of the present application, based on the netlist characteristics of the FPGA gate-level netlist, predictable faults in the initial fault list are determined, including: based on the netlist characteristics, determining node information of the nodes to be fault-injected in the initial fault list; when using the node information to determine that the node is within the logic cone, determining, based on the logic cone, that a fault generated by any node within the logic cone is a predictable fault.
[0056] In some embodiments, when determining predictable faults, the embodiments of the present application may determine the predictable faults through a logic cone, wherein, in the embodiments of the present application, each logic cone starts from the output / trigger of the circuit and traverses all nodes in the circuit forward until the input / trigger (end point) of the circuit, obtaining a cone-shaped structure. All nodes within the cone will affect the value of the starting point of the logic cone. Similarly, all nodes outside the cone have no effect on the starting point of the logic cone.
[0057] For example, Figure 2 As shown, the logic cone of the observation node OUT1 in the embodiment of the present application includes all nodes of FF3, LUT1, LUT2 and the logic cones of FF1 and FF2. Therefore, the fault injected at the output point A1 of LUT1 may propagate to the observation node OUT1, but all faults injected at the input point A2 of LUT3 will not propagate to the observation node OUT1, which is a predictable fault.
[0058] Optionally, in one embodiment of the present application, based on the netlist characteristics of the FPGA gate-level netlist, determining the predictable faults in the initial fault list also includes: when using node information to determine that a node is a constant node, determining that the fault generated by the node is a predictable fault based on the constant node.
[0059] In some other embodiments, the embodiments of the present application may determine predictable faults through constant value nodes, wherein in the embodiments of the present application, the constant value nodes may be understood as constant value signals existing in the circuit after synthesis or during simulation.
[0060] For example, Figure 3 As shown, the value of the node \fifo_buffer[4][7]_i_2_n_0 in the embodiment of the present application is always 1, so it can be predicted that all SA1 faults injected into this node will not affect the circuit.
[0061] Optionally, in one embodiment of the present application, based on the netlist characteristics of the FPGA gate-level netlist, an equivalent fault group in the initial fault list is determined, including: based on the netlist characteristics, obtaining a truth table of the nodes to be fault-injected in the initial fault list; using the truth table to simulate the fault injection behavior of the nodes to obtain a simulated fault injection result of the nodes; based on the simulated fault injection result, determining that the faults generated by the nodes corresponding to the same simulated fault injection result are equivalent fault groups.
[0062] In some embodiments, when determining an equivalent fault group, the embodiment of the present application may determine it through a truth table, wherein the process of extracting an equivalent fault group from the truth table in the embodiment of the present application is as follows: Figure 4 The main contents can be:
[0063] Step S401: Obtain a truth table.
[0064] Step S402: Fixed input.
[0065] Step S403: Obtain a sub-truth table.
[0066] Step S404: Determine the output.
[0067] Step S405: When the outputs are the same, an equivalent fault group is obtained.
[0068] Step S406: If the outputs are different, end the process.
[0069] For example, combining Figure 5 As shown, after obtaining the truth table, the embodiment of the present application needs to extract the output value combination of each input node set to 0 or 1. A set of output value combinations with I0 always being 0 is extracted from the truth table to simulate the behavior of injecting SA0 fault at I0. It is obvious that all the outputs are 0 at this time, which proves that injecting 0 at I0 and injecting 0 at O are equivalent.
[0070] Optionally, in one embodiment of the present application, based on the netlist characteristics of the FPGA gate-level netlist, an equivalent fault group in the initial fault list is determined, including: based on the netlist characteristics, obtaining the circuit connection relationship of the nodes to be fault injected in the initial fault list; based on the circuit connection relationship, determining that the fault generated by the node under the one-to-one circuit connection is an equivalent fault group.
[0071] In some embodiments, when determining the equivalent fault group, the embodiment of the present application can be determined by the circuit connection relationship. It can be understood that the embodiment of the present application can extract the equivalent fault group from the front and back connection relationship of the circuit, that is, the front and back nodes are injected with fault equivalence under a single-to-single circuit connection. The process is as follows Figure 6 As shown, the main contents can be:
[0072] Step S601: Obtain circuit connection relationship.
[0073] Step S602: Determine whether it is a one-to-one circuit connection.
[0074] Step S603: When it is a one-to-one circuit connection, determine an equivalent fault group.
[0075] Step S604: When it is not a one-to-one circuit connection, end the process.
[0076] For example, Figure 7 As shown, the output O of done_sig_tmp_i_1 in the embodiment of the present application is directly connected to the input D of done_sig_tmp_reg, and all faults injected at O will be directly propagated to the D end, so all faults injected at the output point O are equivalent to those injected at the input point D.
[0077] In addition, it should be noted that the embodiment of the present application is no longer applicable when a line has multiple inputs or loads. A fault injected at the input end will propagate to all output ends, which is different from injecting a fault at each node separately.
[0078] In step S103, the initial nodes in the initial fault list are optimized using the predictable faults and / or equivalent fault groups to obtain optimized nodes, and the optimized list corresponding to the initial fault list is constructed using the optimized nodes.
[0079] In some embodiments, the embodiments of the present application can use predictable faults to optimize the initial nodes in the initial fault list to obtain optimized nodes, and then use these optimized nodes to construct an optimized list corresponding to the initial fault list.
[0080] In some embodiments, the embodiments of the present application can use equivalent fault groups to optimize the initial nodes in the initial fault list to obtain optimized nodes, and then use these optimized nodes to construct an optimized list corresponding to the initial fault list.
[0081] In some embodiments, the embodiments of the present application can use predictable faults and equivalent fault groups to optimize the initial nodes in the initial fault list to obtain optimized nodes, and then use these optimized nodes to construct an optimized list corresponding to the initial fault list.
[0082] In step S104, fault injection is performed on the optimization list to obtain a fault injection result of the RTL code.
[0083] As a possible implementation method, the embodiment of the present application can perform fault injection on the optimization list to obtain the fault injection result corresponding to the RTL code.
[0084] Combine the following Figure 8 and Fig. 9 As shown, the working principle of the FPGA-based fault injection optimization method proposed in the embodiment of the present application is introduced with a specific embodiment.
[0085] Specifically, the RTL code of the embodiment of the present application is first comprehensively extracted to obtain an FPGA gate-level netlist and an initial fault list, and then the predictable faults and equivalent fault groups in the initial fault list are determined according to the netlist characteristics of the FPGA gate-level netlist, and then the initial fault list is optimized to construct an optimized list corresponding to the initial fault list, and then only faults are injected into the optimized list to obtain the fault injection result of the RTL code.
[0086] In addition, the embodiments of the present application may also utilize AI methods to train a machine learning model using a portion of the fault injection results to predict the remaining fault injection results, but the prediction accuracy is difficult to guarantee, which will affect the reliability of the final fault coverage.
[0087] According to the FPGA-based fault injection optimization method proposed in the embodiment of the present application, the FPGA gate-level netlist and the initial fault list can be extracted from the RTL code to be fault-injected, and then the predictable faults and / or equivalent fault groups are determined, and the initial fault list is optimized using the predictable faults and / or equivalent fault groups, so as to construct an optimized list corresponding to the initial fault list, and perform fault injection on the optimized list to obtain the fault injection result, which reduces the time of fault injection to a certain extent, especially when the verification system is relatively complex and the fault space is particularly large, greatly saving the time and resources of fault injection, and more in line with actual use requirements. Thus, the problem in the related art that as the scale of the FPGA circuit expands, the number of injected faults increases at a nearly exponential rate, resulting in serious time consumption during fault injection and failure to meet actual use requirements is solved.
[0088] Next, the FPGA-based fault injection optimization device proposed according to the embodiment of the present application is described with reference to the accompanying drawings.
[0089] Fig.10 It is a block diagram of an FPGA-based fault injection optimization device provided according to an embodiment of the present application.
[0090] like Fig.10 As shown, the FPGA-based fault injection optimization device 10 includes: an extraction module 100 , a determination module 200 , a construction module 300 and a generation module 400 .
[0091] The extraction module 100 is used to obtain the RTL code to be subjected to fault injection, and to extract the FPGA gate-level netlist and the initial fault list from the RTL code.
[0092] The determination module 200 is used to determine the predictable faults and / or equivalent fault groups in the initial fault list based on the netlist characteristics of the FPGA gate-level netlist.
[0093] The construction module 300 is used to optimize the initial nodes in the initial fault list by using the predictable faults and / or equivalent fault groups to obtain optimized nodes, and to construct an optimized list corresponding to the initial fault list by using the optimized nodes.
[0094] The generating module 400 is used to perform fault injection on the optimization list to obtain the fault injection result of the RTL code.
[0095] Optionally, in one embodiment of the present application, the determination module 200 includes: a first determination unit and a second determination unit.
[0096] The first determining unit is used to determine the node information of the node to be injected with fault in the initial fault list based on the netlist characteristics.
[0097] The second determining unit is configured to determine, when determining by using the node information that the node is located in the logic cone, that a fault generated by any node in the logic cone is a predictable fault based on the logic cone.
[0098] Optionally, in one embodiment of the present application, the determination module 200 further includes: a third determination unit.
[0099] The third determination unit is used to determine that a fault generated by the node is a predictable fault based on the constant value node when the node is determined to be a constant value node by using the node information.
[0100] Optionally, in one embodiment of the present application, the determination module 200 includes: a first acquisition unit, a generation unit and a fourth determination unit.
[0101] The first acquisition unit is used to acquire the truth table of the node to be fault-injected in the initial fault list based on the netlist characteristics.
[0102] The generation unit is used to simulate the fault injection behavior of the node by using the truth table to obtain the simulated fault injection result of the node.
[0103] The fourth determining unit is used to determine, based on the simulated fault injection result, that the faults generated by the nodes corresponding to the same simulated fault injection result are an equivalent fault group.
[0104] Optionally, in one embodiment of the present application, the determination module 200 includes: a second acquisition unit and a fifth determination unit.
[0105] The second acquisition unit is used to acquire the circuit connection relationship of the node to be injected with fault in the initial fault list based on the netlist characteristics.
[0106] The fifth determining unit is used to determine, based on the circuit connection relationship, that the faults generated by the nodes in the one-to-one circuit connection are an equivalent fault group.
[0107] It should be noted that the above explanation of the embodiment of the FPGA-based fault injection optimization method is also applicable to the FPGA-based fault injection optimization device of this embodiment, and will not be repeated here.
[0108] According to the FPGA-based fault injection optimization device proposed in the embodiment of the present application, the FPGA gate-level netlist and the initial fault list can be extracted from the RTL code to be fault-injected, and then the predictable faults and / or equivalent fault groups are determined, and the initial fault list is optimized using the predictable faults and / or equivalent fault groups, thereby constructing an optimized list corresponding to the initial fault list, and performing fault injection on the optimized list to obtain the fault injection result, which reduces the time of fault injection to a certain extent, especially when the verification system is relatively complex and the fault space is particularly large, greatly saving the time and resources of fault injection, and more in line with actual use requirements. Thus, the problem in the related art that as the scale of the FPGA circuit expands, the number of injected faults increases at a nearly exponential rate, resulting in serious time consumption during fault injection and failure to meet actual use requirements is solved.
[0109] Fig.11 This is a schematic diagram of the structure of an electronic device provided according to an embodiment of the present application. The electronic device may include:
[0110] A memory 1101 , a processor 1102 , and a computer program stored in the memory 1101 and executable on the processor 1102 .
[0111] When the processor 1102 executes the program, the FPGA-based fault injection optimization method provided in the above embodiment is implemented.
[0112] Furthermore, the electronic device further comprises:
[0113] The communication interface 1103 is used for communication between the memory 1101 and the processor 1102 .
[0114] The memory 1101 is used to store computer programs that can be executed on the processor 1102 .
[0115] The memory 1101 may include a high-speed RAM memory, and may also include a non-volatile memory (non-volatile memory), such as at least one disk memory.
[0116] If the memory 1101, the processor 1102 and the communication interface 1103 are implemented independently, the communication interface 1103, the memory 1101 and the processor 1102 can be connected to each other through a bus and communicate with each other. The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Fig.11 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.
[0117] Optionally, in a specific implementation, if the memory 1101, the processor 1102 and the communication interface 1103 are integrated on a chip, the memory 1101, the processor 1102 and the communication interface 1103 can communicate with each other through an internal interface.
[0118] The processor 1102 may be a central processing unit (CPU), or an application specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of the present application.
[0119] An embodiment of the present application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the above-mentioned FPGA-based fault injection optimization method.
[0120] An embodiment of the present application also provides a computer program product, including a computer program, which implements the above FPGA-based fault injection optimization method when executed.
[0121] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or N embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.
[0122] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of this application, "N" means at least two, such as two, three, etc., unless otherwise clearly and specifically defined.
[0123] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, fragment or portion of code comprising one or N executable instructions for implementing the steps of a custom logical function or process, and the scope of the preferred embodiments of the present application includes alternative implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in reverse order depending on the functions involved, which should be understood by technicians in the technical field to which the embodiments of the present application belong.
[0124] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as an ordered list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by an instruction execution system, device or apparatus (such as a computer-based system, a system including a processor, or other system that can fetch instructions from an instruction execution system, device or apparatus and execute instructions), or in combination with these instruction execution systems, devices or apparatuses. For the purpose of this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate or transmit a program for use by an instruction execution system, device or apparatus, or in combination with these instruction execution systems, devices or apparatuses. More specific examples of computer-readable media (a non-exhaustive list) include the following: an electrical connection with one or N wirings (electronic devices), a portable computer disk box (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), a fiber optic device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically by optically scanning the paper or other medium and then editing, interpreting or processing in other suitable ways as necessary and then storing it in a computer memory.
[0125] It should be understood that the various parts of the present application can be implemented by hardware, software, firmware or a combination thereof. In the above embodiment, the N steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. If implemented by hardware, as in another embodiment, it can be implemented by any one or a combination of multiple of the following technologies known in the art: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.
[0126] A person skilled in the art may understand that all or part of the steps in the method for implementing the above-mentioned embodiment may be completed by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, which, when executed, includes one or a combination of the steps of the method embodiment.
[0127] In addition, each functional unit in each embodiment of the present application may be integrated into a processing module, or each unit may exist physically separately, or two or more units may be integrated into one module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium.
[0128] The storage medium mentioned above may be a read-only memory, a magnetic disk or an optical disk, etc. Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limiting the present application. A person of ordinary skill in the art may change, modify, replace and modify the above embodiments within the scope of the present application.
Claims
1. A fault injection optimization method based on FPGA, characterized in that: The following steps are involved: Obtaining a register transfer level RTL code to be subjected to fault injection, and extracting a field programmable gate array FPGA gate level netlist and an initial fault list from the RTL code; Determining predictable faults and / or equivalent fault groups in the initial fault list based on the netlist characteristics of the FPGA gate-level netlist; Optimizing the initial nodes in the initial fault list using the predictable faults and / or equivalent fault groups to obtain optimized nodes, and constructing an optimized list corresponding to the initial fault list using the optimized nodes; Fault injection is performed on the optimization list to obtain a fault injection result of the RTL code.
2. The method according to claim 1, characterized in that The determining of the predictable faults in the initial fault list based on the netlist characteristics of the FPGA gate-level netlist includes: Based on the netlist characteristics, determining node information of nodes to be subjected to fault injection in the initial fault list; When it is determined by using the node information that the node is located in a logic cone, a fault generated by any node located in the logic cone is determined to be a predictable fault based on the logic cone.
3. The method according to claim 2, characterized in that The determining of the predictable faults in the initial fault list based on the netlist characteristics of the FPGA gate-level netlist further includes: When the node is determined to be a constant value node by using the node information, a fault generated by the node is determined to be a predictable fault based on the constant value node.
4. The method according to claim 1, characterized in that: The determining of the equivalent fault group in the initial fault list based on the netlist characteristics of the FPGA gate-level netlist includes: Based on the netlist characteristics, obtaining a truth table of the nodes to be subjected to fault injection in the initial fault list; Using the truth table to simulate the fault injection behavior of the node to obtain a simulated fault injection result of the node; Based on the simulated fault injection results, faults generated at nodes corresponding to the same simulated fault injection results are determined as an equivalent fault group.
5. The method according to claim 1, characterized in that The determining of the equivalent fault group in the initial fault list based on the netlist characteristics of the FPGA gate-level netlist includes: Based on the netlist characteristics, obtaining the circuit connection relationship of the nodes to be subjected to fault injection in the initial fault list; Based on the circuit connection relationship, the faults generated by the nodes in the one-to-one circuit connection are determined as an equivalent fault group.
6. A fault injection optimization device based on FPGA, characterized in that: include: An extraction module, used for acquiring the RTL code to be subjected to fault injection, and extracting an FPGA gate-level netlist and an initial fault list from the RTL code; A determination module, configured to determine the predictable faults and / or equivalent fault groups in the initial fault list based on the netlist characteristics of the FPGA gate-level netlist; A construction module, configured to optimize the initial nodes in the initial fault list by using the predictable faults and / or equivalent fault groups to obtain optimized nodes, and to construct an optimized list corresponding to the initial fault list by using the optimized nodes; A generating module is used to perform fault injection on the optimization list to obtain a fault injection result of the RTL code.
7. The device according to claim 6, characterized in that The determining module comprises: A first determining unit, configured to determine node information of a node to be subjected to fault injection in the initial fault list based on the netlist characteristics; A second determining unit is configured to determine, when using the node information to determine that the node is located in a logic cone, that a fault generated by any node in the logic cone is a predictable fault based on the logic cone.
8. An electronic device, characterized in that: include: A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the FPGA-based fault injection optimization method according to any one of claims 1 to 5.
9. A computer-readable storage medium having a computer program stored thereon, characterized in that: The program is executed by a processor to implement the FPGA-based fault injection optimization method as described in any one of claims 1 to 5.
10. A computer program product, characterized in that It comprises a computer program, which, when executed, is used to implement the FPGA-based fault injection optimization method as described in any one of claims 1 to 5.