Memory control method and memory storage device

Abstract

The present application provides a memory control method and a memory storage device, which can maintain the stability of the write speed. The memory control method is used in a rewritable non-volatile memory module. The rewritable non-volatile memory module includes a plurality of physical units. The memory control method includes: selecting a plurality of target physical units from the plurality of physical units, wherein the plurality of target physical units includes a first number of first target physical units and a second number of second target physical units; and determining a write mode of a second write operation according to a switching condition when performing a first write operation in a continuous write operation, wherein the second write operation is a next write operation of the first write operation, wherein the write mode includes a first write mode and a second write mode, the first target physical units correspond to the first write mode, the second target physical units correspond to the second write mode, and the first write mode is different from the second write mode.

Description

TECHNICAL FIELD

[0001] The present application relates to a storage technology field, and more particularly, to a memory control method and a memory storage device. BACKGROUND

[0002] Smartphones, tablet computers and personal computers have grown rapidly in recent years, making the consumer demand for storage media also rapidly increased. Because of rewritable non-volatile memory module (for example, flash memory) has the characteristics of data non-volatility, power saving, small size, and no mechanical structure, so it is very suitable for built-in various portable multimedia devices as mentioned above.

[0003] In the field of storage technology, the fixed write mode is mostly used to perform continuous write operation, so that the write speed varies greatly. Therefore, how to maintain the stability of the data write speed is the focus of the researchers in the field. SUMMARY

[0004] The exemplary embodiments of the present application provide a memory control method and a memory storage device, which can maintain the stability of the write speed.

[0005] The exemplary embodiments of the present application provide a memory control method for a rewritable non-volatile memory module. The rewritable non-volatile memory module includes a plurality of physical units. The memory control method includes: selecting a plurality of target physical units from the plurality of physical units, wherein the plurality of target physical units includes a first number of first target physical units and a second number of second target physical units; determining a write mode of a second write operation according to a switching condition when performing a first write operation in a continuous write operation, wherein the second write operation is a next write operation of the first write operation, wherein the write mode includes a first write mode and a second write mode, the first target physical units correspond to the first write mode, the second target physical units correspond to the second write mode, and the first write mode is different from the second write mode.

[0006] In the exemplary embodiments of the present application, the memory control method further includes: obtaining a first write speed, a second write speed and a target write speed corresponding to the continuous write operation before performing the continuous write operation; and calculating a first ratio according to the target write speed, the first write speed and the second write speed.

[0007] In an example embodiment of the present application, the first write speed is a write speed required to complete the continuous write operation in the first write mode, and the second write speed is a write speed required to complete the continuous write operation in the second write mode.

[0008] In an example embodiment of the present application, the step of determining the write mode of the second write operation according to the switching condition comprises: obtaining a first data amount of the first target physical unit and a second data amount of the second target physical unit; calculating a second ratio according to the first data amount and the second data amount; and determining the write mode of the second write operation according to the first ratio and the second ratio.

[0009] In an example embodiment of the present application, the first data amount is a written data amount of the first target physical unit, and the second data amount is a written data amount of the second target physical unit.

[0010] In an example embodiment of the present application, the plurality of target physical units respectively have a plurality of logical-to-physical information, and the plurality of logical-to-physical information respectively record a written order of the plurality of target physical units and a mapping relationship between a physical address and a logical address of the plurality of target physical units.

[0011] In an example embodiment of the present application, after the second target physical unit is filled, the first target physical unit is no longer used to store data.

[0012] In an example embodiment of the present application, the memory control method further comprises: if a logical address is mapped to a plurality of physical addresses of the plurality of target physical units, querying a latest physical address in the plurality of physical addresses according to the written order of the plurality of target physical units in the plurality of logical-to-physical information.

[0013] In an example embodiment of the present application, the memory control method further comprises: during the execution of the continuous write operation, establishing a first switching time table and a second switching time table, wherein the first switching time table is used to record a physical address and a time stamp corresponding to the latest data stored in the second target physical unit when switching from the second write mode to the first write mode, and the second switching time table is used to record a physical address and a time stamp corresponding to the latest data stored in the first target physical unit when switching from the first write mode to the second write mode.

[0014] In an example embodiment of this disclosure, the memory control method further comprises, if the logical address is mapped to a plurality of entity addresses of the plurality of target entity units, querying the plurality of entity addresses from the plurality of logical-to-entity information; querying a plurality of time stamps corresponding to the plurality of entity addresses from at least one of the first switching schedule and the second switching schedule; and determining a latest entity address of the plurality of entity addresses according to the plurality of time stamps.

[0015] An example embodiment of this disclosure further provides a memory storage device, which includes a connection interface unit, a rewritable non-volatile memory module, and a memory control circuit unit. The memory control circuit unit is coupled to the connection interface unit and the rewritable non-volatile memory module. The connection interface unit is configured to be coupled to a host system. The rewritable non-volatile memory module includes a plurality of entity units. The memory control circuit unit is configured to select a plurality of target entity units from the plurality of entity units, wherein the plurality of target entity units includes a first number of first target entity units and a second number of second target entity units. The memory control circuit unit is further configured to determine a write mode of a second write operation according to a switching condition when performing a first write operation of a plurality of consecutive write operations, wherein the second write operation is a next write operation of the first write operation, wherein the write mode includes a first write mode and a second write mode, the first target entity units correspond to the first write mode, the second target entity units correspond to the second write mode, and the first write mode is different from the second write mode.

[0016] In an example embodiment of this disclosure, the memory control circuit unit is further configured to obtain a first write speed, a second write speed, and a target write speed corresponding to the plurality of consecutive write operations, and calculate a first ratio according to the target write speed, the first write speed, and the second write speed before performing the plurality of consecutive write operations.

[0017] In an example embodiment of this disclosure, the memory control circuit unit is further configured to obtain a first data amount of the first target entity units and a second data amount of the second target entity units. The memory control circuit unit is further configured to calculate a second ratio according to the first data amount and the second data amount. The memory control circuit unit is further configured to determine the write mode of the second write operation according to the first ratio and the second ratio.

[0018] In an example embodiment of the present application, if a logical address is mapped to a plurality of entity addresses of the plurality of target entity units, the memory control circuit unit is further configured to query the latest entity address from the plurality of entity addresses according to the write-in order of the plurality of target entity units in the plurality of logical-to-entity information.

[0019] In an example embodiment of the present application, during the execution of the continuous write operation, the memory control circuit unit is further configured to establish a first switch schedule and a second switch schedule, wherein the first switch schedule is used to record the entity address and the time stamp corresponding to the latest data stored in the second target entity unit when switching from the second write mode to the first write mode, and the second switch schedule is used to record the entity address and the time stamp corresponding to the latest data stored in the first target entity unit when switching from the first write mode to the second write mode.

[0020] In an example embodiment of the present application, if a logical address is mapped to a plurality of entity addresses of the plurality of target entity units, the memory control circuit unit is further configured to query the plurality of entity addresses from the plurality of logical-to-entity information. The memory control circuit unit is further configured to query a plurality of time stamps corresponding to the plurality of entity addresses from at least one of the first switch schedule and the second switch schedule. The memory control circuit unit is further configured to determine the latest entity address from the plurality of entity addresses according to the plurality of time stamps.

[0021] Based on the above, the present application provides a memory control method and a memory storage device. By performing a continuous write operation on a plurality of target entity units and timely switching the write mode of the continuous write operation, the write speed control in a small data amount (i.e., the write data amount corresponding to the continuous write operation) can be achieved to improve the stability of the write speed.

[0022] In order to make the above features and advantages of the present application more apparent, specific examples are described below in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1 is a schematic diagram of a host system, a memory storage device and an input / output (I / O) device according to an example embodiment of the present application;

[0024] Figure 2 is a schematic diagram of a host system, a memory storage device and an I / O device according to an example embodiment of the present application;

[0025] Figure 3is a schematic diagram of a host system and a memory storage device shown in accordance with an example embodiment of the present invention;

[0026] Figure 4 is a schematic diagram of a memory storage device shown in accordance with an example embodiment of the present invention;

[0027] Figure 5 is a schematic diagram of a memory control circuit unit shown in accordance with an example embodiment of the present invention;

[0028] Figure 6 is a flowchart of a memory control method shown in accordance with an example embodiment of the present invention;

[0029] Figure 7 is a schematic diagram of a first open pool and a second open pool shown in accordance with an example embodiment of the present invention;

[0030] Figure 8 is a schematic diagram of logical to physical information shown in accordance with an example embodiment of the present invention;

[0031] Figure 9 is a schematic diagram of a first switching schedule and a second switching schedule shown in accordance with an example embodiment of the present invention;

[0032] Figure 10 is a flowchart of a memory control method shown in accordance with an example embodiment of the present invention. DETAILED DESCRIPTION

[0033] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used in the different drawings / taken to indicate the same or similar elements.

[0034] Generally speaking, a memory storage device (also referred to as a memory storage system) includes a rewritable non-volatile memory module and a controller (also referred to as a control circuit). The memory storage device can be used with a host system so that the host system can write data to or read data from the memory storage device.

[0035] Figure 1 is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device shown in accordance with an example embodiment of the present invention. Figure 2 is a schematic diagram of a host system, a memory storage device, and an I / O device shown in accordance with an example embodiment of the present invention.

[0036] Reference will now be made to Figure 1 and Figure 2The host system 11 can include a processor 111, a random access memory (RAM) 112, a read only memory (ROM) 113, and a data transmission interface 114. The processor 111, the random access memory 112, the read only memory 113, and the data transmission interface 114 can be coupled to a system bus 110.

[0037] In an example embodiment, the host system 11 can be coupled to the memory storage device 10 through the data transmission interface 114. For example, the host system 11 can store data to or read data from the memory storage device 10 via the data transmission interface 114. In addition, the host system 11 can be coupled to the I / O device 12 through the system bus 110. For example, the host system 11 can transmit output signals to or receive input signals from the I / O device 12 via the system bus 110.

[0038] In an example embodiment, the processor 111, the random access memory 112, the read only memory 113, and the data transmission interface 114 can be disposed on a motherboard 20 of the host system 11. The number of the data transmission interface 114 can be one or more. Through the data transmission interface 114, the motherboard 20 can be coupled to the memory storage device 10 via wired or wireless manner.

[0039] In an example embodiment, the memory storage device 10 can be, for example, a flash drive 201, a memory card 202, a solid state drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 can be, for example, a near field communication (NFC) memory storage device, a wireless fidelity (WiFi) memory storage device, a Bluetooth memory storage device, or a Bluetooth low energy (BLE) memory storage device (e.g., iBeacon), or the like memory storage device based on various wireless communication technologies. In addition, the motherboard 20 can also be coupled to various I / O devices, such as a global positioning system (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, a speaker 210, and the like, through the system bus 110. For example, in an example embodiment, the motherboard 20 can access the wireless memory storage device 204 through the wireless transmission device 207.

[0040] In an example embodiment, the host system 11 is a computer system. In an example embodiment, the host system 11 can be any system that can substantially cooperate with the memory storage device to store data. In an example embodiment, the host system 11 is an in-vehicle system. In an example embodiment, the memory storage device 10 and the host system 11 can respectively comprise Figure 3 the memory storage device 30 and the host system 31 according to an example embodiment of the present application.

[0041] Figure 3 is a schematic diagram of a host system and a memory storage device shown according to an example embodiment of the present application.

[0042] Referring to Figure 3 , the memory storage device 30 can be used with the host system 31 to store data. For example, the host system 31 can be a digital camera, a camcorder, a communication device, an audio player, a video player, or a tablet computer, etc. For example, the memory storage device 30 can be a secure digital (SD) card 32, a compact flash (CF) card 33, or an embedded storage device 34, etc. of various non-volatile memory storage devices used by the host system 31. The embedded storage device 34 includes an embedded multi media card (eMMC) 341 and / or an embedded multi chip package (eMCP) storage device 342, etc. of various embedded storage devices that directly couple memory modules on a substrate of the host system.

[0043] Figure 4 is a schematic diagram of a memory storage device shown according to an example embodiment of the present application.

[0044] Referring to Figure 4 , the memory storage device 10 includes a connection interface unit 41, a memory control circuit unit 42, and a rewritable non-volatile memory module 43.

[0045] The connection interface unit 41 is used to couple the memory storage device 10 to the host system 11. The memory storage device 10 can communicate with the host system 11 via the connection interface unit 41. In an example embodiment, the connection interface unit 41 is compatible with the Peripheral Component Interconnect Express (PCI Express) standard. In an example embodiment, the connection interface unit 41 can also be compliant with the Serial Advanced Technology Attachment (SATA) standard, the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronic Engineers (IEEE) 1394 standard, the Universal Serial Bus (USB) standard, the SD interface standard, the Ultra High Speed-I (UHS-I) interface standard, the Ultra High Speed-II (UHS-II) interface standard, the Memory Stick (MS) interface standard, the MCP interface standard, the MMC interface standard, the eMMC interface standard, the Universal Flash Storage (UFS) interface standard, the eMCP interface standard, the CF interface standard, the Integrated Device Electronics (IDE) standard, or other suitable standards. The connection interface unit 41 can be packaged in a chip with the memory control circuit unit 42, or the connection interface unit 41 is disposed outside a chip that contains the memory control circuit unit 42.

[0046] The memory control circuit unit 42 is coupled to the connection interface unit 41 and the rewritable non-volatile memory module 43. The memory control circuit unit 42 is used to execute a plurality of logic gates or control instructions implemented in a hardware type or a firmware type and perform data writing, reading, erasing, and other operations in the rewritable non-volatile memory module 43 according to instructions of the host system 11.

[0047] The rewritable nonvolatile memory module 43 stores data written by the host system 11. The rewritable nonvolatile memory module 43 can include a single level cell (SLC) NAND type flash memory module (i.e., a flash memory module in which one bit can be stored in one memory cell), a multi level cell (MLC) NAND type flash memory module (i.e., a flash memory module in which two bits can be stored in one memory cell), a triple level cell (TLC) NAND type flash memory module (i.e., a flash memory module in which three bits can be stored in one memory cell), a quad level cell (QLC) NAND type flash memory module (i.e., a flash memory module in which four bits can be stored in one memory cell), another flash memory module, or another memory module having the same characteristics.

[0048] Each memory cell in the rewritable nonvolatile memory module 43 stores one or more bits by changing a voltage (hereinafter also referred to as a threshold voltage). Specifically, there is a charge trapping layer between a control gate and a channel of each memory cell. By applying a write voltage to the control gate, the amount of electrons of the charge trapping layer is changed, and thus the threshold voltage of the memory cell is changed. This operation of changing the threshold voltage of the memory cell is also referred to as "writing data to the memory cell" or "programming the memory cell". As the threshold voltage is changed, each memory cell in the rewritable nonvolatile memory module 43 has a plurality of storage states. By applying a read voltage, it is possible to determine which storage state a memory cell belongs to, and thus it is possible to acquire one or more bits stored in the memory cell.

[0049] In an example embodiment, the memory cells of the rewritable nonvolatile memory module 43 can constitute a plurality of physical program units, and the physical program units can constitute a plurality of physical units. Specifically, the memory cells on the same word line can form one or more physical program units. If each memory cell can store more than two bits, the physical program units on the same word line can be classified into at least lower physical program units and upper physical program units. For example, the least significant bit (LSB) of a memory cell belongs to a lower physical program unit, and the most significant bit (MSB) of a memory cell belongs to an upper physical program unit. Generally, in an MLC NAND type flash memory, the write speed of a lower physical program unit is greater than that of an upper physical program unit, and / or the reliability of a lower physical program unit is higher than that of an upper physical program unit.

[0050] In an example embodiment, a physical program unit is the smallest unit of programming. That is, a physical program unit is the smallest unit of writing data. For example, a physical program unit can be a physical page or a physical sector. If a physical program unit is a physical page, the physical program units can include a data bit area and a redundancy bit area. The data bit area contains a plurality of physical sectors for storing user data, and the redundancy bit area is for storing system data (e.g., management data such as error correction codes). In the present example embodiment, the data bit area contains 32 physical sectors, and the size of one physical sector is 512 bytes (B). However, in other example embodiments, the data bit area can contain 8, 16, or a greater or smaller number of physical sectors, and the size of each physical sector can be greater or smaller. On the other hand, a physical unit is the smallest unit of erasing. That is, each physical unit contains a minimum number of memory cells that are erased together. For example, a physical unit is a physical block.

[0051] Figure 5 FIG. 1 is a schematic diagram of a memory control circuit unit according to an example embodiment of the present application.

[0052] Please refer to Figure 5 The memory control circuit unit 42 includes a memory management circuit 51, a host interface 52, and a memory interface 53.

[0053] The memory management circuit 51 is used to control the overall operation of the memory control circuit unit 42. Specifically, the memory management circuit 51 has a plurality of control instructions, and these control instructions are executed to perform data write, read and erase operations, etc. when the memory storage device 10 is in operation. The following description of the operation of the memory management circuit 51 is equivalent to the description of the operation of the memory control circuit unit 42.

[0054] In an exemplary embodiment, the control instructions of the memory management circuit 51 are implemented in firmware. For example, the memory management circuit 51 has a microprocessor unit (not shown) and a read-only memory (not shown), and these control instructions are burned into the read-only memory. When the memory storage device 10 is in operation, these control instructions are executed by the microprocessor unit to perform data write, read and erase operations, etc.

[0055] In an exemplary embodiment, the control instructions of the memory management circuit 51 can also be stored in code form in a specific area (e.g., a system area in the memory module for storing system data) of the rewritable non-volatile memory module 43. In addition, the memory management circuit 51 has a microprocessor unit (not shown), a read-only memory (not shown) and a random access memory (not shown). In particular, the read-only memory has a boot code, and when the memory control circuit unit 42 is enabled, the microprocessor unit first executes the boot code to load the control instructions stored in the rewritable non-volatile memory module 43 into the random access memory of the memory management circuit 51. Then, the microprocessor unit executes these control instructions to perform data write, read and erase operations, etc.

[0056] In an example embodiment, the control instructions of the memory management circuit 51 can also be implemented in a hardware type. For example, the memory management circuit 51 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory cell management circuit, the memory write circuit, the memory read circuit, the memory erase circuit, and the data processing circuit are coupled to the microcontroller. The memory cell management circuit is used to manage the memory cells or the groups of memory cells of the rewritable non-volatile memory module 43. The memory write circuit is used to issue a write instruction sequence to the rewritable non-volatile memory module 43 to write data into the rewritable non-volatile memory module 43. The memory read circuit is used to issue a read instruction sequence to the rewritable non-volatile memory module 43 to read data from the rewritable non-volatile memory module 43. The memory erase circuit is used to issue an erase instruction sequence to the rewritable non-volatile memory module 43 to erase data from the rewritable non-volatile memory module 43. The data processing circuit is used to process the data to be written into the rewritable non-volatile memory module 43 and the data read from the rewritable non-volatile memory module 43. The write instruction sequence, the read instruction sequence, and the erase instruction sequence can each include one or more codes or instruction codes and are used to instruct the rewritable non-volatile memory module 43 to perform corresponding write, read, and erase operations, etc. In an example embodiment, the memory management circuit 51 can also issue other types of instruction sequences to the rewritable non-volatile memory module 43 to instruct to perform corresponding operations.

[0057] The host interface 52 is coupled to the memory management circuit 51. The memory management circuit 51 can communicate with the host system 11 through the host interface 52. The host interface 52 can be used to receive and identify the instructions and data transmitted by the host system 11. For example, the instructions and data transmitted by the host system 11 can be transmitted to the memory management circuit 51 through the host interface 52. In addition, the memory management circuit 51 can transmit data to the host system 11 through the host interface 52. In the present example embodiment, the host interface 52 is compatible with the PCI Express standard. However, it must be understood that the present application is not limited thereto, and the host interface 52 can also be compatible with the SATA standard, the PATA standard, the IEEE 1394 standard, the USB standard, the SD standard, the UHS-I standard, the UHS-II standard, the MS standard, the MMC standard, the eMMC standard, the UFS standard, the CF standard, the IDE standard, or other suitable data transmission standards.

[0058] The memory interface 53 is coupled to the memory management circuit 51 and is used to access the rewritable non-volatile memory module 43. For example, the memory management circuit 51 can access the rewritable non-volatile memory module 43 through the memory interface 53. That is, data to be written to the rewritable non-volatile memory module 43 is converted into a format acceptable to the rewritable non-volatile memory module 43 via the memory interface 53. Specifically, if the memory management circuit 51 wants to access the rewritable non-volatile memory module 43, the memory interface 53 transmits a corresponding instruction sequence. For example, the instruction sequence can include a write instruction sequence indicating write data, a read instruction sequence indicating read data, an erase instruction sequence indicating erase data, and a corresponding instruction sequence to indicate various memory operations (e.g., change the read voltage level or perform a garbage collection operation, etc.). These instruction sequences are generated, for example, by the memory management circuit 51 and transmitted to the rewritable non-volatile memory module 43 through the memory interface 53. These instruction sequences can include one or more signals, or data on a bus. These signals or data can include instruction codes or codes. For example, in a read instruction sequence, the identification code of the read, the memory address, etc. information is included.

[0059] In an example embodiment, the memory control circuit unit 42 further includes an error checking and correction circuit 54, a buffer memory 55, and a power management circuit 56.

[0060] The error checking and correction circuit 54 is coupled to the memory management circuit 51 and is used to perform error checking and correction operations to ensure the correctness of data. Specifically, when the memory management circuit 51 receives a write instruction from the host system 11, the error checking and correction circuit 54 generates a corresponding error correcting code (ECC) and / or error detecting code (EDC) for the data corresponding to this write instruction, and the memory management circuit 51 writes the data corresponding to this write instruction and the corresponding error correcting code and / or error detecting code into the rewritable non-volatile memory module 43. Then, when the memory management circuit 51 reads data from the rewritable non-volatile memory module 43, the error correcting code and / or error detecting code corresponding to this data is also read, and the error checking and correction circuit 54 performs error checking and correction operations on the read data according to the error correcting code and / or error detecting code.

[0061] The buffer memory 55 is coupled to the memory management circuit 51 and is used to temporarily store data. The power management circuit 56 is coupled to the memory management circuit 51 and is used to control the power of the memory storage device 10.

[0062] In an example embodiment,Figure 4 The rewritable non-volatile memory module 43 can comprise a flash memory module. In an example embodiment, Figure 4 The memory control circuit unit 42 can comprise a flash memory controller. In an example embodiment, Figure 5 The memory management circuit 51 can comprise a flash memory management circuit.

[0063] The memory storage device 10 nowadays mostly uses a single open block as a unit to manage the storage space of the rewritable non-volatile memory module 43. However, this open block is single fixed, for example, is written based on a single-level cell (SLC) write mode, or is written based on a triple-level cell (TLC) write mode. The way of using a single open block as a unit to manage the storage space is difficult to cope with the requirement of continuous write operation, and thus affects the write speed.

[0064] In view of the above, the present application provides a memory management method, which can use multiple target physical units as a unit to manage the storage space of the rewritable non-volatile memory module 43, and timely switches the write mode of the continuous write operation in the process of performing the continuous write operation, so as to realize the write speed control in small data amount (i.e. the write data amount corresponding to the continuous write operation), to improve the stability of the write speed.

[0065] Figure 6 is a flowchart of a memory control method according to an example embodiment of the present application; Figure 7 is a schematic diagram of a first open pool and a second open pool according to an example embodiment of the present application. Please refer to Figure 6 to Figure 7 .

[0066] In step S601, the memory management circuit 51 can select multiple target physical units OB11-OB13, OB21 from multiple physical units. In an example embodiment, the target physical units OB11-OB13, OB21 are respectively, for example, a physical erase unit (for example, a physical block).

[0067] In an example embodiment, as shown in Figure 7As shown, the plurality of target entity units OB11-OB13, OB21 includes a first number (e.g., 3) of first target entity units OB11-OB13 and a second number (e.g., 1) of second target entity units OB21. The first target entity units OB11-OB13 correspond to a first write mode, e.g., the first target entity units OB11-OB13 can be written based on a single-level cell (SLC) write mode. The second target entity unit OB21 corresponds to a second write mode, e.g., the second target entity unit OB21 can be written based on a multi-level cell (MLC) write mode, a triple-level cell (TLC) write mode, or a quad-level cell (QLC) write mode. The first write mode is different from the second write mode. The first target entity units OB11-OB13 are associated with the first open pool P1. The second target entity unit OB21 is associated with the second open pool P2. That is, the memory management circuit 51 can manage the storage space of the rewritable non-volatile memory module 43 in units of 3 first target entity units OB11-OB13 and 1 second target entity unit OB21.

[0068] In step S602, the memory management circuit 51 can obtain the first write speed, the second write speed, and the target write speed corresponding to the continuous write operation.

[0069] In an example embodiment, the memory management circuit 51 can determine the first write speed, the second write speed, and the target write speed, e.g., according to historical write data, user usage habits, and / or performance of the memory storage device 10. Specifically, the first write speed is a write speed required to complete the continuous write operation in the first write mode (e.g., the SLC write mode), and the second write speed is a write speed required to complete the continuous write operation in the second write mode (e.g., the TLC write mode).

[0070] Further, the memory management circuit 51 can calculate an average write speed required to complete the continuous write operation using only a single target entity unit of the memory storage device 10, e.g., according to historical write data, user usage habits, and / or performance of the memory storage device 10. For example, the average write speed required to complete the continuous write operation using only a single target entity unit corresponding to the SLC write mode is the first write speed. For example, the average write speed required to complete the continuous write operation using only a single target entity unit corresponding to the TLC write mode is the second write speed. Accordingly, the memory management circuit 51 can set the target write speed required to complete the continuous write operation using a plurality of target entity units corresponding to different write modes according to the first write speed and the second write speed. Alternatively, the target write speed can also be designed by the user as needed, which is not limited by the present disclosure.

[0071] In step S603, the memory management circuit 51 can calculate the first ratio according to the target write speed, the first write speed and the second write speed.

[0072] In an example embodiment, since the write operations corresponding to different write modes have different write speeds, there is a problem of write speed instability when performing continuous write operations. In the process of performing continuous write operations, in order to achieve the effect of having the same write speed (i.e., the target write speed) in different write modes, the memory management circuit 51 can calculate the first ratio according to the first write speed, the second write speed and the target write speed as the basis for switching the operation mode. The first ratio can be obtained by formula (1) and formula (2).

[0073] Formula (1):

[0074]

[0075] Formula (2):

[0076]

[0077] Wherein, X represents the data amount (the capacity of the physical page) in the single-level cell (SLC) mode; Y represents the data amount (the capacity of the physical page) in the triple-level cell (TLC) mode.

[0078] In an example embodiment, in the process of performing continuous write operations, the memory management circuit 51 can first write the write data into the target physical unit OB21 based on the TLC write mode, and then switch the write mode to the SLC write mode after the memory management circuit 51 writes the write data with the data amount Y in the target physical unit OB21. After that, the write mode is switched to the TLC write mode after the memory management circuit 51 writes the write data with the data amount X in the target physical unit OB11 (or the target physical unit OB12, the target physical unit OB13), and so on until the continuous write operation is completed. In this way, the memory management circuit 51 can maintain the write speed of the continuous write operation at the target write speed by using multiple target physical units OB11-OB13 and OB21, so as to ensure the stability of the write speed.

[0079] For example, assume that the rewritable non-volatile memory module 43 is a Triple Level Cell (TLC) NAND flash memory module, and the rewritable non-volatile memory module 43 has 4 physical planes, and the rewritable non-volatile memory module 43 has 4000 physical pages. If the target write speed corresponding to the continuous write operation is 200 MB / s, the first write speed is 250 MB / s, and the second write speed is 100 MB / s, substituting the formula (1), formula (2) can be derived that the first ratio is 5. It should be noted that the minimum write unit of the TLC NAND flash memory is 3 physical pages. The 3 physical pages are the lower physical page, the middle physical page, and the upper physical page, and the capacity of a physical page may, for example, be 16 KB, so the minimum write amount is 16*3 = 48 KB. Since the rewritable non-volatile memory module 43 has 4 physical planes, the total write amount is 48*4 = 192 KB.

[0080] That is, in the process of performing the continuous write operation, the memory management circuit 51 can first write the write data into the first 3 physical pages in the target physical unit OB21 based on the TLC write mode, then switch to the SLC write mode to write the write data into the first 3*5 = 15 physical pages in the target physical unit OB11 (or the target physical unit OB12, the target physical unit OB13), then switch the write mode to the TLC write mode, and repeat the above process until the continuous write operation is completed, so as to maintain the write speed of the continuous write operation at the target write speed (i.e., 200 MB / s).

[0081] Further, in order to maintain the write speed of the continuous write operation above the target write speed (i.e., 200 MB / s), the memory management circuit 51 can switch to the TLC write mode to write 192 KB of data after writing 192*5 = 960 KB of data in the SLC write mode, and then switch back to the SLC write mode, and repeat the above process until the continuous write operation is completed. Accordingly, the data amount corresponding to one complete write cycle is 192+960 = 1152 KB. In other words, the data amount (chunk size) corresponding to one complete write cycle is approximately equal to 1 MB (i.e., 1024 KB). Therefore, the memory control method of the present application can achieve uniform and stable control of the write speed of the data amount corresponding to one complete write cycle at 200 MB / s.

[0082] If the write speed is controlled in the conventional manner based on the data amount of one physical unit (e.g., one open block), the write speed will fluctuate greatly due to the switching between different modes of the physical erase unit.

[0083] It is noted that in the conventional 2D NAND flash memory, one physical block includes, for example, 32 to 128 physical pages, each of which has a capacity of, for example, 4096B to 8192B. In comparison with the 3D NAND flash memory, the size (capacity) of a physical block can be different due to the different structure. Specifically, the capacity of one physical block of the 3D NAND flash memory can reach 16MB. Accordingly, the capacity of one physical block in either the 2D NAND flash memory or the 3D NAND flash memory is greater than the data amount (chunk size, i.e., 1MB) of one complete write cycle.

[0084] According to the above, the manner of controlling the write speed in units of chunk size provided by the example embodiments of the present application helps to improve the write efficiency and reduce the write amplification. Meanwhile, the manner of controlling the write speed at the target write speed (200MB / s) to alternately write data to the first target physical unit and the second target physical unit helps to balance the write load, thereby improving the performance of the memory storage device 10. In addition, the manner of alternately writing data to the first target physical unit and the second target physical unit also helps to achieve a more uniform wear distribution, avoiding excessive wear of a specific physical unit, thereby improving the reliability and durability of the memory storage device 10.

[0085] In step S604, the memory management circuit 51 can obtain the first data amount of the first target physical units OB11 to OB13 and the second data amount of the second target physical unit OB21 when performing the first write operation of the continuous write operation.

[0086] In an example embodiment, the memory management circuit 51 sequentially performs multiple write operations in the process of performing the continuous write operation. In other words, the continuous write operation includes multiple write operations. When the memory management circuit 51 performs the first write operation (i.e., the current write operation) of the continuous write operation, the memory management circuit 51 can determine the write mode of the next write operation (i.e., the second write operation) according to the switching condition (i.e., the first ratio described above) so that the write speed of the continuous write operation is maintained at the target write speed.

[0087] Assume that the first write operation is the first pen write operation in the continuous write operation. During the first pen write operation, the memory management circuit 51 can first write the write data corresponding to the first pen write operation in the continuous write operation into the first three physical pages of the target physical unit OB21 based on the TLC write mode, and obtain a first data amount of the first target physical unit OB11-OB13 and a second data amount of the second target physical unit OB21. The first data amount is the written data amount of the first target physical unit OB11-OB13, and the second data amount is the written data amount of the second target physical unit OB21. At this time, the first data amount of the first target physical unit OB11-OB13 is the capacity of 0 physical pages, and the second data amount of the second target physical unit OB21 is the capacity of 3 physical pages.

[0088] In step S605, the memory management circuit 51 can calculate the second ratio according to the first data amount and the second data amount.

[0089] In an example embodiment, the second ratio can be, for example, the ratio of the first data amount to the second data amount. For example, during the first pen write operation described above, the second ratio is the ratio of the capacity of 0 physical pages to the capacity of 3 physical pages, i.e., 0.

[0090] In step S606, the memory management circuit 51 can determine the write mode of the second write operation according to the first ratio and the second ratio.

[0091] In an example embodiment, assume that the first ratio is 1. Since the memory management circuit 51 needs to write the write data into the target physical units OB11-OB13, OB21 according to the first ratio to maintain the stability of the write speed during the execution of the continuous write operation. Therefore, after writing the write data into the three physical pages of the target physical unit OB21 in the TLC write mode, the memory management circuit 51 needs to write the write data into the three physical pages of the target physical unit OB11-OB13 in the SLC write mode, and then switch back to the TLC write mode, and repeat this process until the continuous write operation is completed. Accordingly, during the execution of the continuous write operation, the memory management circuit 51 can determine the write mode of the second write operation by comparing the size of the second ratio and the first ratio.

[0092] Specifically, the second ratio is a ratio of the amount of data written in the target physical units OB 11 to OB 13 to the amount of data written in the target physical unit OB 21. If the second ratio corresponding to the current write operation is smaller than the first ratio, it means that the next write operation needs to be performed based on the SLC write mode to maintain the stability of the write speed. In contrast, if the second ratio corresponding to the current write operation is not smaller than the first ratio, it means that the next write operation needs to be performed based on the TLC write mode to maintain the stability of the write speed.

[0093] During the first write operation described above, the second ratio is 0. Since the second ratio is smaller than the first ratio (i.e., 1), the memory management circuit 51 performs the next write operation (i.e., the second write operation in the continuous write operation) in the SLC write mode.

[0094] According to the above, during the execution of a write operation (i.e., the current write operation) in the continuous write operation, the memory management circuit 51 can determine the write mode of the next write operation according to the first ratio derived from the target write speed and the second ratio reflecting the data written in the target physical units OB 11 to OB 13 and OB 21, to timely switch the write mode of the continuous write operation during the execution of the continuous write operation, to achieve the write speed control in small data amount and improve the stability of the write speed.

[0095] On the other hand, since the present application uses a plurality of target physical units OB 11 to OB 13 and OB 21 corresponding to different write modes to store the write data of the continuous write operation. That is, the present application uses the plurality of target physical units OB 11 to OB 13 and OB 21 as a unit to manage the storage space of the rewritable non-volatile memory module 43. For this purpose, the memory management circuit 51 needs to establish mapping information and / or a record table to manage the target physical units OB 11 to OB 13 and OB 21.

[0096] Figure 8 is a schematic diagram of logical-to-physical information according to an example embodiment of the present application. Please refer to Figure 8 In an example embodiment, the memory management circuit 51 can establish respective logical-to-physical information T 11 to T 13 and T 21 for the target physical units OB 11 to OB 13 and OB 21. That is, the target physical units OB 11 to OB 13 and OB 21 respectively have respective logical-to-physical information T 11 to T 13 and T 21. In detail, the logical-to-physical information T 11 to T 13 and T 21 respectively record the write-in order of the target physical units OB 11 to OB 13 and OB 21 and the mapping relationship between the physical addresses and the logical addresses of the target physical units OB 11 to OB 13 and OB 21.

[0097] As shown in FIG. 1 1, the memory storage device 10 has 4 physical planes plO~pl3, the target physical unit OB 1 1 ~OB 13 each has 1000 physical pages, and the target physical unit OB 21 each has 3000 physical pages. The numbers in the logical-to-physical information T 1 1 ~T 13, T 21 represent the write-in order of the physical pages in the target physical unit OB 1 1 ~OB 13 during the continuous write-in operation. In other words, the smaller the number, the older the data stored in the corresponding physical page. Figure 8 In an example embodiment, the first ratio is 1. During the execution of the continuous write-in operation, the memory management circuit 51 can first write the write-in data corresponding to the first write-in operation in the continuous write-in operation into the physical pages pO~p2 of the target physical unit OB 21 based on the TLC write-in mode, record the mapping relationship between the physical addresses of the physical pages pO~p2 of the target physical unit OB 21 and their corresponding logical addresses in the logical-to-physical information T 21, and mark the physical pages pO~p2 as number 0 in the logical-to-physical information T 21.

[0098] Next, the memory management circuit 51 can switch to the SLC write-in mode to sequentially write the write-in data corresponding to the second write-in operation in the continuous write-in operation into the physical page pO of the target physical unit OB 1 1, the write-in data corresponding to the third write-in operation in the continuous write-in operation into the physical page p 1 of the target physical unit OB 1 1, and the write-in data corresponding to the fourth write-in operation in the continuous write-in operation into the physical page p2 of the target physical unit OB 1 1.

[0099] At this time, the memory management circuit 51 can record the mapping relationship between the physical addresses of the physical pages pO~p2 of the target physical unit OB 1 1 and their corresponding logical addresses in the logical-to-physical information T 1 1, and mark the physical pages pO~p2 as number 1 in the logical-to-physical information T 1 1.

[0100] It is to be noted that although the physical pages pO~p2 of the target physical unit OB 1 1 store the write-in data corresponding to the second to fourth write-in operations in the continuous write-in operation, the three write-in operations are sequentially written into the target physical unit OB 1 1 based on the same write-in mode, so the memory management circuit 51 regards the write-in order of the three write-in operations as the same, and marks the physical pages pO~p2 as number 1 in the logical-to-physical information T 1 1.

[0101]

[0102] ​Afterwards, the memory management circuit 51 can switch back to the TLC write mode, and write the write data corresponding to the fifth write operation in the continuous write operation into the physical pages p3-p5 of the target physical unit OB21, and record the mapping relationship between the physical addresses of the physical pages p3-p5 of the target physical unit OB21 and their corresponding logical addresses in the logical-to-physical information T21, and mark the physical pages p3-p5 as number 2 in the logical-to-physical information T21, and repeat the above process until the continuous write operation is completed.

[0103] It should be noted that in the above process of performing the continuous write operation, the memory management circuit 51 can determine the timing of switching the write mode according to the method of Figure 6 , and thus is not described herein.

[0104] In an example embodiment, since the memory management circuit 51 can record the write order of the physical pages in the target physical units OB11-OB13, OB21 in the logical-to-physical information T11-T13, T21. Therefore, when multiple (two or more) physical addresses of the physical pages in the target physical units OB11-OB13, OB21 are mapped to the same logical address, the memory management circuit 51 can query the storage location of the latest data corresponding to the logical address according to the write order in the logical-to-physical information T11-T13, T21. That is, the memory management circuit 51 can query the latest physical address from the multiple physical addresses mapped to the same logical address in the logical-to-physical information T11-T13, T21.

[0105] It should be noted that in actual application scenarios, when the target physical unit OB21 corresponding to the TLC write mode is full, the last target physical unit OB13 corresponding to the SLC write mode can not be full. Since the information stored in the logical-to-physical information T11-T13, T21 reflects the actual situation of performing the continuous write operation according to the first ratio, in order to ensure the correctness of the write order in the logical-to-physical information T11-T13, T21, after the target physical unit OB21 is full, the target physical units OB11-OB13 will no longer be used to store data.

[0106] Figure 9 is a schematic diagram of the first switching schedule and the second switching schedule according to an example embodiment of the present application. Please refer to Figure 9 .

[0107] In addition to the above-described way of managing the target physical units OB11-OB13, OB21 using the logical-to-physical information T11-T13, T21, the present application also provides a way of managing the target physical units OB11-OB13, OB21 using the logical-to-physical information T11-T13, T21 and the logical-to-physical information T31-T33, as shown in Figure 9The first and second switch schedules TS1, TS2 are used to manage the target physical units OB11-OB13, OB21.

[0108] In an example embodiment, the memory management circuit 51 can establish the first and second switch schedules TS1, TS2 during execution of a continuous write operation.

[0109] In particular, the switch schedule TS1 is used to record the physical address corresponding to the latest data stored in the target physical unit OB21 when switching from the second write mode (e.g., TLC write mode) to the first write mode (e.g., SLC write mode). Similarly, the switch schedule TS2 is used to record the physical address corresponding to the latest data stored in the target physical units OB11-OB13 when switching from the SLC write mode to the TLC write mode.

[0110] During execution of a continuous write operation, the memory management circuit 51 can first write the write data into the target physical unit OB21 based on the TLC write mode, then switch the write mode to write the write data into the target physical units OB11-OB13 based on the SLC write mode, and then switch back to the TLC write mode to write the write data into the target physical unit OB21, and so on until the continuous write operation is completed. At each time of switching the write mode, the memory management circuit 51 can record the physical address corresponding to the latest data stored in the target physical unit OB21 (or the target physical units OB11-OB13) in the switch schedule TS1 (or the switch schedule TS2).

[0111] As shown, the timestamps ts-0-ts-11 in the switch schedules TS1, TS2 can be used to represent the switching sequence of the write modes. The timestamp ts-0 represents the first time of switching the write mode, the timestamp ts-1 represents the second time of switching the write mode, and so on. Figure 9

[0112] ​In the process of performing the continuous write operation, when the memory management circuit 51 switches the write mode for the first time (e.g., from the TLC write mode to the SLC write mode), the memory management circuit 51 can record in the switching time table TS1 a time stamp ts-0 and a physical address PCA-0 corresponding to the latest data stored in the target physical unit OB21. Next, when the memory management circuit 51 switches the write mode again (i.e., from the SLC write mode back to the TLC write mode), the memory management circuit 51 can record in the switching time table TS2 a time stamp ts-1 and a physical address PCA-1 corresponding to the latest data stored in the target physical units OB11-OB13. Then, when the memory management circuit 51 switches the write mode again (i.e., from the TLC write mode to the SLC write mode), the memory management circuit 51 can record in the switching time table TS1 a time stamp ts-2 and a physical address PCA-2 corresponding to the latest data stored in the target physical unit OB21. The other contents in the switching time tables TS1, TS2 can be similarly deduced.

[0113] In an example embodiment, when a plurality of physical addresses of a plurality of physical pages in the target physical units OB11-OB13, OB21 are mapped to the same logical address, the memory management circuit 51 can first query the plurality of physical addresses corresponding to the logical address from the logical-to-physical information T11-T13, T21. Then, the memory management circuit 51 can query a plurality of time stamps corresponding to the plurality of physical addresses from the switching time tables TS1, TS2, and determine the order of the plurality of time stamps to determine the latest physical address among the plurality of physical addresses.

[0114] In general, the switching time tables TS1, TS2 can be used to represent the order in which the target physical units OB11-OB13, OB21 are written with data. Thus, when a plurality of physical addresses of a plurality of physical pages in the target physical units OB11-OB13, OB21 are mapped to the same logical address, the memory management circuit 51 can query the storage location of the latest data corresponding to the logical address according to the time stamps in the switching time tables TS1, TS2.

[0115] In this way, the order of writing recorded in the logical-to-physical information T11-T13, T21 can no longer be relied upon to determine the age of data. Thus, when both the logical-to-physical information T11-T13, T21 and the switching time tables TS1, TS2 are used, when the target physical unit OB21 is full, the target physical units OB11-OB13 that are not full (e.g., the target physical unit OB13) can continue to be used to store data.

[0116] In an example embodiment, during the execution of the continuous write operation, if the target physical unit (e.g., target physical unit OB13) that is not yet full is not written with data after a preset time period, the target physical unit OB13 no longer continues to store data. The preset time period can be designed by the user as needed, and the present application does not impose any limitation. Accordingly, the example embodiment of the present application can achieve that when the target physical unit OB21 is full, the remaining target physical units (e.g., target physical unit OB13) that are not yet full are continued to be used, so as to improve the usage rate of the rewritable non-volatile memory module 43, and to avoid the problem that the target physical unit OB13 is not closed for a long time without being used based on the preset time period.

[0117] Figure 10 is a flowchart of a memory management method according to an example embodiment of the present application. Please refer to Figure 10 In step S1001, a plurality of target physical units are selected from a plurality of physical units, wherein the plurality of target physical units include a first number of first target physical units and a second number of second target physical units. In step S1002, when a first write operation in a continuous write operation is executed, a write mode of a second write operation is determined according to a switching condition, wherein the second write operation is a next write operation of the first write operation, the write mode includes a first write mode and a second write mode, the first target physical units correspond to the first write mode, the second target physical units correspond to the second write mode, and the first write mode is different from the second write mode.

[0118] However, Figure 10 The steps in the above method have been described in detail, and thus will not be repeated here. It is worth noting that, Figure 10 The steps in the above method can be implemented as a plurality of program codes or circuits, and the present application does not impose any limitation. In addition, Figure 10 The method of the above embodiment can be used in combination with the above embodiment, or can be used alone, and the present application does not impose any limitation.

[0119] In summary, the memory control method and the memory storage device according to the example embodiment of the present application can manage the storage space of the rewritable non-volatile memory module by using a plurality of target physical units as a unit, and can timely switch the write mode of the continuous write operation during the execution of the continuous write operation, so as to achieve the write speed control in a small data amount, and to improve the smoothness of the write speed.

[0120] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, and are not intended to limit the present application; although the present application has been described in detail with reference to the above embodiments, those skilled in the art should understand that the technical solutions recorded in the above embodiments can be modified, or some or all of the technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A memory control method, characterized in that, For a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes multiple physical units, and the memory control method includes: Multiple target entity units are selected from the plurality of entity units, wherein the plurality of target entity units includes a first number of first target entity units and a second number of second target entity units; When performing the first write operation in a continuous write operation, a first write speed, a second write speed, and a target write speed corresponding to the continuous write operation are obtained, wherein the first write speed and the second write speed correspond to the first write mode and the second write mode, respectively. Calculate the first ratio based on the target write speed, the first write speed, and the second write speed; Obtain the first data volume of the first target entity unit and the second data volume of the second target entity unit; Calculate the second ratio based on the first data volume and the second data volume; and The write mode of the second write operation is determined based on the first ratio and the second ratio, wherein the second write operation is the next write operation after the first write operation, and the write mode is either the first write mode or the second write mode.

2. The memory control method according to claim 1, wherein the first write speed is the write speed required to complete the continuous write operation in the first write mode, and the second write speed is the write speed required to complete the continuous write operation in the second write mode.

3. The memory control method according to claim 1, wherein the first data amount is the amount of data written to the first target entity unit, and the second data amount is the amount of data written to the second target entity unit.

4. The memory control method according to claim 1, wherein the plurality of target entity units each have a plurality of logic-to-entity information, and the plurality of logic-to-entity information are respectively used to record the writing order of the plurality of target entity units and the mapping relationship between the entity address and the logical address of the plurality of target entity units.

5. The memory control method according to claim 4, wherein after the second target entity unit is filled, the first target entity unit is no longer used to store data.

6. The memory control method according to claim 5 further includes: If a logical address is mapped to multiple entity addresses of the multiple target entity units, the latest entity address among the multiple entity addresses is queried according to the writing order of the multiple target entity units in the multiple logical-to-entity information.

7. The memory control method according to claim 4, further comprising: During the execution of the continuous write operation, a first switching schedule and a second switching schedule are established, wherein... The first switching timetable is used to record the entity address and timestamp corresponding to the latest data stored in the second target entity unit when switching from the second write mode to the first write mode, and The second switching timetable is used to record the entity address and timestamp corresponding to the latest data stored in the first target entity unit when switching from the first write mode to the second write mode.

8. The memory control method according to claim 7, further comprising: If a logical address is mapped to multiple entity addresses of the multiple target entity units, query the multiple entity addresses from the multiple logical-to-entity information; Query multiple timestamps corresponding to the multiple entity addresses from at least one of the first switching schedule and the second switching schedule; as well as The latest entity address among the multiple entity addresses is determined based on the multiple timestamps.

9. A memory storage device, characterized in that, include: A connection interface unit for coupling to the host system; A rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes multiple physical units; as well as The memory control circuit unit is coupled to the connection interface unit and the rewritable non-volatile memory module. The memory control circuit unit is used to: Multiple target entity units are selected from the plurality of entity units, wherein the plurality of target entity units includes a first number of first target entity units and a second number of second target entity units; When performing the first write operation in a continuous write operation, a first write speed, a second write speed, and a target write speed corresponding to the continuous write operation are obtained, wherein the first write speed and the second write speed correspond to the first write mode and the second write mode, respectively. Calculate the first ratio based on the target write speed, the first write speed, and the second write speed; Obtain the first data volume of the first target entity unit and the second data volume of the second target entity unit; Calculate the second ratio based on the first data volume and the second data volume; as well as The write mode of the second write operation is determined based on the first ratio and the second ratio, wherein the second write operation is the next write operation after the first write operation, and the write mode is either the first write mode or the second write mode.

10. The memory storage device according to claim 9, wherein the first write speed is the write speed required to complete the continuous write operation in the first write mode, and the second write speed is the write speed required to complete the continuous write operation in the second write mode.

11. The memory storage device according to claim 9, wherein the first data amount is the amount of data written to the first target entity unit, and the second data amount is the amount of data written to the second target entity unit.

12. The memory storage device according to claim 9, wherein the plurality of target entity units each have a plurality of logical-to-entity information, and the plurality of logical-to-entity information are respectively used to record the writing order of the plurality of target entity units and the mapping relationship between the entity address and logical address of the plurality of target entity units.

13. The memory storage device according to claim 12, wherein after the second target entity unit is filled, the first target entity unit is no longer used to store data.

14. The memory storage device according to claim 13, wherein the memory control circuit unit is further configured to: If a logical address is mapped to multiple entity addresses of the multiple target entity units, the latest entity address among the multiple entity addresses is queried according to the writing order of the multiple target entity units in the multiple logical-to-entity information.

15. The memory storage device according to claim 12, wherein the memory control circuit unit is further configured to: During the execution of the continuous write operation, a first switching schedule and a second switching schedule are established, wherein... The first switching timetable is used to record the entity address and timestamp corresponding to the latest data stored in the second target entity unit when switching from the second write mode to the first write mode, and The second switching timetable is used to record the entity address and timestamp corresponding to the latest data stored in the first target entity unit when switching from the first write mode to the second write mode.

16. The memory storage device according to claim 15, wherein the memory control circuit unit is further configured to: If a logical address is mapped to multiple entity addresses of the multiple target entity units, query the multiple entity addresses from the multiple logical-to-entity information; Query multiple timestamps corresponding to the multiple entity addresses from at least one of the first switching schedule and the second switching schedule; and The latest entity address among the multiple entity addresses is determined based on the multiple timestamps.

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