Virtual prototype platform branch prediction method and device, equipment and medium

Abstract

The invention relates to a virtual prototype platform branch prediction method and device, equipment and a medium, and the method comprises the steps: calling a preset scoring strategy, and predicting the jump direction of a current branch instruction by a branch jump direction predictor in a branch prediction model according to a memory address corresponding to the current branch instruction; if the current branch instruction is in a skipping state, a branch skipping address predictor in the branch prediction model predicts a to-be-skipped program counter address corresponding to the current branch instruction according to a memory address corresponding to the current branch instruction by adopting a preset scoring strategy; if the current branch instruction is in a non-jump state, the branch jump address predictor determines a program counter address of a next instruction of the current branch instruction according to a memory address corresponding to the current branch instruction so as to complete branch prediction of the virtual prototype platform; according to the method, the coverage degree of branch prediction is remarkably improved, so that the function verification of the virtual prototype platform is more comprehensive.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a virtual prototype platform branch prediction method, a corresponding device, an electronic device and a computer-readable storage medium. Background Art

[0002] In the context of the rapid development of modern computing technology, the complexity of CPU design is increasing day by day, and the market's requirements for product launch speed are also getting higher and higher. Driven by Gordon Moore's prediction of technological progress, the integration of CPUs is constantly improving, and performance requirements are also rising. In order to remain competitive in the fierce market competition, the design and development cycle of CPUs needs to be greatly shortened, while ensuring the high performance and high reliability of products. The traditional design process of hardware first and software later can no longer meet the needs of rapid iteration. Therefore, the electronic system level (ESL) design method has become a key technology to solve this problem. By building a virtual prototype in the early stages of the design process, the design team can achieve collaborative development of hardware and software. This method not only speeds up the design cycle of the CPU, but also allows more comprehensive testing and verification in the early stages of the design, greatly improving the efficiency of the design and the quality of the product. Therefore, virtual prototyping technology plays a vital role in the field of CPU design. It allows designers to discover and solve potential problems before the actual manufacturing of the product, effectively promoting the rapid development and innovation of CPU technology.

[0003] Branch prediction has been studied for decades, mainly focusing on predicting the direction of conditional branches, because this aspect usually represents the main source of mispredictions. It is a basic means to ensure the smooth execution of the processor instruction flow, efficiency and performance optimization. By flexibly using data such as PC values ​​and historical information, a series of branch prediction algorithms have been developed to prevent processor pipeline stalls caused by branch prediction errors. For high-accuracy branch predictors, the TAGE branch predictor is one of the most important branch prediction algorithms, named because it uses the geometric length of historical tags for branch prediction. Because it has higher prediction accuracy and more balanced resource consumption, it is often used for processor branch prediction optimization. The TAGE-SC-L branch prediction model is such an algorithm extended based on the TAGE branch prediction technology. It is an advanced branch prediction technology currently used in CPU design and was proposed by André Seznec in 2011. However, the verification of such high-accuracy branch prediction algorithms is mainly limited to fast algorithm evaluation in simulators or verification on actual processors. Such models have not yet been fully functionally verified in virtual prototyping (VP) platforms at the electronic system level (ESL).

[0004] In summary, the TAGE-SC-L branch prediction model in the prior art has not yet been fully functionally verified on the virtual prototype (VP) platform at the electronic system level (ESL). The applicant has made corresponding explorations to solve this problem. Summary of the invention

[0005] The purpose of the present application is to solve the above-mentioned problems and to provide a virtual prototype platform branch prediction method, a corresponding device, an electronic device and a computer-readable storage medium.

[0006] In order to meet the various objectives of this application, this application adopts the following technical solutions:

[0007] A virtual prototype platform branch prediction method proposed to meet one of the purposes of this application includes:

[0008] In response to the branch prediction instruction of the virtual prototype platform, the instruction simulator in the CPU core structure is triggered to send the memory address corresponding to the current branch instruction to the preset branch prediction model in the decoding stage;

[0009] Calling a preset scoring strategy, the branch jump direction predictor in the branch prediction model predicts the jump direction of the current branch instruction according to the memory address corresponding to the current branch instruction, wherein the jump direction includes a first jump direction and a second jump direction, the first jump direction indicates that the current branch instruction is in a jump state, and the second jump direction indicates that the current branch instruction is in a non-jump state;

[0010] If the current branch instruction is in a jump state, the branch jump address predictor in the branch prediction model adopts a preset scoring strategy to predict the address of the to-be-jumped program counter corresponding to the current branch instruction according to the memory address corresponding to the current branch instruction;

[0011] If the current branch instruction is in a non-jump state, the branch jump address predictor determines the program counter address of the next instruction of the current branch instruction according to the memory address corresponding to the current branch instruction;

[0012] The actual jump result of the current branch instruction is determined in the CPU core structure, and the actual jump result is sent to the branch jump direction predictor in the branch prediction model to update the branch prediction model to complete the branch prediction of the virtual prototype platform.

[0013] Optionally, the basic network architecture of the branch prediction model is an improved TAGE-SC-L branch prediction model, and the improved TAGE-SC-L branch prediction model is constructed by a TAGE-SC-L branch predictor that introduces a scoring strategy and a perceptron.

[0014] Optionally, after the step of triggering the instruction simulator in the CPU core structure to send the memory address corresponding to the current branch instruction to the preset branch prediction model, the method further includes:

[0015] Calling a preset scoring strategy to initialize initial scoring variables corresponding to the main predictor, the statistical correction predictor, and the cyclic predictor;

[0016] If the prediction result corresponding to any branch predictor matches its corresponding actual result, its corresponding prediction score increases by 1; if the prediction result of any branch predictor does not match its actual result, its corresponding prediction score is set to 0;

[0017] Compare the first prediction score corresponding to the main predictor, the second prediction score corresponding to the statistical correction predictor, and the third prediction score corresponding to the loop predictor. If the third prediction score corresponding to the loop predictor is greater than the first prediction score corresponding to the main predictor and the second prediction score corresponding to the statistical correction predictor, take the third prediction result corresponding to the loop predictor as the final prediction result.

[0018] Optionally, after comparing the first prediction score corresponding to the main predictor, the second prediction score corresponding to the statistical correction predictor, and the third prediction score corresponding to the cycle predictor, if the third prediction score corresponding to the cycle predictor is greater than the first prediction score corresponding to the main predictor and the second prediction score corresponding to the statistical correction predictor, then taking the third prediction result corresponding to the cycle predictor as the final prediction result, the method further comprises:

[0019] If the second prediction score corresponding to the statistically corrected predictor is greater than the first prediction score corresponding to the main predictor, the second prediction result corresponding to the statistically corrected predictor is used as the final prediction result; otherwise, the first prediction result corresponding to the main predictor is selected as the final prediction result;

[0020] If the first condition flag corresponding to the statistical correction predictor is not equal to 1, the determination includes: if the second condition flag corresponding to the loop predictor is equal to 1, selecting the third prediction result corresponding to the loop predictor as the final prediction result; otherwise, selecting the first prediction result corresponding to the main predictor as the final prediction result;

[0021] If the first condition flag corresponding to the statistical correction predictor is equal to 1, directly selecting the optimal branch predictor selected based on the preset scoring strategy;

[0022] The above steps are executed in a loop, and the prediction result of the branch predictor finally selected is returned.

[0023] Optionally, the master predictor includes a base table and a plurality of tag tables, wherein the base table is indexed by a program counter address, and the tag table is indexed by a hash operation of history information of a variable geometric history length and a program counter address to index a prediction result, and if no tag table hits, the prediction result of the base table is selected;

[0024] Otherwise, the prediction result of the tag table with the longest history length is selected from all the hit tag tables as the final prediction direction.

[0025] Optionally, the CPU core structure includes a four-stage pipeline of instruction fetch, decoding, execution and write-back.

[0026] Optionally, in the decoding stage, the get_prediction() function in the branch jump direction predictor in the branch prediction model is called to predict the jump direction of the current branch instruction according to the memory address corresponding to the current branch instruction;

[0027] In the execution phase, the preset update_predictor() function is called to send the actual jump result to the branch jump direction predictor in the branch prediction model.

[0028] A virtual prototype platform branch prediction device provided for another purpose of the present application includes:

[0029] A memory address sending module is configured to respond to a branch prediction instruction of a virtual prototype platform, triggering an instruction simulator in a CPU core structure to send a memory address corresponding to a current branch instruction to a preset branch prediction model during a decoding phase;

[0030] A jump direction prediction module, configured to call a preset scoring strategy, wherein a branch jump direction predictor in the branch prediction model predicts a jump direction of the current branch instruction according to a memory address corresponding to the current branch instruction, wherein the jump direction includes a first jump direction and a second jump direction, wherein the first jump direction indicates that the current branch instruction is in a jump state, and the second jump direction indicates that the current branch instruction is in a non-jump state;

[0031] The to-be-jumped address prediction module is configured to, if the current branch instruction is in a jump state, predict the to-be-jumped program counter address corresponding to the current branch instruction by using a preset scoring strategy based on the memory address corresponding to the current branch instruction;

[0032] a program counter address determination module, configured to determine, if the current branch instruction is in a non-jump state, the branch jump address predictor to determine the program counter address of the next instruction of the current branch instruction according to the memory address corresponding to the current branch instruction;

[0033] A branch prediction model update module is configured to determine an actual jump result of the current branch instruction in the CPU core structure, and send the actual jump result to a branch jump direction predictor in the branch prediction model to update the branch prediction model to complete the branch prediction of the virtual prototype platform.

[0034] An electronic device provided to meet another purpose of the present application includes a central processing unit and a memory, wherein the central processing unit is used to call and run a computer program stored in the memory to execute the steps of the virtual prototype platform branch prediction method described in the present application.

[0035] A computer-readable storage medium is provided to meet another purpose of the present application, which stores a computer program implemented according to the virtual prototype platform branch prediction method in the form of computer-readable instructions. When the computer program is called and executed by a computer, the steps included in the corresponding method are executed.

[0036] Compared with the prior art, the present application aims at the problem that the TAGE-SC-L branch prediction model in the prior art has not been fully functionally verified on the virtual prototype (VP) platform at the electronic system level (ESL). The present applicant has made corresponding explorations to solve the problem. The present application includes but is not limited to the following beneficial effects:

[0037] First, this application defines an improved branch prediction model based on a virtual prototype platform architecture, which has more comprehensive functional verification. This technology introduces a branch prediction model based on a virtual prototype, which can more comprehensively test and evaluate the functions of the branch prediction algorithm through simulation and verification during the design phase. The virtual prototype can provide more verification and optimization opportunities for various branch prediction scenarios, thereby ensuring that the final prediction model is more accurate and reliable.

[0038] Second, this application uses a higher level of abstraction hardware description language SystemC to design the branch prediction algorithm module, which has a faster simulation speed. Using a higher level of abstraction hardware description language for design makes the simulation of the branch prediction algorithm module more efficient. The SystemC language supports hardware-level parallelization and abstract modeling. Compared with traditional low-level languages, it can simulate faster, reduce the design and verification cycle, and improve development efficiency.

[0039] Third, this application adopts a new scoring strategy to design the TAGE-SC-LS model with higher prediction accuracy. By introducing a new scoring strategy to design the TAGE-SC-LS model, the accuracy of branch prediction is significantly improved. The scoring strategy can allocate scores to different historical patterns, making the TAGE model more accurate in capturing complex branch patterns.

[0040] Fourthly, this application integrates the perceptron by introducing the TAGE-SC-L branch predictor with a scoring strategy and designs the TAGE-SC-LP model with higher prediction coverage. By integrating the scoring strategy with the perceptron, the design of the TAGE-SC-LP model is further optimized, and the coverage of branch prediction is significantly improved. The perceptron is an algorithm based on machine learning, which can adjust the prediction strategy through dynamic learning, so that the model can cover more types of branch patterns, enhancing the adaptability and generalization ability of the model. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0042] Figure 1 A schematic diagram of the flow of a virtual prototype platform branch prediction method in an embodiment of the present application;

[0043] Figure 2 An exemplary architecture of an improved branch prediction model based on a virtual prototype platform in an embodiment of the present application;

[0044] Figure 3 This is an exemplary structure of the main predictor in the embodiment of the present application;

[0045] Figure 4 is an exemplary structure of the original TAGE-SC-L branch prediction model in the embodiments of the present application;

[0046] Figure 5 This is a principle block diagram of a virtual prototype platform branch prediction device in an embodiment of the present application;

[0047] Figure 6 It is a schematic diagram of the structure of the computer device in the embodiment of the present application. DETAILED DESCRIPTION

[0048] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be interpreted as limiting the present application.

[0049] It will be understood by those skilled in the art that, unless expressly stated, the singular forms "one", "said", and "the" used herein may also include plural forms. It should be further understood that the term "comprising" used in the specification of the present application refers to the presence of the features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof. It should be understood that when we refer to an element as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be intermediate elements. In addition, the "connection" or "coupling" used herein may include wireless connection or wireless coupling. The term "and / or" used herein includes all or any unit and all combinations of one or more associated listed items.

[0050] It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those generally understood by those skilled in the art to which this application belongs. It should also be understood that terms such as those defined in general dictionaries should be understood to have meanings consistent with the meanings in the context of the prior art, and will not be interpreted with idealized or overly formal meanings unless specifically defined as here.

[0051] It will be understood by those skilled in the art that the "client", "terminal" and "terminal device" used herein include both devices with wireless signal receivers, which are devices with only wireless signal receivers without transmission capabilities, and devices with receiving and transmitting hardware, which are devices with receiving and transmitting hardware capable of two-way communication on a two-way communication link. Such devices may include: cellular or other communication devices such as personal computers, tablet computers, which have single-line displays or multi-line displays or cellular or other communication devices without multi-line displays; PCS (Personal Communications Service, personal communication system), which can combine voice, data processing, fax and / or data communication capabilities; PDA (Personal Digital Assistant, personal digital assistant), which may include a radio frequency receiver, pager, Internet / intranet access, web browser, notepad, calendar and / or GPS (Global Positioning System, global positioning system) receiver; conventional laptop and / or palmtop computers or other devices, which have and / or include a conventional laptop and / or palmtop computer or other device with and / or including a radio frequency receiver. The "client", "terminal" and "terminal device" used herein may be portable, transportable, installed in a vehicle (air, sea and / or land), or suitable for and / or configured to run locally, and / or in a distributed form, at any other location on the earth and / or in space. The "client", "terminal" and "terminal device" used herein may also be a communication terminal, an Internet terminal, a music / video playing terminal, for example, a PDA, a MID (Mobile Internet Device) and / or a mobile phone with a music / video playing function, or a smart TV, a set-top box and other devices.

[0052] The hardware referred to by the names such as "server", "client", and "service node" in this application is essentially an electronic device with the equivalent capabilities of a personal computer. It is a hardware device with the necessary components revealed by the von Neumann principle, such as a central processing unit (including an arithmetic unit and a controller), a memory, an input device, and an output device. The computer program is stored in its memory, and the central processing unit calls the program stored in the external memory into the internal memory for execution, executes the instructions in the program, and interacts with the input and output devices to complete specific functions.

[0053] It should be pointed out that the concept of "server" referred to in this application can also be extended to the case of server clusters. According to the network deployment principle understood by those skilled in the art, the servers should be logically divided. In physical space, these servers can be independent of each other but can be called through interfaces, or integrated into a physical computer or a set of computer clusters. Those skilled in the art should understand this flexibility, and should not use it to restrict the implementation of the network deployment method of this application.

[0054] Unless expressly specified, one or more technical features of the present application can be deployed on a server for implementation and accessed by a client through a remote call to obtain an online service interface provided by the server, or can be directly deployed and run on a client for access.

[0055] The neural network models referenced or may be referenced in this application, unless expressly specified, can be deployed on a remote server and remotely called on the client, or can be deployed and directly called on a client with sufficient device capabilities. In some embodiments, when it runs on the client, its corresponding intelligence can be obtained through transfer learning to reduce the requirements for the client's hardware operating resources and avoid excessive occupation of the client's hardware operating resources.

[0056] Unless explicitly specified, the various data involved in this application can be stored remotely on a server or on a local terminal device, as long as it is suitable for being called by the technical solution of this application.

[0057] Those skilled in the art should be aware that, although the various methods of the present application are described based on the same concept and thus present commonality to each other, unless otherwise specified, these methods can be independently executed. Similarly, for each embodiment disclosed in the present application, they are all proposed based on the same inventive concept, therefore, concepts with the same expression, and concepts that are appropriately changed for convenience despite different expressions, should be understood as equivalent.

[0058] Unless the mutually exclusive relationship between the embodiments to be disclosed in this application is explicitly stated, the relevant technical features involved in each embodiment can be cross-combined to flexibly construct a new embodiment, as long as such combination does not deviate from the creative spirit of this application and can meet the needs of the prior art or solve certain deficiencies in the prior art. Those skilled in the art should be aware of this flexibility.

[0059] See also Figure 1 In one embodiment, the virtual prototype platform branch prediction method of the present application includes:

[0060] Step S10, responding to the branch prediction instruction of the virtual prototype platform, triggering the instruction simulator in the CPU core structure to send the memory address corresponding to the current branch instruction to the preset branch prediction model in the decoding stage;

[0061] The virtual prototype platform branch prediction model architecture in the terminal device can respond to the virtual prototype platform branch prediction instruction, triggering the instruction simulator in the CPU core structure to send the memory address corresponding to the current branch instruction to the preset branch prediction model during the decoding stage; wherein, the basic network architecture of the branch prediction model is an improved TAGE-SC-L branch prediction model, and the improved TAGE-SC-L branch prediction model is constructed by a TAGE-SC-L branch predictor that introduces a scoring strategy and a perceptron.

[0062] Step S20, calling a preset scoring strategy, the branch jump direction predictor in the branch prediction model predicts the jump direction of the current branch instruction according to the memory address corresponding to the current branch instruction, wherein the jump direction includes a first jump direction and a second jump direction, the first jump direction indicates that the current branch instruction is in a jump state, and the second jump direction indicates that the current branch instruction is in a non-jump state;

[0063] Step S30: If the current branch instruction is in a jump state, the branch jump address predictor in the branch prediction model adopts a preset scoring strategy to predict the address of the to-be-jumped program counter corresponding to the current branch instruction according to the memory address corresponding to the current branch instruction;

[0064] Step S40: If the current branch instruction is in a non-jump state, the branch jump address predictor determines the program counter address of the next instruction of the current branch instruction according to the memory address corresponding to the current branch instruction;

[0065] Step S50, determining the actual jump result of the current branch instruction in the CPU core structure, and sending the actual jump result to the branch jump direction predictor in the branch prediction model to update the branch prediction model to complete the branch prediction of the virtual prototype platform.

[0066] In some embodiments, the main predictor includes a base table and multiple tag tables, wherein the base table is indexed by a program counter address, and the tag table indexes the prediction result by hashing historical information of a variable-length geometric history length and the program counter address, and if no tag table hits, the prediction result of the base table is selected; otherwise, the prediction result of the tag table with the longest history length is selected from all the hit tag tables as the final prediction direction.

[0067] In some embodiments, in the decoding stage, the get_prediction() function in the branch jump direction predictor in the branch prediction model is called to predict the jump direction of the current branch instruction based on the memory address corresponding to the current branch instruction; in the execution stage, the preset update_predictor() function is called to send the actual jump result to the branch jump direction predictor in the branch prediction model.

[0068] Specifically, see Figure 2 , Figure 2 The exemplary architecture of the improved branch prediction model based on the virtual prototype platform in the embodiment of the present application, the virtual prototype platform branch prediction method of the present application can be implemented based on the improved branch prediction model architecture of the virtual prototype platform, and the virtual prototype platform branch prediction model architecture includes a CPU core structure and a branch prediction model structure, wherein: Figure 2 The left side shows the CPU core structure, which is implemented through the instruction simulator (ISS). The CPU core can be configured with the RV32IM instruction set or the RV64IM instruction set, including a four-stage pipeline: instruction fetch (IF), decode (ID), execute (EX) and write back (WB). Figure 2 On the right is the branch prediction model structure. This CPU core structure is interconnected with the CPU core through its operating logic in the pipeline. It includes a branch jump direction predictor and a branch jump address predictor (BTB).

[0069] The operating principle of the improved branch prediction model architecture based on the virtual prototype platform of the present application is as follows:

[0070] The improved TAGE-SC-L branch prediction model of the present application is integrated into the pipeline model of the CPU core structure. In decoding (ID), the branch instruction and PC address are identified. The branch instruction is passed to the execution (EX) stage for operation, and the PC address is passed to the branch prediction model. The get_prediction() function in the branch prediction model receives the PC address and determines whether the instruction jumps. The branch prediction state table is used to save the prediction information.

[0071] The branch jump address predictor (BTB is used to predict the jump target address of the branch instruction. It will output the program counter address to be jumped (PC address). Jump_PC_addr represents the program counter address to be jumped and the program counter address (PC address) of the next instruction of the current branch instruction. Branch PC addr+4 represents the program counter address of the next instruction of the current branch instruction.

[0072] For each branch instruction, the branch prediction model will give two predicted directions (PredDir), jump or not jump. If the jump result is adopted, the program counter address to be jumped (Jump_PC_addr) will be sent to the instruction fetch (IF) stage, otherwise, the program counter address of the next instruction (Branch PC addr+4) will be sent to the instruction fetch (IF) stage. In the instruction simulator (ISS), the execution of the branch instruction will not be interrupted. In the execution (EX) stage, the actual jump result (Actual_result) will be sent to the update_predictor() function to update the state of the branch predictor.

[0073] In some embodiments, the present application uses a higher abstraction level hardware description language SystemC to design a high-accuracy branch prediction model, and uses a scoring strategy to design an improved TAGE-SC-L branch prediction model with higher accuracy than the original TAGE-SC-L branch prediction model, which is named TAGE-SC-LS branch prediction model, where TAGE is the main predictor, SC represents the statistical correction predictor, L represents the loop predictor, and S represents the scoring strategy.

[0074] See also Figure 3 , Figure 3 An exemplary structure of the main predictor (TAGE), the main predictor (TAGE) can capture a wide range of dynamic branch patterns in branch prediction. The main predictor (TAGE) consists of a base table (Base) and multiple tag tables. The base table is indexed by the PC value, and the tag table is hashed by the history information of the variable geometric history length and the PC value to index the prediction result. If there is no tag table hit, the prediction result of the Base table is selected; otherwise, the prediction result of the tag table with the longest history length is selected from all the hit tag tables as the final prediction direction. Although the main predictor (TAGE) can capture many branch patterns and has strong adaptability, the main predictor (TAGE) does not work well when processing some irregular loop bodies. The loop predictor provides a solution. When a loop body with a fixed number of iterations is detected and when the confidence exceeds the threshold, the prediction result of the loop predictor will be selected as the final output. In addition, for branch patterns with statistical regularities, the performance of the main predictor (TAGE) and the loop predictor (L) is poor. The statistical correction predictor can solve this problem. It can invert the prediction result of the main predictor (TAGE) as the final output result when the confidence of the main predictor (TAGE) is low.

[0075] See also Figure 4 , Figure 4The exemplary structure of the original TAGE-SC-L branch prediction model is shown. Generally speaking, the selection priority of the prediction results of the three branch predictors in the TAGE-SC-L branch predictor, namely the main predictor (TAGE), the statistical correction predictor (SC) and the loop predictor (L), is loop predictor (L), statistical correction predictor (SC), and main predictor (TAGE). The higher priority loop predictor (L) sometimes overrides the result of the SC predictor.

[0076] In order to give full play to the potential of the statistically corrected predictor (SC), the improved TAGE-SC-L branch prediction model of this application introduces a scoring strategy, and the pseudo code of the scoring strategy is as follows:

[0077]

[0078] From the pseudo code of the above scoring strategy, it can be seen that Score_TAGE represents the first prediction score corresponding to the main predictor, Score_SC represents the second prediction score corresponding to the statistical correction predictor, Score_loop represents the third prediction score corresponding to the loop predictor, Pred_TAGE represents the first prediction result corresponding to the main predictor, Pred_SC represents the second prediction result corresponding to the statistical correction predictor, Pred_LP represents the third prediction result corresponding to the loop predictor, Actual_result represents the actual execution result of the branch instruction, PredDir_Select represents the best branch predictor result selected based on the score strategy, PredDir represents the final selected branch prediction result, use_sc represents the first conditional flag corresponding to the statistical correction predictor, and use_loop represents the second conditional flag corresponding to the loop predictor.

[0079] From the pseudo code of the above scoring strategy, it can be seen that the scoring strategy of this application adopts the following mechanism:

[0080] The main predictor (TAGE), the statistical correction predictor (SC) and the loop predictor (L) are respectively assigned a scoring parameter, which includes Score_TAGE, Score_SC and Score_loop, wherein Score_TAGE represents the first prediction score corresponding to the main predictor, Score_SC represents the second prediction score corresponding to the statistical correction predictor, and Score_loop represents the third prediction score corresponding to the loop predictor. If the jump directions predicted by each of them are the same as the actual jump directions, the corresponding scores are increased by one, otherwise they are decreased by one. When the scores are set to 0, the prediction results of the main predictor (TAGE) and the loop predictor (L) are selected according to the original logic in the original TAGE-SC-L branch prediction model; when SC is valid, the present application applies a scoring strategy to the original TAGE-SC-L predictor and selects the jump direction of the predictor with the highest score as the final prediction result.

[0081] In a specific embodiment, after the step of triggering the instruction simulator in the CPU core structure to send the memory address corresponding to the current branch instruction to the preset branch prediction model, the method includes:

[0082] Step S201, calling a preset scoring strategy to initialize initial scoring variables corresponding to the main predictor, the statistical correction predictor and the cyclic predictor;

[0083] Step S202: If the prediction result corresponding to any branch predictor matches the actual result corresponding to it, then its corresponding prediction score is increased by 1; if the prediction result of any branch predictor does not match the actual result, then its corresponding prediction score is set to 0;

[0084] Step S203, compare the first prediction score corresponding to the main predictor, the second prediction score corresponding to the statistical correction predictor, and the third prediction score corresponding to the loop predictor; if the third prediction score corresponding to the loop predictor is greater than the first prediction score corresponding to the main predictor and the second prediction score corresponding to the statistical correction predictor, take the third prediction result corresponding to the loop predictor as the final prediction result.

[0085] After comparing the first prediction score corresponding to the main predictor, the second prediction score corresponding to the statistical correction predictor, and the third prediction score corresponding to the cycle predictor, if the third prediction score corresponding to the cycle predictor is greater than the first prediction score corresponding to the main predictor and the second prediction score corresponding to the statistical correction predictor, then taking the third prediction result corresponding to the cycle predictor as the final prediction result, the method further comprises:

[0086] Step S2001: If the second prediction score corresponding to the statistical correction predictor is greater than the first prediction score corresponding to the main predictor, the second prediction result corresponding to the statistical correction predictor is used as the final prediction result; otherwise, the first prediction result corresponding to the main predictor is selected as the final prediction result;

[0087] Step S2002, if the first condition flag corresponding to the statistical correction predictor is not equal to 1, the judgment includes: if the second condition flag corresponding to the loop predictor is equal to 1, selecting the third prediction result corresponding to the loop predictor as the final prediction result; otherwise, selecting the first prediction result corresponding to the main predictor as the final prediction result;

[0088] Step S2003: If the first condition flag corresponding to the statistical correction predictor is equal to 1, directly selecting the optimal branch predictor selected based on the preset scoring strategy;

[0089] Step S2004, loop through the above steps and return the prediction result of the branch predictor finally selected.

[0090] In a further embodiment, since the TAGE-SC-LS branch prediction model of the present application has a low prediction accuracy in scenarios of long dependencies and nonlinear recognition, and the perceptron (P) is considered to be an effective method to improve the prediction accuracy, the perceptron (P) uses a perceptron for branch prediction, which is represented by a weight vector, which indicates the correlation between different branches. In order to provide coverage of more diverse program behaviors, we combine TAGE-SC-LS with the perceptron (P) through a scoring strategy to obtain a more optimized branch prediction model TAGE-SC-LSP, which is the final improved TAGE-SC-L branch prediction model of the present application, and it further improves the accuracy of branch prediction.

[0091] It can be seen from the above embodiments that, compared with the prior art, the present application aims at the problem that the TAGE-SC-L branch prediction model in the prior art has not been fully functionally verified on the virtual prototype (VP) platform at the electronic system level (ESL). The present applicant has made corresponding explorations to solve the problem. The present application includes but is not limited to the following beneficial effects:

[0092] First, this application defines an improved branch prediction model based on a virtual prototype platform architecture, which has more comprehensive functional verification. This technology introduces a branch prediction model based on a virtual prototype, which can more comprehensively test and evaluate the functions of the branch prediction algorithm through simulation and verification during the design phase. The virtual prototype can provide more verification and optimization opportunities for various branch prediction scenarios, thereby ensuring that the final prediction model is more accurate and reliable.

[0093] Second, this application uses a higher level of abstraction hardware description language SystemC to design the branch prediction algorithm module, which has a faster simulation speed. Using a higher level of abstraction hardware description language for design makes the simulation of the branch prediction algorithm module more efficient. The SystemC language supports hardware-level parallelization and abstract modeling. Compared with traditional low-level languages, it can simulate faster, reduce the design and verification cycle, and improve development efficiency.

[0094] Third, this application adopts a new scoring strategy to design the TAGE-SC-LS model with higher prediction accuracy. By introducing a new scoring strategy to design the TAGE-SC-LS model, the accuracy of branch prediction is significantly improved. The scoring strategy can allocate scores to different historical patterns, making the TAGE model more accurate in capturing complex branch patterns.

[0095] Fourthly, this application integrates the perceptron by introducing the TAGE-SC-L branch predictor with a scoring strategy, designs the TAGE-SC-LP model, and has a higher prediction coverage. By integrating the scoring strategy with the perceptron, the design of the TAGE-SC-LP model is further optimized, and the coverage of branch prediction is improved. The perceptron is an algorithm based on machine learning, which can adjust the prediction strategy through dynamic learning, so that the model can cover more types of branch patterns, enhancing the adaptability and generalization ability of the model.

[0096] See also Figure 5, a virtual prototype platform branch prediction device provided to meet one of the purposes of the present application, includes a memory address sending module 1100, a jump direction prediction module 1200, a to-be-jumped address prediction module 1300, a program counter address determination module 1400 and a branch prediction model update module 1500. Among them, the memory address sending module 1100 is configured to respond to the virtual prototype platform branch prediction instruction, triggering the instruction simulator in the CPU core structure to send the memory address corresponding to the current branch instruction to the preset branch prediction model in the decoding stage; the jump direction prediction module 1200 is configured to call a preset scoring strategy, and the branch jump direction predictor in the branch prediction model predicts the jump direction of the current branch instruction according to the memory address corresponding to the current branch instruction, wherein the jump direction includes a first jump direction and a second jump direction, the first jump direction indicates that the current branch instruction is in a jump state, and the second jump direction indicates that the current branch instruction is in a non-jump state; the to-be-jumped address prediction module 1300 is configured to, if the current branch instruction is in a jump state, the The branch jump address predictor in the branch prediction model adopts a preset scoring strategy to predict the program counter address to be jumped corresponding to the current branch instruction according to the memory address corresponding to the current branch instruction; the program counter address determination module 1400 is configured so that if the current branch instruction is in a non-jump state, the branch jump address predictor determines the program counter address of the next instruction of the current branch instruction according to the memory address corresponding to the current branch instruction; the branch prediction model update module 1500 is configured to determine the actual jump result of the current branch instruction in the CPU core structure, and send the actual jump result to the branch jump direction predictor in the branch prediction model to update the branch prediction model to complete the branch prediction of the virtual prototype platform.

[0097] Based on any embodiment of this application, please refer to Figure 6 Another embodiment of the present application further provides an electronic device, which can be implemented by a computer device, such as Figure 6As shown, a schematic diagram of the internal structure of a computer device. The computer device includes a processor, a computer-readable storage medium, a memory, and a network interface connected via a system bus. Among them, the computer-readable storage medium of the computer device stores an operating system, a database, and computer-readable instructions. The database may store a control information sequence. When the computer-readable instructions are executed by the processor, the processor can implement a virtual prototype platform branch prediction method. The processor of the computer device is used to provide computing and control capabilities to support the operation of the entire computer device. The memory of the computer device may store computer-readable instructions. When the computer-readable instructions are executed by the processor, the processor can execute the virtual prototype platform branch prediction method of the present application. The network interface of the computer device is used to connect and communicate with a terminal. Those skilled in the art can understand that Figure 6 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0098] In this embodiment, the processor is used to execute Figure 5 The memory stores the program code and various data required to execute the above modules or submodules. The network interface is used to transmit data between user terminals or servers. The memory in this embodiment stores the program code and data required to execute all modules in the branch prediction device of the virtual prototype platform of this application, and the server can call the program code and data of the server to execute the functions of all modules.

[0099] The present application also provides a storage medium storing computer-readable instructions. When the computer-readable instructions are executed by one or more processors, the one or more processors execute the steps of the virtual prototype platform branch prediction method described in any embodiment of the present application.

[0100] The present application also provides a computer program product, including a computer program / instruction, which, when executed by one or more processors, implements the steps of the virtual prototype platform branch prediction method described in any embodiment of the present application.

[0101] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiments of the present application can be implemented by instructing the relevant hardware through a computer program, and the computer program can be stored in a computer-readable storage medium. When the program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, the aforementioned storage medium can be a computer-readable storage medium such as a disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM).

[0102] The above description is only a partial implementation method of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A virtual prototype platform branch prediction method, characterized in that: include: In response to the branch prediction instruction of the virtual prototype platform, the instruction simulator in the CPU core structure is triggered to send the memory address corresponding to the current branch instruction to the preset branch prediction model in the decoding stage; Calling a preset scoring strategy, the branch jump direction predictor in the branch prediction model predicts the jump direction of the current branch instruction according to the memory address corresponding to the current branch instruction, wherein the jump direction includes a first jump direction and a second jump direction, the first jump direction indicates that the current branch instruction is in a jump state, and the second jump direction indicates that the current branch instruction is in a non-jump state; If the current branch instruction is in a jump state, the branch jump address predictor in the branch prediction model adopts a preset scoring strategy to predict the address of the to-be-jumped program counter corresponding to the current branch instruction according to the memory address corresponding to the current branch instruction; If the current branch instruction is in a non-jump state, the branch jump address predictor determines the program counter address of the next instruction of the current branch instruction according to the memory address corresponding to the current branch instruction; The actual jump result of the current branch instruction is determined in the CPU core structure, and the actual jump result is sent to the branch jump direction predictor in the branch prediction model to update the branch prediction model to complete the branch prediction of the virtual prototype platform.

2. The virtual prototype platform branch prediction method according to claim 1, characterized in that: The basic network architecture of the branch prediction model is an improved TAGE-SC-L branch prediction model, and the improved TAGE-SC-L branch prediction model is constructed by a TAGE-SC-L branch predictor that introduces a scoring strategy and a perceptron.

3. The virtual prototype platform branch prediction method according to claim 2, characterized in that: After the step of triggering the instruction simulator in the CPU core structure to send the memory address corresponding to the current branch instruction to the preset branch prediction model, the method includes: Calling a preset scoring strategy to initialize initial scoring variables corresponding to the main predictor, the statistical correction predictor, and the cyclic predictor; If the prediction result corresponding to any branch predictor matches its corresponding actual result, its corresponding prediction score increases by 1; if the prediction result of any branch predictor does not match its actual result, its corresponding prediction score is set to 0; Compare the first prediction score corresponding to the main predictor, the second prediction score corresponding to the statistical correction predictor, and the third prediction score corresponding to the loop predictor. If the third prediction score corresponding to the loop predictor is greater than the first prediction score corresponding to the main predictor and the second prediction score corresponding to the statistical correction predictor, take the third prediction result corresponding to the loop predictor as the final prediction result.

4. The virtual prototype platform branch prediction method according to claim 3, characterized in that: After comparing the first prediction score corresponding to the main predictor, the second prediction score corresponding to the statistical correction predictor, and the third prediction score corresponding to the cycle predictor, if the third prediction score corresponding to the cycle predictor is greater than the first prediction score corresponding to the main predictor and the second prediction score corresponding to the statistical correction predictor, then taking the third prediction result corresponding to the cycle predictor as the final prediction result, the method further comprises: If the second prediction score corresponding to the statistically corrected predictor is greater than the first prediction score corresponding to the main predictor, the second prediction result corresponding to the statistically corrected predictor is used as the final prediction result; otherwise, the first prediction result corresponding to the main predictor is selected as the final prediction result; If the first condition flag corresponding to the statistical correction predictor is not equal to 1, the determination includes: if the second condition flag corresponding to the loop predictor is equal to 1, selecting the third prediction result corresponding to the loop predictor as the final prediction result; otherwise, selecting the first prediction result corresponding to the main predictor as the final prediction result; If the first condition flag corresponding to the statistical correction predictor is equal to 1, directly selecting the optimal branch predictor selected based on the preset scoring strategy; The above steps are executed in a loop, and the prediction result of the branch predictor finally selected is returned.

5. The virtual prototype platform branch prediction method according to claim 2, characterized in that: The master predictor includes a base table and a plurality of tag tables, wherein the base table is indexed by a program counter address, and the tag table is indexed by a hash operation of history information of a variable geometric history length and a program counter address to index a prediction result, and if no tag table hits, the prediction result of the base table is selected; Otherwise, the prediction result of the tag table with the longest history length is selected from all the hit tag tables as the final prediction direction.

6. The virtual prototype platform branch prediction method according to any one of claim 1, characterized in that: The CPU core structure includes a four-stage pipeline of instruction fetching, decoding, executing and writing back.

7. The virtual prototype platform branch prediction method according to claims 1 to 6, characterized in that: In the decoding stage, the get_prediction() function in the branch jump direction predictor in the branch prediction model is called to predict the jump direction of the current branch instruction according to the memory address corresponding to the current branch instruction; In the execution stage, the preset update_predictor() function is called to send the actual jump result to the branch jump direction predictor in the branch prediction model.

8. A virtual prototype platform branch prediction device, characterized in that: include: A memory address sending module is configured to respond to a branch prediction instruction of a virtual prototype platform, triggering an instruction simulator in a CPU core structure to send a memory address corresponding to a current branch instruction to a preset branch prediction model during a decoding phase; A jump direction prediction module, configured to call a preset scoring strategy, wherein a branch jump direction predictor in the branch prediction model predicts a jump direction of the current branch instruction according to a memory address corresponding to the current branch instruction, wherein the jump direction includes a first jump direction and a second jump direction, wherein the first jump direction indicates that the current branch instruction is in a jump state, and the second jump direction indicates that the current branch instruction is in a non-jump state; The to-be-jumped address prediction module is configured to, if the current branch instruction is in a jump state, predict the to-be-jumped program counter address corresponding to the current branch instruction by using a preset scoring strategy based on the memory address corresponding to the current branch instruction; a program counter address determination module, configured to determine, if the current branch instruction is in a non-jump state, the branch jump address predictor to determine the program counter address of the next instruction of the current branch instruction according to the memory address corresponding to the current branch instruction; A branch prediction model update module is configured to determine an actual jump result of the current branch instruction in the CPU core structure, and send the actual jump result to a branch jump direction predictor in the branch prediction model to update the branch prediction model to complete the branch prediction of the virtual prototype platform.

9. An electronic device, comprising a central processing unit and a memory, characterized in that: The central processing unit is used to call and run the computer program stored in the memory to execute the steps of the method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: It stores a computer program implemented according to the method described in any one of claims 1 to 7 in the form of computer-readable instructions, and when the computer program is called and executed by a computer, the steps included in the corresponding method are executed.

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