Asynchronous micro-pipeline structure based on the "send-relay-receive" architecture

Abstract

The present invention discloses an asynchronous micro-pipeline structure based on a "send-relay-receive" structure, which includes an asynchronous control component. The asynchronous control component includes one or more of a Sender, a Relay, a Receiver, or a Permitted Relay (PmtRelay). The Sender includes a trigger, an inverter, and a delay module; the Relay is composed of an exclusive-OR gate, an exclusive-NOR gate, an AND gate, a D flip-flop, an inverter, and a delay module, and is implemented based on a Click asynchronous controller; the Receiver includes a trigger; the PmtRelay adds a pmt control mechanism to the Click controller; the asynchronous control component is one of a Fifo, a PmtFifo, a Selector, a Splitter, a WaitMerge, and a MutexMerge, and an asynchronous micro-pipeline structure is built by one or more of the asynchronous control components. The asynchronous micro-pipeline structure of the present invention provides fine-grained control, uses event flow to drive control, adopts a unified control chain template, is more straightforward and simple in design, pays more attention to the delay and generation conditions of event signals, and is more flexible and efficient in the design process.

Description

Technical Field

[0001] The present invention belongs to the technical field of asynchronous control circuits, and particularly relates to an asynchronous micro-pipeline structure based on a "send-relay-receive" structure. Background Art

[0002] The asynchronous micro-pipeline structure is the core of building asynchronous circuits. Traditional micro-pipelines are implemented using a coarse-grained static data flow structure. The design method based on the static data flow structure adopts a coarse-grained control structure. Designers only need to master a small number of event-driven details and design event-driven circuits entirely from the perspective of the control method. This structure can better distinguish the control path and the data path, ensure the consistency of data throughout the circuit, and avoid data conflicts or errors. However, the pipelines with coarse-grained control structures need to be refined multiple times according to functions and levels, resulting in difficulty in describing the event mechanism from the control aspect and requiring manual customization of some structures. Moreover, pipelines of this structure use a large number of C units as basic structures. In large-scale digital designs, the use of C units increases the difficulty of circuit verification and introduces additional obstacles to large-scale designs. In addition, when using the coarse-grained static data flow structure for engineering practice, additional customized design tools are required, and the design process is not compatible with the existing mainstream design processes.

[0003] Based on the static micro-pipeline, a more fine-grained "chain-link" structure model has been proposed in research. The "chain-link" structure model combines various asynchronous controllers and necessary delays. The chain structure is responsible for event transmission and delay within the controlled module, while the link structure is responsible for event exchange and function module management. Different from the static data flow structure at the macro scale, the "chain-link" structure focuses on the dynamic drive mechanism of events rather than the abstract control method, which is more in line with the working principle of event-driven design. This method can adjust the implementation of the micro-pipeline structure from the micro aspect and is suitable for the development of high-speed asynchronous circuits. However, the development process of this structure requires mastering a large number of asynchronous controller principles and details and involves the transformation and division of asynchronous control circuits. Developing a micro-pipeline based on the "chain-link" structure is a difficult task. Summary of the Invention

[0004] Aiming at the problems existing in the above background art, the purpose of the present invention is to provide an asynchronous micro-pipeline structure based on a "send-relay-receive" structure.

[0005] To achieve the above purpose, the present invention adopts the following technical solutions:

[0006] The present invention provides an asynchronous micro-pipeline structure based on a "send-relay-receive" structure, including an asynchronous control component, where the asynchronous control component includes one or more of a Sender, a Relay, a Receiver, or a Permissive Relay, and:

[0007] Sender: It includes a trigger, an inverter, and a delay module. When receiving the driving pulse signal i_drive, the Sender flips the output level signal, and the input pulse signal i_free is output as o_free after passing through the delay module.

[0008] Relay: It consists of an exclusive OR gate, an exclusive NOR gate, an AND gate, a D flip-flop, an inverter, and a delay module, and is implemented based on the Click asynchronous controller.

[0009] Receiver: It includes a trigger, and the trigger is activated when receiving the lower-level pulse signal i_freeNext.

[0010] Permissive Relay: A permission (pmt) control mechanism is added to the Click controller, and the output end of the Click controller is connected to the pmt control signal. After the trigger pulse signal reaches the trigger end of the flip-flop, it controls the output level of the flip-flop to flip.

[0011] The asynchronous control component includes one of a Fifo, a PmtFifo, a Selector, a Splitter, a WaitMerge, and a MutexMerge. An asynchronous micro-pipeline structure is built by one or more of the asynchronous control components. The asynchronous control chain composed of the asynchronous control components is as follows:

[0012] (1) Asynchronous control chain composed of Fifo: An input control chain and an output control chain. After the signals corresponding to events and data pass through the input control chain, multiple pulse signals are generated during the transmission process to trigger the combinational logic circuit, and the signals corresponding to events and data are output by the output control chain; a delay module is added to the asynchronous control chain.

[0013] (2) Asynchronous control chain composed of PmtFifo: An input control chain and an output control chain. After the signals corresponding to events and data pass through the input control chain, the transmission is controlled by the permission mechanism, and one pulse signal is generated during the transmission process to trigger the combinational logic circuit, and the signals corresponding to events and data are output by the output control chain; a delay module is added to the asynchronous control chain.

[0014] (3)Asynchronous control chain composed of Selector: One input control chain and two branch chains. The signals corresponding to events and data are input through the input control chain, and after being transmitted through the branch chains, the signals corresponding to the events and data of one branch chain are selected and output; a delay module is added to the asynchronous control chain;

[0015] (4)Asynchronous control chain composed of Splitter: One input control chain and multiple branch output control chains. The signals corresponding to events and data are input through the input control chain and are divided into multiple signals corresponding to events and data, which are respectively output through multiple branch output control chains;

[0016] (5)Asynchronous control chain composed of WaitMerge: Multiple input control chains and one output control chain. The signals corresponding to multiple events and data are respectively input through multiple input control chains, and after being merged, they are output through one output control chain; a delay module is added to the asynchronous control chain;

[0017] (6)Asynchronous control chain composed of MutexMerge: Multiple input control chains and one output control chain. The signals corresponding to multiple events and data are respectively input through multiple input control chains, and the signals corresponding to the events and data of a valid input are identified and output through the output control chain.

[0018] Further, the Fifo includes: Sender, Relay, Receiver; the PmtFifo includes: Sender, PmtRelay, Receiver, AND gate; the Selector includes: Sender, Relay, Receiver, AND gate, NOT gate; the Splitter includes: Contap, AND gate, OR gate, NOR gate; the WaitMerge includes: Contap, AND gate, OR gate; the MutexMerge includes: Contap, AND gate, OR gate, multiplexer; the Contap uses a Sender that does not generate a free signal. The Contap includes a trigger and an inverter, and is used to convert a pulse signal into a level signal.

[0019] Further, in the Fifo, after the Sender receives the drive pulse signal drive from the upper-level module, it sends it to the Relay, and multiple Relay sequentially generate multiple pulse signals fire, which are used to trigger the combinational logic circuit. When all the pulse signals fire are triggered, they are sent to the Receiver to generate the drive pulse signal drive of the lower level and are transmitted to the lower-level module; at the same time, the Fifo returns a free signal to the upper-level module, indicating that the current module has completed the operation and can receive a new drive pulse signal.

[0020] Further, in the PmtFifo, after the Sender receives the drive pulse signal drive from the upper-level module, it sends the signal to the PmtRelay. After waiting for the permission control mechanism to change the state, the PmtRelay generates a pulse signal fire, which is used to trigger the combinational logic circuit. When the pulse signal fire is triggered, it is sent to the Receiver to generate the drive pulse signal drive of the lower level and is transmitted to the lower-level module. At the same time, the PmtFifo returns a free signal to the upper-level module, indicating that the current module has completed the operation and can receive a new drive pulse signal.

[0021] Further, in the Selector, after the Sender receives the drive pulse signal drive from the upper-level module, it is output to the Relay after being delayed by the delay module. The Relay generates a pulse fire, which is transmitted to two AND gates after being delayed by the delay module. One of the two AND gates conducts and generates the drive pulse signal drive of the lower level, and the output data controls the trigger in the Receiver to collect data, thereby triggering the entire branch selection process.

[0022] Further, in the Splitter, when the event and data trigger the Splitter through the drive pulse signal drive, the Splitter copies and distributes the event and data to multiple branches. The multiple branches process the event and data simultaneously. After all branches complete the processing and return the reply signal, the Splitter sends a free signal to the upper-level module through the free signal and waits to receive the next event.

[0023] Further, in the WaitMerge, after receiving the drive pulse signals drive and the corresponding data data from multiple upper-level modules, the WaitMerge merges the multiple drive pulse signals into a single drive pulse signal and transmits it to the lower-level module. At the same time, it splices the multiple data streams into a single data stream and transmits it to the lower-level module.

[0024] Further, in the MutexMerge, after receiving the drive pulse signals drive and the corresponding data data from multiple upper-level modules, the result of the OR operation of the drive pulse signals drive of the multiple upper-level modules is used as the valid input signal, and the event and data corresponding to the valid input signal are transmitted to the lower-level module. At the same time, the drive pulse signals drive of the multiple upper-level modules respectively control the Contap, and the output signal of the Contap is used as the selection signal of the selector. One path of data is selected through the selection signal. After all inputs are processed, the MutexMerge sends a free signal to the upper-level module and waits to receive new data.

[0025] Compared with the disadvantages and deficiencies of the prior art, the present invention has the following beneficial effects:

[0026] (1) The asynchronous micro-pipeline structure based on the "send-relay-receive" structure proposed by the present invention provides fine-grained control, making the mechanism for describing events at the control level more intuitive. Moreover, it uses the flow of events to drive control, adopts a unified control chain template, and is more straightforward and simple in design;

[0027] (2) Compared with the coarse-grained static data flow structure that uses a large number of C units, the relay in the present invention is implemented based on the Click asynchronous controller. The Click unit replaces the C unit of the coarse-grained control structure. While transmitting the handshake signal, the Click unit will generate a trigger edge. This asynchronous control method is closer to synchronous control and is beneficial to the verification of the circuit in large-scale design;

[0028] (3) The asynchronous control chain composed of asynchronous control components in the present invention is built using basic logic units and can be fully compatible with the synchronous design process in design. This greatly alleviates the disadvantage that asynchronous design lacks specific EDA, standardizes the design process, and reduces the dependence on customized design tools;

[0029] (4) Compared with the "chain-link" structure that requires mastering a large number of asynchronous controller principles and details, the asynchronous micro-pipeline structure proposed by the present invention simplifies the design process. Designers only need to master a small number of event-driven details and design event-driven circuits entirely from the perspective of the control method, reducing the learning difficulty of engineering personnel and enabling them to understand and apply these structures more quickly. In addition, the asynchronous micro-pipeline structure of the present invention pays more attention to the delay and generation conditions of event signals, making the design process more flexible and efficient. Brief Description of the Drawings

[0030] Figure 1 is a schematic structural diagram of the Sender provided by an embodiment of the present invention;

[0031] Figure 2 is a schematic structural diagram of the Relay provided by an embodiment of the present invention;

[0032] Figure 3 is a schematic structural diagram of the Receiver provided by an embodiment of the present invention;

[0033] Figure 4 is a schematic structural diagram of the PmtRelay provided by an embodiment of the present invention;

[0034] Figure 5 is a schematic structural diagram of the Fifo provided by an embodiment of the present invention;

[0035] Figure 6 is a schematic structural diagram of the PmtFifo provided by an embodiment of the present invention;

[0036] Figure 7 It is a schematic structural diagram of the Selector provided by an embodiment of the present invention;

[0037] Figure 8 It is a schematic structural diagram of the Splitter provided by an embodiment of the present invention;

[0038] Figure 9 It is a schematic structural diagram of the WaitMerge provided by an embodiment of the present invention;

[0039] Figure 10 It is a schematic structural diagram of the MutexMerge provided by an embodiment of the present invention. Detailed implementation manners

[0040] In order to make the objectives, technical solutions and advantages of the present invention clearer and more understandable, the present invention will be further described in detail below in conjunction with specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0041] The present invention proposes a coarse-grained asynchronous micro-pipeline structure based on the "send-relay-receive" structure. The granularity of this structure is between static data flow and the "chain-link" structure, focusing on the delay and generation conditions of event signals, making the design process more flexible and efficient. This structure includes one or more of four basic structures, and the four basic structures are: Sender, Relay, Receiver, and Permitted Relay (PmtRelay). The core event-driven mechanism is expressed through these four basic structures, and the driving logic circuit of the event signal is expressed using Boolean logic.

[0042] Sender: The structure is as Figure 1 shown, including a trigger, an inverter, and a delay module, responsible for starting the operation of the asynchronous control path and ensuring the reliable transmission of data. When receiving the driving pulse signal i_drive, the Sender flips the output level signal, and the input pulse signal i_free is output as o_free after passing through the delay module. The specific process is as follows: At the initial moment, the output port outR is at a low level, and the D terminal of the trigger is at a high level. When the pulse signal i_free arrives, the data at the D terminal of the trigger is copied to the Q terminal, the output port outR changes to a high level, and the D terminal changes to a low level.

[0043] Relay: The structure is as Figure 2As shown, it is composed of an XOR gate, an XOR gate, an AND gate, a D flip-flop, an inverter, and a delay module, and is implemented based on a Click asynchronous controller. The Click controller interacts with the outside through two inputs and three outputs, where the input includes inR and outA signals, and the output includes inA, outR, and pulse fire. Pulse fire is responsible for controlling the trigger to collect data. The Click controller strictly manages data flow through pulse fire, and the remaining four signals are used to interact with adjacent Click controllers. In the initial state, all input and output level signals remain at a low level. The XOR operation of inR and inA results in inRA being a low level, and the XOR operation of outA and outR results in outRA being a high level. When inRA and outRA perform an AND operation, they continue to maintain a low level, so pulse fire also remains at a low level. When inR flips, the controller starts, inRA changes from a low level to a high level, and pulse fire also changes from a low level to a high level. At the same time, the trigger copies the data at the D end to the Q end. After a delay unit, the level signals of inA and outR will also be pulled high, and the next-level Click request signal and the previous-level Click response signal will be generated at the same time. Subsequently, the pulse fire is pulled down from the high level to generate a complete pulse signal, and the data is transmitted smoothly under this control. When the next level Click feedback outA, the controller is ready to receive the next round of event triggers. This is also the handshake mechanism between the two-level controllers, thereby ensuring the binding transmission of events and data.

[0044] Receiver: The structure is as follows Figure 3 As shown, it includes a trigger. When receiving the lower-level pulse signal i_freeNext, the trigger is activated, and the data at the D end of the trigger is copied to the Q end, that is, inR is passed to inA, to achieve data synchronization and ensure data consistency in the pipeline. This structure is usually located at the end of the micropipeline and is responsible for resetting the entire asynchronous control path.

[0045] PmtRelay: structure is as follows Figure 4 As shown in the figure, a permission (pmt) control mechanism is added to the Click controller to achieve more sophisticated data transmission control. The output of the Click controller is connected to the pmt control signal. When pmt is low level 0, the pulse fire cannot reach the trigger end of the trigger. When pmt is high level 1, the pulse fire reaches the trigger end of the trigger and controls the output level of the trigger to flip. In addition, the behavior of the two inputs inR and outA and the two outputs inA and outR is consistent with Click.

[0046] Construct a variety of complex asynchronous control components with four basic structures: Fifo, PmtFifo, Selector, Splitter, WaitMerge, MutexMerge. Build an asynchronous micro-pipeline structure with one or more asynchronous control components, and these asynchronous control components will form an asynchronous control chain to complete various complex control tasks.

[0047] Asynchronous control chain composed of Fifo: an input control chain and an output control chain. After the signals corresponding to events and data pass through the input control chain, multiple pulse signals are generated during the transmission process, which are used to trigger the combinational logic circuit, thereby realizing the control of data flow in the pipeline; the signals corresponding to events and data are output by the output control chain; a delay module is added to the asynchronous control chain.

[0048] The structure of Fifo is as Figure 5 shown, including: Sender, multiple Relays, Receiver. After receiving the driving pulse signal i_drive from the upper-level module, Sender sends it to n Relays, reaching Relay 0, Relay 1... Relay n-1 in sequence, and then the signals o_fire_0, o_fire_1... o_fire_n-1 are generated in sequence, which are used to trigger the combinational logic circuit. After o_fire_n-1 is generated, the lower-level driving pulse signal o_driveNext is generated through a delay module at the lower level, and then through another delay module, the pulse signal o_free is generated, and the lower-level pulse signal i_freeNext is transmitted, indicating that the current module has completed the operation and can receive a new driving pulse signal. rst is the reset signal of the module, which returns the module to the initial state. Fifo can generate any number of pulses fire to meet different data flow control requirements, and these driving pulses have a strict sequence in time. The design of Fifo maps event transmission to the specific control level of the circuit, making the asynchronous circuit design based on this clearer and more understandable and maintainable in logic.

[0049] Asynchronous control chain composed of PmtFifo: an input control chain and an output control chain. After the signals corresponding to events and data pass through the input control chain, the transmission is controlled by an allowance mechanism, and a single pulse signal is generated during the transmission process, which is used to trigger the combinational logic circuit; the signals corresponding to events and data are output by the output control chain; a delay module is added to the asynchronous control chain.

[0050] The structure of PmtFifo is as Figure 6As shown in the figure, it includes: Sender, PmtRelay, and Receiver. After receiving the drive pulse signal i_drive from the upper-level module, Sender sends it to PmtRelay0, waits for the inversion of the input enable signal pmt, and then generates the o_fire signal, which is used to trigger the combinational logic circuit. After o_fire is generated, the lower-level drive pulse signal o_driveNext is generated through a delay module at the lower level. After passing through another delay module, the pulse signal o_free is generated and passed to the lower-level pulse signal i_freeNext, indicating that the current module has completed the operation and can receive a new drive pulse signal. rst is the reset signal of the module, which returns the module to the initial state. PmtFifo adds an enable control mechanism on the basis of Fifo to achieve more refined signal reception, processing, and transmission.

[0051] The asynchronous control chain composed of Selectors: one input control chain and two branch chains. The signals corresponding to events and data are input through the input control chain and output the signals corresponding to the events and data of one of the branch chains after being transmitted through the branch chains; a delay module is added to the asynchronous control chain.

[0052] The structure of Selector is as Figure 7As shown, it includes: Sender, Relay, Receiver, AND gate, and NOT gate. After receiving the drive pulse signal i_drive from the upper-level module, Sender outputs it to Relay0 after being delayed by the delay module. The output data controls the trigger in Receiver to collect data, thus triggering the entire branch selection process. Relay0 generates the signal o_fire_0, which is transmitted to two AND gates after being delayed by the delay module. The two AND gates respectively generate the drive pulse signals o_dirveNext0 and o_dirveNext1 of the lower level. According to the selection bit in the input data i_data_x, only one of the two AND gates will conduct, that is, either o_dirveNext0 or o_dirveNext1 generates a pulse, and the output data is o_data0_y or o_data1_y. After the o_fire_0 signal is generated, the pulse signal o_free is generated through the delay module and transmitted to the lower-level pulse signals i_freeNext0 and i_freeNext1, indicating that the current module has completed the operation. rst is the reset signal of the module, which returns the module to the initial state. The branch signal, as a key control bit, dynamically indicates which branch the data and signals should flow to. Selector ensures that the output drive pulse signal and output data of the correct branch are only valid when the branch signal is high; correspondingly, the output drive pulse signal of the wrong branch is only valid when the branch signal is low. The structure of Selector allows the designer to flexibly determine the data transmission path according to the input branch signal, while the data bound to the branch event is user-defined, enabling Selector to adapt to various different data processing requirements and increasing the flexibility and adaptability of the design.

[0053] The asynchronous control chain composed of Splitters: one input control chain and multiple branch output control chains. The signals corresponding to events and data are input through the input control chain and are output by multiple branch output control chains as multiple signals corresponding to events and data respectively.

[0054] The structure of Splitter is as Figure 8As shown, it includes: Contap, AND gate, OR gate, NOR gate. Contap uses a Sender that does not generate a free signal. Contap includes a flip-flop and an inverter, which convert a pulse signal into a level signal. Splitter receives the drive pulse signal i_drive and the data i_data_x. i_drive is directly connected to the two output signals o_driveNext0 and o_driveNext1. At the same time, the input data i_data_x is split into two output data o_data0_y and o_data1_z. i_drive pulls up the signal through Contap, and i_freeNext0 and i_freeNext1 pull down the signal through Contap to control the generation of the signal o_free, and then transmit the downstream pulse signals i_freeNext0 and i_freeNext1. rst is the reset signal of the module, which returns the module to the initial state. Splitter copies and distributes events and data to multiple branches. Multiple branches process events and data simultaneously, allowing events to be processed in parallel in multiple branches, increasing the parallelism and throughput of the system. After all branches complete processing and return the reply signal, Splitter sends a free signal to the upper-level module through the free signal and waits to receive the next event. This handshake mechanism ensures the orderly flow of events in Splitter, avoiding data conflicts and processing errors. Especially in scenarios where a single event needs to be distributed to multiple processing units for parallel processing, it can not only improve the efficiency of event processing, but also allow the system to perform different operations on different branches, thus increasing the flexibility and scalability of the system.

[0055] The asynchronous control chain composed of WaitMerge: multiple input control chains and one output control chain. Signals corresponding to multiple events and data are input through multiple input control chains respectively and output through one output control chain after merging; a delay module is added to the asynchronous control chain.

[0056] The structure of WaitMerge is as Figure 9As shown in the figure, it includes: Contap, AND gate, and OR gate. Contap uses a Sender that does not generate a free signal. Contap includes a flip-flop and an inverter to convert a pulse signal into a level signal. After WaitMerge receives the driving pulse signals and corresponding data from multiple upper-level modules, WaitMerge merges the multiple driving pulse signals into a single driving pulse signal and transmits it to the lower-level module, indicating that it can safely process the spliced data. At the same time, it splices the multiple data streams into a single data stream and transmits it to the lower-level module. This spliced data stream contains all the data provided by the upper-level modules. These data are merged together to form a complete data set so that the lower-level module can perform further processing or operations. Two input signals, i_drive0 and i_drive1, respectively control the two Contaps to raise their output signals. Only when both i_drive0 and i_drive1 arrive, the output signal o_driveNext is generated. o_driveNext pulls down the signal through Contap to control the generation of the signal o_free. The lower-level pulse signal i_freeNext restores the output signals of the two Contaps to their initial states. The input data i_data0_x and i_data1_x are spliced into new data and output as o_data_y. rst is the reset signal of the module, which returns the module to its initial state. WaitMerge plays a role in data aggregation and control synchronization in the asynchronous micro-pipeline, enabling the lower-level module to efficiently process the merged data stream, thereby improving the data processing capacity and efficiency of the entire system.

[0057] The asynchronous control chain composed of MutexMerge: multiple input control chains and one output control chain. Signals corresponding to multiple events and data are respectively input through the multiple input control chains. The signals corresponding to the events and data of a valid input are identified and output through the output control chain. This design ensures that even if there are multiple input ports, only one input carrying events and data arrives at the lower-level module during each processing, thus avoiding data conflicts.

[0058] The structure of MutexMerge is as Figure 10As shown in the figure, it includes: Contap, AND gate, OR gate, multiplexer. Contap uses a Sender that does not generate a free signal. Contap includes a flip-flop and an inverter to convert the pulse signal into a level signal. After MutexMerge receives the drive pulse signals and corresponding data from multiple upper-level modules, the result of ORing the drive pulse signals of multiple upper-level modules is used as the valid input signal, and the events and data corresponding to the valid input signal are transmitted to the lower-level module. The result of ORing the two input signals i_drive0 and i_drive1 is used as the output result of o_driveNext; at the same time, i_drive0 and i_drive1 respectively control two Contaps, and their output signals are used as the selection signals of the selector, so as to select one of the two input data i_data0_x and i_data1_y as the output result of i_data0_z. After all inputs are processed, MutexMerge sends an o_free signal to the upper-level module, and the lower-level pulse signal i_freeNext restores the output signals of the two Contaps to the initial state. rst is the reset signal of the module, which returns the module to the initial state. By ensuring that only one path of data and events is output each time, MutexMerge simplifies the management of multiple inputs, improves the stability and efficiency of the system, and is particularly suitable for scenarios that require ensuring data order and mutually exclusive access.

[0059] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, and improvements made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. An asynchronous micro-pipeline structure based on a "send-relay-receive" structure, characterized in that: The asynchronous control component includes one or more of Sender, Relay, Receiver, and PmtRelay, wherein: Sender: includes a trigger, an inverter and a delay module. When receiving the drive pulse signal i_drive, Sender flips the output level signal, and the input pulse signal i_free is delayed by the delay module and output as o_free. Relay: It consists of XOR gate, XNOR gate, AND gate, D flip-flop, inverter, and delay module, and is implemented based on Click asynchronous controller; Receiver: includes a trigger, which is activated when receiving the lower-level pulse signal i_freeNext; PmtRelay: Add a pmt control mechanism to the Click controller, connect the output of the Click controller to the pmt control signal, and control the output level of the trigger to flip after the trigger pulse signal reaches the trigger end of the trigger; The asynchronous control component is one of Fifo, PmtFifo, Selector, Splitter, WaitMerge, and MutexMerge. The Fifo includes: Sender, Relay, Receiver; the PmtFifo includes: Sender, PmtRelay, Receiver, and AND gate; the Selector includes: Sender, Relay, Receiver, AND gate, and NOT gate; the Splitter includes: Contap, AND gate, OR gate, and NOR gate; the WaitMerge includes: Contap, AND gate, OR gate; the MutexMerge includes: Contap, AND gate, OR gate, and multiplexer; the Contap uses a Sender that does not generate a free signal, and the Contap includes a trigger and an inverter, which is used to convert a pulse signal into a level signal; An asynchronous micro-pipeline structure is constructed by one or more of the asynchronous control components, and the asynchronous control chain composed of the asynchronous control components is as follows: (1) Asynchronous control chain composed of Fifo: an input control chain and an output control chain. After the signals corresponding to the events and data pass through the input control chain, multiple pulse signals are generated during the transmission process to trigger the combinational logic circuit. The signals corresponding to the events and data are output by the output control chain. A delay module is added to the asynchronous control chain. (2) The asynchronous control chain composed of PmtFifo: an input control chain and an output control chain. After the signals corresponding to the events and data pass through the input control chain, the transmission is controlled by the permission mechanism. During the transmission process, a pulse signal is generated to trigger the combinational logic circuit. The signals corresponding to the events and data are output by the output control chain. A delay module is added to the asynchronous control chain. (3) Asynchronous control chain composed of Selectors: an input control chain and two branch chains. The signals corresponding to events and data are input by the input control chain, and after being transmitted by the branch chain, the signals corresponding to events and data of one branch chain are selected for output. A delay module is added to the asynchronous control chain. (4) Asynchronous control chain composed of Splitters: one input control chain and multiple branch output control chains. The signals corresponding to events and data are input by the input control chain, and the signals corresponding to multiple events and data are output by multiple branch output control chains respectively. (5) Asynchronous control chain composed of WaitMerge: multiple input control chains and one output control chain. Signals corresponding to multiple events and data are input by multiple input control chains respectively, and are output by one output control chain after merging. A delay module is added to the asynchronous control chain. (6) Asynchronous control chain composed of MutexMerge: multiple input control chains and one output control chain. The signals corresponding to multiple events and data are input by multiple input control chains respectively, and the signals corresponding to the events and data of one valid input are identified and output by the output control chain.

2. The asynchronous micro-pipeline structure based on the "send-relay-receive" structure as claimed in claim 1, characterized in that: In the Fifo, the Sender receives the driving pulse signal drive from the upper module and sends it to the Relay, which generates multiple pulse signals fire in sequence through multiple Relays to trigger the combinational logic circuit. When all the pulse signals fire are excited, they are sent to the Receiver to generate the lower-level driving pulse signal drive, which is transmitted to the lower-level module; at the same time, the Fifo returns a free signal to the upper-level module, indicating that the module at this level has completed the operation and is waiting to receive a new driving pulse signal.

3. The asynchronous micro-pipeline structure based on the "send-relay-receive" structure as claimed in claim 1, characterized in that: In the PmtFifo, after the Sender receives the driving pulse signal drive from the upper module, it sends it to PmtRelay. After waiting for the permission control mechanism to change the state, PmtRelay generates a pulse signal fire to trigger the combinational logic circuit. When the pulse signal fire is excited, it is sent to the Receiver to generate the lower-level driving pulse signal drive, which is transmitted to the lower-level module. At the same time, PmtFifo returns a free signal to the upper-level module, indicating that the module at this level has completed the operation and is waiting to receive a new driving pulse signal.

4. The asynchronous micro-pipeline structure based on the "send-relay-receive" structure as claimed in claim 1, characterized in that: In the Selector, after the Sender receives the driving pulse signal drive from the upper module, it is output to the Relay after being delayed by the delay module. The Relay generates a pulse fire, which is transmitted to the two AND gates after being delayed by the delay module. One of the two AND gates is turned on and generates a lower-level driving pulse signal drive. The output data controls the trigger in the Receiver to collect data, thereby triggering the entire branch selection process.

5. The asynchronous micro-pipeline structure based on the "send-relay-receive" structure as claimed in claim 1, characterized in that: In the Splitter, when events and data trigger the Splitter through the driving pulse signal drive, the Splitter copies and distributes the events and data to multiple branches. Multiple branches process events and data simultaneously. After all branches complete processing and return reply signals, the Splitter sends a free signal to the superior module through the free signal, waiting to receive the next event.

6. The asynchronous micro-pipeline structure based on the "send-relay-receive" structure as claimed in claim 1, characterized in that: In the WaitMerge, after receiving the drive pulse signals drive and corresponding data data from multiple upper modules, WaitMerge merges the multiple drive pulse signals into a single drive pulse signal and transmits it to the lower module, and at the same time splices the multiple data into a single data stream and transmits it to the lower module.

7. The asynchronous micro-pipeline structure based on the "send-relay-receive" structure as claimed in claim 1, characterized in that: In the MutexMerge, after receiving the drive pulse signals drive and corresponding data data of multiple upper-level modules, the result of the phase-OR of the drive pulse signals drive of the multiple upper-level modules is used as a valid input signal, and the events and data corresponding to the valid input signal are transmitted to the lower-level modules; at the same time, the drive pulse signals drive of the multiple upper-level modules respectively control Contap, and the Contap output signal is used as the selection signal of the selector. One data output is selected by the selection signal. After all inputs are processed, MutexMerge sends a free signal to the upper-level module and waits for receiving new data.

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