Layout design method for reducing substrate noise coupling

Abstract

The invention relates to a layout design method for reducing substrate noise coupling, which comprises the following steps of: 1) firstly distinguishing a noise module and separating the noise module from a static module; 2) carrying out layout design on an output-stage inverter structure according to a design rule of an ESD IO device, and adding an isolating ring and a DUMMY tube between the two devices for isolating an output-stage device from an ESD device; (3) the output-stage power supply ground ring and the ESD ring are wired separately, and can be laminated on the device on the premise of ensuring the current requirement; (4) power buses in the functional unit area are called static power buses, and the static power buses are separated from the sensitive signal lines; 5) providing enough multi-substrate ground wire contact around the noise source and the noise sensitive circuit for power supply grounds with different functional areas; and 6) directly extracting a thick wire from the PAD for the power ground wire of the static module in the functional area for connection. According to the method, the noise coupling of the substrate is reduced through the layout, the isolation between the modules and the independent wiring, and the method can be used in the layout of a high-speed and high-precision chip according to the final post-simulation result and the final chip-level verification.

Description

Technical Field

[0001] The invention belongs to the field of integrated circuit analog layout, and in particular relates to a layout design method for reducing substrate noise coupling in a system with a relatively high dynamic range. Background Art

[0002] Integrated circuit layout is to convert the results of logic synthesis into physical layout files through layout and routing technology. At present, integrated circuit layout needs to meet the design requirements of chip low cost, small size, high performance, low power consumption, etc.

[0003] For high-speed and high-precision digital-analog hybrid systems, the impact of substrate noise on the circuit level depends on many factors, such as circuit type, layout, power network deviation and package type. In terms of layout, the forward bias conduction of the source and drain-substrate pn junctions of the tube, or the crosstalk introduced by the power connection points, will cause the substrate potential to jitter and deviate, which is substrate noise. Due to the electrical conductivity of the semiconductor substrate itself, the modules cannot be completely isolated from each other. The noise signal generated by the digital circuit is injected into the substrate through the coupling of capacitors, devices and interconnects, causing the substrate potential to fluctuate. The noise will inevitably propagate throughout the substrate and will come into contact with the nearby power ground wire, causing system signal distortion or circuit function failure in the analog circuit. Summary of the invention

[0004] In order to solve the problems of the prior art, the present invention provides a layout design method for reducing substrate noise coupling, which reduces substrate noise coupling through layout layout and isolation and independent routing between modules, and can be used in the layout of high-speed and high-precision chips based on the final post-simulation results and final chip-level verification.

[0005] The technical solution of the present invention is: the present invention is a layout design method for reducing substrate noise coupling, and its special feature is that the method comprises the following steps:

[0006] 1) First, distinguish the "noise" module and separate it from the "static" module;

[0007] 2) Design the output stage inverter structure according to the design rules of the ESD IO device, and add an isolation ring and a DUMMY tube between the two devices to isolate the output stage device from the ESD device;

[0008] 3) The output stage power ground ring and ESD ring are routed separately and can be stacked on the device while ensuring the current requirements;

[0009] 4) The power bus in the functional unit area is called the "static" power bus, which separates these "static" power buses from sensitive signal lines;

[0010] 5) Provide sufficient substrate ground contacts around noise sources and noise-sensitive circuits for different power grounds in functional areas;

[0011] 6) For the power ground line of the "static" module in the functional area, directly extract a thick wire from the PAD for connection.

[0012] Furthermore, the specific steps of step 1) are: the power supply noise generated in the I / O area is the largest, and the oscillator clock signal and the output signal of the power tube are grouped together close to the I / O area, called the "noise" power bus; and separated from the "static" module.

[0013] Furthermore, the specific steps of step 2) are: designing the layout of the output stage inverter structure according to the design rules of the ESD IO device, widening the source and drain ends of the PMOS tube and the NMOS tube respectively, and increasing the active area in the PMOS and NMOS devices, and then separately wrapping the PMOS and NMOS devices with isolation rings and adding DUMMY tubes to isolate the output stage devices and the ESD devices.

[0014] Further, the specific steps of step 3) are: the output stage power ground ring is only connected to the through hole of the output stage tube, and the power ground ring on the ESD is only connected to the through hole of the ESD tube. Under the premise of ensuring the current requirement, a metal layer can be stacked on the device;

[0015] Furthermore, the specific steps of step 6) are: directly extract a thick wire from the PAD and connect it to the power ground wire of the "static" module in the functional area, divide this thick wire into two paths to supply the static power ground of the internal area and the power ground of the sensitive module respectively, and try to ensure that the internal power ground ring is independent.

[0016] Furthermore, after step 6), step 7) is also included to add a decoupling capacitor to increase the stability of the power ground.

[0017] The layout design method for reducing substrate noise coupling provided by the present invention reduces substrate noise coupling by means of layout layout and isolation and independent routing between modules, and can be used in the layout of high-speed and high-precision chips according to the final post-simulation results and the final chip-level verification. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 This is an example of the layout structure of the present invention Figure 1 ;

[0019] Figure 2 This is an example of the layout structure of the present invention Figure 2 . DETAILED DESCRIPTION

[0020] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0021] The method steps of the specific embodiment of the present invention are as follows:

[0022] 1) First, distinguish the "noise" module. Because the power supply noise generated in the I / O area is the largest, the noise module composed of the oscillator clock signal and the output signal of the power tube needs to be close to the I / O area. They are collectively called the "noise" power bus and separated from the "static" module;

[0023] 2) Design the output-stage inverter structure according to the design rules of the ESD IO device, add an isolation ring and a DUMMY tube between the two devices to isolate the output-stage device from the ESD device; specifically: design the output-stage inverter structure according to the design rules of the ESD IO device, widen the source and drain ends of the PMOS tube and the NMOS tube respectively, and increase the active area of ​​the PMOS and NMOS devices, then separately wrap the PMOS and NMOS devices with isolation rings and add DUMMY tubes to isolate the output-stage device from the ESD device, such as Figure 1 As shown;

[0024] 3) The output stage power ground ring and the ESD ring are routed separately. Under the premise of ensuring the current requirements, they can be stacked on the device. Specifically, in order to separate the output power ground and the ESD power ground, the output stage power ground ring is only connected to the through-holes of the output stage tube, and the ESD power ground ring is only connected to the through-holes of the ESD tube. Under the premise of ensuring the current requirements, metal layers can be stacked on the device.

[0025] 4) The power bus in the functional unit area is called the "static" power bus, which separates these static power buses from sensitive signal lines;

[0026] 5) Provide enough VIA-stack and substrate ground contacts around noise sources and noise-sensitive circuits for different power grounds in functional areas. The noise current is absorbed by the ground contacts before reaching the sensitive circuits, and a low-impedance ground network can be provided at the same time.

[0027] 6) For the power ground of the "static" module in the functional area, a thick wire is directly extracted from the PAD for connection. Specifically, a thick wire is directly extracted from the PAD and connected to the power ground of the "static" module in the functional area. This thick wire is divided into two paths to supply the static power ground of the internal area and the power ground of the sensitive module respectively, and try to ensure that the internal power ground loop is independent, such as Figure 2 As shown;

[0028] 7) Add decoupling capacitors to increase the stability of the power ground.

[0029] The combination method provided by the present invention can effectively reduce substrate noise coupling.

[0030] The above are only specific embodiments disclosed in the present invention, but the protection scope of the present invention is not limited thereto. The protection scope of the present invention shall be based on the protection scope of the claims.

[0031] The content of the present invention and the technical content not specifically described in the above embodiments are the same as the prior art.

[0032] The present invention is not limited to the above embodiments, and all of the contents of the present invention can be implemented and have the above good effects.

Claims

1. A layout design method for reducing substrate noise coupling, characterized in that: The method comprises the following steps: 1) First, distinguish the "noise" module and separate it from the "static" module; 2) Design the output stage inverter structure according to the design rules of the ESD IO device, and add an isolation ring and a DUMMY tube between the two devices to isolate the output stage device from the ESD device; 3) The output stage power ground ring and ESD ring are routed separately and can be stacked on the device while ensuring the current requirements; 4) The power bus in the functional unit area is called the "static" power bus, which separates these "static" power buses from sensitive signal lines; 5) Provide sufficient substrate ground contacts around noise sources and noise-sensitive circuits for different power grounds in functional areas; 6) For the power ground line of the "static" module in the functional area, directly draw a thick wire from the PAD for connection.

2. The layout design method for reducing substrate noise coupling according to claim 1, characterized in that: The specific steps of step 1) are: the power supply noise generated in the I / O area is the largest, and the oscillator clock signal and the output signal of the power tube are grouped together close to the I / O area, which is called a "noise" power bus; and separated from the "static" modules.

3. The layout design method for reducing substrate noise coupling according to claim 2, characterized in that: The specific steps of step 2) are: designing the output stage inverter structure according to the design rules of the ESDIO device, widening the source and drain ends of the PMOS tube and the NMOS tube respectively, and increasing the active area in the PMOS and NMOS devices, and then separately enclosing the PMOS and NMOS devices with isolation rings and adding DUMMY tubes to isolate the output stage devices and the ESD devices.

4. The layout design method for reducing substrate noise coupling according to claim 3, characterized in that: The specific steps of step 3) are: the output stage power ground ring is only connected to the through hole of the output stage tube, and the power ground ring on the ESD is only connected to the through hole of the ESD tube. Under the premise of ensuring the current requirements, a metal layer can be stacked on the device.

5. The layout design method for reducing substrate noise coupling according to claim 4, characterized in that: The specific steps of step 6) are: directly extract a thick wire from the PAD and connect it to the power ground wire of the "static" module in the functional area, divide this thick wire into two paths to supply the static power ground of the internal area and the power ground of the sensitive module respectively, and try to ensure that the internal power ground ring is independent.

6. The layout design method for reducing substrate noise coupling according to any one of claims 1 to 5, characterized in that: The step 6) further includes the step 7) of adding a decoupling capacitor to increase the stability of the power ground.

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