Multilayer ceramic capacitor and method of manufacturing same

Abstract

A multilayer ceramic capacitor and a method of manufacturing the same are provided. The multilayer ceramic capacitor includes: a capacitor body including a dielectric layer and an inner electrode; and an external electrode disposed outside the capacitor body, in which the dielectric layer includes a plurality of dielectric crystal grains and crystal grain boundaries between adjacent dielectric crystal grains, the crystal grain boundaries including a barium titanate-based main component including barium (Ba) and titanium (Ti) and an inorganic element including silicon (Si), and a standard deviation of atomic% of the inorganic element with respect to a total amount of components of the grain boundary is 0.20 to 0.80, and the standard deviation is a square root of an average value of the square of the deviation.

Description

Technical Field

[0001] The present disclosure relates to a multilayer ceramic capacitor and a method of manufacturing the same. Background Art

[0002] Electronic components using ceramic materials include capacitors, inductors, piezoelectric elements, varistors, thermistors, etc. Among these ceramic electronic components, multilayer ceramic capacitors (MLCCs) are used in various electronic devices due to the advantages of being small, ensuring high capacity, and being easy to mount.

[0003] For example, MLCCs can be used as chip capacitors mounted on substrates of various electronic products such as imaging devices (such as liquid crystal displays (LCDs), plasma display panels (PDPs), and organic light emitting diodes (OLEDs), computers, personal portable terminals, and smart phones and used for charging or discharging.

[0004] Recently, as MLCCs become more highly integrated, MLCCs are becoming ultra-small, and high reliability in a thin-layer design is required. Summary of the invention

[0005] The present disclosure provides a multilayer ceramic capacitor having high reliability.

[0006] The present disclosure also provides a method of manufacturing a multilayer ceramic capacitor.

[0007] Some embodiments of the present disclosure provide a multilayer ceramic capacitor, comprising: a capacitor body, including a dielectric layer and an inner electrode; and an outer electrode, arranged outside the capacitor body, wherein the dielectric layer includes a plurality of dielectric grains and grain boundaries between adjacent dielectric grains, the grain boundaries include a barium titanate-based main component including barium (Ba) and titanium (Ti) and an inorganic element including silicon (Si), and the standard deviation of the atomic % of the total amount of the inorganic element composition relative to the grain boundaries is 0.20 to 0.80, and the standard deviation is the square root of the average of the squares of the deviations.

[0008] The grain boundary may have a barium (Ba)-inorganic element composite phase.

[0009] The grain boundary may further include nickel (Ni), and in the grain boundary, an atomic ratio of the inorganic element to nickel (Ni) may be 1.00 to 2.10.

[0010] In the grain boundary, an atomic ratio of the inorganic element to titanium (Ti) may be 0.010 to 0.065.

[0011] The inorganic element may further include at least one selected from the group consisting of magnesium (Mg), lithium (Li), copper (Cu), niobium (Nb), samarium (Sm), and gadolinium (Gd).

[0012] The grain boundary may further include a subcomponent including at least one selected from the group consisting of dysprosium (Dy), terbium (Tb), manganese (Mn), vanadium (V), barium (Ba), aluminum (Al), and calcium (Ca).

[0013] The subcomponent may include dysprosium (Dy), and in the grain boundary, an atomic ratio of the inorganic element to dysprosium (Dy) in the subcomponent may be 0.10 to 3.00.

[0014] At least one dielectric grain among the plurality of dielectric grains may have a core-shell structure including a core portion and a shell portion surrounding the core portion.

[0015] The shell part may include a barium titanate-based main component including barium (Ba) and titanium (Ti), and an inorganic element including silicon (Si).

[0016] The inorganic element of the shell may further include at least one selected from the group consisting of magnesium (Mg), lithium (Li), copper (Cu), niobium (Nb), samarium (Sm), and gadolinium (Gd).

[0017] The shell portion may further include a subcomponent including at least one selected from the group consisting of dysprosium (Dy), terbium (Tb), manganese (Mn), vanadium (V), barium (Ba), aluminum (Al), and calcium (Ca).

[0018] The capacitor body may have an active region in which the dielectric layers and the inner electrodes are alternately disposed, and a magnitude of a silicon (Si) peak in the dielectric layers in the active region may be 8.6 kcps to 25 kcps.

[0019] Another embodiment of the present disclosure provides a method for manufacturing a multilayer ceramic capacitor, the method comprising: preparing a dielectric powder in which a surface of a barium titanate-based main component powder including barium (Ba) and titanium (Ti) is coated with an inorganic element including silicon (Si); preparing a dielectric green sheet using a dielectric slurry including the dielectric powder, and forming a conductive paste layer on a surface of the dielectric green sheet; preparing a dielectric green sheet laminate by laminating the dielectric green sheets on which the conductive paste layer is formed; preparing a capacitor body including a dielectric layer and an inner electrode by firing the dielectric green sheet laminate; and forming an outer electrode on a surface of the capacitor body, wherein the dielectric layer includes a plurality of dielectric grains and a grain boundary between adjacent dielectric grains, the grain boundary including a barium titanate-based main component including barium (Ba) and titanium (Ti) and an inorganic element including silicon (Si), and a standard deviation of atomic % of the inorganic element relative to a total amount of the component of the grain boundary is 0.20 to 0.80, and the standard deviation is a square root of an average of squares of the deviations.

[0020] The operation of preparing the dielectric powder may include: performing hydrothermal synthesis of the barium titanate-based main component powder to complete grain growth; adding an inorganic salt containing silicon (Si) after completing the grain growth; and performing heat treatment after adding the inorganic salt.

[0021] The inorganic salt may further include at least one selected from the group consisting of magnesium (Mg), lithium (Li), copper (Cu), niobium (Nb), samarium (Sm), and gadolinium (Gd).

[0022] The inorganic salts include alkoxide-based compounds.

[0023] The inorganic salt may be added in an amount of 0.1 to 5.0 parts by mol based on 100 parts by mol of the barium titanate-based main component powder.

[0024] The heat treatment may be performed at a temperature of 100°C to 300°C.

[0025] The dielectric slurry may further include a subcomponent powder, the subcomponent powder including at least one selected from the group consisting of a dysprosium (Dy)-containing compound, a terbium (Tb)-containing compound, a manganese (Mn)-containing compound, a vanadium (V)-containing compound, a barium (Ba)-containing compound, an aluminum (Al)-containing compound, and a calcium (Ca)-containing compound.

[0026] The amount of the sub-component powder may be 0.01 parts by mol to 5 parts by mol based on 100 parts by mol of the barium titanate-based main component powder.

[0027] According to the embodiment, since the multilayer ceramic capacitor has the dielectric layer in which the additive component is uniformly distributed, high reliability can be ensured even in a thin dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 is a perspective view showing a multilayer ceramic capacitor according to an embodiment.

[0029] Figure 2 is along Figure 1 A cross-sectional view of the multilayer ceramic capacitor taken along line II'.

[0030] Figure 3 is along Figure 1 A cross-sectional view of the multilayer ceramic capacitor taken along line II-II'.

[0031] Figure 4 is a schematic diagram showing the structure of a dielectric layer according to an embodiment.

[0032] Figure 5 is a schematic diagram illustrating a method of preparing dielectric powder according to an embodiment.

[0033] Figure 6 is a schematic diagram illustrating a method of preparing a dielectric layer according to an embodiment.

[0034] Figure 7 is a TEM analysis image of an effective area of ​​the multilayer ceramic capacitor according to Example 1.

[0035] Figure 8 1 and 2 are SEM-EDS line analysis images of a cover portion and an active area of ​​the multilayer ceramic capacitor according to Example 1.

[0036] Fig. 9 1 and 2 are SEM-EDS line analysis images of a cover portion and an active area of ​​a multilayer ceramic capacitor according to Comparative Example 1.

[0037] Fig.10 is a graph showing high temperature stress reliability of the multilayer ceramic capacitor according to Example 1.

[0038] Fig.11 is a graph showing high temperature stress reliability of the multilayer ceramic capacitor according to Comparative Example 1. DETAILED DESCRIPTION

[0039] In the following detailed description, only certain embodiments of the present disclosure are shown and described by way of illustration only. The drawings and descriptions are to be considered illustrative and not restrictive in nature. Throughout the specification, the same reference numerals represent the same elements. In addition, some constituent elements in the drawings may be exaggerated, omitted or schematically shown, and the size of each constituent element does not fully reflect the actual size.

[0040] In addition, the drawings are provided to help easily understand the embodiments disclosed in this specification, and the technical spirit disclosed in this specification is not limited by the drawings, and it should be understood that the present disclosure includes all modifications, equivalents, and alternatives included in the spirit and technical scope of the present disclosure.

[0041] Terms including ordinal numbers such as first and second are used to describe various constituent elements, but the constituent elements are not limited by these terms. These terms are only used to distinguish one constituent element from another constituent element.

[0042] In addition, it should be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element, or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements. In addition, when an element is "on" a reference portion, the element is located above or below the reference portion, and it does not necessarily mean that the element is located "above" or "on" in a direction opposite to the direction of gravity.

[0043] In the present application, it should be understood that the terms "include" and "have" are intended to indicate the presence of the features, quantities, steps, operations, constituent elements, components, or combinations thereof described in the specification, and do not preclude the possibility of the presence or addition of one or more other features, quantities, steps, operations, constituent elements, components, or combinations thereof. Therefore, unless explicitly described to the contrary, the word "include" and its variations (such as "comprises" or "have") will be understood to imply the inclusion of the stated elements but not the exclusion of any other elements.

[0044] Furthermore, throughout the specification, “on a plane” means observing a target component from above, and “on a cross section” means observing a cross section obtained by vertically cutting the target component from the side.

[0045] Furthermore, throughout the specification, “connected” may mean not only that two or more constituent elements are directly connected, but also that two or more constituent elements are indirectly connected, physically connected, electrically connected via another constituent element, or may indicate that two or more constituent elements are integrated even if the two or more constituent elements are referred to by different names according to position and function.

[0046] In the following, reference will be made to Figures 1 to 3 A multilayer ceramic capacitor according to an embodiment is described.

[0047] Figure 1 is a perspective view showing a multilayer ceramic capacitor according to an embodiment, Figure 2 is along Figure 1 A cross-sectional view of a multilayer ceramic capacitor taken along line II', and Figure 3 is along Figure 1 A cross-sectional view of the multilayer ceramic capacitor taken along line II-II'.

[0048] Figures 1 to 3 The L-axis direction, W-axis direction, and T-axis direction shown in represent the length direction, width direction, and thickness direction of the capacitor body 110, respectively. Here, the thickness direction (T-axis direction) may be a direction perpendicular to the wide surface (main surface) of the sheet component, and, for example, may be used as the same concept as the stacking direction of the stacked dielectric layer 111, for example. The length direction (L-axis direction) may be a direction extending in parallel to the wide surface (main surface) of the sheet component, and may be approximately perpendicular to the thickness direction (T-axis direction), and, for example, may be a direction along which the first external electrode 131 and the second external electrode 132 are relative to each other. The width direction (W-axis direction) may be a direction extending in parallel to the wide surface (main surface) of the sheet component, and may be approximately perpendicular to the thickness direction (T-axis direction) and the length direction (L-axis direction), and the length of the sheet component in the length direction (L-axis direction) may be longer than the length of the sheet component in the width direction (W-axis direction).

[0049] Reference Figures 1 to 3 , the multilayer ceramic capacitor 100 according to some embodiments of the present disclosure includes a capacitor body 110 and external electrodes 131 and 132 disposed outside the capacitor body 110. The external electrodes may include a first external electrode 131 and a second external electrode 132 disposed at both ends of the capacitor body 110 that are opposite to each other in the length direction (L-axis direction).

[0050] The capacitor body 110 may have, for example, a substantially hexahedral shape.

[0051] For the convenience of describing the embodiments, the two surfaces of the capacitor body 110 opposite to each other in the thickness direction (T-axis direction) are referred to as the first surface and the second surface, the two surfaces of the capacitor body 110 connected to the first surface and the second surface and opposite to each other in the length direction (L-axis direction) are referred to as the third surface and the fourth surface, and the two surfaces of the capacitor body 110 connected to the first surface and the second surface and connected to the third surface and the fourth surface and opposite to each other in the width direction (W-axis direction) are referred to as the fifth surface and the sixth surface.

[0052] As an example, the first surface as the lower surface may be a mounting surface. In addition, the first to sixth surfaces may be flat, but the embodiment is not limited thereto. For example, the first to sixth surfaces may be curved surfaces with a convex central portion, and the edges at the boundaries of each surface may be rounded.

[0053] The shape and size of the capacitor body 110 and the number of stacked layers of the dielectric layer 111 are not limited to the shape and size and the number of stacked layers shown in the drawings of the present embodiment.

[0054] The capacitor body 110 includes a plurality of dielectric layers 111 and a plurality of internal electrodes 121 and 122. Specifically, the capacitor body 110 includes first internal electrodes 121 and second internal electrodes 122, which are alternately arranged in a thickness direction (T-axis direction) with the dielectric layer 111 interposed therebetween.

[0055] At this time, adjacent dielectric layers of the capacitor body 110 may be integrated so that it is difficult to identify a boundary between the adjacent dielectric layers without using a scanning electron microscope (SEM).

[0056] The capacitor body 110 may have an effective region. The effective region is a region where the dielectric layer 111 and the internal electrodes 121 and 122 are alternately disposed, and is a portion that contributes to the capacitance of the multilayer ceramic capacitor 100. Specifically, the effective region may be a region where the first internal electrode 121 and the second internal electrode 122 stacked in the thickness direction (T-axis direction) are stacked.

[0057] In addition, the capacitor body 110 may further include a cover portion and a side edge portion.

[0058] The cover is an edge portion in the thickness direction and may be located on the upper and lower surfaces of the active area in the thickness direction (T-axis direction). The cover may be formed by stacking a single dielectric layer or two or more dielectric layers on the upper and lower surfaces of the active area.

[0059] The side edge portion may be referred to as a side covering portion (i.e., an edge portion in the width direction), and may be located on both sides of the active region that are opposite to each other in the width direction (W-axis direction), i.e., on the surface of the active region corresponding to the fifth surface and the sixth surface of the capacitor body 110. The side edge portion may be formed by applying the conductive paste for the internal electrode only to a partial area of ​​the dielectric green sheet without applying the conductive paste on both sides of the surface of the dielectric green sheet when applying the conductive paste for the internal electrode on the surface of the dielectric green sheet, stacking the dielectric green sheets, and then firing the stacked dielectric green sheets.

[0060] Both the covering portion and the side margin portion serve to prevent damage to the first and second internal electrodes 121 and 122 due to physical stress or chemical stress.

[0061] In the following, reference will be made to Figure 4 The dielectric layer 111 is described.

[0062] Figure 4 is a schematic diagram showing the structure of a dielectric layer according to some embodiments of the present disclosure.

[0063] Reference Figure 4 , the dielectric layer may include a plurality of dielectric grains 10 and grain boundaries 20 located between adjacent dielectric grains 10 .

[0064] The grain boundary 20 may include a barium titanate-based main component including barium (Ba) and titanium (Ti), and an inorganic element including silicon (Si).

[0065] The barium titanate-based main component may be a dielectric matrix material, may have a high dielectric constant, and may contribute to forming the capacitance of the multilayer ceramic capacitor 100 .

[0066] The barium titanate-based main component may include, for example, at least one selected from the group consisting of BaTiO3, Ba(Ti,Zr)O3, Ba(Ti,Sn)O3, (Ba,Ca)TiO3, (Ba,Ca)(Ti,Ca)O3, (Ba,Ca)(Ti,Zr)O3, (Ba,Ca)(Ti,Sn)O3, (Ba,Sr)TiO3, (Ba,Sr)(Ti,Zr)O3 and (Ba,Sr)(Ti,Sn)O3.

[0067] The inorganic elements may be uniformly distributed in the grain boundaries 20. According to some embodiments, a dielectric powder having an additive component coated on the surface of a barium titanate-based main component may be prepared by adding an additive component (such as an inorganic element in the form of an inorganic salt) to obtain a multilayer ceramic capacitor in which the inorganic elements are uniformly distributed in the dielectric layer 111 (specifically, in the grain boundaries 20).

[0068] Specifically, in the grain boundaries 20, the standard deviation of the atomic % of the inorganic element relative to the total amount of the components of the grain boundaries 20 (hereinafter referred to as the atomic % of the inorganic element) may be 0.20 to 0.80, for example, 0.20 to 0.70. When the standard deviation of the inorganic element content is within this range, the inorganic element such as silicon (Si) can be uniformly distributed in the grain boundaries 20, and thus, a thin multilayer ceramic capacitor with excellent reliability can be ensured.

[0069] The standard deviation (σ) of the atomic % of the inorganic element can be obtained by squaring and summing the deviations of the atomic % and dividing the sum by the number of measurements and taking the square root, i.e., the square root of the average of the squares of the deviations of the atomic % as shown in Formula 1 below.

[0070] [Formula 1]

[0071]

[0072] The standard deviation of the atomic % of the inorganic elements at the grain boundaries 20 can be obtained by transmission electron microscopy-energy dispersive spectroscopy (TEM-EDS) analysis.

[0073] Specifically, a cross-sectional sample can be obtained to observe the effective area of ​​the capacitor body 110 (where the dielectric layer 111 and the internal electrodes 121 and 122 are alternately arranged) in the following manner: the multilayer ceramic capacitor 100 is placed in an epoxy resin mixed solution and cured after being taken out, and then the surface (WT surface) of the capacitor body 110 in the W-axis direction and the T-axis direction is polished to a depth of 1 / 2 along the L-axis direction, and the WT surface is fixed and maintained in a vacuum atmosphere chamber. Next, the effective area of ​​the cross-sectional sample can be measured with a transmission electron microscope (TEM). Xe-FIB (focused ion beam) can be used for measurement under the conditions of an acceleration voltage of 200kV and a magnification of 79k times, and at least one layer of each of the dielectric layer 111 and the internal electrodes 121 and 122 can be measured, for example, one to ten layers. Next, in the measured TEM image of the cross-sectional sample, EDS analysis is performed on at least one point (e.g., 1 to 100 points, 2 to 50 points, or 3 to 30 points) at the grain boundary in the dielectric layer to obtain the standard deviation of the atomic % of the inorganic element.

[0074] The grain boundary 20 may have a barium (Ba)-inorganic element composite phase. Since the barium (Ba)-inorganic element composite phase is formed in the grain boundary 20, firing at a low temperature is possible, and the reliability of the multilayer ceramic capacitor can be improved by improving the grain boundary resistance.

[0075] The grain boundary 20 may further include nickel (Ni). Nickel (Ni) is a component for forming the internal electrodes 121 and 122, and may be a component obtained by being diffused into the dielectric layer 111 after firing.

[0076] In the grain boundary 20, the atomic ratio X / Ni of the inorganic element (X) to nickel (Ni) may be 1.00 to 2.10, for example 1.01 to 1.90. When the atomic ratio X / Ni of the inorganic element (X) to nickel (Ni) is within this range, the reliability of the multilayer ceramic capacitor may be improved.

[0077] In addition, in the grain boundary 20, the atomic ratio X / Ti of the inorganic element (X) to titanium (Ti) may be 0.010 to 0.065, for example 0.015 to 0.064. When the atomic ratio X / Ti of the inorganic element (X) to titanium (Ti) is within this range, the reliability of the multilayer ceramic capacitor may be improved.

[0078] In addition to silicon (Si), the inorganic element may further include at least one selected from the group consisting of magnesium (Mg), lithium (Li), copper (Cu), niobium (Nb), samarium (Sm), and gadolinium (Gd). For example, the inorganic element may further include magnesium (Mg).

[0079] The grain boundary 20 may further include a subcomponent including at least one selected from the group consisting of dysprosium (Dy), terbium (Tb), manganese (Mn), vanadium (V), barium (Ba), aluminum (Al), and calcium (Ca).

[0080] As an example, the subcomponent may include dysprosium (Dy). When the subcomponent includes dysprosium (Dy), in the grain boundary 20, the atomic ratio X / Dy of the inorganic element (X) to dysprosium (Dy) may be 0.10 to 3.00, for example, 0.30 to 2.60. When the atomic ratio of the inorganic element (X) to dysprosium (Dy) is within this range, the reliability of the multilayer ceramic capacitor may be improved.

[0081] The above-mentioned X / Ni atomic ratio, X / Ti atomic ratio and X / Dy atomic ratio can be obtained by transmission electron microscope-energy dispersive spectrometer (TEM-EDS) analysis. Here, since TEM-EDS analysis is the same as the method for measuring the standard deviation of the atomic % of inorganic elements, its description is omitted.

[0082] At least one of the plurality of dielectric grains 10 may have a core-shell structure including a core portion 11 and a shell portion 12 surrounding the core portion 11 .

[0083] The core portion 11 may include a barium titanate-based main component including barium (Ba) and titanium (Ti).

[0084] The shell portion 12 may include a barium titanate-based main component including barium (Ba) and titanium (Ti) and an inorganic element including silicon (Si). When the shell portion includes an inorganic element such as silicon (Si), the reliability of the multilayer ceramic capacitor may be improved.

[0085] The inorganic element included in the shell 12 may include at least one selected from the group consisting of magnesium (Mg), lithium (Li), copper (Cu), niobium (Nb), samarium (Sm), and gadolinium (Gd), in addition to silicon (Si).

[0086] The shell portion 12 may further include a subcomponent including at least one selected from the group consisting of dysprosium (Dy), terbium (Tb), manganese (Mn), vanadium (V), barium (Ba), aluminum (Al), and calcium (Ca).

[0087] According to some embodiments, in a scanning electron microscope-energy dispersive spectrometer (SEM-EDS) line analysis of an active region, the amplitude of a silicon (Si) peak in the dielectric layer 111 may be 8.6 kcps to 25 kcps, for example, 8.6 kcps to 23 kcps. In the SEM-EDS line analysis, if the amplitude of the silicon (Si) peak is within this range, the fluctuation of the peak intensity of silicon (Si) is large, and this means that the content of silicon (Si) in the dielectric layer 111 is high compared to the Si content in the adjacent internal electrodes 121 and 122. This may be the result of preparing and using a dielectric powder in which an additive component (such as an inorganic element) is coated on the surface of a barium titanate-based main component. For reference, when the dielectric layer is formed, the Si present in the internal electrode may be derived from the Si component introduced in the form of an inorganic salt during firing to prepare the dielectric powder.

[0088] The amplitude of the silicon (Si) peak is a value expressed based on the minimum value of the silicon (Si) peak set to zero.

[0089] SEM-EDS line analysis can be performed by the following method. A cross-sectional sample can be obtained to observe the effective area of ​​the capacitor body 110 (where the dielectric layer 111 and the internal electrodes 121 and 122 are alternately arranged) and the covering portion (located on any one of the upper and lower surfaces of the effective area in the thickness direction (T-axis direction)) by placing the multilayer ceramic capacitor 100 in an epoxy resin mixed solution and curing it after taking it out, polishing the surface (WT surface) of the capacitor body 110 in the W-axis direction and the T-axis direction to a depth of 1 / 2 along the L-axis direction, and fixing and maintaining the WT surface in a vacuum atmosphere chamber. Next, a portion of the effective area and a portion of the covering portion of the cross-sectional sample can be measured with a scanning electron microscope (SEM). The SEM uses, for example, a Verios G4 product from Thermofisher Scientific, with measurement conditions of 10 kV and 0.2 nA, a magnification of 50 k times, and can measure at least 1 layer, at least 3 layers, at least 5 layers, or at least 10 layers of the exposed dielectric layer 111 and the internal electrodes 121 and 122. Next, in the SEM image of the measured cross-sectional sample, in a line passing through at least two layers (for example, 2 to 10 layers) of dielectric layers and internal electrodes from the cover to the active area, EDS analysis is performed on at least one (for example, 1 to 100, 2 to 50, and 3 to 30) points in the dielectric layer 111 to obtain the amplitude of the silicon (Si) peak in the dielectric layer.

[0090] The average thickness (average length in the T-axis direction) of the dielectric layer 111 may be 0.3 μm to 8.0 μm, for example 0.5 μm to 7.8 μm. When the average thickness of the dielectric layer 111 is within this range, the reliability of the multilayer ceramic capacitor is excellent.

[0091] The average thickness of the dielectric layer 111 can be measured by placing the multilayer ceramic capacitor 100 in an epoxy resin mixed solution and curing it after taking it out, polishing the multilayer ceramic capacitor 100, and then ion milling the multilayer ceramic capacitor 100, and analyzing it by scanning electron microscopy (SEM). SEM uses, for example, the Verios G4 product from Thermo Fisher Scientific, the measurement conditions are 10kV and 0.2nA, the magnification can be 100 times, and at least 1 layer, at least 3 layers, at least 5 layers, or at least 10 layers of the exposed dielectric layer 111 can be measured. In the SEM image, the center point of the dielectric layer 111 in the length direction (L axis direction) or the width direction (W axis direction) is set as a reference point, and the arithmetic mean of the thickness of the dielectric layer 111 can be obtained at 10 points spaced apart from the reference point by a predetermined interval. The intervals between the 10 points can be adjusted according to the scale of the SEM image, and can be, for example, 1 μm to 100 μm, 1 μm to 50 μm, or 1 μm to 10 μm. At this time, all of the 10 points need to be located in the dielectric layer 111, and if the 10 points are not all located in the dielectric layer 111, the position of the reference point can be changed or the intervals between the 10 points can be adjusted.

[0092] The first internal electrode 121 and the second internal electrode 122 are electrodes having different polarities and are alternately arranged opposite to each other along the T-axis direction with the dielectric layer 111 interposed therebetween, and one end of the first internal electrode 121 and one end of the second internal electrode 122 may be exposed through the third surface and the fourth surface of the capacitor body 110, respectively.

[0093] The first and second internal electrodes 121 and 122 may be electrically insulated from each other by the dielectric layer 111 disposed therebetween.

[0094] Ends of the first and second internal electrodes 121 and 122 alternately exposed through the third and fourth surfaces of the capacitor body 110 may contact and be electrically connected to the first and second external electrodes 131 and 132 , respectively.

[0095] The first and second internal electrodes 121 and 122 may include a conductive metal, for example, a metal such as Ni, Cu, Ag, Pd, Au, or an alloy thereof such as an Ag—Pd alloy.

[0096] In addition, the first and second internal electrodes 121 and 122 may further include dielectric particles including the same composition as the ceramic material included in the dielectric layer 111 .

[0097] The first and second internal electrodes 121 and 122 may be formed using a conductive paste including a conductive metal. A printing method of the conductive paste may be a screen printing method or a gravure printing method.

[0098] The average thickness of the first and second internal electrodes 121 and 122 may be 0.1 μm to 2 μm. The average thickness of the first and second internal electrodes 121 and 122 may be measured by scanning electron microscope (SEM) analysis. Here, since the SEM analysis is the same as the above-mentioned method for measuring the average thickness of the dielectric layer 111, its detailed description is omitted.

[0099] The capacitor body 110 may be formed by firing a laminated body in which a plurality of dielectric layers 111 and a plurality of internal electrodes 121 and 122 are laminated.

[0100] The first and second external electrodes 131 and 132 are supplied with voltages of different polarities, and contact and are electrically connected to exposed portions of the first and second internal electrodes 121 and 122 , respectively.

[0101] According to the above configuration, when a predetermined voltage is applied to the first external electrode 131 and the second external electrode 132, charges are accumulated between the first internal electrode 121 and the second internal electrode 122 facing each other. At this time, the capacitance of the multilayer ceramic capacitor 100 is proportional to the overlapping area of ​​the first internal electrode 121 and the second internal electrode 122 overlapping each other in the T-axis direction in the active region.

[0102] The first outer electrode 131 may include a first connecting portion and a first band portion, and the second outer electrode 132 may include a second connecting portion and a second band portion, the first connecting portion is arranged on the third surface of the capacitor body 110 to be connected to the first inner electrode 121, the second connecting portion is arranged on the fourth surface of the capacitor body 110 to be connected to the second inner electrode 122, the first band portion is arranged at the edge where the third surface of the capacitor body 110 intersects with the first surface and the second surface and / or the fifth surface and the sixth surface, and the second band portion is arranged at the edge where the fourth surface of the capacitor body 110 intersects with the first surface and the second surface and / or the fifth surface and the sixth surface.

[0103] The first and second band portions may extend from the first and second connecting portions, respectively, to a portion of the first and second surfaces and / or a portion of the fifth and sixth surfaces of the capacitor body 110. The first and second band portions may be used to increase the bonding strength between the first and second external electrodes 131 and 132 and the capacitor body 110.

[0104] The first and second external electrodes 131 and 132 may each include a sintered metal layer contacting the capacitor body 110 , a conductive resin layer disposed to cover the sintered metal layer, and a plated layer disposed to cover the conductive resin layer.

[0105] The sintered metal layer may include conductive metal and glass.

[0106] The conductive metal may include at least one selected from the group consisting of copper (Cu), nickel (Ni), silver (Ag), palladium (Pd), gold (Au), platinum (Pt), tin (Sn), tungsten (W), titanium (Ti), lead (Pb), and alloys thereof. For example, the conductive metal may include copper (Cu) or a copper (Cu) alloy. When the conductive metal includes copper, a metal other than copper may be included in an amount of 5 mol parts or less based on 100 mol parts of copper.

[0107] The glass may include a composition having a mixed oxide, such as one or more selected from the group consisting of silicon oxide, boron oxide, aluminum oxide, transition metal oxide, alkali metal oxide, and alkaline earth metal oxide. The transition metal may be one or more selected from the group consisting of zinc (Zn), titanium (Ti), copper (Cu), vanadium (V), manganese (Mn), iron (Fe), and nickel (Ni), the alkali metal may be one or more selected from the group consisting of lithium (Li), sodium (Na), and potassium (K), and the alkaline earth metal may be one or more selected from the group consisting of magnesium (Mg), calcium (Ca), strontium (Sr), and barium (Ba).

[0108] Alternatively, the conductive resin layer is formed on the sintered metal layer and, for example, may be formed to completely cover the sintered metal layer. In addition, the first and second external electrodes 131 and 132 may not include the sintered metal layer, and in this case, the conductive resin layer may directly contact the capacitor body 110 .

[0109] The conductive resin layer extends to the first and second surfaces and / or the fifth and sixth surfaces of the capacitor body 110, and the length of the region (i.e., the band portion) of the conductive resin layer extending to the first and second surfaces and / or the fifth and sixth surfaces of the capacitor body 110 may be greater than the length of the region (i.e., the band portion) of the sintered metal layer extending to the first and second surfaces and / or the fifth and sixth surfaces of the capacitor body 110. The conductive resin layer is formed on the sintered metal layer and may be formed to completely cover the sintered metal layer.

[0110] The conductive resin layer may include resin and conductive metal.

[0111] The resin included in the conductive resin layer is not particularly limited as long as the resin has adhesion and impact absorption properties and can be mixed with the conductive metal powder to form a paste, for example, the resin may include phenolic resin, acrylic resin, silicone resin, epoxy resin or polyimide resin.

[0112] The conductive metal included in the conductive resin layer may serve to electrically connect with the first and second internal electrodes 121 and 122 or the sintered metal layer.

[0113] The conductive metal included in the conductive resin layer may have a spherical shape, a flake shape, or a combination thereof. That is, the conductive metal may be formed only in a flake shape or a spherical shape, or may also be formed in a mixed form of a flake shape and a spherical shape.

[0114] Here, the spherical shape may also include a shape that is not a perfect sphere, for example, a shape in which the length ratio of the major axis to the minor axis (major axis / minor axis) is 1.45 or less. The flake shape refers to a flat and elongated shape, and is not particularly limited, for example, the length ratio of the major axis to the minor axis (major axis / minor axis) may be greater than or equal to 1.95.

[0115] The first and second external electrodes 131 and 132 may further include a plating layer disposed outside the conductive resin layer.

[0116] The plating layer may include at least one selected from the group consisting of nickel (Ni), copper (Cu), tin (Sn), palladium (Pd), platinum (Pt), gold (Au), silver (Ag), tungsten (W), titanium (Ti), lead (Pb) and alloys thereof. For example, the plating layer may be a nickel (Ni) plating layer or a tin (Sn) plating layer, or may be a nickel (Ni) plating layer and a tin (Sn) plating layer stacked in sequence, or may be a tin (Sn) plating layer, a nickel (Ni) plating layer and a tin (Sn) plating layer stacked in sequence. In addition, the plating layer may also include a plurality of nickel (Ni) plating layers and / or a plurality of tin (Sn) plating layers.

[0117] The plating layer may improve the mountability to a substrate, structural reliability, durability to the outside, heat resistance, and equivalent series resistance (ESR) of the multilayer ceramic capacitor 100 .

[0118] Hereinafter, a method of manufacturing the multilayer ceramic capacitor 100 according to the embodiment will be described.

[0119] The multilayer ceramic capacitor 100 according to the embodiment can be manufactured by: preparing a dielectric powder in which the surface of a barium titanate-based main component powder including barium (Ba) and titanium (Ti) is coated with an inorganic element including silicon (Si); preparing a dielectric green sheet using a dielectric slurry including the dielectric powder, and forming a conductive paste layer on the surface of the dielectric green sheet; preparing a dielectric green sheet laminate by stacking the dielectric green sheets on which the conductive paste layer is formed; preparing a capacitor body including a dielectric layer and an inner electrode by firing the dielectric green sheet laminate; and forming an outer electrode on the surface of the capacitor body.

[0120] First, refer to Figure 5 The steps for preparing dielectric powders are described.

[0121] Figure 5 is a schematic diagram illustrating a method of preparing dielectric powder according to an embodiment.

[0122] Reference Figure 5 A dielectric powder in which the surface of a barium titanate-based main component powder is coated with an inorganic element including silicon (Si) can be prepared by: performing hydrothermal synthesis of the barium titanate-based main component powder to complete grain growth; after completing the grain growth, adding an inorganic salt containing silicon (Si); and performing heat treatment after adding the inorganic salt.

[0123] The hydrothermal synthesis of the barium titanate-based main component powder can be carried out by mixing a titanium (Ti) precursor (such as oxides, hydroxides, chlorides and nitrates of titanium (Ti)) and a barium (Ba) precursor (such as oxides, hydroxides, chlorides and nitrates of barium (Ba)) with an aqueous solvent, and then reacting the mixture under high temperature and high pressure.

[0124] According to some embodiments, in the process of synthesizing barium titanate-based main component powder in an aqueous solvent, an inorganic salt is added separately after grain growth is completed, so that no additional additives need to be processed and the processing time can be shortened. In addition, when heat treatment is performed at high temperature and high pressure, a barium (Ba)-inorganic element composite phase is formed, and the inorganic element can be uniformly coated on the surface of the barium titanate-based main component powder.

[0125] The titanium (Ti) precursor and the barium (Ba) precursor may be mixed in a molar ratio of 1:0.5 to 1:1.5.

[0126] The high temperature and high pressure may be performed at a pressure of 0.5 MPa to 10 MPa and a temperature of 150°C to 300°C.

[0127] After the grain growth of the barium titanate-based main component powder is completed by hydrothermal synthesis, an inorganic salt containing silicon (Si) may be added.

[0128] In addition to silicon (Si), the inorganic salt may further include at least one selected from the group consisting of magnesium (Mg), lithium (Li), copper (Cu), niobium (Nb), samarium (Sm), and gadolinium (Gd). For example, the inorganic salt may further include magnesium (Mg).

[0129] The inorganic salt may include an alkoxide-based compound including an inorganic element such as silicon (Si). For example, the inorganic salt may include tetraethyl orthosilicate (TEOS), etc. The alkoxide-based compound may be stably hydrolyzed.

[0130] After the grain growth is completed, an inorganic salt (especially an alkoxide-based compound containing an inorganic element) is added to an aqueous solution in which the barium titanate-based main component powder is dispersed and heat-treated, so that a coating can be formed on the surface of the barium titanate-based main component powder through the dissolution and reprecipitation process of the inorganic element (as an additive component).

[0131] Specifically, when an inorganic salt is added to an aqueous solution in which a barium titanate-based main component powder is dispersed, after a hydrolysis reaction of the inorganic salt (particularly an alkoxide-based compound containing an inorganic element), reactants of silicon oxide with barium (Ba) ions and titanium (Ti) ions can be precipitated on the surface of the barium titanate-based main component powder through a polymerization reaction and a neutralization reaction, thereby forming a coating.

[0132] The formed coating layer can serve as a dispersion path for the secondary components such as dysprosium (Dy), thereby improving the dispersion characteristics of the additive and helping to form a shell in which the additive is uniformly distributed. For example, a uniform additive dispersion layer can be formed on the coating layer.

[0133] Based on 100 molar parts of the barium titanate-based main component powder, the inorganic salt can be added in an amount of 0.1 to 5.0 molar parts (e.g., 0.4 to 3.3 molar parts). When the inorganic salt is added in this content range, the inorganic element can be easily coated on the surface of the barium titanate-based main component powder.

[0134] After the inorganic salt is added, heat treatment may be performed at a temperature for grain growth of the barium titanate-based main component powder or at a lower temperature. For example, heat treatment may be performed at a temperature of 100° C. to 300° C. (e.g., 150° C. to 250° C.). When heat treatment is performed within this temperature range, polymerization reaction and neutralization reaction occur smoothly after the hydrolysis reaction, so that the inorganic element can be easily coated on the surface of the barium titanate-based main component powder.

[0135] Figure 6 is a schematic diagram illustrating a method of preparing a dielectric layer according to an embodiment.

[0136] Reference Figure 6, a dielectric layer can be formed by a dielectric slurry including the prepared dielectric powder through a firing process. The formed dielectric layer includes dielectric grains having a core-shell structure and grain boundaries between adjacent dielectric grains. By using the dielectric powder prepared according to the embodiment, that is, a dielectric powder in which the surface of the barium titanate-based main component is coated with an inorganic element containing silicon (Si), damage to the core can be minimized, and the concentration of the inorganic element in the grain boundary can be increased. Therefore, a thin multilayer ceramic capacitor with excellent reliability can be prepared.

[0137] The dielectric slurry may further include a subcomponent powder, the subcomponent powder including at least one selected from the group consisting of a dysprosium (Dy)-containing compound, a terbium (Tb)-containing compound, a manganese (Mn)-containing compound, a vanadium (V)-containing compound, a barium (Ba)-containing compound, an aluminum (Al)-containing compound, and a calcium (Ca)-containing compound.

[0138] The subcomponent powder may include an oxide, a nitride, or a salt compound, or may be used in the form of a sol dispersed in an organic solvent.

[0139] Based on 100 parts by mole of the barium titanate-based main component powder, the auxiliary component powder may be included in an amount of 0.01 to 5 parts by mole (e.g., 0.1 to 3 parts by mole). When the auxiliary component powder is included within this content range, a thin multilayer ceramic capacitor with excellent reliability can be prepared.

[0140] The dielectric slurry may be prepared by additionally mixing a solvent and additives such as a dispersant, a binder, a plasticizer, a lubricant, and an antistatic agent.

[0141] The dispersant may include, for example, a phosphate dispersant, a polycarboxylic acid dispersant, or a combination thereof. Based on 100 parts by weight of the barium titanate-based main component powder, the dispersant may be mixed in an amount of 0.1 to 5 parts by weight (e.g., 0.3 to 3 parts by weight). When the dispersant is mixed within this content range, the dispersibility of the dielectric slurry is excellent, and the amount of impurities included in the prepared dielectric layer can be reduced.

[0142] The binder may include, for example, acrylic resin, polyvinyl butyl resin, polyvinyl acetal resin, ethyl cellulose resin, etc. The binder may be added in an amount of 0.1 to 50 parts by weight, for example, 3 to 30 parts by weight, based on 100 parts by weight of the barium titanate-based main component powder. When the binder is mixed within this content range, the dispersibility of the dielectric slurry is excellent, and the amount of impurities included in the prepared dielectric layer can be reduced.

[0143] For example, the plasticizer may include: phthalic acid compounds such as dioctyl phthalate, benzyl butyl phthalate, dibutyl phthalate, dihexyl phthalate, di(2-ethylhexyl) phthalate and di(2-ethylbutyl) phthalate; adipic acid compounds such as dihexyl adipate and di(2-ethylhexyl) adipate; glycol compounds such as ethylene glycol, diethylene glycol and triethylene glycol; glycol ester compounds such as triethylene glycol dibutyrate, triethylene glycol di(2-ethyldibutyrate) and triethylene glycol di(2-ethylhexanoate), etc. Based on 100 parts by weight of the barium titanate-based main component powder, the plasticizer may be added in an amount of 0.1 to 20 parts by weight, for example, 1 to 10 parts by weight. When the plasticizer is mixed within this content range, dispersibility of the dielectric slurry is excellent, and the amount of impurities included in the prepared dielectric layer may be reduced.

[0144] The solvent may be an aqueous solvent such as water; an alcohol solvent such as ethanol, methanol, benzyl alcohol and methoxyethanol; an ethylene glycol solvent such as ethylene glycol and diethylene glycol; a ketone solvent such as acetone, methyl ethyl ketone, methyl isobutyl ketone and cyclohexanone; an ester solvent such as butyl acetate, ethyl acetate, carbitol acetate and butyl carbitol acetate; an ether solvent such as methyl cellosolve, ethyl cellosolve, butyl ether and tetrahydrofuran; an aromatic solvent such as benzene, toluene and xylene. For example, in consideration of the solubility and dispersibility of various additives included in the dielectric slurry, the solvent may include an alcohol solvent or an aromatic solvent. Based on 100 parts by weight of the barium titanate-based main component powder, the solvent may be mixed in an amount of 50 parts by weight to 1000 parts by weight, for example, in an amount of 100 parts by weight to 500 parts by weight. When the solvent is mixed within this content range, the dielectric slurry components can be fully mixed, and thereafter, removal of the solvent is easy.

[0145] A wet ball mill or a stirring mill may be used to mix the dielectric slurry coating containing the dielectric powder (in which the surface of the barium titanate-based main component powder is coated with an inorganic element). When zirconia balls are used in a wet ball mill, a plurality of zirconia balls having a diameter of 0.1 mm to 10 mm may be used for wet mixing for 8 to 48 hours, or 10 to 24 hours.

[0146] The prepared dielectric slurry is formed into a dielectric layer after firing.

[0147] The method of forming the prepared dielectric slurry into a sheet shape may use a belt molding method such as a doctor blade method and a calendar roll method such as a roll-on molding coater of a head discharge method, and then a dielectric green sheet may be obtained by drying the molded body.

[0148] In order to form a conductive paste layer that becomes an internal electrode after firing, the conductive paste can be prepared by mixing a conductive powder including a conductive metal or its alloy, a binder and a solvent. In addition, if necessary, barium titanate powder as a common material can be mixed together. The common material can be used to suppress the sintering of the conductive powder during the firing process. The conductive paste layer is formed by applying the conductive paste to the surface of the dielectric green sheet in a predetermined pattern using various printing methods such as screen printing or transfer printing.

[0149] The conductive powder may include nickel (Ni) or a nickel (Ni) alloy.

[0150] Next, a dielectric green sheet laminate is prepared by laminating the dielectric green sheets on which the internal electrode patterns are formed into a plurality of layers and then pressing the dielectric green sheets in the laminating direction. At this time, the dielectric green sheets may be laminated so that the dielectric green sheets are located on the upper and lower surfaces of the dielectric green sheet laminate in the laminating direction.

[0151] An operation of cutting the prepared dielectric green sheet laminate into a predetermined size by dicing or the like may be selectively performed.

[0152] Furthermore, if necessary, the dielectric green sheet stack may be cured and dried to remove the plasticizer and the like, and after curing and drying, the dielectric green sheet stack may be drum polished using a horizontal centrifugal drum machine and the like. In drum polishing, the dielectric green sheet stack is added to a drum container together with a medium and a polishing liquid, and unnecessary portions such as burrs generated during cutting may be polished by applying a rotational motion or vibration to the drum container. Furthermore, after drum polishing, the dielectric green sheet stack may be washed with a cleaning solution such as water and dried.

[0153] Subsequently, the dielectric green sheet stack may be degreased and fired to prepare a capacitor body.

[0154] The degreasing conditions may be appropriately adjusted according to the composition of the dielectric layer or the composition of the inner electrode. For example, the heating rate during degreasing may be 5°C / hour to 300°C / hour, the carrier temperature may be 180°C to 400°C, and the temperature holding time may be 0.5 hour to 24 hours. The atmosphere during degreasing may be air or a reducing atmosphere.

[0155] The firing conditions may be appropriately adjusted according to the main component composition of the dielectric layer or the main component composition of the inner electrode. For example, the firing may be performed at a temperature of 1100° C. to 1400° C., for example, at a temperature of 1200° C. to 1350° C. The firing may also be performed for 0.5 hours to 8 hours, for example, 1 hour to 3 hours. In addition, the firing may be performed in a reducing atmosphere, for example, in a humidified atmosphere of a mixed gas of nitrogen and hydrogen. When the inner electrode includes nickel (Ni) or a nickel (Ni) alloy, the oxygen partial pressure in the firing atmosphere may be 1.0×10 -14MPa to 1.0×10 -10 MPa.

[0156] After firing, annealing may be performed as needed. Annealing is a process for reoxidizing the dielectric layer, and may be performed when the dielectric layer is fired in a reducing atmosphere. The annealing conditions may also be appropriately adjusted according to the composition of the dielectric layer. For example, the temperature during annealing may be 950°C to 1150°C, the annealing time may be 0 hours (greater than 0 hours) to 20 hours, and the heating rate may be 50°C / hour to 500°C / hour. The annealing atmosphere may be a humidified nitrogen (N2) atmosphere, and the oxygen partial pressure may be 1.0×10 -9 MPa to 1.0×10 -5 MPa.

[0157] In degreasing, firing, or annealing, for example, nitrogen or mixed gas may be humidified using a wetting agent or the like, and in this case, the water temperature may be 5° C. to 75° C. Degreasing, firing, and annealing may be performed continuously or independently.

[0158] Optionally, the third surface and the fourth surface of the prepared capacitor body 110 may be subjected to surface treatment such as sandblasting, laser irradiation, barrel polishing, etc. By performing this surface treatment, the end of the first inner electrode and the end of the second inner electrode may be exposed to the third surface and the fourth surface, respectively, and thus, the electrical connection between the first outer electrode and the first inner electrode and the electrical connection between the second outer electrode and the second inner electrode become good, and an alloy portion may be easily formed.

[0159] Next, external electrodes are formed on the surface of the prepared capacitor body 110 .

[0160] As an example, a paste for forming a sintered metal layer may be applied to the external electrode and then sintered to form the sintered metal layer.

[0161] The paste forming the sintered metal layer may include a conductive metal and glass.

[0162] Since the description of the conductive metal and the glass is the same as above, the repeated description thereof is omitted. In addition, the paste forming the sintered metal layer may selectively include a binder, a solvent, a dispersant, a plasticizer, an oxide powder, etc. The binder may be, for example, ethyl cellulose, acrylic acid, butyral, etc., and the solvent may be, for example, an organic solvent (such as terpineol, butyl carbitol, ethanol, methyl ethyl ketone, acetone, toluene, etc.) or an aqueous solvent.

[0163] The method of coating the paste forming the sintered metal layer on the surface of the capacitor body 110 may use a dipping method, various printing methods such as a screen printing method, a coating method using a dispenser, and a spraying method using a sprayer. The paste forming the sintered metal layer is applied to at least the third and fourth surfaces of the capacitor body 110, and may be selectively applied to at least a portion of the first, second, fifth, or sixth surfaces on which the band portions of the first and second external electrodes are formed.

[0164] Thereafter, the capacitor body 110 on which the paste for forming the sintered metal layer is applied is dried and sintered at a temperature of 700° C. to 1000° C. for 0.1 to 3 hours to form a sintered metal layer.

[0165] Optionally, a conductive resin layer forming paste may be applied to the outer surface of the obtained capacitor body 110 and then cured to form a conductive resin layer.

[0166] The paste forming the conductive resin layer may include resin and conductive metal, and optionally include non-conductive filler. Since the description of conductive metal and resin is the same as above, its repeated description is omitted. In addition, the paste forming the conductive resin layer may optionally include adhesive, solvent, dispersant, plasticizer, oxide powder, etc. The adhesive may be, for example, ethyl cellulose, acrylic acid, butyral, etc., and the solvent may be an organic solvent (such as terpineol, butyl carbitol, ethanol, methyl ethyl ketone, acetone, toluene, etc.) or an aqueous solvent.

[0167] For example, the method of forming the conductive resin layer may include: immersing the capacitor body 110 in a paste for forming the conductive resin layer, and then curing the paste for forming the conductive resin layer to form the conductive resin layer; or printing the paste for forming the conductive resin layer on the surface of the capacitor body 110 by screen printing, gravure printing, etc.; or coating the paste for forming the conductive resin layer on the surface of the capacitor body 110, and then curing.

[0168] Next, a plating layer is formed on the outer side of the conductive resin layer.

[0169] For example, the plated layer may be formed by a plating method, or may also be formed by a sputtering method or an electrolytic plating (electrodeposition) method.

[0170] The above embodiments will be described in more detail by the following examples. However, the following examples are only for illustrative purposes and do not limit the scope of the present disclosure.

[0171] (Preparation of Multilayer Ceramic Capacitors)

[0172] Examples 1 to 3

[0173] Titanium hydroxide and barium hydroxide are mixed in a molar ratio of 1:1.1 and subjected to a hydrothermal reaction at a pressure of 4 MPa and a temperature of 250°C to complete the grain growth of barium titanate (BaTiO3) powder. Based on 100 molar parts of barium titanate powder, 0.8 molar parts of tetraethyl orthosilicate (TEOS) are added to an aqueous solution in which the barium titanate powder in which the grain growth is completed is dispersed. Next, a heat treatment is performed at a temperature of 200°C for 2 hours to prepare a dielectric powder in which the surface of the barium titanate-based main component powder is coated with Si.

[0174] A dielectric slurry was prepared by mixing the prepared dielectric powder with 0.8 mol parts of dysprosium oxide (Dy2O3) relative to 100 mol parts of barium titanate powder.

[0175] The mixing was performed by using zirconium oxide balls (ZrO2 balls) as a dispersion medium, adding ethanol / toluene and polyvinyl butyral (PVB) resin as a wetting dispersant and a binder, and then mechanically grinding.

[0176] A dielectric green sheet was prepared from the prepared dielectric slurry using a roll-up coater of a die-discharging type.

[0177] A dielectric green sheet laminate (width×length×height=3.2 mm×2.5 mm×2.5 mm) was prepared by printing a conductive paste containing nickel (Ni) on the surface of a dielectric green sheet to form a conductive paste layer, and laminating and pressing the dielectric green sheets formed with the conductive paste layer.

[0178] The dielectric green sheet laminate was degreased in a nitrogen atmosphere at 400°C or less and fired at a temperature of 1300°C or less and a hydrogen (H2) concentration of 1.0% or less to prepare a capacitor body. For reference, Examples 1 to 3 prepared capacitor bodies by firing at a firing temperature of 1150°C to 1170°C, specifically, firing at 1150°C, 1160°C, and 1170°C, respectively.

[0179] Next, external electrodes are formed through a process such as plating to prepare a multilayer ceramic capacitor.

[0180] Comparative Examples 1 to 4

[0181] Titanium hydroxide and barium hydroxide were mixed in a molar ratio of 1:1.1, hydrothermally reacted at a pressure of 4 MPa and a temperature of 250°C, and then dried to prepare barium titanate (BaTiO3) powder.

[0182] The dielectric slurry is prepared by mixing the prepared barium titanate powder with silicon dioxide (SiO2) and dysprosium oxide (Dy2O3) as auxiliary component powders. At this time, based on 100 molar parts of barium titanate powder, silicon dioxide (SiO2) and dysprosium oxide (Dy2O3) are mixed in 0.8 molar parts and 0.8 molar parts, respectively. Mixing is performed in the following manner: using zirconium oxide balls (ZrO2 balls) as a dispersion medium, adding ethanol / toluene and polyvinyl butyral (PVB) resin as a wetting dispersant and a binder, and then mechanically grinding.

[0183] A multilayer ceramic capacitor was manufactured using the prepared dielectric slurry in the same manner as Example 1. At this time, Comparative Examples 1 to 4 prepared capacitor bodies by firing at a firing temperature of 1150° C. to 1180° C., specifically, the capacitor bodies were prepared at 1150° C., 1160° C., 1170° C., and 1180° C., respectively.

[0184] Assessment 1: TEM-EDS analysis

[0185] The multilayer ceramic capacitors manufactured in Examples 1 to 3 and Comparative Examples 1 to 4 were subjected to transmission electron microscopy-energy dispersive spectroscopy (TEM-EDS) analysis, and the results are shown in FIG. Figure 7 and Table 1.

[0186] TEM-EDS analysis was performed by the following method. A cross-sectional sample can be obtained to observe the effective area where the dielectric layers and the internal electrodes are alternately arranged in the following manner: the multilayer ceramic capacitors prepared in Examples 1 to 3 and Comparative Examples 1 to 4 are placed in an epoxy resin mixed solution and cured after being taken out, and then the surface (WT surface) of the capacitor body in the W-axis direction and the T-axis direction is polished to a depth of 1 / 2 along the L-axis direction, and the WT surface is fixed and maintained in a vacuum atmosphere chamber. In the effective area of ​​the cross-sectional sample, the three dielectric layers and two internal electrodes exposed in the center are measured using TEM. The measurement was performed using a Xe-FIB (focused ion beam) under the conditions of an acceleration voltage of 200kV and a magnification of 79k. The measured image of Example 1 is shown in Figure 7 middle.

[0187] In the TEM image of the measured cross-sectional sample, seven random points at the grain boundary in the dielectric layer were subjected to EDS analysis, and the standard deviation of the atomic % of Si, the atomic ratio of Si / Ti, the atomic ratio of Si / Ni, and the atomic ratio of Si / Dy were calculated and shown in the following Table 1. Here, the standard deviation of the atomic % of Si represents the standard deviation of the atomic % of Si relative to the total amount of the grain boundary component, and the standard deviation is the square root of the average of the squares of the deviations.

[0188] Figure 7 is a TEM image of an active region of the multilayer ceramic capacitor according to Example 1.

[0189] (Table 1)

[0190]

[0191] From Table 1, it can be seen that in Examples 1 to 3 using dielectric powders having silicon (Si) coated on the surface of barium titanate powder according to the embodiment, the standard deviation of the atomic % of Si has a value in the range of 0.20 to 0.80, compared with Comparative Examples 1 to 4. From these results, it can be seen that the dielectric layer of the multilayer ceramic capacitor according to the embodiment has an inorganic element uniformly distributed on the surface of barium titanate (BT) within the grain boundary. For example, Figure 7 It can be seen that the relatively brighter part is the inorganic elements on the surface of barium titanate uniformly distributed within the grain boundary.

[0192] Assessment 2: SEM-EDS line analysis

[0193] The multilayer ceramic capacitors manufactured in Example 1 and Comparative Example 1 were subjected to scanning electron microscope-energy dispersive spectroscopy (SEM-EDS) line analysis, and the results are shown in Figure 8 and Fig. 9 And Table 2.

[0194] SEM-EDS line analysis is performed by the following method. A cross-sectional sample can be obtained to observe the effective area (where the dielectric layer and the internal electrode are alternately arranged) and the covering portion (located on either the upper surface or the lower surface of the effective area in the thickness direction (T-axis direction)) by placing the multilayer ceramic capacitor in an epoxy resin mixed solution and curing it after taking it out, and then polishing the surface of the capacitor body in the W-axis direction and the T-axis direction (WT surface) along the L-axis direction to a depth of 1 / 2, and fixing and maintaining the WT surface in a vacuum atmosphere chamber. Next, the five internal electrodes in the effective area and the dielectric layer located between the internal electrodes from the exposed covering portion of the cross-sectional sample are measured by a scanning electron microscope (SEM). The SEM uses, for example, the Verios G4 product from Thermo Fisher Scientific, with measurement conditions of 10kV and 0.2nA and a magnification of 50k times. Next, in the SEM image of the measured cross-sectional sample, refer to Figure 8 and Fig. 9 , in a line passing through five internal electrodes and the dielectric layer from the cover to the active area, seven points in the dielectric layer (corresponding to #1 to #7 in Table 2 below) were subjected to EDS analysis to calculate the amplitude of the silicon (Si) peak in the dielectric layer. In Table 2 below, the unit of the amplitude is kcps, and the minimum value of the silicon (Si) peak is designated as 0 as a reference value.

[0195] Figure 8is a SEM-EDS line analysis image of the cover portion and the active area of ​​the multilayer ceramic capacitor according to Example 1, Fig. 9 1 and 2 are SEM-EDS line analysis images of a cover portion and an active area of ​​a multilayer ceramic capacitor according to Comparative Example 1.

[0196] (Table 2)

[0197] Example 1 Comparative Example 1 #1 21 8.5 #2 21.5 3.5 #3 8.6 5 #4 11.5 3 #5 14.5 2 #6 16 4 #7 16.5 5.5

[0198] like Figure 8 and Fig. 9 As shown in Table 2, it can be seen that in Example 1 using the dielectric powder in which silicon (Si) is coated on the surface of the barium titanate powder according to the embodiment, the amplitude of the silicon (Si) peak in the dielectric layer satisfies the range of 8.6 kcps to 25 kcps, compared with Comparative Example 1. This means that the peak intensity of silicon (Si) fluctuates greatly, and therefore, it can be seen that the silicon (Si) content in the dielectric layer is greater than the Si content in the adjacent internal electrode.

[0199] Assessment 3: Reliability

[0200] The high temperature stress reliability (HALT) of the multilayer ceramic capacitors manufactured in Example 1 and Comparative Example 1 was measured, and the results are shown in FIG. Fig.10 and Fig.11 middle.

[0201] Specifically, each multilayer ceramic capacitor manufactured in Example 1 and Comparative Example 1 was prepared and mounted on a measurement substrate, and high temperature stress reliability (HALT) was measured under the conditions of 105° C., 12 hours, and 2 Vr using an ESPEC (PV-222, HALT) device.

[0202] Fig.10 is a graph showing high temperature stress reliability of the multilayer ceramic capacitor according to Example 1, Fig.11 is a graph showing high temperature stress reliability of the multilayer ceramic capacitor according to Comparative Example 1.

[0203] Reference Fig.10 and Fig.11 , it can be seen that, compared with Comparative Example 1, in Example 1 in which the standard deviation of the atomic % of the inorganic element of Si has a value in the range of 0.20 to 0.80, the distribution characteristics of the insulation resistance (IR) are excellent, and thus the high temperature stress reliability is excellent.

[0204] While the present disclosure has been described in connection with what are presently considered to be practical embodiments, it should be understood that the present disclosure is not limited to the disclosed embodiments, but is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

[0205] <Description of Reference Numerals>

[0206] 100: Multilayer ceramic capacitors

[0207] 110: Capacitor body

[0208] 111: Dielectric layer

[0209] 121: First inner electrode

[0210] 122: Second inner electrode

[0211] 131: First outer electrode

[0212] 132: Second outer electrode

[0213] 10: Dielectric particles

[0214] 11: Nuclear Department

[0215] 12: Shell

[0216] 20: Grain Boundary

Claims

1. A multilayer ceramic capacitor comprising: a capacitor body including a dielectric layer and inner electrodes; as well as An external electrode, disposed outside the capacitor body, The dielectric layer includes a plurality of dielectric grains and grain boundaries between adjacent dielectric grains. The grain boundaries include a barium titanate-based main component including barium and titanium and an inorganic element including silicon, and The standard deviation of the atomic % of the inorganic element relative to the total amount of the components of the grain boundaries is 0.20 to 0.80, and the standard deviation is a square root of an average of squares of the deviations.

2. The multilayer ceramic capacitor according to claim 1, wherein: The grain boundaries have a barium-inorganic element composite phase.

3. The multilayer ceramic capacitor of claim 1, wherein: The grain boundaries also include nickel, and In the grain boundaries, an atomic ratio of the inorganic element to nickel is 1.00 to 2.

10.

4. The multilayer ceramic capacitor of claim 1, wherein: In the grain boundary, the atomic ratio of the inorganic element to titanium is 0.010 to 0.

065.

5. The multilayer ceramic capacitor of claim 1, wherein: The inorganic element further includes at least one selected from the group consisting of magnesium, lithium, copper, niobium, samarium, and gadolinium.

6. The multilayer ceramic capacitor of claim 1, wherein: The grain boundary further includes a subcomponent including at least one selected from the group consisting of dysprosium, terbium, manganese, vanadium, barium, aluminum, and calcium.

7. The multilayer ceramic capacitor of claim 6, wherein: The secondary component includes dysprosium, and In the grain boundary, an atomic ratio of the inorganic element to dysprosium in the subcomponent is 0.10 to 3.

00.

8. The multilayer ceramic capacitor of claim 1, wherein: At least one dielectric grain among the plurality of dielectric grains has a core-shell structure including a core portion and a shell portion surrounding the core portion.

9. The multilayer ceramic capacitor of claim 8, wherein: The shell portion includes a barium titanate-based main component including barium and titanium, and an inorganic element including silicon.

10. The multilayer ceramic capacitor of claim 8, wherein: The inorganic element of the shell further includes at least one selected from the group consisting of magnesium, lithium, copper, niobium, samarium, and gadolinium.

11. The multilayer ceramic capacitor of claim 8, wherein: The shell portion further includes a subcomponent including at least one selected from the group consisting of dysprosium, terbium, manganese, vanadium, barium, aluminum, and calcium.

12. The multilayer ceramic capacitor of claim 1, wherein: The capacitor body has an active area in which the dielectric layers and the inner electrodes are alternately arranged, and The magnitude of the silicon peak in the dielectric layer in the active region is 8.6 kcps to 25 kcps.

13. A method of manufacturing a multilayer ceramic capacitor, comprising: preparing a dielectric powder in which a surface of a barium titanate-based main component powder containing barium and titanium is coated with an inorganic element including silicon; preparing a dielectric green sheet using a dielectric slurry including the dielectric powder, and forming a conductive paste layer on a surface of the dielectric green sheet; laminating the dielectric green sheets on which the conductive paste layers are formed to prepare a dielectric green sheet laminate; firing the dielectric green sheet laminate to prepare a capacitor body including a dielectric layer and an inner electrode; and forming external electrodes on a surface of the capacitor body, The dielectric layer includes a plurality of dielectric grains and grain boundaries between adjacent dielectric grains. The grain boundaries include a barium titanate-based main component including barium and titanium and an inorganic element including silicon, and The standard deviation of the atomic % of the inorganic element relative to the total amount of the components of the grain boundaries is 0.20 to 0.80, and the standard deviation is a square root of an average of squares of the deviations.

14. The method for manufacturing a multilayer ceramic capacitor according to claim 13, wherein: The operation of preparing the dielectric powder includes: Performing hydrothermal synthesis of the barium titanate-based main component powder to complete grain growth; After the grain growth is completed, adding an inorganic salt containing silicon; and The addition of the inorganic salt is followed by heat treatment.

15. The method for manufacturing a multilayer ceramic capacitor according to claim 14, wherein: The inorganic salt further includes at least one selected from the group consisting of magnesium, lithium, copper, samarium niobium and gadolinium.

16. The method for manufacturing a multilayer ceramic capacitor according to claim 14, wherein: The inorganic salts include alkoxide-based compounds.

17. The method for manufacturing a multilayer ceramic capacitor according to claim 14, wherein: The inorganic salt is added in an amount of 0.1 parts by mol to 5.0 parts by mol based on 100 parts by mol of the barium titanate-based main component powder.

18. The method for manufacturing a multilayer ceramic capacitor according to claim 14, wherein: The heat treatment is performed at a temperature of 100°C to 300°C.

19. The method for manufacturing a multilayer ceramic capacitor according to claim 13, wherein: The dielectric slurry further includes a subcomponent powder including at least one selected from the group consisting of a dysprosium-containing compound, a terbium-containing compound, a manganese-containing compound, a vanadium-containing compound, a barium-containing compound, an aluminum-containing compound, and a calcium-containing compound.

20. The method of manufacturing a multilayer ceramic capacitor according to claim 19, wherein: The amount of the sub-component powder is 0.01 parts by mol to 5 parts by mol based on 100 parts by mol of the barium titanate-based main component powder.

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