Deep groove etching method

Abstract

The invention discloses a deep trench etching method, which belongs to the technical field of semiconductors, and comprises the following steps: providing a substrate, and covering the substrate with a mask layer; the mask layer is etched, at least two first openings are formed, and a gap is formed between the first openings; performing ion implantation on the substrate along the first opening to form a first ion implantation region with a certain height; removing the mask layer between the first openings; carrying out ion implantation on a region between the first ion implantation regions to form a second ion implantation region; processing the first ion implantation region and the second ion implantation region to form an isolation layer which is made of a material different from that of the substrate; and removing the substrate in the isolation layer and the isolation layer to form a required groove. The isolation layer made of a material different from that of the substrate is formed, and the substrate and the isolation layer in the isolation layer are sequentially removed, so that the high-aspect-ratio groove with good morphology is formed, and the lateral erosion phenomenon and the bottom micro groove are prevented from occurring in the isotropic etching process.

Description

Technical Field

[0001] The invention relates to the field of semiconductor technology, and in particular to a deep trench etching method. Background Art

[0002] In traditional semiconductor etching processes, wet etching technology is difficult to achieve precise etching with high aspect ratios due to its lack of anisotropy. Current technology can usually only achieve deep groove processing of 100 to 200µm. When trying to reach a deeper etching depth, the hydrogen bubbles generated during the etching process will be adsorbed on the surface of the silicon wafer to form a unique mask. This mask will cause a conical protrusion to form on the inside of the trench, significantly increasing the surface roughness, affecting the subsequent polysilicon filling effect, and causing serious impact on the performance of the device. It is difficult to meet the strict requirements of MEMS devices and special IGBT processes for etching depth (5 to 500µm).

[0003] Especially when dealing with fine-size etching less than 3µm, the applicability of wet etching is significantly reduced, and wet etching is unable to control the morphology. Especially in situations where precise control of line width or sidewall angle is required, the widespread side etching phenomenon will increase the etching deviation and increase the difficulty of line width control, making it particularly difficult to accurately control the etching morphology. The side etching phenomenon may also cause a decline in device performance. The morphology of the groove will affect the area of ​​the device's on-current and the distribution of the electric field during breakdown, thereby affecting the device's specific on-resistance and breakdown voltage. Micro-grooves are also easily generated at the bottom of the groove. For deep groove structures, micro-grooves will cause the aggregation effect of potential lines, generating high electric fields that cause the device to break down prematurely, thereby reducing the device's breakdown voltage.

[0004] It should be noted that the information disclosed in the background technology section of the invention is only intended to deepen the understanding of the general background technology of the invention, and should not be regarded as an admission or suggestion in any form that the information constitutes prior art already known to those skilled in the art. Summary of the invention

[0005] The purpose of the present invention is to provide a deep trench etching method to solve the morphology problem in the deep trench etching process.

[0006] In order to solve the above technical problems, the present invention provides a deep trench etching method, comprising the following steps: Providing a substrate, on which a mask layer is covered; Etching the mask layer to form at least two first openings, with a gap between the first openings; Performing ion implantation into the substrate along the first opening to form a first ion implantation region having a certain height; removing the mask layer between the first openings; Performing ion implantation into the region between the first ion implantation regions to form a second ion implantation region; Processing the first ion implantation region and the second ion implantation region to form an isolation layer made of a material different from that of the substrate; The substrate in the isolation layer and the isolation layer are removed to form a required groove.

[0007] Preferably, the second ion implantation region is connected to the first ion implantation region.

[0008] Preferably, the ions implanted to form the first ion implantation region and the second ion implantation region are nitrogen ions, and the material of the isolation layer is silicon nitride.

[0009] Preferably, the substrate is subjected to high temperature annealing treatment so that the first ion implantation region and the second ion implantation region form an isolation layer.

[0010] Preferably, an ion implanter is used to implant nitrogen ions into the first opening multiple times, with an implantation energy of 0.1 keV to 1.2 MeV and an implantation dose of 1E16 cm -2 ~5E22 cm -2 .

[0011] Preferably, an ion implanter is used to perform multiple nitrogen ion implantations into the region between the first ion implantation regions, with an implantation energy of 0.1 keV to 1.2 MeV and an implantation dose of 1E16 cm -2 ~5E22 cm -2 .

[0012] Preferably, HF and HNO are used. 3 The mixed solution removes the substrate from the isolation layer.

[0013] Preferably, H 3 PO 4 The isolation layer is removed.

[0014] Preferably, the aspect ratio of the groove is 5:1-10:1.

[0015] Preferably, after forming the trench, the mask layer is removed.

[0016] The deep groove etching method provided by the present invention forms an ion implantation area in the required area, processes the ion implantation area, forms an isolation layer different from the substrate material, and sequentially removes the substrate and the isolation layer in the isolation layer, which helps to form a groove with good morphology, especially to form a high aspect ratio groove, effectively prevents side etching and bottom micro-grooves during isotropic etching, thereby reducing the on-resistance of the device and increasing the breakdown voltage, thereby significantly improving the overall performance of the product device. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Those skilled in the art will appreciate that the accompanying drawings are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention. Figure 1 is a schematic structural diagram of a mask layer according to an embodiment of the present invention; Figure 2 is a schematic structural diagram of a first opening according to an embodiment of the present invention; Figure 3 is a schematic structural diagram of a first ion implantation region according to an embodiment of the present invention; Figure 4 is a schematic structural diagram of a second opening according to an embodiment of the present invention; Figure 5 is a schematic structural diagram of a second ion implantation region according to an embodiment of the present invention; Figure 6 is a schematic diagram of the structure after forming an isolation layer according to an embodiment of the present invention; Figure 7 is a schematic structural diagram of removing a substrate in an isolation layer according to an embodiment of the present invention; Figure 8 is a schematic diagram of the structure after removing the isolation layer according to an embodiment of the present invention; Fig. 9 is a schematic diagram of the structure after removing the mask layer according to an embodiment of the present invention; Fig.10 It is an execution flow chart of an embodiment of the present invention.

[0018] In the attached figure: 100, substrate; 101, first ion implantation region; 102, second ion implantation region; 103, isolation layer; 104, trench; 200, mask layer; 201, first opening; 202, second opening. DETAILED DESCRIPTION

[0019] In order to make the purpose, advantages and features of the present invention more clear, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0020] As used in the present invention, the singular forms "one", "an", and "the" include plural objects, the term "or" is usually used to include the meaning of "and / or", the term "several" is usually used to include the meaning of "at least one", and the term "at least two" is usually used to include the meaning of "two or more". In addition, the terms "first", "second", and "third" are used only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first", "second", and "third" may explicitly or implicitly include one or at least two of the features. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to the specific circumstances.

[0021] Among them, although the word "groove" is traditionally used to define a long and narrow channel, the word "groove" used in the present disclosure is not limited to a long and narrow channel, but should be interpreted broadly to include rectangular holes, square holes, circular or round holes that are not long and narrow, and even holes with winding or polygonal geometric shapes, any and all of which are deemed "grooves" in the present disclosure.

[0022] Research has found that compared with dry etching, wet etching can provide more uniform surface treatment and is widely used in etching processes that require high wafer surface flatness, such as deep trench etching processes for certain dielectric layers (silicon oxide layers, silicon nitride layers, etc.). However, the hydrogen bubbles generated during wet etching adhere to the inner wall of the trench, greatly affecting the morphology of the deep trench. Side etching and micro-grooving phenomena also occur during the etching process, affecting the area of ​​the device's on-current and the distribution of the electric field during breakdown, thereby affecting the device's specific on-resistance and breakdown voltage, especially when finely etching high aspect ratio trenches with a CD value of less than 3µm.

[0023] Based on this, the core idea of ​​the present invention is to form an ion implantation area in the required area and process the ion implantation area to form an isolation layer different from the substrate material, and remove the substrate and isolation layer in the isolation layer in turn, which helps to form a groove with good morphology, especially a high aspect ratio groove; prevent side etching and bottom micro-grooves during isotropic groove etching, reduce the on-resistance of the device, and increase the breakdown voltage, thereby significantly improving the overall performance of the product device.

[0024] For details, please refer to Figure 1-Figure 10 , which is a schematic diagram of an embodiment of the present invention. Fig.10 As shown, a deep trench etching method comprises the following steps: S1, providing a substrate 100, and covering the substrate 100 with a mask layer 200. Figure 1As shown, a mask layer 200 is formed on the substrate 100. The material of the mask layer 200 is not particularly limited here, as long as it has a certain corrosion resistance and can block the bombardment of subsequent ion implantation.

[0025] The material of the substrate 100 may include semiconductor materials, insulating materials, conductive materials or any combination thereof; and the substrate 100 may be a single-layer structure or a multi-layer structure. For example, the substrate 100 may be a semiconductor material such as Si, SiGe, SiGeC, SiC, GaAs, InAs, InP and other III / V or II / VI compound semiconductors. And the substrate 100 may be, for example, a layered substrate of Si / SiGe, Si / SiC, silicon on insulator (SOI) or silicon germanium on insulator.

[0026] S2, such as Figure 2 As shown, the mask layer 200 is etched to form at least two first openings 201, and the first openings 201 are spaced apart to obtain a specific mask pattern. It can be understood that the size of the first opening 201 is set according to the required size of the groove 104, but the CD value of the first opening 201 is not greater than the CD value of the required groove 104. In the case where the CD value of the required groove 104 is small, only one first opening 201 can be etched to form, and after ion implantation and treatment, a columnar isolation layer 103 is formed, and the isolation layer 103 is removed to obtain a groove 104 with a desired size.

[0027] Exemplarily, the CD value of the groove 104 is, for example, 1-5 µm, the CD value of the first opening 201 is correspondingly set to 1 µm, and the aspect ratio of the groove 104 is 5:1-10:1.

[0028] S3, ion implantation is performed along the first opening 201 into the substrate 100 to form a first ion implantation region 101 having a certain height, such as Figure 3 According to the theory of interaction between ions and matter, since the ion implantation depth and implantation dosage are controllable, the implantation depth of nitrogen ions varies with the implantation energy, and the concentration of the implanted ions is Gaussian distributed. The ion implanter first performs multiple multi-energy implantations on the first opening 201 formed in the side area of ​​the trench 104, and implants the nitrogen ions as shown in FIG. Figure 3 The sidewall of the substrate 100 is shown as a designated position. However, the implanted ions are not limited to nitrogen ions, and carbon ions or other ions that can form an isolation layer 103 of a material different from that of the substrate 100 after secondary processing can also be used.

[0029] In one embodiment, the ions implanted to form the first ion implantation area 101 and the second ion implantation area 102 are nitrogen ions, and the material of the isolation layer 103 is silicon nitride. An ion implanter is used to implant nitrogen ions into the first opening 201 multiple times, with an implantation energy of 0.1 keV to 1.2 MeV and an implantation dose of 1E16 cm -2 ~5E22 cm -2 .

[0030] S4, removing the mask layer 200 between the first openings 201, such as Figure 4 As shown, the mask layer 200 between the first openings 201 is removed by dry or wet method, glue coating and development, etc. to form the second openings 202 .

[0031] S5, ion implantation is performed into the area between the first ion implantation areas 101 to form a second ion implantation area 102. According to the depth of the groove 104 required by the process, the ion implantation machine is used again to perform multiple multi-energy nitrogen ion implantation processes to form the second ion implantation area 102 at a specific depth. At this time, ion implantation can be performed directly in the second opening 202 without forming a photoresist pattern in the second opening 202. During the two ion implantation processes, only one mask layer 200 needs to be deposited to complete the subsequent ion implantation, thereby simplifying the process flow.

[0032] Exemplarily, the second ion implantation region 102 is connected to the first ion implantation region 101. Figure 5 As shown, the first ion implantation region 101 and the second ion implantation region 102 are connected to form a concave structure matching the size of the groove 104. Further, for the groove 104 with a high aspect ratio, ion implantation can be performed from the back side of the substrate 100 to form the second ion implantation region 102 according to the thickness of the substrate 100, thereby obtaining a groove 104 with a larger aspect ratio.

[0033] Specifically, an ion implanter is used to perform multiple nitrogen ion implantations into the area between the first ion implantation areas 101, with an implantation energy of 0.1 keV to 1.2 MeV and an implantation dose of 1E16 cm -2 ~5E22 cm -2 .

[0034] S6, such as Figure 6 As shown, the first ion implantation region 101 and the second ion implantation region 102 are processed to form an isolation layer 103 made of a material different from that of the substrate 100. Specifically, the substrate 100 is subjected to a high temperature annealing process to form the isolation layer 103 in the first ion implantation region 101 and the second ion implantation region 102.

[0035] In one embodiment, the substrate 100 after ion implantation is subjected to a high temperature annealing process at a temperature of 1200° C., so that the implanted nitrogen elements are rearranged and distributed with the silicon elements inside the substrate 100 to form a dense silicon nitride isolation layer 103. After the high temperature annealing, a large amount of implantation damage is eliminated, and at the same time, the interface between the substrate 100 and the silicon nitride becomes steep, forming a good isolation layer 103.

[0036] S7, removing the substrate 100 in the isolation layer 103 and the isolation layer 103 to form a required trench 104.

[0037] like Figure 7 As shown, using HF and HNO 3 The substrate 100 in the isolation layer 103 is removed by a mixed solution of HF and HNO 3 The substrate 100 is etched by a solution of HF and HNO 3 The solution has a higher etching selectivity for the substrate 100, and the silicon nitride isolation layer 103 has a higher corrosion resistance than the undoped substrate 100, so that all silicon in the isolation layer 103 can be removed to obtain a better morphology.

[0038] like Figure 8 As shown, using H 3 PO 4 Remove the isolation layer 103. Use wet denitridation of silicon, using hot H 3 PO 4 , the mixed solution with a concentration of 85%-95% removes the silicon nitride isolation layer 103, due to the heat H 3 PO 4 The etching rate of the substrate 100 is relatively low. When the temperature is 160-200°C, the etching rate is about 0.15-0.2 nm / min. The etching rate of the isolation layer 103 is about 3-14 nm / min. 3 PO 4 The etching selectivity for the substrate 100 is particularly small (the selectivity ratio is greater than 30:1). The isolation layer 103 is etched by combining the thickness of the isolation layer 103 after ion implantation and the etching process time. Finally, the etching endpoint is detected by optical mass spectrometry. After the detection is completed, a complete groove 104 is obtained.

[0039] Since the isolation layer 103 formed by ion implantation has good uniformity, less than 1%, the wet H 3 PO 4 During the etching process of the isolation layer 103, the uniformity is good, about 1%-1.5%, and H 3 PO 4There is almost no corrosion to the silicon substrate 100, so the morphology of the obtained groove 104 is good. It not only avoids the problem of poor surface uniformity (5%-7%) of the groove 104 caused by dry etching, but also overcomes the problems of rough surface of the groove 104 and uneven bottom of the groove 104 caused by traditional wet isotropic etching, thereby avoiding the performance degradation of the device.

[0040] It can be understood that compared with the limitations of the dry etching process, the plasma etching process chamber can only process one substrate 100 and has a narrow range of applicable materials or devices. The wet etching method is used to form a groove 104 with a high aspect ratio, which can realize batch processing of substrates 100, such as processing 50 substrates 100 as a batch, with high efficiency and low cost, and a wide range of applicable materials or devices.

[0041] After the trench 104 is formed, the mask layer 200 is removed.

[0042] In the deep trench etching method provided by the present invention, the trench 104 with an opening less than 3 μm has a good etching aspect ratio. A mask layer 200 is formed on the substrate 100, an opening for ion implantation is formed on the mask layer 200, ion implantation is performed on the substrate 100, and then a layer of difficult-to-etch isolation layer 103 is formed in a specific area of ​​the substrate 100. Subsequently, the corresponding area is removed by wet etching to obtain a trench 104 with a large aspect ratio and good morphology. This etching method improves the aspect ratio of the formed trench 104. When the isolation layer 103 is subsequently finely etched in the trench 104, the side etching phenomenon and the bottom micro-groove caused by isotropic etching are prevented, so that the morphology of the trench 104 tends to be perfect, thereby reducing the on-resistance and improving the breakdown voltage, thereby significantly improving the overall performance of the product device.

[0043] The above description is only a description of the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the technical solution of the present invention.

Claims

1. A deep trench etching method, characterized in that: The following steps are involved: Providing a substrate, on which a mask layer is covered; Etching the mask layer to form at least two first openings, with a gap between the first openings; Performing ion implantation into the substrate along the first opening to form a first ion implantation region; removing the mask layer between the first openings; Performing ion implantation into the region between the first ion implantation regions to form a second ion implantation region; Processing the first ion implantation region and the second ion implantation region to form an isolation layer made of a material different from that of the substrate; The substrate in the isolation layer and the isolation layer are removed to form a required groove.

2. The deep trench etching method according to claim 1, characterized in that: The second ion implantation region is connected to the first ion implantation region.

3. The deep trench etching method according to claim 1, characterized in that: The ions implanted to form the first ion implantation region and the second ion implantation region are nitrogen ions, and the material of the isolation layer is silicon nitride.

4. The deep trench etching method according to claim 3, characterized in that: The substrate is annealed so that the first ion implantation region and the second ion implantation region form an isolation layer.

5. The deep trench etching method according to claim 3, characterized in that: An ion implanter is used to implant nitrogen ions into the first opening multiple times, with an implantation energy of 0.1keV~1.2MeV and an implantation dose of 1E16 cm -2 ~5E22 cm -2 .

6. The deep trench etching method according to claim 3, characterized in that: An ion implanter is used to perform multiple nitrogen ion implantations into the area between the first ion implantation areas, with an implantation energy of 0.1keV~1.2MeV and an implantation dose of 1E16cm -2 ~5E22 cm -2 .

7. The deep trench etching method according to claim 3, characterized in that: The substrate in the isolation layer is removed using a mixed solution of HF and HNO 3 .

8. The deep trench etching method according to claim 3, characterized in that: The isolation layer was removed using H3PO4.

9. The deep trench etching method according to claim 1, characterized in that: The depth-to-width ratio of the groove is 5:1-10:

1.

10. The deep trench etching method according to claim 1, characterized in that: After forming the trench, the mask layer is removed.

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