Copper-cylinder-free wafer PLP packaging method
Through flip-flop, the chips on the copper-free column wafer are transferred to the substrate, and copper columns are generated through metal epitaxial, which solves the difficulty and offset problems of copper-free column wafers in PLP packaging, and achieves efficient and accurate chip packaging, improving production quality and efficiency.
Patent Information
- Application Number
- CN202510186444.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-20
- Publication Date
- 2025-05-13
AI Technical Summary
The existing PLP packaging technology is mainly aimed at wafers with existing copper columns, which leads to difficulties in absorbing copper column-free wafers during the transfer process, which may lead to chip offset problems, affect production quality, and require additional process to produce copper columns, which increases cost and time.
A copper-free column wafer PLP packaging method is proposed. The chip on the copper-free column wafer is transferred to the substrate by flip-flop, and the substrate is removed after forming the first plastic sealing layer, the chip pins are exposed, and the copper column is generated through metal epitaxial. Then, the second plastic sealing layer is formed and ground to the top of the exposed copper column, and the circuit is carried out to complete the packaging.
This method can directly package copper-free column wafers, saving time, improving packaging efficiency, reducing chip offset problems, improving line production accuracy and product quality.
Smart Images
Figure CN119993848A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor packaging technology, and in particular to a copper pillar-free wafer PLP packaging method. Background Art
[0002] PLP packaging (Panel-Level Packaging) is an advanced semiconductor packaging technology. Its core idea is to package multiple chips simultaneously on a large-size panel substrate, rather than traditional single wafer or chip-level packaging. By expanding the substrate area (such as a 24×18-inch panel), PLP can significantly improve packaging efficiency and reduce costs. It is especially suitable for scenarios that require high-density integration (such as AI chips, HPC, automotive electronics, etc.).
[0003] The PLP packaging process generally involves preparing the panel substrate, then cutting the wafer to obtain individual chips, placing these chips on the panel, and then establishing interconnections, such as RDL, to form electrical connections, followed by molding and encapsulation with epoxy resin to protect the chip. Grinding and thinning the package may then be performed, and finally the panel is cut into individual packaged devices for testing.
[0004] However, existing PLP packaging is performed on wafers that have been made with copper pillars (Bump i ng). The chips cut from the wafers with copper pillars are directly placed on the chips to establish connections and plastic seal. However, if the incoming wafers have copper pillars, it will cause difficulties in chip absorption during transfer, resulting in offset problems after transfer, thereby affecting production quality. Summary of the invention
[0005] The present application aims to solve at least one of the technical problems existing in the prior art. To this end, the present application proposes a PLP packaging method for copper-free wafers to solve the technical problem of how to perform PLP packaging on copper-free wafers.
[0006] The present application provides a copper pillar-free wafer PLP packaging method, the method comprising:
[0007] Providing a copper pillar-free wafer and a substrate, and transferring all chips on the copper pillar-free wafer to the substrate by flip-chip method;
[0008] After forming a first plastic packaging layer wrapping the chip on the substrate, removing the substrate to expose the pins of the chip;
[0009] Performing metal epitaxy on the pins of the chip to generate copper pillars;
[0010] forming a second plastic encapsulation layer on the first plastic encapsulation layer to encapsulate the copper column;
[0011] The second plastic packaging layer is ground until the top of the copper pillar is exposed, and circuits are fabricated based on the exposed copper pillar to complete the final chip packaging.
[0012] In one embodiment of the above copper pillar-free wafer PLP packaging method,
[0013] The method of transferring all the chips on the copper-post-free wafer to the substrate by flip-chip method includes: transferring all the chips on the copper-post-free wafer to the substrate with a double-sided adhesive film, wherein a side of the chip with pins is attached to the double-sided adhesive film.
[0014] In one embodiment of the above copper pillar-free wafer PLP packaging method,
[0015] The method further comprises: after removing the substrate to expose the pins of the chip, using a plasma surface treatment process to clean the surface of the first plastic packaging layer where the pins are exposed.
[0016] In one embodiment of the above copper pillar-free wafer PLP packaging method,
[0017] The step of performing metal epitaxy on the pins of the chip to generate copper pillars comprises:
[0018] Obtaining the actual position of the chip and its pins, and generating a positioning drawing;
[0019] Depositing a layer of copper on the surface of the first plastic packaging layer where the pins are exposed to form a seed layer;
[0020] According to the positions of the chip and its pins on the positioning drawing, an epitaxial hole is formed on the seed layer along the edge of the pin by using an image transfer method;
[0021] A copper column is fabricated and generated in the epitaxial hole by electroplating.
[0022] In one embodiment of the above copper pillar-free wafer PLP packaging method,
[0023] The method of obtaining the actual position of the chip and its pins and generating a positioning drawing includes: obtaining the actual position of the chip and its pins based on optical scanning; correcting the original chip and its pin drawing according to the actual position to generate a final positioning drawing of the chip and its pins.
[0024] In one embodiment of the above copper pillar-free wafer PLP packaging method,
[0025] The method of forming an epitaxial hole on the seed layer along the edge of the pin by using an image transfer method includes: generating a photoresist film on the seed layer by using an image transfer method to form the epitaxial hole of the pin, wherein the photoresist film is arranged in an area outside the pattern formed by the pin.
[0026] In one embodiment of the above copper pillar-free wafer PLP packaging method,
[0027] The method further comprises: after the copper pillar is generated, removing the photoresist film and the seed layer outside the copper pillar.
[0028] In one embodiment of the above copper pillar-free wafer PLP packaging method,
[0029] The circuit manufacturing based on the exposed copper pillars to complete the final chip packaging includes: multi-layer circuit manufacturing based on one or more methods of copper deposition, image transfer, and electroplating to complete the final chip packaging.
[0030] In one embodiment of the above copper pillar-free wafer PLP packaging method,
[0031] The first plastic sealing layer and the second plastic sealing layer are plastic sealed with epoxy resin molding compound or liquid packaging material.
[0032] One or more of the above embodiments of the present application have at least one or more of the following beneficial effects:
[0033] The present application performs PLP packaging on incoming copper-free wafers, transfers all chips on the copper-free wafers to a substrate by flipping the wafer, forms a first plastic sealing layer on the substrate to wrap the chips, removes the substrate to expose the pins of the chips, and can directly perform subsequent processes after the pins are extended to complete the chip packaging structure. Compared with the existing PLP packaging process that is aimed at copper-free wafers, the PLP packaging process of the present application can directly package copper-free wafers, eliminating the need to make copper pillars after the wafers leave the factory, saving a lot of chip packaging time and improving The overall packaging efficiency of the chip is improved; at the same time, the copper-free chip is easy to absorb, transfer and fix during the production process, which reduces the chip offset problem during the packaging process, improves the accuracy of chip circuit production, and improves the product production quality; further, since the present application directly exposes the pins and performs metal epitaxy through a flip-chip method, the process steps are simple, the cost is low and the efficiency is high. At the same time, the subsequent process of scanning and positioning is performed after plastic sealing, which eliminates the problem of inaccurate positioning caused by the expansion and contraction and offset of the chip due to plastic sealing, which can effectively improve the positioning accuracy of subsequent processes and improve the production quality of products.
[0034] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS
[0035] The disclosure of the present application will become more easily understood with reference to the accompanying drawings. It is easy for those skilled in the art to understand that these drawings are only for illustrative purposes and are not intended to limit the scope of protection of the present application. In addition, similar numbers in the drawings are used to represent similar components, among which:
[0036] Figure 1 It is a schematic flow chart of the main steps of a copper pillar-free wafer PLP packaging method according to an embodiment of the present application;
[0037] Figure 2 is a schematic diagram of a packaging structure after chip transfer according to an embodiment of the present application;
[0038] Figure 3 is a schematic diagram of a chip packaging structure after the first plastic packaging according to an embodiment of the present application;
[0039] Figure 4 is a schematic diagram of a chip packaging structure after the board is removed according to an embodiment of the present application;
[0040] Figure 5 It is a schematic flow chart of the main steps of generating copper pillars from chip pins according to one embodiment of the present application;
[0041] Figure 6 is a schematic diagram of a chip packaging structure during positioning scanning according to an embodiment of the present application;
[0042] Figure 7 is a schematic diagram of a chip packaging structure after copper deposition according to an embodiment of the present application;
[0043] Figure 8 is a schematic diagram of a chip packaging structure after image transfer according to an embodiment of the present application;
[0044] Fig. 9 is a schematic diagram of a chip packaging structure after electroplating according to an embodiment of the present application;
[0045] Fig.10 is a schematic diagram of a chip packaging structure after copper pillars are formed according to an embodiment of the present application;
[0046] Fig.11 is a schematic diagram of a chip packaging structure after a second plastic encapsulation according to an embodiment of the present application;
[0047] Fig.12 yes Fig.11Schematic diagram of chip packaging structure after the plastic sealing layer is ground;
[0048] Fig.13 It is a schematic diagram of the chip packaging finished product structure according to an embodiment of the present application.
[0049] The markings in the figure are:
[0050] 100, chip; 101, pin;
[0051] 200, substrate; 201, double-sided adhesive film; 202, epitaxial hole;
[0052] 300, first plastic packaging layer; 400, seed layer; 500, photoresist film; 600, copper pillar. DETAILED DESCRIPTION
[0053] Some embodiments of the present application are described below with reference to the accompanying drawings. Those skilled in the art should understand that these embodiments are only used to explain the technical principles of the present application and are not intended to limit the protection scope of the present application.
[0054] As described in the background technology, the existing PLP packaging is performed on wafers that have been made with copper pillars (Bump i ng), that is, the incoming wafers already have copper pillars, but the chips with copper pillars are difficult to absorb during the transfer process, which may cause chip offset problems, thereby affecting the production quality; at the same time, since the existing PLP packaging is for wafers that already have copper pillars, the wafer must first undergo a process for making copper pillars before packaging, which increases the overall packaging cost and time and affects the packaging efficiency. Based on this, the present application proposes a PLP packaging method for copper-free wafers to solve the above problems.
[0055] See attached Figure 1 , Figure 1 FIG. 1 is a schematic flow chart of the main steps of a copper pillar-free wafer PLP packaging method according to an embodiment of the present application. Figure 1 As shown, a copper pillar-free wafer PLP packaging method in an embodiment of the present invention mainly includes the following steps S101 to S105:
[0056] Step S101, providing a copper pillar-free wafer and a substrate, and transferring all chips on the copper pillar-free wafer to the substrate by flip-chip method;
[0057] In one embodiment, see Figure 2 The incoming material is a copper-post-free wafer. All chips 100 on the copper-post-free wafer are transferred to a substrate 200 having a double-sided adhesive film 201, wherein one side of the chip 100 having the pins 101 is attached to the double-sided adhesive film 201, that is, the chip 100 is flip-chip mounted on the substrate 200, and the double-sided adhesive film 201 can be made of polyimide or epoxy resin.
[0058] Step S102, after forming a first plastic packaging layer wrapping the chip on the substrate, the substrate is removed to expose the pins of the chip;
[0059] In one embodiment, reference Figure 3 The chip 100 is molded with a molding material to form a first molding layer 300 that wraps the chip 100. After the molding is completed, Figure 4 , remove the substrate 200 and the double-sided adhesive film 201 to expose the pins 101 of the chip 100 . At this time, the pins 101 of the chip 100 are on the same plane as the surface of the first plastic packaging layer 300 .
[0060] In one embodiment, after removing the substrate 200 and exposing the pins 101 of the chip 100, a plasma surface treatment process (Plasma) is used to clean the surface of the first plastic packaging layer 300 exposing the pins 101, so that the surface is free of pollution. Plasma surface cleaning is mainly based on a large number of active particles generated by plasma discharge. Under certain conditions, these active particles will react with pollutants on the surface of the cleaned object to achieve a cleaning effect. Through cleaning, the surface of the chip 100 and its pins 101 after the substrate 200 is removed is free of residue, which is more conducive to subsequent metal epitaxy or circuit processes.
[0061] Step S103, performing metal epitaxy on the pins of the chip to generate copper pillars;
[0062] In one embodiment, reference Figure 5 , the specific steps of performing metal epitaxy on the pin 101 of the chip and generating the copper pillar include:
[0063] Step S1031, obtaining the actual position of the chip and its pins on the substrate, and generating a positioning drawing;
[0064] Step S1032, depositing a layer of copper on the surface of the first plastic packaging layer where the pins are exposed to form a seed layer;
[0065] Step S1033, according to the position of the chip and its pins on the positioning drawing, an epitaxial hole is formed along the edge of the pin on the seed layer by using an image transfer method;
[0066] Step S1034: fabricate and generate copper pillars in the epitaxial holes by electroplating.
[0067] Specifically, refer to Figure 6In step S1031, the actual positions of the chip 100 and its pins 101 are obtained based on optical scanning; the original chip 100 and its pins 101 drawings are corrected according to the actual positions, and the final positioning drawings of the chip 100 and its pins 101 are generated; the scanning positioning is performed after the chip 100 is plastic-sealed. At this time, the positions of the chip 100 and the pins 101 are the precise actual positions after the expansion, shrinkage or offset after the plastic sealing. The positioning drawings corrected according to the actual positions are more accurate as the positioning drawings for the subsequent processes, and there is no need to estimate the expansion, shrinkage or offset values, which greatly improves the positioning accuracy of the chips and pins 101 in the subsequent processes and effectively improves the product production quality.
[0068] Specifically, refer to Figure 7 In step S1032, a layer of copper is deposited on the surface of the first plastic packaging layer 300 exposing the pins 101 of the chip 100 to form a seed layer 400; chemical copper plating can provide a uniform thin layer as the seed layer 400, which serves as a conductive base for the subsequent electroplating process, and copper deposition provides a uniform initial conductive layer, so that the electroplated copper can quickly thicken the wire.
[0069] Specifically, refer to Figure 8 and Fig. 9 In steps S1033-S1034, a photoresist film 500 is generated on the seed layer 400 by image transfer to form an epitaxial hole 202 of the pin 101, wherein the photoresist film 500 is arranged in an area outside the pattern formed by the pin 101, and a copper column 600 is generated in the epitaxial hole 202 by electroplating.
[0070] In one possible implementation, reference Fig.10 After the copper pillar 600 is generated, the photoresist film 500 and the seed layer 400 outside the copper pillar 600 are removed to complete the metal epitaxy of the pin 101, which is convenient for subsequent circuit production.
[0071] Step S104, forming a second plastic packaging layer wrapping the copper column on the first plastic packaging layer;
[0072] In one embodiment, reference Fig.11 A second plastic encapsulation layer is formed on the first plastic encapsulation layer 300 to encapsulate the copper pillar 600. The second plastic encapsulation layer and the first plastic encapsulation layer 300 form a whole to encapsulate the chip 100 and the copper pillar 600. Since the pins 101 of the chip 100 have been extended through the copper pillar 600, when the circuit is manufactured, it only needs to be electrically connected through the copper pillar 600. Furthermore, the first plastic encapsulation layer 300 and the second plastic encapsulation layer use epoxy resin molding compound or liquid packaging material.
[0073] Step S105 , grinding the second plastic packaging layer until the top of the copper pillar is exposed, and performing circuit fabrication based on the exposed copper pillar to complete the final chip packaging.
[0074] In one embodiment, reference Fig.12 The second plastic encapsulation layer is ground until the top of the copper pillar 600 is exposed, that is, the excess plastic encapsulation material is removed to expose the copper pillar 600 for circuit connection. The specific circuit connection can be made by copper deposition, image transfer, electroplating, or one or more methods to complete the final chip packaging. Fig.13 Finished chip packaging products.
[0075] Based on the above implementation mode, reference Figure 1-Figure 13 , a possible packaging process of the copper pillar-free wafer PLP packaging method of the present application:
[0076] Chip transfer: All chips 100 on the copper pillar-free wafer are transferred to a substrate 200 with a double-sided adhesive film 201 by flip-chip method;
[0077] First plastic encapsulation: using a plastic encapsulation material to form a first plastic encapsulation layer 300 including the chip 100 on the substrate 200, completing the plastic encapsulation of the chip 100;
[0078] Disassembling the board: removing the double-sided adhesive film 201 and the substrate 200 in contact with the chip 100 to expose the side of the chip 100 with the pins 101;
[0079] Plasma: Cleaning the side of the chip 100 having the pins 101 and the surface of the first plastic packaging layer 300 by Plasma;
[0080] Chip scanning: using optical scanning to locate the actual position of the chip 100 and its pins 101, and modify the positioning drawings for subsequent processes;
[0081] Copper deposition: depositing a layer of copper on the surface of the first plastic packaging layer 300 where the chip pins 101 are exposed, to form a seed layer 400;
[0082] Image transfer: a photoresist film 500 is generated around the pin 101 on the seed layer 400 to form an epitaxial hole 202 by image transfer;
[0083] Making copper pillars: using electroplating to generate copper pillars 600 in the epitaxial holes 202;
[0084] Copper pillar forming: removing the seed layer 400 other than the photoresist film 500 and the copper pillar 600, and completing the metal epitaxy of the pin 101;
[0085] Second plastic encapsulation: the copper pillar 600 is plastic encapsulated with a plastic encapsulation material to form a plastic encapsulation whole with the first plastic encapsulation layer 300, including the entire chip 100 and the copper pillar 600;
[0086] Grinding: removing excess plastic packaging material, and grinding the second plastic packaging layer until the top of the copper pillar 600 is exposed;
[0087] Circuit production: Based on the copper pillar 600, multi-layer circuits are produced through one or more methods such as copper deposition, image transfer, electroplating, etc., and finally surface packaging is performed to obtain the final chip packaging structure.
[0088] Based on the above steps S101-S105, the embodiment of the present application performs PLP packaging on incoming copper-post-free wafers, transfers all chips on the copper-post-free wafers to the substrate in a flip-chip manner, forms a first plastic packaging layer wrapping the chips on the substrate, removes the substrate to expose the pins of the chips, and can directly proceed to subsequent processes after the pins are extended to complete the chip packaging structure. Compared with the existing PLP packaging process that is aimed at copper-post wafers, the PLP packaging process of the present application can directly package copper-post-free wafers, eliminating the need to make copper pillars after the wafers leave the factory, saving a lot of time. The chip packaging time is shortened, and the overall chip packaging efficiency is improved; at the same time, the copper-free chip is easy to absorb, transfer and fix during the production process, which reduces the chip offset problem during the packaging process, improves the accuracy of chip circuit production, and improves the product production quality; further, since the present application directly exposes the pins and performs metal epitaxy through a flip-chip method, the process steps are simple, the cost is low and the efficiency is high. At the same time, the subsequent process of scanning and positioning is performed after plastic sealing, which eliminates the problem of inaccurate positioning caused by the expansion and contraction and offset of the chip due to plastic sealing, which can effectively improve the positioning accuracy of subsequent processes and improve the production quality of products.
[0089] It should be pointed out that although the various steps in the above embodiments are described in a specific order, those skilled in the art can understand that in order to achieve the effects of the present invention, different steps do not have to be performed in such an order. They can be performed simultaneously (in parallel) or in other orders. These changes are within the scope of protection of the present invention.
[0090] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.
[0091] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.
Claims
1. A copper pillar-free wafer PLP packaging method, characterized in that: The method comprises: Providing a copper pillar-free wafer and a substrate, and transferring all chips on the copper pillar-free wafer to the substrate by flip-chip method; After forming a first plastic packaging layer wrapping the chip on the substrate, removing the substrate to expose the pins of the chip; Performing metal epitaxy on the pins of the chip to generate copper pillars; forming a second plastic encapsulation layer on the first plastic encapsulation layer to encapsulate the copper column; The second plastic packaging layer is ground until the top of the copper pillar is exposed, and circuits are fabricated based on the exposed copper pillar to complete the final chip packaging.
2. The copper pillar-free wafer PLP packaging method according to claim 1, characterized in that: The method of transferring all the chips on the copper-post-free wafer to the substrate by flip-chip method includes: transferring all the chips on the copper-post-free wafer to the substrate with a double-sided adhesive film, wherein a side of the chip with pins is attached to the double-sided adhesive film.
3. The copper pillar-free wafer PLP packaging method according to claim 1, characterized in that: The method further comprises: after removing the substrate to expose the pins of the chip, using a plasma surface treatment process to clean the surface of the first plastic packaging layer where the pins are exposed.
4. The copper pillar-free wafer PLP packaging method according to any one of claims 1 to 3, characterized in that: The step of performing metal epitaxy on the pins of the chip to generate copper pillars comprises: Obtaining the actual position of the chip and its pins, and generating a positioning drawing; Depositing a layer of copper on the surface of the first plastic packaging layer where the pins are exposed to form a seed layer; According to the positions of the chip and its pins on the positioning drawing, an epitaxial hole is formed on the seed layer along the edge of the pin by using an image transfer method; A copper column is fabricated and generated in the epitaxial hole by electroplating.
5. The copper pillar-free wafer PLP packaging method according to claim 4, characterized in that: The method of obtaining the actual position of the chip and its pins and generating a positioning drawing includes: obtaining the actual position of the chip and its pins based on optical scanning; correcting the original chip and its pin drawing according to the actual position to generate a final positioning drawing of the chip and its pins.
6. The copper pillar-free wafer PLP packaging method according to claim 4, characterized in that: The method of forming an epitaxial hole on the seed layer along the edge of the pin by using an image transfer method includes: generating a photoresist film on the seed layer by using an image transfer method to form the epitaxial hole of the pin, wherein the photoresist film is arranged in an area outside the pattern formed by the pin.
7. The copper pillar-free wafer PLP packaging method according to claim 5, characterized in that: The method further comprises: after the copper pillar is generated, removing the photoresist film and the seed layer outside the copper pillar.
8. The copper pillar-free wafer PLP packaging method according to claim 1, characterized in that: The circuit manufacturing based on the exposed copper pillars to complete the final chip packaging includes: multi-layer circuit manufacturing based on one or more methods of copper deposition, image transfer, and electroplating to complete the final chip packaging.
9. The copper pillar-free wafer PLP packaging method according to claim 1, characterized in that: The first plastic sealing layer and the second plastic sealing layer are plastic sealed with epoxy resin molding compound or liquid packaging material.