SOI chip top silicon dislocation defect detection method

Abstract

The invention relates to the technical field of semiconductor manufacturing, in particular to an SOI (silicon on insulator) wafer top silicon dislocation defect detection method, which comprises the following steps of: providing an SOI wafer to be detected, and measuring the initial thickness H0 of a top silicon layer for determining subsequent processing parameters; placing the SOI silicon wafer in a corrosive liquid, and when the thickness H0 is reduced to a set value in the corrosion process of the top silicon layer, enabling the dislocation defect region to be corroded and penetrated preferentially to generate micropores penetrating through the buried oxide layer; placing the SOI silicon wafer subjected to corrosion treatment in hydrofluoric acid for treatment so as to expand a dislocation defect perforation area to a visible range, observing the expanded dislocation perforation area through an optical microscope, and counting the number of dislocation defects in a plurality of visual fields; according to the method, chemical corrosion is combined with optical microscope detection, the equipment cost is low, the detection consumable cost is controllable, the detection cost is greatly reduced, and the method is suitable for online quality detection of large-batch SOI silicon wafers.

Description

Technical Field

[0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for detecting silicon dislocation defects on top of an SOI wafer. Background Art

[0002] SOI (Silicon On Insulator) technology is a semiconductor manufacturing technology that introduces a silicon oxide insulating layer between the silicon wafer and the substrate. Compared with the traditional bulk silicon process, SOI wafers have the advantages of small parasitic capacitance, less leakage, low power consumption, high temperature resistance and radiation resistance, and are widely used in high-performance integrated circuits, radio frequency chips and power devices. The core advantage of SOI wafers is that they can effectively suppress the short channel effect, improve device performance, and reduce power consumption, making them an important basic material for advanced microelectronics manufacturing processes.

[0003] However, during the manufacturing process of SOI wafers, the top silicon layer is prone to dislocation defects due to process steps such as material growth, oxidation, and annealing. Dislocation defects are a type of line defect with lattice dislocation, which can cause local stress concentration, resulting in uneven electrical properties, affecting the reliability, life, and performance of the device. For example, during the manufacturing process of SOI wafers, dislocation defects can lead to problems such as increased leakage current, decreased breakdown voltage, and reduced device mobility. Therefore, accurately detecting and controlling the dislocation defect density of the top silicon layer of SOI wafers has become a key link in improving product quality and optimizing manufacturing processes.

[0004] At present, the detection of silicon dislocation defects on the top of SOI wafers mainly relies on the following technologies:

[0005] Transmission electron microscopy (TEM): Through high-energy electron beams penetrating the sample, dislocation defect detection at the nanometer level can be achieved, and crystal structure defects can be directly observed. However, TEM detection is costly, sample preparation is complex, and the sample detection range is small, making it difficult to screen a large area.

[0006] Cathodoluminescence (CL) characterization technology: It uses electron beams to excite materials to produce fluorescence and analyze the changes in optical characteristics caused by defects. It has high sensitivity. However, its detection equipment is expensive, the operation is complicated, and it has high requirements for the surface state of the sample.

[0007] X-ray topography (XRT) technology: X-rays are used to irradiate silicon wafers and analyze crystal defects through diffraction imaging. Although this method can perform non-destructive testing on large-area samples, its spatial resolution is limited and it is difficult to accurately locate tiny defects.

[0008] Raman spectroscopy: It uses optical laser to analyze the changes in lattice stress, which indirectly reflects the existence of dislocation defects. This method is suitable for rapid screening, but it is difficult to distinguish different types of crystal defects.

[0009] Laser confocal microscopy: It combines optical microscopy with laser scanning to achieve non-contact surface defect analysis. It is suitable for detecting large-area samples, but its ability to detect buried defects is relatively weak.

[0010] Although the above detection methods can realize defect analysis of SOI wafers to a certain extent, the above equipment is expensive and has a long detection cycle, which limits its application in large-scale production; existing methods usually require single-point or local detection, which makes it difficult to quickly evaluate the defect density of the entire silicon wafer; surface detection is mainly used, and it is difficult to identify deep defects: for areas with deeper dislocation defects, conventional methods are often difficult to detect accurately, affecting the reliability of the final evaluation. Summary of the invention

[0011] To this end, the purpose of the present invention is to provide a method for detecting silicon dislocation defects on the top of a SOI wafer, which utilizes chemical etching technology, controls the type, concentration, temperature and other process parameters of the etching solution, and combines real-time thickness monitoring and defect expansion processing to achieve efficient and accurate detection of silicon dislocation defects on the top of the SOI wafer. The method can effectively distinguish the difference in etching rate between the dislocation defect area and the normal lattice area, so that the defect area is corroded first, and then observed and counted by an optical microscope, providing a low-cost and high-efficiency dislocation defect density detection solution to solve the problems of high detection cost, low efficiency, and inability to conduct large-scale statistics in the prior art.

[0012] To achieve the above object, the present invention provides the following technical solutions:

[0013] A method for detecting silicon dislocation defects on the top of an SOI wafer comprises the following steps:

[0014] Step S1, providing a SOI silicon wafer to be tested, and measuring the initial thickness H0 of the top silicon layer for determining subsequent processing parameters;

[0015] Step S2, placing the SOI silicon wafer in an etching solution, and when the thickness H0 of the top silicon layer is reduced to a set value during the etching process, utilizing the difference in etching rate between the dislocation defect region and the non-defect region, the dislocation defect region is preferentially corroded to generate micropores penetrating the buried oxide layer;

[0016] Step S3, placing the etched SOI silicon wafer in hydrofluoric acid for treatment to expand the dislocation defect perforation area to a visible range;

[0017] Step S4, observing the expanded dislocation perforation area through an optical microscope, and counting the number of dislocation defects in multiple fields of view;

[0018] Step S5: Calculate the dislocation defect density according to the number of defects and the microscope field area, and evaluate the sample quality.

[0019] The present invention is further configured as follows: Step 2 specifically comprises the following steps:

[0020] S21, the parameters include the type of etching solution, concentration C and temperature T, and the type of etching solution is selected from alkaline etching solution or oxidizing etching solution according to the material characteristics of the top silicon layer;

[0021] S22, placing the SOI silicon wafer in the etching solution, and using a thickness monitor to measure the thickness H(t) of the top silicon layer in real time, wherein the thickness is etched over time t according to the following mathematical model:

[0022] Where H0 is the initial thickness of the top silicon layer; is the corrosion rate of the defect area, defined as: ; Where k is the reaction rate constant of the corrosive solution; is the corrosion activation energy; R is the gas constant, and T is the temperature of the corrosive liquid.

[0023] S23, when the thickness of the top silicon layer is reduced to the set value H Target When the corrosion rate difference between the dislocation defect area and the defect-free area is used, the corrosion rate V defect = .V normal

[0024] in is the rate enhancement factor, which ranges from 2 to 4;

[0025] S24. According to the real-time thickness monitoring data, the concentration and temperature of the etching solution are dynamically adjusted to keep the corrosion rate within the set target range. The adjustment methods include:

[0026] If the actual corrosion rate V c When the rate is lower than the target rate, increase the concentration of the corrosive solution by 3%-5% and the temperature by 10℃-15℃.

[0027] If the actual corrosion rate V c When the rate is higher than the target rate, reduce the concentration of the corrosive solution by 3%-5% and lower the temperature by 10℃-15℃;

[0028] S25, when the corrosion reaches the end condition, that is, the top silicon thickness is reduced to the set value H Target Finally, the etching process is terminated and the SOI silicon wafer is cleaned to remove residual corrosion products and ensure that the surface of the top silicon layer is clean.

[0029] The present invention is further configured as follows: the alkaline corrosive liquid is TMAH, and the concentration is 10%-40%; the oxidizing corrosive liquid is potassium permanganate solution, and the concentration is 10%-40%.

[0030] The present invention is further configured as follows: in step S3, the concentration of the hydrofluoric acid solution is controlled at 10%-20%, and the processing time is 60-120 seconds.

[0031] The present invention is further configured as follows: the microscope field area A is calculated according to the following formula:

[0032] Wherein, the diameter of the field of view d is the estimated number of fields of view of the microscope D 显微镜 And the magnification M is calculated: .

[0033] The present invention is further configured as follows: the defect density The calculation formula is: ,

[0034] in is the average number of defects under multiple microscope fields of view, and A is the area of ​​the microscope field of view.

[0035] The present invention is further configured to: evaluate the quality of the sample according to the calculated dislocation defect density, and the quality grade classification standard is as follows:

[0036] Superior quality: dislocation defect density is less than 100 / mm²;

[0037] Good product: dislocation defect density is 100-300 / mm²;

[0038] Defective product: The dislocation defect density is greater than 300 / mm².

[0039] Compared with the shortcomings of the prior art, the beneficial effects of the present invention are:

[0040] The present invention adopts chemical corrosion combined with optical microscope detection, has low equipment cost, controllable detection consumables cost, greatly reduces detection cost, and is suitable for online quality detection of large quantities of SOI silicon wafers.

[0041] The difference in corrosion rate between defective areas and non-defective areas is utilized to ensure that defective areas are corroded first. Combined with hydrofluoric acid expansion treatment, the defect location is fully exposed to avoid missed detection and ensure the accuracy and consistency of defect density assessment. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 is a process flow chart of the present invention;

[0043] Figure 2 Schematic diagram of silicon dislocation defect on the top of SOI wafer;

[0044] Figure 3 Schematic diagram after top silicon etching;

[0045] Figure 4This is a schematic diagram after immersion in hydrofluoric acid;

[0046] Figure 5 These are images taken with an optical microscope at 50x and 500x viewing angles. DETAILED DESCRIPTION

[0047] Reference Figure 1-Figure 5 The embodiment of the method for detecting dislocation defects of top silicon of SOI wafer of the present invention is further described. The SOI silicon wafer is composed of a top silicon layer 1, a buried oxide layer 2 and a substrate silicon 3. Generally, the thickness of the top silicon layer 1 can be between tens of nanometers and several micrometers, which varies according to the device requirements. The detection method includes the following steps:

[0048] Step 1: Provide the SOI silicon wafer to be tested. The thickness of the top silicon layer can be measured by high-precision testing instruments such as ellipsometer, reflectometer or X-ray reflection. The initial thickness of the top silicon layer H0 is measured and used as the corrosion target H0. Target And the basis for corrosion rate control. After recording H0, we can proceed to the next stage of corrosion process design.

[0049] Step 2: By removing a certain thickness of the top silicon layer in the etching solution, the dislocation defect area is preferentially corroded through the buried oxide layer to form micropores, which is convenient for the subsequent visualization and statistics of defects.

[0050] Etching solution type and parameter setting: If the top silicon layer material is conventional (100) silicon or (111) silicon, alkaline etching solution TMAH (tetramethylammonium hydroxide) can be used with a concentration range of 10%-40%. If higher selectivity or stronger oxidation ability is required, oxidizing etching solution potassium permanganate solution can also be used with a concentration range of 10%-40%.

[0051] In the actual process, the specific etching solution needs to be selected based on comprehensive considerations such as equipment conditions, requirements for the surface roughness of the top silicon layer, corrosion uniformity, and environmental factors.

[0052] Corrosive liquid concentration C: Initially set in the range of 10%-40%. The specific value can be determined based on experience or small-scale tests.

[0053] Etching liquid temperature T: Generally controlled within the range of 60–90°C. The higher the temperature, the faster the corrosion rate; the lower the temperature, the slower the corrosion rate, but the surface flatness may be better.

[0054] For the defect-free area, the corrosion rate It can be expressed as follows:

[0055]

[0056] Where H0 is the initial thickness of the top silicon layer; where k is the reaction rate constant of the etching solution; is the corrosion activation energy; R is the gas constant, and T is the temperature of the corrosive liquid.

[0057] The SOI silicon wafer is placed in an etching solution with set temperature and concentration to start etching. Through online thickness monitoring (such as laser interferometry, ellipsometry online monitoring, etc.), a curve of the current top silicon layer thickness H(t) changing with time is obtained;

[0058] The thickness variation of the defect-free area can be approximately expressed as:

[0059] In actual operation, the corrosion rate should be closely monitored to ensure that the corrosion proceeds stably within the target range.

[0060] Determine the thickness of the top silicon layer that needs to be removed based on process requirements or preliminary tests, and obtain the target thickness H Target , when it is monitored that H(t) drops to H Target When the corrosion end point is reached,

[0061] Using dislocation defect areas to accelerate corrosion mechanism: When there are dislocations or other crystal defects in the top silicon, lattice stress concentration or lattice distortion will make the area more sensitive to the corrosive solution, and the corrosion rate will be greater than that of the defect-free area;

[0062] Assume that the corrosion rate of the dislocation defect region is V defect , then V defect = .V normal ,in is the rate enhancement factor, which ranges from 2 to 4.

[0063] When the remaining thickness of the top silicon layer gradually becomes thinner, the dislocations will be preferentially "opened" due to the higher corrosion rate, forming micropores that penetrate the buried oxide layer; this provides conditions for the subsequent hydrofluoric acid solution to further etch / expand the buried oxide layer and micropores.

[0064] Dynamically adjust the concentration and temperature of the etching solution: In order to achieve the corrosion depth within a reasonable time and take into account the corrosion surface quality, a target corrosion rate range needs to be determined in advance , real-time monitoring rate V c If it exceeds this range, the concentration and temperature of the corrosive liquid must be adjusted in time.

[0065] If the actual corrosion rate V c When the rate is lower than the target rate, increase the concentration of the corrosive solution by 3%-5% and the temperature by 10℃-15℃.

[0066] If the actual corrosion rate V cWhen the rate is higher than the target rate, reduce the concentration of the corrosive solution by 3%-5% and lower the temperature by 10℃-15℃;

[0067] When the measured value of the top silicon layer thickness H(t) = H Target When the corrosion rate remains stable, it is considered that the corrosion endpoint has been reached; at this time, microporous structures have been formed at most dislocation defects, and pore expansion treatment can be carried out subsequently using HF (hydrofluoric acid) solution.

[0068] Remove the SOI silicon wafer from the etching solution and clean it thoroughly (ultrapure water combined with ultrasound or spin washing can be used);

[0069] The purpose is to remove corrosion products and residual corrosion liquid to avoid their influence on subsequent HF hole expansion and microscopic observation.

[0070] Step 3: Place the etched SOI wafer in hydrofluoric acid for treatment. The concentration of the hydrofluoric acid solution is controlled at 10%-20%, and the treatment time is 60-120 seconds. Make appropriate adjustments based on the size of the micropores and the required observation clarity. Too long a time may cause the micropores to expand excessively, increasing the difficulty of counting.

[0071] HF can selectively etch silicon dioxide (buried oxide layer) and the oxide layer on the silicon surface, further expanding the micropores horizontally or vertically;

[0072] A clear "through hole" is formed in the dislocation area, which can be more easily identified by naked eyes or under a microscope. After the hole is expanded, rinse it again with ultrapure water; after washing, it can be blown dry with nitrogen or placed in a clean environment to dry naturally, ensuring that there is no water stain or ion residue on the surface to ensure the quality of microscopic observation.

[0073] Step 4. Select a metallographic microscope or an inverted microscope with a magnification of 50–200 times (select the magnification appropriately according to the aperture size and defect density);

[0074] The size of the field of view (field of view diameter d) must be clearly quantified in order to calculate the defect density.

[0075] Select multiple fields of view (e.g. 5-10) on the same SOI wafer to avoid the discreteness of local samples affecting the overall judgment; record the number of holes (defects) in each field of view, and obtain the number of defects N1, N2, ..., Ni of multiple fields of view, and take the average value As the number of statistical defects.

[0076] The microscope field area A is calculated according to the following formula: , where the field diameter d is the estimated number of microscope fields D 显微镜 And the magnification M is calculated:

[0077] Step 5. Calculate the dislocation defect density based on the number of defects and the microscope field of view area, and evaluate the sample quality.

[0078] The average number of defects combined from multiple fields of view and single field of view area A, defect density The calculation formula is: ,

[0079] According to the calculated dislocation defect density, the sample quality is graded and the quality grade classification standards are as follows:

[0080] Superior quality: dislocation defect density is less than 100 / mm²;

[0081] Good product: dislocation defect density is 100-300 / mm²;

[0082] Defective product: The dislocation defect density is greater than 300 / mm².

[0083] For SOI silicon wafers that require high reliability and high performance devices, the lower the dislocation defect density, the better the stability of the manufactured device;

[0084] If the defect density is too high, device performance and life will be significantly affected, requiring further process optimization or supplier replacement.

[0085] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Common changes and substitutions made by those skilled in the art within the scope of the technical solution of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for detecting silicon dislocation defects on the top of a SOI wafer, characterized in that: The steps include: Step S1, providing a SOI silicon wafer to be tested, and measuring the initial thickness H0 of the top silicon layer for determining subsequent processing parameters; Step S2, placing the SOI silicon wafer in an etching solution, and when the thickness H0 of the top silicon layer is reduced to a set value during the etching process, utilizing the difference in etching rate between the dislocation defect region and the non-defect region, the dislocation defect region is preferentially corroded to generate micropores penetrating the buried oxide layer; Step S3, placing the etched SOI silicon wafer in hydrofluoric acid for treatment to expand the dislocation defect perforation area to a visible range; Step S4, observing the expanded dislocation perforation area through an optical microscope, and counting the number of dislocation defects in multiple fields of view; Step S5: Calculate the dislocation defect density according to the number of defects and the microscope field area, and evaluate the sample quality.

2. A method for detecting silicon dislocation defects on top of a SOI wafer according to claim 1, characterized in that: The step 2 specifically includes the following steps: S21, the parameters include the type of etching solution, concentration C and temperature T, and the type of etching solution is selected from alkaline etching solution or oxidizing etching solution according to the material characteristics of the top silicon layer; S22, placing the SOI silicon wafer in the etching solution, and using a thickness monitor to measure the thickness H(t) of the top silicon layer in real time, wherein the thickness is etched over time t according to the following mathematical model: , Where H0 is the initial thickness of the top silicon layer; is the corrosion rate of the defect area, defined as: ; Where k is the reaction rate constant of the corrosive solution; is the corrosion activation energy; R is the gas constant, T is the temperature of the corrosive liquid; S23, when the thickness of the top silicon layer is reduced to the set value H Target When the corrosion rate difference between the dislocation defect area and the defect-free area is used, the corrosion rate V defect = .V normal in is the rate enhancement factor, which ranges from 2 to 4; S24. According to the real-time thickness monitoring data, the concentration and temperature of the etching solution are dynamically adjusted to keep the corrosion rate within the set target range. The adjustment methods include: If the actual corrosion rate V c When the rate is lower than the target rate, increase the concentration of the corrosive solution by 3%-5% and the temperature by 10℃-15℃. If the actual corrosion rate V c When the rate is higher than the target rate, reduce the concentration of the corrosive solution by 3%-5% and lower the temperature by 10℃-15℃; S25, when the corrosion reaches the end condition, that is, the top silicon thickness is reduced to the set value H Target Finally, the etching process is terminated and the SOI silicon wafer is cleaned to remove residual corrosion products and ensure that the surface of the top silicon layer is clean.

3. A method for detecting silicon dislocation defects on the top of an SOI wafer according to claim 2, characterized in that: The alkaline corrosive solution is TMAH, and the concentration is 10%-40%; the oxidizing corrosive solution is potassium permanganate solution, and the concentration is 10%-40%.

4. The method for detecting silicon dislocation defects on the top of an SOI wafer according to claim 2, characterized in that: In step S3, the concentration of the hydrofluoric acid solution is controlled at 10%-20%, and the treatment time is 60-120 seconds.

5. The method for detecting silicon dislocation defects on the top of an SOI wafer according to claim 2, characterized in that: The microscope field area A is calculated according to the following formula: , Wherein, the diameter of the field of view d is the estimated number of fields of view of the microscope D 显微镜 And the magnification M is calculated: .

6. A method for detecting silicon dislocation defects on top of a SOI wafer according to claim 5, characterized in that: The defect density The calculation formula is: , in is the average number of defects under multiple microscope fields of view, and A is the area of ​​the microscope field of view.

7. A method for detecting silicon dislocation defects on the top of a SOI wafer according to claim 6, characterized in that: According to the calculated dislocation defect density, the sample quality is graded and the quality grade classification standards are as follows: Superior quality: dislocation defect density is less than 100 / mm²; Good product: dislocation defect density is 100-300 / mm²; Defective product: The dislocation defect density is greater than 300 / mm².

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