Preparation method of thick metal wiring with small line width spacing
By etching the trench group and silicon fins on the surface of the silicon substrate, and forming the silicon oxide dielectric layer and fins using the silicon thermal oxidation process, the problem of long and high cost of preparation of thick metal wiring in the prior art is solved, and low-cost and high-efficiency preparation of thick metal wiring is achieved.
Patent Information
- Application Number
- CN202411934393.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-26
- Publication Date
- 2025-05-13
AI Technical Summary
The existing thick metal wiring preparation methods have problems of time-consuming and high cost, mainly because they need to deposit a dielectric layer with a thickness of not less than the metal wiring thickness and etch the trench group with a depth corresponding to the metal wiring thickness therein.
The trench group and silicon fins are formed by etching on the surface of the silicon substrate, and the silicon oxide dielectric layer and fins are formed through the silicon thermal oxidation process, and metal lines are then deposited in the trench group to avoid the deposition and etching of the thick dielectric layer.
The low-cost preparation of thick metal wiring with small line width spacing is achieved, which shortens preparation time, reduces costs, and improves interconnect density through mature silicon trench etching technology.
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Figure CN119993906A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the field of integrated circuit manufacturing and advanced packaging, and specifically provides a method for preparing thick metal wiring with small line width spacing. Technical Background
[0002] In silicon adapters and silicon bridge chips used in integrated circuit chips and advanced packaging, metal wiring is used to provide electrical connections, and the metal wiring and the silicon substrate, as well as the different metal lines of the metal wiring, are electrically isolated by dielectrics. In order to avoid attenuation, delay, and energy loss of electrical signals, metal wiring needs to have as small a resistance as possible, which requires the metal lines of the metal wiring to have large line widths and thicknesses; on the other hand, in order to increase the interconnection density, the metal lines of the metal wiring need to have small line widths and spacings, so it is impossible to reduce resistance by increasing the line width; therefore, thick metal wiring with small line widths and spacings has been widely studied and applied.
[0003] At present, the thick metal wiring preparation method based on the existing technology is as follows Figure 1 As shown; first, a thick dielectric layer 120 (eg, silicon oxide) is deposited on the surface of the substrate 110, and the thickness T1 of the dielectric layer 120 is not less than the thickness of the metal wiring, such as Figure 1 Then, a groove group 130 corresponding to the metal wiring pattern is formed in the dielectric layer 120 by photolithography and dielectric etching, and the depth of the groove group 130 corresponds to the thickness of the metal wiring, as shown in FIG. Figure 1 Finally, a metal wiring 140 is formed in the groove group 130, as shown in (b); Figure 1 In short, the preparation of thick metal wiring based on the prior art requires the deposition of a dielectric layer with a thickness not less than the thickness of the metal wiring, and the etching of a groove group with a depth corresponding to the thickness of the metal wiring in the dielectric layer. The thickness of the metal wiring is limited by the dielectric layer deposition process and the dielectric layer etching process. However, according to the current level of the dielectric layer deposition process and the dielectric layer etching process, the dielectric deposition time and dielectric etching time required for the preparation of thick metal wiring based on the prior art are both long, and the cost is high. Summary of the invention
[0004] The purpose of the present invention is to provide a method for preparing thick metal wiring with small line width spacing to avoid thick dielectric layer deposition and etching, thereby solving the problems of long time consumption and high cost in existing thick metal wiring preparation methods.
[0005] To achieve the above object, the technical solution adopted by the present invention is:
[0006] A method for preparing thick metal wiring with small line width spacing, characterized by comprising the following steps:
[0007] Step 1, etching on the surface of the silicon substrate to form at least one groove group and at least one silicon fin, wherein the groove group includes at least two linear grooves, and the silicon fin is arranged between adjacent linear grooves;
[0008] Step 2: oxidizing the groove wall and the groove bottom of the groove group by a silicon thermal oxidation process to form a silicon oxide dielectric layer, and the silicon fin is simultaneously and completely oxidized to form a silicon oxide fin, thereby forming an electrical isolation structure between adjacent linear grooves;
[0009] Step 3: depositing metal lines in the grooves of the groove group.
[0010] Furthermore, in step 1, the depth of the linear groove is greater than its width, and the depth of the linear groove is greater than twice the spacing between adjacent linear grooves.
[0011] Furthermore, in step 1, the depth of the linear groove is greater than 3 microns, and the width of the silicon fin is less than 2 microns.
[0012] Furthermore, in step 2, the thickness of the silicon oxide dielectric layer is T2, and the width of the silicon oxide fin 250 is less than 2×T2.
[0013] Furthermore, the specific process of step 1 is:
[0014] Step 1.1, forming a patterned photoresist layer on the surface of the silicon substrate by photolithography, corresponding to the etching area of the reserved groove group;
[0015] Step 1.2, etching silicon using a reactive ion etching process to form a groove group on the surface of the silicon substrate, and forming silicon fins between adjacent linear grooves in the groove group;
[0016] Step 1.3, remove the photoresist layer.
[0017] Furthermore, the specific process of step 3 is:
[0018] Step 3.1, sputtering a seed layer of metal on the surface of the groove bottom and the groove wall of the groove group;
[0019] Step 3.2, using the seed layer metal to perform metal electroplating to form electroplated metal in the groove group and on the surface of the substrate;
[0020] Step 3.3: remove the metal on the surface of the substrate by grinding, chemical mechanical polishing or etching, and retain the seed layer metal and the electroplated metal in the groove group to form metal lines together.
[0021] Based on the above technical solution, the beneficial effects of the present invention are:
[0022] The present invention provides a method for preparing thick metal wiring with small line width spacing. The dielectric layer between the metal lines is prepared by thermally oxidizing all silicon fins. The thickness of silicon oxide required for thermal oxidation only needs to be greater than half of the metal line spacing. The required thickness of silicon oxide is independent of the thickness of the metal wiring. The dielectric layer between the metal lines of the thick metal wiring with small line width spacing can be easily and low-costly realized, avoiding the deposition of a thick dielectric layer. In addition, the present invention replaces dielectric layer groove etching with silicon groove etching. The high aspect ratio deep silicon groove etching technology is more mature than the high aspect ratio deep dielectric layer etching technology, and the etching rate is faster. The grooves for placing metal lines required for the preparation of thick metal wiring with small line width spacing can be easily and low-costly realized, avoiding the etching of a thick dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] Figure 1 The figure is a schematic diagram of a process for preparing thick metal wiring based on the prior art.
[0024] Figure 2 A schematic flow chart of a method for preparing thick metal wiring with small line width spacing provided by the present invention.
[0025] Figure 3 A schematic diagram of a detailed step-by-step process of a method for preparing thick metal wiring with small line width spacing provided by the present invention.
[0026] Figure 4 A detailed flow chart of step 1 in the method for preparing thick metal wiring with small line width spacing provided by the present invention.
[0027] Figure 5 A detailed flow chart of step 3 in the method for preparing thick metal wiring with small line width spacing provided by the present invention. DETAILED DESCRIPTION
[0028] In order to make the purpose, technical solution and beneficial effects of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments.
[0029] This embodiment provides a method for preparing thick metal wiring with small line width spacing, and the process is as follows: Figure 2 , Figure 3 As shown, the specific steps include:
[0030] Step 1: At least one groove group 220 and at least one silicon fin 230 are formed by etching on the surface of the silicon substrate 210, wherein the groove group 220 includes at least two linear grooves, and the silicon fin 230 is disposed between adjacent linear grooves; specifically, the silicon substrate 210 is as follows: Figure 3 As shown in (a), a groove group 220 and a silicon fin 230 are formed by etching in the silicon substrate 210. Figure 3As shown in (b);
[0031] Step 2: Oxidize the groove wall and the groove bottom of the groove group 220 through a silicon thermal oxidation process to form a silicon oxide dielectric layer 240. At the same time, completely oxidize the silicon fin 230 to form a silicon oxide fin 250, thereby forming an electrical isolation structure between adjacent linear grooves; specifically, oxidize the groove wall (groove side) and the groove bottom (groove bottom surface) of the groove group 220 through a silicon thermal oxidation process to form a silicon oxide dielectric layer 240, and the thickness of the formed silicon oxide dielectric layer is T2. At the same time, the silicon fin 230 is completely oxidized to form a silicon oxide fin 250 due to its small width. The width of the silicon oxide fin will be greater than the width of the silicon fin 230, and the width of the silicon oxide fin 250 is less than 2×T2, such as Figure 3 As shown in (c);
[0032] Step 3: depositing metal lines 260 in the grooves of the groove group; specifically, electroplating metal lines 260 in the linear grooves of the groove group, such as Figure 3 As shown in (d).
[0033] Furthermore, the specific process of step 1 is as follows Figure 4 As shown, the following steps are included:
[0034] Step 1.1, a patterned photoresist layer 310 is formed on the surface of the silicon substrate 210 by photolithography, wherein the line-shaped blank area 320 of the photoresist corresponds to the position of the groove group, including at least two line-shaped blank areas, and the central area 330 between adjacent line-shaped blank areas corresponds to the position of the silicon fin, and the side areas on both sides of the line-shaped blank area form a shielding for other surfaces of the silicon substrate, such as Figure 4 As shown in (a);
[0035] Step 1.2, using reactive ion etching process to perform silicon etching, etching the line-shaped blank area 320 on the surface of the silicon substrate to form a groove group 220, and synchronously forming silicon fins 230 between adjacent line-shaped grooves in the groove group, such as Figure 4 As shown in (b);
[0036] Step 1.3, remove the photoresist layer, such as Figure 4 As shown in (c).
[0037] Furthermore, the specific process of step 3 is as follows Figure 5 As shown, the following steps are included:
[0038] Step 3.1, sputtering a seed layer metal 410 on the surface of the groove bottom and groove wall of the groove group 220, such as Figure 5 As shown in (a);
[0039] Step 3.2: Use the seed layer metal 410 to perform metal electroplating to form electroplated metal 420 on the surface of the substrate 210 and in the grooves of the groove group 220, such as Figure 5 As shown in (b);
[0040] Step 3.3, remove the electroplated metal on the surface of the substrate 210 by grinding, chemical mechanical polishing or etching, and retain the seed layer metal 410 and the electroplated metal 420 inside the groove group, which together form the metal line 260, such as Figure 5 As shown in (c).
[0041] Furthermore, in a preferred embodiment, the seed layer metal is one or more of titanium, tantalum, titanium tungsten, titanium nitride, tantalum nitride and copper, and the electroplated metal is copper.
[0042] Furthermore, since the thickness, line width and spacing of the metal wiring are respectively related to the depth, width and spacing of the linear grooves, in a preferred embodiment, in order to achieve thick metal wiring with small line width and spacing, the depth of the linear grooves is greater than their width, and the depth of the linear grooves is greater than 3 microns; in addition, the depth of the linear grooves is greater than 2 times the spacing of the linear grooves (i.e., the width of the silicon fins).
[0043] Furthermore, since the thickness of thermally oxidized silicon required for complete thermal oxidation of the silicon fin needs to be greater than half the width of the silicon fin, in a preferred embodiment, in order to reduce the process time of thermal oxidation of the silicon fin and reduce the spacing of metal wiring, the width of the silicon fin is less than 2 microns.
[0044] The above description is only a specific implementation mode of the present invention. Any feature disclosed in this specification, unless otherwise stated, can be replaced by other alternative features that are equivalent or have similar purposes; all the disclosed features, or all the steps in the methods or processes, except for mutually exclusive features and / or steps, can be combined in any way.
Claims
1. A method for preparing thick metal wiring with small line width spacing, characterized in that: The following steps are involved: Step 1, etching on the surface of the silicon substrate to form at least one groove group and at least one silicon fin, wherein the groove group includes at least two linear grooves, and the silicon fin is arranged between adjacent linear grooves; Step 2: oxidizing the groove wall and the groove bottom of the groove group by a silicon thermal oxidation process to form a silicon oxide dielectric layer, and the silicon fin is simultaneously and completely oxidized to form a silicon oxide fin, thereby forming an electrical isolation structure between adjacent linear grooves; Step 3: Depositing metal lines in the grooves of the groove group.
2. The method for preparing thick metal wiring with small line width spacing according to claim 1, characterized in that: In step 1, the depth of the linear groove is greater than its width, and the depth of the linear groove is greater than twice the spacing between adjacent linear grooves.
3. The method for preparing thick metal wiring with small line width spacing according to claim 1, characterized in that: In step 1, the depth of the linear groove is greater than 3 microns, and the width of the silicon fin is less than 2 microns.
4. The method for preparing thick metal wiring with small line width spacing according to claim 1, characterized in that: In step 2, the thickness of the silicon oxide dielectric layer is T2, and the width of the silicon oxide fin is less than 2×T2.
5. The method for preparing thick metal wiring with small line width spacing according to claim 1, characterized in that: The specific process of step 1 is: Step 1.1, forming a patterned photoresist layer on the surface of the silicon substrate by photolithography, corresponding to the etching area of the reserved groove group; Step 1.2, etching silicon using a reactive ion etching process to form a groove group on the surface of the silicon substrate, and synchronously forming silicon fins between adjacent linear grooves in the groove group; Step 1.3, remove the photoresist layer.
6. The method for preparing thick metal wiring with small line width spacing according to claim 1, characterized in that: The specific process of step 3 is: Step 3.1, sputtering a seed layer of metal on the surface of the groove bottom and the groove wall of the groove group; Step 3.2, using the seed layer metal to perform metal electroplating to form electroplated metal in the groove group and on the surface of the substrate; Step 3.3: remove the metal on the surface of the substrate by grinding, chemical mechanical polishing or etching, and retain the seed layer metal and the electroplated metal in the groove group to form metal lines together.