A multi-layer stacked structure for a high-efficiency heat-dissipating high-power radio frequency chip and a preparation method thereof

Abstract

The present invention discloses a multi-layer stacked structure for a high-power radio frequency chip with high-efficiency heat dissipation and a preparation method thereof; the structure sequentially includes a base layer structure, a first active device layer, a first metal interconnection layer, a heat dissipation buffer layer, a second active device layer, a second metal interconnection layer, and a top-layer heat dissipation structure from bottom to top; wherein, the heat dissipation buffer layer adopts a microchannel structure filled with a phase change material to achieve active temperature regulation; the top-layer heat dissipation structure adopts a graphene-micro needle array composite design and has a switchable heat dissipation mode; this structure significantly improves the heat dissipation efficiency of the high-power radio frequency chip, improves the device reliability, reduces the influence of the heat dissipation structure on the radio frequency performance, and is applicable to high-frequency high-power application scenarios such as 5G communication.

Description

Technical Field

[0001] The present invention relates to the technical field of heat dissipation of radio frequency integrated circuits, and particularly relates to a multi-layer stacked structure for a high-power radio frequency chip with efficient heat dissipation and a preparation method thereof. Background Art

[0002] The operating frequency and power density of radio frequency integrated circuits are continuously increasing, and the problem of chip heating is becoming increasingly prominent; traditional single-layer radio frequency chips have problems in heat dissipation, such as a single heat dissipation channel, a large thermal resistance, and it is difficult to meet the heat dissipation requirements of high-power devices; during the chip stacking process, it is difficult to match the thermal stress between functional layers, which easily leads to a decrease in device reliability; existing heat dissipation structures have a large electromagnetic interference on high-frequency signals, affecting radio frequency performance; there is a lack of an effective temperature control mechanism, and local overheating is likely to occur under high-power operating conditions.

[0003] Currently, although the industry has proposed various improvement solutions, such as using microchannel heat dissipation, phase change material filling and other technologies, these solutions often only solve problems in one aspect and lack a systematic solution.

[0004] Therefore, there is an urgent need to develop a new type of multi-layer stacked structure that can simultaneously solve multiple key problems such as heat dissipation efficiency, thermal stress matching, and electromagnetic compatibility. Summary of the Invention

[0005] The purpose of the present invention is to solve the problems of low heat dissipation efficiency, poor thermal stress matching, and large electromagnetic interference in the prior art. Based on the multi-physical field coupling theory, using new composite materials and micro-nano structures, and adopting a hierarchical heat dissipation strategy, so as to achieve the purpose of efficient heat dissipation and reliable operation of high-power radio frequency chips.

[0006] In order to achieve the above object of the present invention, the present invention adopts the following technical solutions:

[0007] In the first aspect, the present invention provides a multi-layer stacked structure for a high-power radio frequency chip with efficient heat dissipation. The stacked structure sequentially includes from bottom to top: a base layer structure, a first active device layer, a first metal interconnection layer, a heat dissipation buffer layer, a second active device layer, a second metal interconnection layer, and a top heat dissipation structure.

[0008] The base layer structure includes from bottom to top: a metal substrate, an insulating dielectric layer, and a surface micro-groove structure; the metal substrate is made of a metal material with a thermal conductivity of not less than 200 W / (m·K) and a thickness of 0.5 - 2 mm; the insulating dielectric layer is composed of aluminum nitride or aluminum oxide with a thermal conductivity of not less than 170 W / (m·K) and a thickness of 0.2 - 0.5 mm; the surface micro-groove structure is periodically distributed with a groove depth of 10 - 50 μm, a period of 50 - 200 μm, and a groove wall inclination angle of 55° - 75°.

[0009] The first active device layer includes: a radio frequency power amplifier chip, a signal processing chip, wire bonding interconnections between chips, and a solder layer. The wire diameter of the wire bonding interconnections is 18 - 25 μm, and the arc height is 100 - 150 μm.

[0010] The first metal interconnection layer is used to connect the first active device layer and the heat dissipation buffer layer, and includes: multi - layer metal wiring with a gradient line width, vertical interconnection channels TSV, and a dielectric layer; the minimum line width of the signal line is 3 μm, and the maximum line width is 20 μm; the vertical interconnection channel TSV adopts a copper - filled structure with an aspect ratio of not less than 10:1; the dielectric constant of the dielectric layer is not greater than 3.0, and the loss tangent is not greater than 0.002.

[0011] The heat dissipation buffer layer includes a plurality of micro - channel structures, with a channel width of 50 - 200 μm, a depth of 150 - 300 μm, and a spacing of 200 - 400 μm; the micro - channel structures are filled with a phase - change material, with a phase - change temperature range of 60 - 80 °C and a latent heat of not less than 150 J / g; the coating on the channel wall is a hydrophilic coating, and the contact angle is less than 30°.

[0012] The second active device layer includes: a radio frequency transceiver chip and a digital control circuit; the second active device layer is evenly distributed with flip - chip solder interconnection structures and a heat dissipation bump array. The pitch of the solder joints of the flip - chip solder interconnection structures is not greater than 100 μm; the spacing of the heat dissipation bump array is 200 - 400 μm, and the height is 50 - 80 μm.

[0013] The second metal interconnection layer is used to connect the second active device layer and the top - layer heat dissipation structure. The second metal interconnection layer includes: a differential - pair wiring structure, with a line spacing of not greater than 3 times the line width; a power distribution network, adopting a grid - like structure, with a grid size of not greater than λ / 20; an electromagnetic shielding wall, with a height of not less than 5 times the signal line spacing.

[0014] The top - layer heat dissipation structure from bottom to top is successively: a copper thermal diffusion layer, a graphene heat conduction layer, a phase - change material layer, and a micro - needle array; the purity of the copper thermal diffusion layer is not less than 99.9%, and the thickness is 0.3 - 0.8 mm; the number of layers of the graphene heat conduction layer is 20 - 50 layers, and the thermal conductivity is not less than 3000 W / (m·K); the thermal conductivity of the phase - change material layer is not less than 5 W / (m·K); the height of the needles of the micro - needle array is 0.5 - 1.5 mm, the needle diameter is 50 - 100 μm, and the arrangement density is not less than 25 needles / mm 2 。

[0015] Further, the metal substrate is made of a copper-molybdenum-copper composite material or a copper-tungsten-copper composite material. The thermal expansion coefficient of the composite material matches that of the silicon chip and is 6-8 ppm / K. A grid-like micro-groove structure is provided at the bottom of the metal substrate, with a groove depth of 100-200 μm and a groove width of 200-400 μm.

[0016] Further, the phase change material in the heat dissipation buffer layer is a paraffin-based carbon nanotube composite material, and the volume fraction of carbon nanotubes is 5-10%. Silver particles with a diameter of 1-5 μm are uniformly distributed in the phase change material, and the surface of the silver particles is covered with an organic insulating layer with a thickness of 20-50 nm.

[0017] Further, the first metal interconnection layer and the second metal interconnection layer adopt the same multi-layer metal process, including a three-layer metal interconnection structure. The top and bottom layer metals use copper wires with a thickness of 3-5 μm, and the middle layer metal uses aluminum wires with a thickness of 1-2 μm. The density of the vertical interconnection channels TSV is not less than 100 per mm² in the first active device layer region and not less than 50 per mm 2 。

[0018] Further, the micro-needle array of the top layer heat dissipation structure is made of a copper-based alloy material, and the tip curvature radius is less than 10 μm. The surface of the micro-needles is plated with a gold layer with a thickness of 0.5-1 μm to prevent oxidation. The micro-needle array is used in combination with an air-cooled radiator or a liquid-cooled radiator. When the working temperature exceeds 90 °C, the heat dissipation system automatically switches to the forced liquid-cooling mode, and the coolant flow rate is not less than 0.5 L / min.

[0019] Further, the optimal thickness of the heat dissipation buffer layer is determined by a multi-physical field coupling model. The expression of the multi-physical field coupling model is: 。

[0020] Among them, ;

[0021] ;

[0022] ;

[0023] In the formula, is the reference thickness of the heat dissipation buffer layer, with a value of 200 μm, is the effective thermal conductivity of the heat dissipation buffer layer, which changes with the state of the phase change material and ranges from 5-20 W / (m·K); is the reference thermal conductivity, with a value of 1 W / (m·K); is the temperature gradient of the heat dissipation buffer layer, which does not exceed 15 K under normal working conditions; is the Rayleigh number of the microchannels in the heat dissipation buffer layer, with a value range - ; is the reference temperature gradient, with a value of 1 K; is the Prandtl number of the phase change material, with a value range of 5 - 15, is the dielectric constant of the heat dissipation buffer layer, with a value range of 2.5 - 3.5; is the reference dielectric constant, with a value of 1.0; is the frequency response coefficient of the heat dissipation buffer layer; is the operating frequency, with a value range of 28 - 40 GHz; is the reference frequency, with a value of 30 GHz; is the surface roughness of the heat dissipation buffer layer, with a value range of 0.5 - 2 μm; is the elastic modulus of the heat dissipation buffer layer, with a value range of 15 - 25 GPa; is the reference elastic modulus, with a value of 1 GPa; is the yield strength of the heat dissipation buffer layer, with a value range of 50 - 80 Mpa; is the reference stress, with a value of 1 Mpa is the Poisson's ratio of the heat dissipation buffer layer, with a value range of 0.28 - 0.32; is the working stress of the heat dissipation buffer layer, not exceeding 30 Mpa.

[0024] Furthermore, the thickness of the graphene heat conduction layer of the top - layer heat dissipation structure is calculated by the formula: ; where is the number of graphene layers, with a value range of 20 - 50 layers; is the thermal expansion coefficient of graphene, with a value of / K; is the operating temperature, in units of K, is the reference temperature, taking 293 K.

[0025] And a nano - silver paste transition layer with a thickness of 5 - 10 μm is provided between the graphene heat conduction layer and the phase change material layer. The silver content of the nano - silver paste is not less than 85 wt%, the sintering temperature is not higher than 250 °C, and the thermal conductivity after sintering is not less than 250 W / (m·K).

[0026] Second, the present invention provides a preparation method for a multi - layer stacked structure of a high - efficiency heat - dissipating high - power radio - frequency chip, used to prepare the multi - layer stacked structure in the first aspect; the preparation method includes the following steps:

[0027] Step S1, preparing a metal substrate;

[0028] The metal substrate is processed by an electrochemical polishing method, and a grid-like microgroove structure is formed at the bottom of the metal substrate by a laser etching process; the metal sheet is cut into the required size, and the metal sheet is made of copper or a composite metal of copper and molybdenum; the surface roughness is made to reach Ra≤0.2μm by an electrochemical polishing method to form a metal substrate; a grid-like microgroove structure is formed at the bottom of the metal substrate by a laser etching process; the surface of the metal substrate is subjected to plasma activation treatment to improve the bonding strength with the insulating dielectric layer.

[0029] Step S2, preparing an insulating dielectric layer and a microgroove structure;

[0030] An insulating dielectric layer is deposited on the metal substrate by a plasma enhanced chemical vapor deposition method, and a surface microgroove structure is prepared by a photolithography process.

[0031] A thin film of aluminum nitride or aluminum oxide is deposited on the metal substrate by a plasma enhanced chemical vapor deposition (PECVD) method; the deposition temperature is controlled at , and the deposition rate is ; after the deposition is completed, annealing is performed for 4-8 hours in a nitrogen atmosphere of to eliminate internal stress.

[0032] A photoresist is coated on the surface of the insulating dielectric layer, and a microgroove pattern is formed by exposure and development; a microgroove structure is formed by using a reactive ion etching RIE process; after the photoresist is removed, of passivation layer is deposited on the inner wall of the trench by atomic layer deposition ALD.

[0033] Step S3, preparing a first active device layer;

[0034] A titanium / copper / gold multi-layer metal thin film is deposited on the microgroove surface by magnetron sputtering as a chip soldering layer; a solder is coated by a precision template screen printing technique with a thickness of 30-50μm; an RF power amplifier chip and a signal processing chip are placed by using a precision chip mounter; reflow soldering is performed in a nitrogen atmosphere at 250-280°C; chip-to-chip interconnection is completed by an ultrasonic gold wire bonding technique with a wire diameter of 18-25μm and an arc height of 100-150μm.

[0035] Step S4, preparing a first metal interconnection layer;

[0036] A dielectric layer with a dielectric constant not greater than 3.0 is deposited by low-temperature PECVD; a vertical interconnection channel TSV with an aspect ratio not less than 10:1 is formed by DRIE; a diffusion barrier layer is deposited on the inner wall of the TSV by ion beam assisted deposition; the TSV is filled by a pulse electroplating process; a multi-layer metal wiring with a gradient line width is formed by a dual damascene process, and the minimum line width of the signal line is 3μm and the maximum line width is 20μm.

[0037] Step S5, prepare a heat dissipation buffer layer;

[0038] Use the DRIE process to form a microchannel structure with a channel width of 50 - 200 μm, a depth of 150 - 300 μm, and a pitch of 200 - 400 μm; deposit a hydrophilic coating on the inner wall of the microchannel using electrochemcial deposition technology to make the contact angle less than 30°; prepare a phase change material with a phase change temperature range of 60 - 80 °C and a latent heat of not less than 150 J / g; fill the microchannel using the vacuum perfusion method; perform heat treatment at 90 - 110 °C for 1 - 2 hours.

[0039] Step S6, prepare a second active device layer;

[0040] Place the RF transceiver chip and the digital control circuit using the flip - chip bonding process, with a solder joint pitch of no more than 100 μm; prepare a heat dissipation bump array with a pitch of 200 - 400 μm and a height of 50 - 80 μm.

[0041] Step S7, prepare a second metal interconnection layer;

[0042] Form a differential pair wiring structure with a line pitch of no more than 3 times the line width; fabricate a grid - shaped power distribution network with a grid size of no more than λ / 20, where λ is the free - space wavelength corresponding to the operating frequency; set an electromagnetic shielding wall with a height of no less than 5 times the signal line pitch.

[0043] Step S8, prepare a top - layer heat dissipation structure;

[0044] Deposit a copper - based thermal diffusion layer with a purity of not less than 99.9% and a thickness of 0.3 - 0.8 mm; grow a graphene thermal conduction layer with 20 - 50 layers and a thermal conductivity of not less than 3000 W / (m·K); coat a phase change material layer with a thermal conductivity of not less than 5 W / (m·K); fabricate a micro - needle array with a needle height of 0.5 - 1.5 mm, a needle diameter of 50 - 100 μm, and an arrangement density of not less than 25 needles / mm 2 of.

[0045] Further, the electro - chemical polishing uses a mixed solution of phosphoric acid and sulfuric acid with a volume ratio of 3:1, the temperature is controlled at 40 ± 5 °C, and the current density is 20 - 30 mA / cm 2 ; the laser etching uses a pulsed laser with a wavelength of 1064 nm, a pulse width of 100 - 200 ns, and an energy density of 2 - 5 J / cm 2 ;

[0046] The process gas for PECVD deposition is a mixed gas of trimethylaluminum and ammonia with a flow ratio of 1:5, the RF power is 200 - 300 W, and the substrate temperature is 350 ± 20 °C; the photolithography uses a positive photoresist with an exposure energy of 100 - 150 mJ / cm 2 .

[0047] Further, the thickness ratio of the multi-layer metal thin film is Ti / Cu / Au = 50 nm / 2 μm / 0.5 μm; the welding temperature gradient is controlled within 2 °C / s; the bonding force of the gold wire bonding is 20 - 30 gf.

[0048] The loss tangent of the dielectric layer is not greater than 0.002; the thickness of the diffusion barrier layer on the inner wall of the TSV is 50 - 100 nm; the current density of the pulse electroplating is 2 - 5 mA / cm 2 。

[0049] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0050] The present invention adopts a multi-layer stacked structure and multiple heat dissipation channels, significantly improving the heat dissipation efficiency; tests show that under the same power density, the thermal resistance of the present invention is reduced by more than 50% compared with the traditional structure; the heat dissipation buffer layer is innovatively introduced, and the micro-channel structure filled with phase change material is adopted to realize active temperature control, which can effectively prevent local overheating; through the optimized material design and structure matching, the thermal expansion coefficient matching between functional layers is achieved, significantly improving the reliability and service life of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Figure 1 It is a schematic diagram of the composition of a multi-layer stacked structure of a high-efficiency heat dissipation high-power RF chip according to the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0052] In order to make the objectives, technical solutions and advantages of the present invention clearer, the technical solutions in the present invention will be described clearly and completely below. Apparently, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art without making creative efforts based on the embodiments in the present invention belong to the scope of protection of the present invention.

[0053] Embodiment 1

[0054] As Figure 1 shown, the present invention provides a multi-layer stacked structure of a high-efficiency heat dissipation high-power RF chip. The stacked structure sequentially includes, from bottom to top: a base layer structure, a first active device layer, a first metal interconnection layer, a heat dissipation buffer layer, a second active device layer, a second metal interconnection layer, and a top heat dissipation structure.

[0055] The base layer structure includes, from bottom to top: a metal substrate, an insulating dielectric layer, and a surface micro-groove structure; the metal substrate is made of a metal material with a thermal conductivity of not less than 200 W / (m·K) and has a thickness of 0.5 - 2 mm; the insulating dielectric layer is composed of aluminum nitride or aluminum oxide, has a thermal conductivity of not less than 170 W / (m·K), and has a thickness of 0.2 - 0.5 mm; the surface micro-groove structure is periodically distributed, with a groove depth of 10 - 50 μm, a period of 50 - 200 μm, and a groove wall inclination angle of 55° - 75°.

[0056] The first active device layer includes: a radio frequency power amplifier chip, a signal processing chip, wire bonding interconnections between chips, and a solder layer. The wire diameter of the wire bonding interconnections is 18 - 25 μm, and the arc height is 100 - 150 μm.

[0057] The first metal interconnection layer is used to connect the first active device layer and the heat dissipation buffer layer, and includes: multi-layer metal wirings with a gradient line width, vertical interconnection channels TSV, and a dielectric layer; the minimum line width of the signal line is 3 μm, and the maximum line width is 20 μm; the vertical interconnection channel TSV uses a copper filling structure with an aspect ratio of not less than 10:1; the dielectric constant of the dielectric layer is not greater than 3.0, and the loss tangent is not greater than 0.002.

[0058] The heat dissipation buffer layer includes a plurality of micro-channel structures, with a channel width of 50 - 200 μm, a depth of 150 - 300 μm, and a spacing of 200 - 400 μm; the micro-channel structures are filled with a phase change material, with a phase change temperature range of 60 - 80 °C and a latent heat of not less than 150 J / g; the coating on the channel wall uses a hydrophilic coating, and the contact angle is less than 30°.

[0059] The second active device layer includes: a radio frequency transceiver chip and a digital control circuit; the second active device layer is evenly distributed with flip-chip solder interconnection structures and a heat dissipation bump array. The pitch of the solder joints of the flip-chip solder interconnection structures is not greater than 100 μm; the pitch of the heat dissipation bump array is 200 - 400 μm, and the height is 50 - 80 μm.

[0060] The second metal interconnection layer is used to connect the second active device layer and the top heat dissipation structure. The second metal interconnection layer includes: a differential pair wiring structure, with a line spacing of not greater than 3 times the line width; a power distribution network, using a grid-like structure, with a grid size of not greater than λ / 20; an electromagnetic shielding wall, with a height of not less than 5 times the signal line spacing.

[0061] The top - layer heat - dissipation structure from bottom to top is successively: a copper - based thermal diffusion layer, a graphene thermal - conduction layer, a phase - change material layer, and a micro - needle array; the purity of the copper - based thermal diffusion layer is not less than 99.9%, and its thickness is 0.3 - 0.8 mm; the number of layers of the graphene thermal - conduction layer is 20 - 50 layers, and its thermal conductivity is not less than 3000 W / (m·K); the thermal conductivity of the phase - change material layer is not less than 5 W / (m·K); the height of the needles in the micro - needle array is 0.5 - 1.5 mm, the needle diameter is 50 - 100 μm, and the arrangement density is not less than 25 needles / mm 2 。

[0062] The metal substrate is made of a copper - molybdenum - copper composite material or a copper - tungsten - copper composite material. The thermal expansion coefficient of the composite material matches that of the silicon chip, which is 6 - 8 ppm / K; a grid - shaped micro - trench structure is provided at the bottom of the metal substrate, the trench depth is 100 - 200 μm, and the trench width is 200 - 400 μm.

[0063] The phase - change material in the heat - dissipation buffer layer is a paraffin - based carbon - nanotube composite material, and the volume fraction of carbon nanotubes is 5 - 10%; silver particles with a diameter of 1 - 5 μm are uniformly distributed in the phase - change material, and the surface of the silver particles is covered with an organic insulating layer with a thickness of 20 - 50 nm.

[0064] The first metal interconnection layer and the second metal interconnection layer adopt the same multi - layer metal process, including a three - layer metal interconnection structure; the top - layer and bottom - layer metals use copper wires with a thickness of 3 - 5 μm, and the middle - layer metal uses aluminum wires with a thickness of 1 - 2 μm; the density of the vertical interconnection channels TSV is not less than 100 per mm² in the first active - device layer region and not less than 50 per mm in the heat - dissipation buffer layer region 2 。

[0065] The micro - needle array of the top - layer heat - dissipation structure is made of a copper - based alloy material, and the tip curvature radius is less than 10 μm; a gold layer with a thickness of 0.5 - 1 μm is plated on the surface of the micro - needles to prevent oxidation; the micro - needle array is used in conjunction with an air - cooled radiator or a liquid - cooled radiator. When the working temperature exceeds 90 °C, the heat - dissipation system automatically switches to the forced liquid - cooling mode, and the coolant flow rate is not less than 0.5 L / min.

[0066] The optimal thickness of the heat - dissipation buffer layer is determined by a multi - physical - field coupling model, and the expression of the multi - physical - field coupling model is: 。

[0067] Among them, ;

[0068] ;

[0069] ;

[0070] In the formula, is the reference thickness of the heat dissipation buffer layer, with a value of 200μm, is the effective thermal conductivity of the heat dissipation buffer layer, which changes with the state of the phase change material and ranges from 5 - 20W / (m·K); is the reference thermal conductivity, with a value of 1W / (m·K); is the temperature gradient of the heat dissipation buffer layer, which does not exceed 15K under normal working conditions; is the Rayleigh number of the microchannels in the heat dissipation buffer layer, and the value range is - ; is the reference temperature gradient, with a value of 1K; is the Prandtl number of the phase change material, and the value range is 5 - 15, is the dielectric constant of the heat dissipation buffer layer, and the value range is 2.5 - 3.5; is the reference dielectric constant, with a value of 1.0; is the frequency response coefficient of the heat dissipation buffer layer; is the operating frequency, and the value range is 28 - 40GHz; is the reference frequency, with a value of 30GHz; is the surface roughness of the heat dissipation buffer layer, and the value range is 0.5 - 2μm; is the elastic modulus of the heat dissipation buffer layer, and the value range is 15 - 25Gpa; is the reference elastic modulus, with a value of 1Gpa; is the yield strength of the heat dissipation buffer layer, and the value range is 50 - 80Mpa; is the reference stress, with a value of 1Mpa is the Poisson's ratio of the heat dissipation buffer layer, and the value range is 0.28 - 0.32; is the working stress of the heat dissipation buffer layer, which does not exceed 30Mpa.

[0071] The thickness of the graphene thermal conduction layer of the top - layer heat dissipation structure is calculated by the formula: ; where, is the number of graphene layers, and the value range is 20 - 50 layers; is the thermal expansion coefficient of graphene, with a value of / K; is the working temperature, in units of K, is the reference temperature, taking 293K.

[0072] And a nano-silver paste transition layer with a thickness of 5 - 10 μm is provided between the graphene heat conduction layer and the phase change material layer. The silver content of the nano-silver paste is not less than 85 wt%, the sintering temperature is not higher than 250 °C, and the thermal conductivity after sintering is not less than 250 W / (m·K).

[0073] In addition, an electromagnetic compatibility isolation structure is provided between the first active device layer and the second active device layer. The isolation structure includes: an electromagnetic shielding layer with a thickness of 10 - 30 μm, made of copper - , with a bandgap width of 5 - 15 GHz.

[0074] Radiation suppression trench array, the trench depth is , and the pitch is ; where is the free - space wavelength corresponding to the operating frequency; the total thickness of the electromagnetic compatibility isolation structure is determined by the following relationship:

[0075] In the formula: is the conductivity of the electromagnetic shielding layer in S / m; is the permeability of the electromagnetic shielding layer in H / m; is the operating frequency in Hz.

[0076] And a grounding ring with a width of not less than 200 μm is provided in the edge area of the electromagnetic compatibility isolation structure. The grounding ring is connected to the metal substrate through at least 4 TSVs on each side.

[0077] In order to further improve the heat dissipation efficiency and electromagnetic shielding effect, the following optimization measures can also be taken between the layers:

[0078] A thermal diffusion layer with a thickness of 30 - 50 μm is added between the first active device layer and the heat dissipation buffer layer, filled with a diamond - filled copper - based composite material with a high thermal conductivity (> 380 W / m·K) to effectively alleviate the hot - spot effect.

[0079] Grounding shield lines are arranged on both sides of the differential - pair wiring in the second metal interconnection layer, with a line width 1.5 - 2 times that of the signal line, reducing crosstalk by more than 30%.

[0080] Plasma treatment is performed on the surface of the micro - needle array of the top - layer heat dissipation structure to form a micro - structure with a surface roughness Ra of 0.8 - 1.2 μm, increasing the contact area with the coolant.

[0081] Periodic micro - groove structures are arranged on the inner wall of the micro - channels in the heat dissipation buffer layer, with a groove depth of 2 - 5 μm and a period of 10 - 20 μm, enhancing the heat transfer coefficient by 15 - 25%.

[0082] Example 2

[0083] A preparation method for a multi-layer stacked structure of a high-efficiency heat dissipation high-power radio frequency chip, which is used to prepare the multi-layer stacked structure of Example 1.

[0084] The preparation method includes the following steps:

[0085] Step S1, prepare a metal substrate;

[0086] Treat the metal substrate by electrochemical polishing, and form a grid-like micro-groove structure at the bottom of the metal substrate by laser etching process; cut the metal sheet into the required size, and the metal sheet is made of copper or a composite metal of copper and molybdenum; use electrochemical polishing method to make the surface roughness reach Ra≤0.2μm to form a metal substrate; form a grid-like micro-groove structure at the bottom of the metal substrate; perform plasma activation treatment on the surface of the metal substrate to improve the bonding strength with the insulating dielectric layer.

[0087] Step S2, prepare an insulating dielectric layer and a micro-groove structure;

[0088] Deposit an insulating dielectric layer on the metal substrate by plasma enhanced chemical vapor deposition method, and prepare a surface micro-groove structure by photolithography process.

[0089] Deposit aluminum nitride or aluminum oxide thin film on the metal substrate by plasma enhanced chemical vapor deposition (PECVD) method; control the deposition temperature at , and the deposition rate is ; after the deposition is completed, anneal in nitrogen atmosphere for 4-8 hours to eliminate internal stress.

[0090] Coat photoresist on the surface of the insulating dielectric layer, expose and develop to form a micro-groove pattern; use reactive ion etching (RIE) process to form a micro-groove structure; after removing the photoresist, deposit of passivation layer on the inner wall of the trench by atomic layer deposition (ALD).

[0091] Step S3, prepare the first active device layer;

[0092] Deposit a titanium / copper / gold multi-layer metal film as a chip welding layer on the micro-groove surface by magnetron sputtering; coat solder by precision template screen printing technology, with a thickness of 30-50μm; use a precision pick-and-place machine to place a radio frequency power amplifier chip and a signal processing chip; perform reflow soldering in a nitrogen atmosphere at 250-280°C; complete the interconnection between chips by ultrasonic gold wire bonding technology, with a wire diameter of 18-25μm and an arc height of 100-150μm.

[0093] Step S4, prepare the first metal interconnection layer;

[0094] Deposit a dielectric layer with a dielectric constant not greater than 3.0 using low-temperature PECVD; form a vertical interconnect via TSV with an aspect ratio of not less than 10:1 through DRIE; deposit a diffusion barrier layer on the inner wall of the TSV using ion beam assisted deposition; fill the TSV using a pulse electroplating process; form a multi-layer metal wiring with a gradient line width using a dual damascene process, where the minimum line width of the signal line is 3μm and the maximum line width is 20μm.

[0095] Step S5, prepare a heat dissipation buffer layer;

[0096] Form a microchannel structure using the DRIE process, with a channel width of 50 - 200μm, a depth of 150 - 300μm, and a pitch of 200 - 400μm; deposit a hydrophilic coating on the inner wall of the microchannel using an electrochemical deposition technique to make the contact angle less than 30°; prepare a phase change material with a phase change temperature range of 60 - 80°C and a latent heat of not less than 150 J / g; fill the microchannel using a vacuum perfusion method; perform heat treatment at 90 - 110°C for 1 - 2 hours.

[0097] Step S6, prepare a second active device layer;

[0098] Place the RF transceiver chip and the digital control circuit using a flip-chip bonding process, with a solder joint pitch of not greater than 100μm; prepare a heat dissipation bump array with a pitch of 200 - 400μm and a height of 50 - 80μm.

[0099] Step S7, prepare a second metal interconnect layer;

[0100] Form a differential pair wiring structure with a line pitch of not greater than 3 times the line width; fabricate a grid-shaped power distribution network with a grid size of not greater than λ / 20, where λ is the free space wavelength corresponding to the operating frequency; set an electromagnetic shielding wall with a height of not less than 5 times the signal line pitch.

[0101] Step S8, prepare a top-layer heat dissipation structure;

[0102] Deposit a copper thermal diffusion layer with a purity of not less than 99.9% and a thickness of 0.3 - 0.8mm; grow a graphene thermal conduction layer with 20 - 50 layers and a thermal conductivity of not less than 3000 W / (m·K); coat a phase change material layer with a thermal conductivity of not less than 5 W / (m·K); fabricate a micro-needle array with a needle height of 0.5 - 1.5mm, a needle diameter of 50 - 100μm, and an arrangement density of not less than 25 needles / mm 2 of the micro-needle array.

[0103] Electrochemical polishing uses a mixed solution of phosphoric acid and sulfuric acid with a volume ratio of 3:1, the temperature is controlled at 40 ± 5°C, and the current density is 20 - 30mA / cm 2 ; Laser etching uses a pulsed laser with a wavelength of 1064nm, a pulse width of 100 - 200ns, and an energy density of 2 - 5J / cm 2 ;

[0104] The process gas for PECVD deposition is a mixed gas of trimethylaluminum and ammonia, with a flow rate ratio of 1:5, a radio frequency power of 200 - 300 W, and a substrate temperature of 350 ± 20 °C; positive photoresist is used for lithography, and the exposure energy is 100 - 150 mJ / cm 2 .

[0105] The thickness ratio of the multi-layer metal film is Ti / Cu / Au = 50 nm / 2 μm / 0.5 μm; the welding temperature gradient is controlled within 2 °C / s; the bonding force of the gold wire bonding is 20 - 30 gf.

[0106] The loss tangent of the dielectric layer is not greater than 0.002; the thickness of the diffusion barrier layer on the inner wall of the TSV is 50 - 100 nm; the current density of pulse electroplating is 2 - 5 mA / cm 2 .

[0107] The hydrophilic coating for electrochemical deposition uses a nickel-phosphorus alloy, and the deposition potential is -0.8 to -1.2 V; the phase change material is a paraffin-based carbon nanotube composite, and the volume fraction of carbon nanotubes is 5 - 10%;

[0108] In step S6, lead-free solder paste is used for flip-chip soldering, and the maximum reflow temperature is controlled at 260 ± 5 °C; the heat dissipation bumps use a copper pillar electroplating process, and the current density is 10 - 15 mA / cm²; in step S7, the characteristic impedance of the differential pair wiring is controlled at 100 ± 5 Ω; the electromagnetic shielding wall uses a copper-nickel plating process, and the nickel layer thickness is 0.5 - 1 μm; in step S8, graphene is grown by chemical vapor deposition, and the growth temperature is 1000 ± 50 °C; the micro-needle array uses an electrochemical etching process, and the etching solution is a ferric chloride solution.

[0109] The multi-layer stacked structure of the present invention is applied to a 5G millimeter-wave base station power amplifier, and the specific parameters are as follows:

[0110] Operating frequency: 39 GHz; Output power: >10 W; Power density: >5 W / mm²; Operating temperature range: -40 °C to +85 °C.

[0111] Using the stacked structure of the present invention, the test results after continuous operation for 8 hours are as follows:

[0112] Junction temperature: The maximum temperature is 85.6 °C, and the temperature uniformity is ±3.2 °C; Thermal resistance: 0.42 °C / W, which is 56% lower than the traditional structure; RF performance: Small signal gain 24.5 dB, output power saturation point 42.5 dBm, power added efficiency (PAE) 45%; Reliability: After 1000 temperature cycles of -40 °C / +125 °C, there is no performance degradation.

[0113] Compared with the prior art, the heat dissipation performance is improved: the thermal resistance is reduced by 56%, and the temperature uniformity is increased by 40%; the radio frequency performance is improved: the PAE is increased by 5 percentage points, and the output power is increased by 1.2 dB; the reliability is improved: the MTTF (mean time to failure) is increased by 2.5 times.

[0114] The above test results show that while ensuring the high-frequency performance, the multi-layer stacked structure of the present invention significantly improves the heat dissipation effect and reliability of high-power radio frequency chips, meeting the actual application requirements of 5G millimeter-wave base stations.

[0115] The specific embodiments described above further elaborate on the purpose, technical solutions and beneficial effects of the present invention. It should be understood that the above are only specific embodiments of the present invention and are not used to limit the protection scope of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. An efficient heat dissipation multi-layer stacked structure for high-power radio frequency chips, characterized in that, The stacked structure sequentially includes, from bottom to top: a base layer structure, a first active device layer, a first metal interconnection layer, a heat dissipation buffer layer, a second active device layer, a second metal interconnection layer, and a top heat dissipation structure; The base layer structure includes, from bottom to top: a metal substrate, an insulating dielectric layer, and a surface microgroove structure; the metal substrate is made of a metal material with a thermal conductivity of not less than 200 W / (m·K) and has a thickness of 0.5 - 2 mm; the insulating dielectric layer is composed of aluminum nitride or aluminum oxide, has a thermal conductivity of not less than 170 W / (m·K), and has a thickness of 0.2 - 0.5 mm; the surface microgroove structure is periodically distributed, with a groove depth of 10 - 50 μm, a period of 50 - 200 μm, and a groove wall inclination angle of 55° - 75°; The first active device layer includes: a radio frequency power amplifier chip, a signal processing chip, wire bonding interconnections between chips, and a solder layer. The wire diameter of the wire bonding interconnections is 18 - 25 μm, and the arc height is 100 - 150 μm; The first metal interconnection layer is used to connect the first active device layer and the heat dissipation buffer layer and includes: multi-layer metal wiring with a gradient line width, vertical interconnection channels TSV, and a dielectric layer; the minimum line width of the signal line is 3 μm, and the maximum line width is 20 μm; the vertical interconnection channel TSV adopts a copper-filled structure with an aspect ratio of not less than 10:1; the dielectric constant of the dielectric layer is not greater than 3.0, and the loss tangent is not greater than 0.002; The heat dissipation buffer layer includes a plurality of microchannel structures, with a channel width of 50 - 200 μm, a depth of 150 - 300 μm, and a spacing of 200 - 400 μm; the microchannel structures are filled with a phase change material, with a phase change temperature range of 60 - 80 °C and a latent heat of not less than 150 J / g; the coating on the channel wall adopts a hydrophilic coating, with a contact angle of less than 30°; The second active device layer includes: a radio frequency transceiver chip and a digital control circuit; the second active device layer is evenly distributed with flip-chip bonding interconnection structures and a heat dissipation bump array. The pitch of the solder joints of the flip-chip bonding interconnection structures is not greater than 100 μm; the spacing of the heat dissipation bump array is 200 - 400 μm, and the height is 50 - 80 μm; The second metal interconnection layer is used to connect the second active device layer and the top heat dissipation structure. The second metal interconnection layer includes: a differential pair wiring structure, with a line spacing of not greater than 3 times the line width; a power distribution network, adopting a grid-like structure, with a grid size of not greater than λ / 20; an electromagnetic shielding wall, with a height of not less than 5 times the signal line spacing; The top-layer heat dissipation structure from bottom to top is successively: a copper thermal diffusion layer, a graphene heat conduction layer, a phase change material layer, and a micro-needle array; the purity of the copper thermal diffusion layer is not less than 99.9%, and the thickness is 0.3 - 0.8 mm; the number of layers of the graphene heat conduction layer is 20 - 50 layers, and the thermal conductivity is not less than 3000 W / (m·K); the thermal conductivity of the phase change material layer is not less than 5 W / (m·K); the needle height of the micro-needle array is 0.5 - 1.5 mm, the needle diameter is 50 - 100 μm, and the arrangement density is not less than 25 needles / mm 2 .

2. The multi-layer stacked structure of a high-efficiency heat dissipation high-power radio frequency chip according to claim 1, wherein The metal substrate is made of a copper - molybdenum - copper composite material or a copper - tungsten - copper composite material. The thermal expansion coefficient of the composite material is matched with that of the silicon chip, which is 6 - 8 ppm / K; a grid-like microgroove structure is provided at the bottom of the metal substrate, with a groove depth of 100 - 200 μm and a groove width of 200 - 400 μm.

3. An efficient heat dissipation multi-layer stacked structure for high-power RF chips according to claim 2, characterized in that, The phase change material in the heat dissipation buffer layer is a paraffin - based carbon nanotube composite material, with a carbon nanotube volume fraction of 5 - 10%; silver particles with a diameter of 1 - 5 μm are evenly distributed in the phase change material, and the surface of the silver particles is covered with an organic insulating layer with a thickness of 20 - 50 nm.

4. An efficient heat dissipation multi-layer stacked structure for high-power RF chips according to claim 3, characterized in that, The first metal interconnect layer and the second metal interconnect layer adopt the same multi-layer metal process, including a three-layer metal interconnect structure; the top and bottom layer metals are copper wires with a thickness of 3-5 μm, and the middle layer metal is an aluminum wire with a thickness of 1-2 μm; the density of the vertical interconnect channels TSV is not less than 100 per mm² in the first active device layer region and not less than 50 per mm in the heat dissipation buffer layer region 2 .

5. An efficient heat dissipation multi-layer stacked structure for high-power radio frequency chips according to claim 4, characterized in that The microneedle array of the top-layer heat dissipation structure is made of a copper-based alloy material, and the tip curvature radius is less than 10 μm; a gold layer with a thickness of 0.5 - 1 μm is plated on the microneedle surface to prevent oxidation; the microneedle array is used in combination with an air-cooled radiator or a liquid-cooled radiator. When the working temperature exceeds 90 °C, the heat dissipation system automatically switches to the forced liquid-cooling mode, and the coolant flow rate is not less than 0.5 L / min.

6. An efficient heat dissipation multi-layer stacked structure for high-power radio frequency chips according to any one of claims 1-5, characterized in that, The optimal thickness of the heat dissipation and buffer layer is determined by a multi-physical field coupling model, and the expression of the multi-physical field coupling model is as follows: ; Among them, ; ； ； Wherein, is the reference thickness of the heat dissipation buffer layer, with a value of 200μm, is the effective thermal conductivity of the heat dissipation buffer layer, which varies with the state of the phase change material and ranges from 5 - 20W / (m·K); is the reference thermal conductivity, with a value of 1W / (m·K); is the temperature gradient of the heat dissipation buffer layer, which does not exceed 15K under normal working conditions; is the Rayleigh number of the microchannels in the heat dissipation buffer layer, and the value range is - ; is the reference temperature gradient, with a value of 1K; is the Prandtl number of the phase change material, and the value range is 5 - 15, is the dielectric constant of the heat dissipation buffer layer, and the value range is 2.5 - 3.5; is the reference dielectric constant, with a value of 1.0; is the frequency response coefficient of the heat dissipation buffer layer; is the operating frequency, and the value range is 28 - 40GHz; is the reference frequency, with a value of 30GHz; is the surface roughness of the heat dissipation buffer layer, and the value range is 0.5 - 2μm; is the elastic modulus of the heat dissipation buffer layer, and the value range is 15 - 25Gpa; is the reference elastic modulus, with a value of 1Gpa; is the yield strength of the heat dissipation buffer layer, and the value range is 50 - 80Mpa; is the reference stress, with a value of 1Mpa is the Poisson's ratio of the heat dissipation buffer layer, and the value range is 0.28 - 0.32; is the working stress of the heat dissipation buffer layer, which does not exceed 30Mpa.

7. An efficient heat dissipation multi-layer stacked structure for high-power RF chips according to claim 6, characterized in that The thickness of the graphene thermal conduction layer of the top-layer heat dissipation structure is calculated by the formula: ; where is the number of graphene layers, and the value range is 20 - 50 layers; is the thermal expansion coefficient of graphene, and the value is / K; is the working temperature, in the unit of K, is the reference temperature, taken as 293K; And a nano-silver paste transition layer with a thickness of 5 - 10 μm is provided between the graphene heat conduction layer and the phase change material layer. The silver content of the nano-silver paste is not less than 85 wt%, the sintering temperature is not higher than 250 °C, and the thermal conductivity after sintering is not less than 250 W / (m·K).

8. A method for preparing a multi-layer stacked structure of a high-efficiency heat-dissipating high-power radio frequency chip, which is used to prepare the multi-layer stacked structure according to any one of claims 1-7; characterized in that, The preparation method includes the following steps: Step S1, prepare a metal substrate; The metal substrate is processed by an electrochemical polishing method, and a grid-like micro-groove structure is formed at the bottom of the metal substrate by a laser etching process; the metal sheet is cut into the required size, and the metal sheet is a composite metal of copper or copper and molybdenum; the surface roughness is made to reach Ra≤0.2 μm by an electrochemical polishing method to form a metal substrate; a grid-like micro-groove structure is formed at the bottom of the metal substrate by a laser etching process; the surface of the metal substrate is subjected to plasma activation treatment to improve the bonding strength with the insulating dielectric layer; Step S2, prepare an insulating dielectric layer and a micro-groove structure; An insulating dielectric layer is deposited on the metal substrate by a plasma-enhanced chemical vapor deposition method, and a surface micro-groove structure is prepared by a photolithography process; Deposit aluminum nitride or aluminum oxide thin films on a metal substrate by plasma-enhanced chemical vapor deposition (PECVD); control the deposition temperature at , and the deposition rate is ; after deposition, anneal in a nitrogen atmosphere of for 4-8 hours to eliminate internal stress; A photoresist is coated on the surface of the insulating dielectric layer, and a microgroove pattern is formed by exposure and development; a reactive ion etching (RIE) process is used to form a microgroove structure; after removing the photoresist, an atomic layer deposition (ALD) is adopted to deposit a passivation layer on the inner wall of the groove; Step S3, prepare a first active device layer; A titanium / copper / gold multi-layer metal thin film is deposited on the micro-groove surface by magnetron sputtering as a chip soldering layer; solder is coated by a precision template screen printing technique with a thickness of 30 - 50 μm; an RF power amplifier chip and a signal processing chip are placed using a precision pick-and-place machine; reflow soldering is carried out in a nitrogen atmosphere at 250 - 280 °C; chip-to-chip interconnection is completed by an ultrasonic gold wire bonding technique, with a wire diameter of 18 - 25 μm and an arc height of 100 - 150 μm; Step S4, prepare a first metal interconnection layer; A dielectric layer with a dielectric constant not greater than 3.0 is deposited by low-temperature PECVD; a vertical interconnection channel TSV with an aspect ratio not less than 10:1 is formed by DRIE; a diffusion barrier layer is deposited on the inner wall of the TSV by ion beam-assisted deposition; the TSV is filled by a pulse electroplating process; a multi-layer metal wiring with a gradient line width is formed by a dual damascene process, with a minimum line width of 3 μm and a maximum line width of 20 μm for the signal line; Step S5, prepare a heat dissipation buffer layer; A micro-channel structure is formed by a DRIE process, with a channel width of 50 - 200 μm, a depth of 150 - 300 μm, and a spacing of 200 - 400 μm; a hydrophilic coating is deposited on the inner wall of the micro-channel by an electrochemical deposition technique to make the contact angle less than 30°; a phase change material with a phase change temperature range of 60 - 80 °C and a latent heat not less than 150 J / g is formulated; the micro-channel is filled by a vacuum perfusion method; heat treatment is carried out at 90 - 110 °C for 1 - 2 hours; Step S6, prepare a second active device layer; The radio frequency transceiver chip and the digital control circuit are placed using the flip-chip bonding process, and the solder joint pitch is no more than 100 μm; a heat dissipation bump array is prepared with a pitch of 200 - 400 μm and a height of 50 - 80 μm; Step S7, prepare the second metal interconnection layer; A differential pair wiring structure is formed with a line pitch no more than 3 times the line width; a grid-shaped power distribution network is fabricated with a grid size no more than λ / 20, where λ is the free space wavelength corresponding to the operating frequency; an electromagnetic shielding wall with a height no less than 5 times the signal line pitch is set; Step S8, prepare the top layer heat dissipation structure; A copper thermal diffusion layer with a deposition purity of not less than 99.9% and a thickness of 0.3 - 0.8 mm; a graphene heat conduction layer grown with 20 - 50 layers and a thermal conductivity of not less than 3000 W / (m·K); a phase change material layer coated with a thermal conductivity of not less than 5 W / (m·K); fabricating a microneedle array with a needle height of 0.5 - 1.5 mm, a needle diameter of 50 - 100 μm, and an arrangement density of not less than 25 needles / mm 2 of the microneedle array.

9. The preparation method of a multi-layer stacked structure of a high-efficiency heat dissipation high-power radio frequency chip according to claim 8, wherein, Electrochemical polishing uses a mixed solution of phosphoric acid and sulfuric acid with a volume ratio of 3:1, the temperature is controlled at 40 ± 5 °C, and the current density is 20 - 30 mA / cm 2 ; Laser etching uses a pulsed laser with a wavelength of 1064 nm, a pulse width of 100 - 200 ns, and an energy density of 2 - 5 J / cm 2 ; The process gas for PECVD deposition is a mixed gas of trimethylaluminum and ammonia, with a flow ratio of 1:5, a radio frequency power of 200 - 300 W, and a substrate temperature of 350 ± 20 °C; positive photoresist is used for lithography, and the exposure energy is 100 - 150 mJ / cm 2 .

10. The preparation method of a multi-layer stacked structure of a high-efficiency heat dissipation high-power radio frequency chip according to claim 8, characterized in that The thickness ratio of the multi-layer metal film is Ti / Cu / Au = 50 nm / 2 μm / 0.5 μm; the welding temperature gradient is controlled within 2 °C / s; the bonding force of the gold wire bonding is 20 - 30 gf; The loss tangent of the dielectric layer is not greater than 0.002; the thickness of the diffusion barrier layer on the inner wall of the TSV is 50 - 100 nm; the current density of pulse electroplating is 2 - 5 mA / cm 2 .

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