Charging driving semiconductor structure of battery protection chip

Abstract

The embodiment of the invention provides a charging driving semiconductor structure of a battery protection chip, and relates to the technical field of battery protection, the charging driving semiconductor structure comprises an overcharge protection driving module and a first PMOS transistor, the overcharge protection driving module comprises a first NMOS transistor, the source electrode of the first NMOS transistor is used for connecting the charging negative voltage access end of the battery protection chip, and the source electrode of the first PMOS transistor is used for connecting the charging negative voltage access end of the battery protection chip; the drain electrode is used for connecting a charging control end of the battery protection chip and leading out a first terminal, and the grid electrode leads out a second terminal; the first PMOS transistor is used for being conducted when the battery is in a zero volt state and is connected with a charger, the source electrode of the first PMOS transistor is used for being connected with the power supply end of the battery protection chip, and the drain electrode is provided with a third wiring end used for being connected with the first wiring end or the second wiring end. According to the invention, the chip which supports the charging function in the zero-volt state or prohibits the charging function in the zero-volt state can be efficiently and rapidly provided in a large scale according to the requirements of different manufacturers for different batteries.

Description

Technical Field

[0001] The present invention relates to the technical field of battery protection, and in particular to a charging drive semiconductor structure of a battery protection chip. Background Art

[0002] In order to ensure the safe use of batteries, batteries are usually equipped with protection chips to monitor the battery status. Figure 1 As shown, the chip controls the charging control FET (such as Figure 1 The switch tube M2 in the discharge control FET (such as Figure 1 The switch tube M1 in the circuit is used to control the charge and discharge circuit to realize charging and discharging.

[0003] Existing battery protection chips usually only have basic normal charging and overcharge protection functions. However, the battery protection chip still has a small amount of self-consumption after over-discharge. If the battery is left uncharged for a long time, the battery voltage may drop to close to 0V. Charging some batteries at zero volts may cause irreversible chemical changes inside the battery, which in turn affects the stability of the battery and even causes the risk of explosion, so charging at zero volts is not allowed. Some batteries do not have these problems, so charging at zero volts is allowed.

[0004] At present, in order to adapt to different types of batteries, different manufacturers can only selectively configure the zero-volt state charging control circuit or the zero-volt state charging control circuit on the PCB board. This not only causes the area of ​​the PCB board to increase, but also cannot be conveniently configured in batches, increasing costs. Summary of the invention

[0005] The embodiment of the present invention provides a charging driving semiconductor structure of a battery protection chip to overcome the above technical problems. It can adapt to the needs of different batteries from different manufacturers and efficiently, quickly and in large quantities provide chips that support charging function in the zero-volt state or prohibit charging function in the zero-volt state.

[0006] In order to solve the above problems, an embodiment of the present invention discloses a charging drive semiconductor structure of a battery protection chip, including: an overcharge protection drive module, a first PMOS tube, the overcharge protection drive module includes a first NMOS tube, the source of the first NMOS tube is used to connect to the charging negative voltage access terminal of the battery protection chip, the drain is used to connect to the charging control terminal of the battery protection chip and lead to the first terminal, and the gate leads to the second terminal; the first PMOS tube is used to be turned on when the battery is in a zero volt state and is connected to a charger, the source of the first PMOS tube is used to connect to the power supply terminal of the battery protection chip, the drain has a third terminal, and the third terminal is used to be connected to the first terminal or the second terminal.

[0007] In one embodiment of the present invention, the third terminal is used to be connected to the first terminal or the second terminal through a metal wire.

[0008] In one embodiment of the present invention, the overcharge protection driving module further includes: a second PMOS tube whose turn-on and turn-off are controlled by the overcharge protection driving signal, and the second PMOS tube is connected between the power supply terminal and the second connection terminal.

[0009] In one embodiment of the present invention, the overcharge protection driving module also includes: a second PMOS tube and a voltage divider circuit 1 whose conduction and shutdown are controlled by the overcharge protection driving signal, the second PMOS tube and the voltage divider circuit 1 are connected in series and connected between the power supply end and the charging negative voltage access end; the second terminal and the source of the first NMOS tube are connected through the second resistor in the voltage divider circuit 1.

[0010] In one embodiment of the present invention, a fourth resistor is further included, one end of the fourth resistor is connected to the second terminal, the third terminal is connected to the first terminal, and the other end of the fourth resistor is suspended; or the third terminal is connected to the other end of the fourth resistor.

[0011] In an embodiment of the present invention, the first NMOS transistor is a low-voltage MOS transistor.

[0012] In one embodiment of the present invention, a clamping protection circuit 1 is further included, and the clamping protection circuit 1 is connected between the gate and the source of the first NMOS tube.

[0013] In one embodiment of the present invention, a fifth resistor is further included, one end of the fifth resistor is connected to the first terminal; the third terminal is connected to the other end of the fifth resistor; or the third terminal is connected to the second terminal, and the other end of the fifth resistor is left floating.

[0014] In one embodiment of the present invention, a third PMOS tube and an inverter structure 1 are also included; the on and off of the third PMOS tube are controlled by a charging drive signal, the source of the third PMOS tube is used to connect to the power supply end, and the drain is used to connect to the first terminal; the inverter structure 1 is connected between the power supply end and the battery negative input end of the battery protection chip, the input end inputs an overcharge protection drive signal, and the output end outputs a charging drive signal.

[0015] In one embodiment of the present invention, a sixth resistor is further included, and the sixth resistor is connected between the third PMOS tube and the charging control terminal.

[0016] In one embodiment of the present invention, it includes: a zero-volt charging detection module, which is respectively connected to the power supply terminal, the charging negative voltage access terminal and the battery negative electrode input terminal of the battery protection chip to detect whether the battery is in a zero-volt state and connected to a charger based on voltage signals from the power supply terminal, the battery negative electrode input terminal and the charging negative voltage access terminal, and output a detection result signal; the first PMOS tube is turned on and off based on the detection result signal.

[0017] In one embodiment of the present invention, the zero-volt charging detection module includes: an inverter structure 2 formed by a fourth PMOS tube and a second NMOS tube in common gate connection, and a seventh resistor and a clamping protection circuit 2; The inverter structure 2 is connected in series with the seventh resistor and connected between the power supply end and the charging negative voltage access end. The input end of the inverter structure 2 is used to connect the voltage of the negative input end of the battery, and the output end is used to generate a detection result signal; the clamping protection circuit 2 is connected between the power supply end and the output end of the inverter structure 2.

[0018] In one embodiment of the present invention, the second NMOS transistor is a low voltage MOS transistor.

[0019] The embodiments of the present invention include the following advantages: The charging drive semiconductor structure of the battery protection chip provided by the present invention is very convenient to realize the function of allowing charging of the battery in the zero-volt state or not allowing charging in the zero-volt state. The switching of the two functions can be realized by simply changing the simple connection on the layout, without redesigning the circuit. Among them, the present invention reuses the first NMOS tube in the overcharge protection drive module to realize the function of not allowing charging of the battery in the zero-volt state, so that the realization of the two functions can share most of the mask, reducing the circuit complexity and reducing the cost. In this way, according to the needs of different manufacturers to meet the needs of different batteries, battery protection chips that support the charging function in the zero-volt state or prohibit the charging function in the zero-volt state can be provided efficiently, quickly and in large quantities. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application.

[0021] Figure 1 This is a common charging application diagram of a battery protection chip; Figure 2 is a partial schematic diagram of a charging drive semiconductor structure provided by an embodiment of the present invention; Figure 3 Schematic diagram of a charging driven semiconductor structure provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0022] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments.

[0023] In the following, the terms "second", "first", "XX-one", "XX-two", etc. are only used for convenience of description to distinguish different objects, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "second", "first", etc. may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise specified, the meaning of "plurality" is two or more.

[0024] In the embodiments of the present invention, unless otherwise clearly specified and limited, the term "connection" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. In addition, the term "coupled" can be a direct electrical connection or an indirect electrical connection through an intermediate medium. The term "contact" can be a direct contact or an indirect contact through an intermediate medium.

[0025] Technical term explanation: Normal charging: refers to charging when the battery voltage can meet the normal operation of most circuits in the battery protection chip. It can control the charging control FET (such as Figure 1 The switch tube M2 in the battery is turned on for normal charging.

[0026] Zero volt state: The zero volt state should not be simply and roughly understood as the battery voltage is 0V (volt). In some applications, the charging voltage based on the charger also has requirements, which needs to be greater than the set zero volt chargeable threshold voltage. At this time, the "zero volt state" of the battery should be understood as the state where the battery voltage is close to 0V. In this state, the battery voltage is greater than the set zero volt chargeable threshold voltage). In some other applications, the "zero volt state" of the battery should be understood as the state where the battery voltage is close to 0V and can be detected by the zero volt charging detection module. In short, the zero volt state can be understood as the battery voltage is zero volt or the power is not enough to support the normal operation of most circuits inside the chip.

[0027] Overcharge protection: When the VDD voltage reaches the over-voltage threshold or the charging current reaches the over-current threshold, the battery protection chip controls CO to turn off the charging control FET (such as Figure 1 The switch tube M2 in the circuit disconnects the charging and protects the battery.

[0028] In view of the technical problem of the present invention, an embodiment of the present invention provides a charging drive semiconductor structure of a battery protection chip, referring to Figure 2 , including: an overcharge protection driving module and a first PMOS tube PM1.

[0029] The overcharge protection driving module includes a first NMOS tube NM1, a source of the first NMOS tube NM1 is used to connect to the negative charging voltage access terminal of the battery protection chip (in some descriptions below, the negative charging voltage access terminal is briefly represented by VM), a drain is used to connect to the charging control terminal of the battery protection chip (in some descriptions below, the charging control terminal is briefly represented by CO) and leads to a first terminal A, and a gate leads to a second terminal B; a first PMOS tube PM1 is used to be turned on when the battery is in a zero volt state and a charger is connected, a source thereof is used to connect to the power supply terminal of the battery protection chip, and a drain has a third terminal C, and the third terminal C is used to be connected to the first terminal A or the second terminal B.

[0030] In the function of realizing battery charging or not charging (also called charging inhibition), the charging control FET (such as Figure 1 The key to realize these two functions is to switch on and off the switch tube M2 in the charging circuit. Figure 1 As shown, the source of the switch tube M2 is connected to the negative charging voltage access terminal VM of the battery protection chip (in some descriptions below, the battery protection chip is simply referred to as the chip), and the gate is connected to the charging control terminal CO of the chip. Therefore, whether the battery is charged or not is controlled by the chip controlling the CO voltage relative to the VM voltage to control the on and off of the switch tube M2.

[0031] When the first NMOS transistor NM1 is turned on, the first NMOS transistor NM1 can pull down the CO voltage based on the VM voltage, so that the charging control FET (such as Figure 1 The gate-source voltage difference of the switch tube M2 in the battery is less than its conduction threshold, which makes it unable to conduct, and the charge and discharge circuit between the battery and the charger is cut off, making it impossible to charge. When the chip detects that the VDD voltage reaches the charging overvoltage threshold or the charging current reaches the charging overcurrent threshold, an overcharge protection drive signal ctrl2 is generated, and the overcharge protection drive module can control the first NMOS tube NM1 to conduct based on the overcharge protection drive module. For more detailed principles of overcharge protection, please refer to the relevant existing technology, which will not be elaborated here.

[0032] The first PMOS tube PM1 can be understood as a driving switch controlled by whether the battery is in a zero-volt state and is connected to a charger. The first PMOS tube PM1 is turned on when the battery is in a zero-volt state and is connected to a charger. The gate of the first PMOS tube PM1 can be specifically controlled by a detection result signal ctrl1 indicating whether the battery is in a zero-volt state and is connected to a charger, that is, it can be turned on and off based on the detection result signal ctrl1.

[0033] In order to realize the function of allowing charging in the zero volt state of the chip or not allowing charging in the zero volt state, the drain of the first NMOS tube NM1 of the present invention leads to the first terminal A, the gate leads to the second terminal B, and the drain of the first PMOS tube PM1 leads to the third terminal C. The third terminal C is used to connect to the first terminal A or the second terminal B. In a specific implementation, the third terminal C can be connected to the first terminal A or the second terminal B through a metal wire.

[0034] When the third terminal C of the first PMOS tube PM1 is connected to the first terminal A of the first NMOS tube NM1, the function of allowing charging in the zero-volt state of the battery is realized. Specifically: when the third terminal C is connected to the first terminal A, the drain of the first PMOS tube PM1 is connected to the charging control terminal CO. Since the source of the first PMOS tube PM1 is connected to the power supply terminal of the battery protection chip, when the first PMOS tube PM1 is turned on, CO is connected to VDD, and the CO voltage is pulled up to the VDD voltage. When the battery is in the zero-volt state and a charger is connected, the voltages of VDD and VSS are both zero volts, and the VM voltage is negative, and the charging control FET (such as Figure 1 The source voltage of the switch tube M2 in the charging control circuit is the VM voltage, and the gate voltage is the VDD voltage. The voltage difference between VDD and VM can make the charging control FET (such as Figure 1 The switch tube M2 in the battery is turned on to allow charging when the battery is in the zero volt state.

[0035] When the third terminal C of the first PMOS tube PM1 is connected to the second terminal B of the first NMOS tube NM1, the function of not allowing charging in the zero-volt state of the battery is realized (or the function of prohibiting charging in the zero-volt state of the battery is realized). Specifically: when the third terminal C is connected to the second terminal B, the connection between the drain of the first PMOS tube PM1 and the gate of the first NMOS tube NM1 is realized. When the battery is in the zero-volt state and a charger is connected, the first PMOS tube PM1 is turned on, and the gate of the first NMOS tube NM1 is connected to VDD. Since the source of the first NMOS tube NM1 is connected to VM, the first NMOS tube NM1 is turned on based on the voltage difference between VDD (0V at this time) and VM (negative voltage at this time), and the connection between the charging control terminal CO and the charging negative voltage access terminal VM is realized. The CO voltage is pulled down to the VM voltage, and the function of not allowing charging in the zero-volt state of the battery is realized.

[0036] Based on the charging drive semiconductor structure of the present invention, it is very convenient to realize the function of allowing charging of the battery in the zero-volt state or not allowing charging in the zero-volt state. The switching of the two functions can be realized by simply changing the simple connection on the layout. Among them, the present invention reuses the first NMOS tube NM1 in the overcharge protection drive module to realize the function of not allowing charging of the battery in the zero-volt state, so that the realization of the two functions can share most of the mask, reducing the circuit complexity and reducing the cost. In this way, according to the needs of different manufacturers to meet the needs of different batteries, chips that support the charging function in the zero-volt state or prohibit the charging function in the zero-volt state can be provided efficiently, quickly and in large quantities.

[0037] The overcharge protection driving module of the embodiment of the present invention can be specifically implemented by the following structure: In one embodiment, if Figure 2 As shown, the overcharge protection driving module further includes: a second PMOS tube PM2 whose turn-on and turn-off are controlled by the overcharge protection driving signal ctrl2, and the second PMOS tube PM2 is connected between the power supply terminal and the second wiring terminal B.

[0038] In another embodiment, reference Figure 3 The overcharge protection driving module also includes: a second PMOS tube PM2 whose turn-on and turn-off are controlled by the overcharge protection driving signal ctrl2 and a voltage divider circuit 1; the second PMOS tube PM2 and the voltage divider circuit 1 are connected in series between the power supply terminal VDD and the charging negative voltage access terminal VM; the second terminal B (gate) and the source of the first NMOS tube NM1 are connected through the second resistor R2 in the voltage divider circuit 1.

[0039] In this embodiment, the second PMOS tube PM2 can be understood as an overcharge protection drive switch. When the second PMOS tube PM2 is turned on based on the overcharge protection drive signal ctrl2, different nodes on the voltage divider circuit 1 can divide the voltage difference between VDD and VM. Since the drain of the first NMOS tube NM1 is used to connect the charging control terminal CO, the gate and the source are connected through the second resistor R2 in the voltage divider circuit 1, that is, the gate and the source are respectively connected to different nodes in the voltage divider circuit 1, so that there is a voltage difference between the gate and the source of the first NMOS tube NM1, so that the first NMOS tube NM1 can be turned on (i.e., turned on). In specific applications, the gate voltage and the source voltage of the first NMOS tube NM1 can be controlled separately by adjusting or designing the resistance ratio of each in the voltage divider circuit 1 to ensure that the first NMOS tube NM1 is turned on.

[0040] In this embodiment, a voltage divider circuit is used to divide the voltage difference between VDD and VM by resistors, so that the gate voltage and / or source voltage of the first NMOS transistor NM1 is the divided voltage of the voltage difference between VDD and VM, thereby increasing the gate-source voltage V GS Within a certain range, as long as this range is less than the gate-source breakdown voltage of the low-voltage MOS tube, the first NMOS tube NM1 can be implemented using an ordinary low-voltage MOS tube. This circuit structure reduces the V GS The pressure resistance requirement is compared with Figure 2 In the scheme shown, this embodiment has an additional selectivity when selecting the first NMOS tube NM1, and gets rid of the dependence on the high-voltage thick-gate oxide MOS tube. When a low-voltage MOS tube is used as a CO voltage pull-down device in actual application, compared with using a high-voltage thick-gate oxide MOS tube, the area can be reduced, the mask level can be further reduced, and the chip cost can be reduced.

[0041] Those skilled in the art should understand that the voltage divider circuit referred to in each embodiment of the present invention is a resistor voltage divider circuit, which is generally composed of multiple resistors connected in series. The voltage divider circuit can be implemented in different ways, such as referring to Figure 3 In the implementation shown, the voltage divider circuit 1 also includes a first resistor R1 and a third resistor R3. The first resistor R1, the second resistor R2 and the third resistor R3 are connected in series in sequence. The first resistor R1 is connected to the power supply terminal VDD through the second PMOS tube PM2, and the third resistor R3 is connected to the negative charging voltage access terminal VM. The first resistor R1, the second resistor R2 and the third resistor R3 are schematic representations of the resistor positions in the present invention, and do not mean that they are only one resistor in practice. In practice, one or more of the first resistor R1, the second resistor R2 and the third resistor R3 can also be implemented by a resistor string (i.e., multiple resistors). Figure 3 In the implementation shown, the resistor R3 can prevent the source and drain of the first NMOS transistor NM1 from being broken down, thus playing a protective role.

[0042] Continue to refer Figure 3 The present invention may further include a fourth resistor R4, one end of which is connected to the second terminal B.

[0043] For a chip that realizes the function of allowing charging of a battery in a zero-volt state, the third terminal C is connected to the first terminal A, and the other end of the fourth resistor R4 is suspended.

[0044] For a chip that realizes the function of not allowing charging (forbidding charging) in a zero-volt state, the third terminal C is connected to the other end of the fourth resistor R4, so that the fourth resistor R4 and the second resistor R2 are connected in series to form a voltage divider circuit 2, forming a structure in which the first PMOS tube PM1 and the voltage divider circuit 2 are connected in series between the power supply terminal VDD and the negative charging voltage access terminal VM. When the battery is in a zero-volt state and connected to a charger, the first PMOS tube PM1 is turned on, and the gate and source of the first NMOS tube NM1 are respectively connected to different nodes in the voltage divider circuit 2. At this time, the gate voltage and source voltage of the first NMOS tube NM1 are the voltage division of the voltage difference between VDD and VM. When the battery is in a zero-volt state and connected to a charger, the voltage division can make the gate-source voltage of the first NMOS tube NM1 greater than the turn-on voltage of the first NMOS tube NM1, and then the first NMOS tube NM1 is turned on to pull the CO voltage down to the VM voltage, so that charging is not allowed (forbidding charging) in a zero-volt state.

[0045] Similarly, when realizing the function of not allowing charging (forbidding charging) in the zero volt state, the embodiment of the present invention uses the voltage divider circuit 2 to divide the voltage difference between VDD and VM by resistors, thereby limiting the gate-source voltage of the first NMOS tube NM1 to a certain range. As long as this range is less than the gate-source breakdown voltage of the low-voltage MOS tube, the first NMOS tube NM1 can be implemented using an ordinary low-voltage MOS tube, which is particularly suitable for some applications where the VM voltage is not very negative during charging. This circuit structure reduces the V GS The voltage resistance requirement makes it unnecessary for the first NMOS tube NM1 to use a high-voltage thick-gate oxide MOS tube to withstand the negative high voltage from VDD to VM when the charger is connected at zero volts. Figure 2 In the scheme shown, this embodiment has an additional selectivity when selecting the first NMOS tube NM1, and gets rid of the dependence on the high-voltage thick-gate oxide MOS tube. When a low-voltage MOS tube is used as a CO voltage pull-down device in actual application, compared with using a high-voltage thick-gate oxide MOS tube, the area can be reduced, the mask level can be further reduced, and the chip cost can be reduced.

[0046] based on Figure 3 In the embodiment shown, in a preferred embodiment of the present invention, the first NMOS transistor NM1 is a low voltage MOS transistor.

[0047] Furthermore, in order to improve the application scope of this solution and ensure that the first NMOS tube NM1 can also be implemented with a low-voltage MOS tube in charging applications where the VM voltage is very negative or in applications where the overcharge protection threshold is very large. Figure 3The charging drive semiconductor structure of the present invention further includes a clamping protection circuit 1, which is connected between the gate and the source of the first NMOS tube NM1. The clamping protection circuit 1 can clamp the gate-source voltage of the pull-down MOS tube to ensure that the gate-source voltage difference of the first NMOS tube NM1 implemented by the low-voltage MOS tube is not too large and damaged.

[0048] Furthermore, the charging driving semiconductor structure of the embodiment of the present invention may further include a fifth resistor R5, such as Figure 3 As shown, one end of the fifth resistor R5 is connected to the first terminal A; the third terminal C is connected to the other end of the fifth resistor R5; or the third terminal C is connected to the second terminal B, and the other end of the fifth resistor R5 is suspended. When the third terminal C is connected to the other end of the fifth resistor R5, the fifth resistor R5 can play a current limiting role, so that when the battery is connected to the charger for charging in the zero volt state, on the one hand, it protects the source and drain of the first PMOS tube PM1 and the charging control terminal CO, and on the other hand, it plays an ESD (Electro-Static discharge, electrostatic discharge) protection role.

[0049] The charging driving semiconductor structure of the embodiment of the present invention can also realize the normal charging function, and continue to refer to Figure 2 and Figure 3 , and also includes a third PMOS tube PM3. The on and off of the third PMOS tube PM3 is controlled by the charging drive signal ctrl3. The source of the third PMOS tube PM3 is used to connect to the power supply terminal, and the drain is used to connect to the first terminal A. The third PMOS tube PM3 can be understood as a normal charging drive switch. When the battery power can support the normal operation of most circuits inside the chip, VDD is a positive voltage, and the third PMOS tube PM3 is turned on based on the input charging drive signal ctrl3, and the CO voltage is pulled up by the VDD voltage. For example, the CO voltage is pulled up to equal the VDD voltage, then at this time Figure 1 The gate voltage of the switch tube M2 in the circuit is VDD voltage, and the source voltage of the switch tube M2 is VM voltage, so that the V GS When the voltage is greater than the conduction threshold, the switch tube M2 is turned on to realize charging.

[0050] It is worth noting that, based on the circuit design of the embodiment of the present invention, when the third terminal C of the first PMOS tube PM1 is connected to the first terminal A of the first NMOS tube NM1 to realize the charging function allowed in the zero-volt state of the battery, or when the third PMOS tube PM3 is turned on to realize normal charging, the first PMOS tube PM1, the third PMOS tube PM3 and the first NMOS tube NM1 adopt a non-inverter structure, that is, the first PMOS tube PM1 and the first NMOS tube NM1 are a non-common-gate structure, and the third PMOS tube PM3 and the first NMOS tube NM1 are a non-common-gate structure. This ensures that during charging, even if the VDD voltage gradually rises, before the overcharge protection threshold is reached, the first NMOS tube NM1 is always in the off state, and there is no path from VDD to VM, which can reduce the power consumption of the chip during normal charging and improve the charging efficiency of the chip.

[0051] Different from the prior art which requires complex circuit design to generate the charging driving signal ctrl3, the embodiment of the present invention provides a simple solution for generating the charging driving signal ctrl3, such as Figure 3 As shown, the charging drive semiconductor structure of the present invention also includes an inverter structure 1, which is connected between the power supply terminal VDD and the battery negative electrode input terminal VSS of the battery protection chip, the input terminal inputs the overcharge protection drive signal ctrl2, and the output terminal outputs the charging drive signal ctrl3.

[0052] Furthermore, the charging drive semiconductor structure of the embodiment of the present invention further includes a sixth resistor R6, which is connected between the third PMOS transistor PM3 and the charging control terminal CO. Similarly, the sixth resistor R6 can play a current limiting role in the normal charging process, on the one hand protecting the source and drain of the third PMOS transistor PM3 and the charging control terminal CO, and on the other hand playing a protective role.

[0053] Continue to refer Figure 3 The charging drive semiconductor structure of the embodiment of the present invention also includes a zero-volt charging detection module, which is respectively connected to the power supply terminal, the charging negative voltage access terminal and the battery negative electrode input terminal of the battery protection chip to detect whether the battery is in a zero-volt state and connected to a charger based on the voltage signals of the power supply terminal VDD, the battery negative electrode input terminal VSS and the charging negative voltage access terminal VM, and output a detection result signal ctrl1; the first PMOS tube PM1 is turned on and off based on the detection result signal ctrl1.

[0054] In specific implementation, the level of the detection result signal ctrl1 can be used to characterize the state or other states that the battery is in a zero-volt state and connected to a charger. When the battery is in a zero-volt state and connected to a charger, the detection result signal ctrl1 becomes a valid level, so that the first PMOS tube PM1 is turned on; in other states, the detection result signal ctrl1 becomes an invalid level, and the first PMOS tube PM1 is not turned on. For example, when the battery power can support the normal operation of most circuits inside the chip, VDD is a positive voltage, and the voltages of VSS and VM are 0V. At this time, the detection result signal ctrl1 can be controlled to a high level based on the VDD voltage, and the first PMOS tube PM1 is turned off. When the battery is in a zero-volt state and connected to a charger, the voltages of VDD and VSS are both zero volts, and VM is negative relative to VSS. At this time, the detection result signal ctrl1 can be controlled to a low level based on the VM voltage, and the first PMOS tube PM1 is turned on. When the battery is in a zero-volt state and is not connected to a charger, the entire internal circuit of the chip does not work.

[0055] In one embodiment of the present invention, a specific structure of a zero-volt charging detection module is provided, such as Figure 3 The structure shown may include: an inverter structure 2 formed by a fourth PMOS transistor PM4 and a second NMOS transistor NM2 with a common gate, and a seventh resistor R7 and a clamping protection circuit 2; the inverter structure 2 and the seventh resistor R7 are connected in series and connected between the power supply terminal VDD and the negative charging voltage access terminal VM, the input terminal of the inverter structure 2 is connected to the voltage of the negative input terminal VSS of the battery through the resistor R8, and the output terminal is used to generate a detection result signal ctrl1; the clamping protection circuit 2 is connected between the power supply terminal and the output terminal of the inverter structure 2.

[0056] Based on the different driving capabilities of the fourth PMOS tube PM4 and the second NMOS tube NM2 in the inverter structure 2, the detection result signal ctrl1 can be controlled to a low level or a high level. Specifically, when the battery power can support the normal operation of most circuits inside the chip, VDD is a positive voltage, and the voltages of VSS and VM are 0V. At this time, the fourth PMOS tube PM4 is turned on, the second NMOS tube NM2 is turned off, and the detection result signal ctrl1 is pulled up by the VDD voltage, and the detection result signal ctrl1 is output as a high level. When the battery is in a zero-volt state and a charger is connected, the voltages of VDD and VSS are both zero volts, while the VM voltage is negative. At this time, the fourth PMOS tube PM4 is turned off, the second NMOS tube NM2 is turned on, the detection result signal ctrl1 is pulled down by the VM voltage, and the detection result signal ctrl1 is output as a low level. When the battery is in a zero-volt state and the charger is not connected, the entire internal circuit of the chip does not work. In practical applications, the driving capability of the fourth PMOS tube PM4 can be designed to be higher than that of the second NMOS tube NM2. When the battery has power and is connected to a charger, that is, VDD is a positive voltage, VSS is zero volts, and VM is a negative voltage, the driving capability of the fourth PMOS tube PM4 is stronger, that is, the on-resistance is lower, the fourth PMOS tube PM4 will be turned on and the second NMOS tube NM2 will be turned off, and the level of the detection result signal ctrl1 will be pulled up by the VDD voltage.

[0057] It is worth emphasizing that if only the inverter structure is used to realize the function of the zero-volt charging detection module, the voltage difference between VM and VSS is large, and the second NMOS tube NM2 needs a thick gate oxide MOS tube with high voltage resistance to meet the circuit requirements. However, the use of thick gate oxide MOS tubes will increase its area and increase the number of mask levels, which increases the wafer cost. Figure 3 As shown, the zero-volt charging detection module of the embodiment of the present invention includes not only the inverter structure 2, but also the fourth resistor R4 and the clamping protection circuit 2. Through the joint action of the fourth resistor R4 and the clamping protection circuit 2, the second NMOS tube NM2 can be implemented by selecting an ordinary low-voltage MOS tube, which has one more selectivity than the prior art. Of course, preferably, the second NMOS tube is a low-voltage MOS tube.

[0058] The working principle of the seventh resistor R7 and the second clamping protection circuit is described below: When the battery is in zero volt state and connected to a charger, the VM voltage is negative, and the second NMOS tube NM2 is turned on. At this time, the detection result signal ctrl1 is pulled to the source voltage of the second NMOS tube NM1, which is also a negative voltage, and the level of the detection result signal ctrl1 becomes a low level.

[0059] If the VM voltage is very negative and the voltage difference between it and VSS becomes very large, the voltage of the detection result signal ctrl1 is also pulled to a very negative value, and the clamping protection circuit 2 will clamp the voltage difference between the VDD voltage and the detection result signal ctrl1 to a fixed value. At this time, a current I flows through the clamping protection circuit 2, and flows through the second NMOS tube NM2 to R4 and finally reaches the charging negative voltage access terminal. Since the drain of the second NMOS tube NM2 is the output terminal of the detection result signal ctrl1, it can be considered that the maximum voltage difference between the drain of the second NMOS tube NM2 (i.e., the output terminal of the inverter structure 2) and VDD is clamped and fixed; since when the charging negative voltage access terminal is very negative, the second NMOS tube NM2 must work in the linear region, so its source and drain voltages are basically equal, and it can be considered that the source voltage of the second NMOS tube NM2 and the VDD voltage are also clamped and fixed. When the battery is in a zero-volt state and connected to a charger, the voltages of VSS and VDD are both zero volts, and the gate voltage of the second NMOS tube NM2 is also fixed based on the VSS voltage, which is equivalent to the difference between the gate voltage and the source voltage of the second NMOS tube NM2 being clamped and fixed. In other words, once the voltage difference between VM and VSS reaches the point where the clamping protection circuit 2 can work, the gate-source voltage of the second NMOS tube NM2 is also clamped, which enables the second NMOS tube NM2 to be implemented using a low-voltage NMOS tube.

[0060] Among them, the source voltage of the second NMOS tube NM2 is equal to the VM voltage plus I*R7. Since the gate-source voltage of the second NMOS tube NM2 is also clamped, the source voltage and the VDD voltage are also clamped and fixed. When its gate voltage is 0V, the source voltage is also a fixed value. In different charging applications, the voltage of the connected charger is different, and the negative situation of the VM voltage is also different. When the VM voltage decreases with the application situation, although the current I will increase accordingly, the negative increase in the voltage of VM with the application situation will eventually fall on R7, ensuring that the gate source of the second NMOS tube NM2 implemented using a low-voltage NMOS tube will not be broken down. At the same time, due to the action of the clamping protection circuit 2, the source-drain voltage of the fourth PMOS tube PM4 and the gate-source voltage of the zero-volt charge-forbidden drive switch implemented by the MOS tube will also be clamped, so the clamping protection circuit 2 also protects the fourth PMOS tube PM4 and the first PMOS tube PM1.

[0061] Obviously, based on Figure 3 The design of the zero-volt charging detection module shown not only enables the second NMOS tube NM2 to be implemented with an ordinary low-voltage MOS tube, and the entire circuit achieves a lower level of mask and a small area, reducing the wafer cost, but also makes the battery protection chip provided by this solution more versatile and applicable to chargers with different voltage specifications.

[0062] It is worth noting that although low voltage and high voltage are relative concepts, in this field, technicians in this field have a strong consensus on the distinction between high-voltage MOS tubes and low-voltage MOS tubes: high-voltage MOS tubes usually have higher voltage resistance, but large on-resistance, slow switching speed, multiple layers and large area; low-voltage MOS tubes have smaller on-resistance, fast switching speed, fewer layers and less area, but limited voltage resistance. Structurally, high-voltage MOS tubes usually have thicker oxide layers and longer channels, that is, thick gates to withstand higher voltage stress. In addition, the material selection of high-voltage MOS tubes is also more stringent to ensure stability and reliability under high voltage. The structure of low-voltage MOS tubes is relatively simple, with thin oxide layers and shorter channels, that is, generally thin gates, which helps to increase switching speed and reduce power consumption. Therefore, low-voltage MOS tubes and high-voltage MOS tubes are very clear in this field. In this application, it can be considered that the voltage resistance of low-voltage MOS tubes in one or more voltage resistance indicators such as DS (drain-source) voltage resistance, DB (drain-bulk) voltage resistance and GS (gate-source) voltage resistance is lower than that of high-voltage MOS tubes.

[0063] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0064] The technical solution provided by the present application is described in detail above. The principle and implementation method of the present application are described in this article using specific examples. The description of the above embodiments is only used to help understand the present application, and the content of this specification should not be understood as limiting the present application. At the same time, for those of ordinary skill in the art, according to the present application, there will be different forms of changes in the specific implementation methods and application scopes. It is not necessary and impossible to list all the implementation methods here, and the obvious changes or modifications derived therefrom are still within the scope of protection of the present application.

Claims

1. A charging drive semiconductor structure of a battery protection chip, characterized in that: include: Overcharge protection drive module, first PMOS tube, The overcharge protection driving module includes a first NMOS tube, the source of the first NMOS tube is used to connect the negative charging voltage access terminal of the battery protection chip, the drain is used to connect the charging control terminal of the battery protection chip and lead to a first wiring terminal, and the gate leads to a second wiring terminal; The first PMOS tube is used to be turned on when the battery is in a zero volt state and connected to a charger, and its source is used to connect to the power supply end of the battery protection chip, and the drain has a third terminal, which is used to be connected to the first terminal or the second terminal.

2. The charging drive semiconductor structure of the battery protection chip according to claim 1, characterized in that: The third terminal is used to be connected to the first terminal or the second terminal through a metal wire.

3. The charging drive semiconductor structure of the battery protection chip according to claim 1, characterized in that: The overcharge protection driving module further includes: a second PMOS tube whose on and off is controlled by an overcharge protection driving signal, and the second PMOS tube is connected between the power supply terminal and the second connection terminal.

4. The charging drive semiconductor structure of the battery protection chip according to claim 1, characterized in that: The overcharge protection driving module also includes: The second PMOS tube and the voltage divider circuit 1 are turned on and off by the overcharge protection drive signal. The second PMOS tube and the voltage divider circuit are connected in series and connected between the power supply terminal and the negative charging voltage access terminal; The second connection terminal and the source of the first NMOS tube are connected via the second resistor in the first voltage divider circuit.

5. The charging drive semiconductor structure of the battery protection chip according to claim 4, characterized in that: It also includes a fourth resistor, one end of which is connected to the second terminal. The third terminal is connected to the first terminal, and the other end of the fourth resistor is suspended; Alternatively, the third terminal is connected to the other end of the fourth resistor.

6. The charging drive semiconductor structure of the battery protection chip according to claim 4 or 5, characterized in that: The first NMOS tube is a low-voltage MOS tube.

7. The charging driving semiconductor structure of the battery protection chip according to claim 6, characterized in that: It also includes a clamping protection circuit 1, which is connected between the gate and the source of the first NMOS tube.

8. The charging drive semiconductor structure of the battery protection chip according to any one of claims 1 to 5, characterized in that: It also includes a fifth resistor, one end of which is connected to the first wiring terminal; The third terminal is connected to the other end of the fifth resistor; or The third wiring terminal is connected to the second wiring terminal, and the other end of the fifth resistor is suspended.

9. The charging drive semiconductor structure of the battery protection chip according to claim 3 or 4, characterized in that: Also includes a third PMOS tube and an inverter structure 1; The on and off of the third PMOS tube is controlled by a charging drive signal, the source of the third PMOS tube is used to connect to the power supply terminal, and the drain is used to connect to the first terminal; The inverter structure 1 is connected between the power supply end and the battery negative electrode input end of the battery protection chip, the input end inputs the overcharge protection driving signal, and the output end outputs the charging driving signal.

10. The charging drive semiconductor structure of the battery protection chip according to any one of claims 1 to 5, characterized in that: Also includes: Zero volt charging detection module, The zero-volt charging detection module is connected to the power supply terminal, the charging negative voltage access terminal and the battery negative electrode input terminal of the battery protection chip respectively, so as to detect whether the battery is in a zero-volt state and connected to a charger based on the voltage signals of the power supply terminal, the battery negative electrode input terminal and the charging negative voltage access terminal, and output a detection result signal; The first PMOS tube is turned on and off based on the detection result signal.

11. The charging driving semiconductor structure of the battery protection chip according to claim 10, characterized in that: The zero-volt charging detection module includes: an inverter structure 2 formed by a fourth PMOS tube and a second NMOS tube in common gate connection, and a seventh resistor and a clamping protection circuit 2; The second inverter structure is connected in series with the seventh resistor and connected between the power supply terminal and the negative charging voltage access terminal. The input terminal of the second inverter structure is used to connect the voltage of the negative input terminal of the battery, and the output terminal is used to generate the detection result signal. The second clamping protection circuit is connected between the power supply terminal and the output terminal of the second inverter structure.

12. The charging driving semiconductor structure of the battery protection chip according to claim 11, characterized in that: The second NMOS tube is a low-voltage MOS tube.

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