An inverter-based pvt-compensated ultra-low voltage fully differential ota amplifier

Abstract

The application discloses a kind of PVT compensation ultra-low voltage full differential OTA amplifiers based on inverter, comprising: based on the amplification circuit of inverter and PVT compensation substrate bias circuit;The amplification circuit based on inverter includes the differential input pair of CMOS inverter being controlled by the substrate bias circuit of PMOS and NMOS pipe, common-mode feedback amplifier, variable current source being controlled by common-mode feedback amplifier, first and second resistance;The PVT compensation substrate bias circuit includes the starting circuit of MOS pipe, the reference current source of temperature proportion being formed by MOS pipe and resistance, the circuit of simultaneously outputting PMOS pipe and NMOS pipe body bias voltage being formed by MOS pipe.This application can stabilize the gain and bandwidth of amplifier when temperature or process parameter changes, and still can work normally under ultra-low voltage, significantly reduce the power consumption of amplifier.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of integrated circuits, and more particularly relates to a kind of PVT compensation ultra-low voltage full differential OTA amplifier based on inverter. BACKGROUND

[0002] In recent years, due to the stringent requirements on power consumption in Internet of Things sensor nodes, the design of ultra-low power Sigma-Delta converter has become a research hotspot, and the traditional converter structure is difficult to meet the demand. Fortunately, in many applications of Internet of Things, the conversion speed requirement is not high, so the implementation of ultra-low power Sigma-Delta converter is possible. The key to realizing low power consumption is to reduce the power consumption of the operational amplifier used in the integrator in the converter, and the inverter-based amplifier is currently a common choice. However, the inverter-based amplifier is easily affected by process, voltage and temperature changes (PVT), which causes significant changes in the operating point, gain, unity gain bandwidth and output swing of the inverter, greatly affecting the performance of the modulator. Therefore, based on the inverter-based amplifier, PVT compensation strategy must be adopted to reduce the influence of PVT changes on gain and bandwidth. SUMMARY

[0003] To solve the above problems, the present application provides an ultra-low voltage full differential OTA amplifier based on inverter PVT compensation, to realize more reliable circuit performance under ultra-low voltage working condition.

[0004] To achieve the above purpose, the present application provides an ultra-low voltage full differential OTA amplifier based on inverter PVT compensation, which includes an inverter-based amplification circuit and a PVT-compensated substrate biasing circuit. The inverter-based amplification circuit includes a differential input pair composed of CMOS inverters whose substrates are controlled by the biasing circuit, a common-mode feedback amplifier, a variable current source controlled by the common-mode feedback amplifier, and first and second resistors. The PVT-compensated substrate biasing circuit includes a start-up circuit composed of MOS transistors, a temperature-proportional reference current source composed of MOS transistors and resistors, and a circuit that simultaneously outputs PMOS and NMOS body bias voltages composed of MOS transistors. The working state of the substrate biasing circuit is as follows:

[0005] When temperature or process parameters change, the temperature-proportional reference current source composed of the sixteenth to twenty-first MOS transistors and the third resistor generates a changing current, which is output through the circuit composed of the twenty-second and twenty-third MOS transistors, the twenty-fourth and twenty-fifth MOS transistors to control the body voltages of the PMOS and NMOS transistors of the amplification circuit, to offset the influence of temperature or process parameter changes on the circuit and stabilize the circuit performance.

[0006] The inverter-based amplification circuit comprises first to twelfth MOS tubes and first and second resistors, the first and second MOS tubes and the seventh and eighth MOS tubes form a pair of inverters respectively, and simultaneously serve as differential inputs of the amplification circuit, the third to sixth MOS tubes serve as current sources, and the ninth to twelfth MOS tubes form a common-mode feedback amplifier, wherein the first, third, fifth, seventh, ninth and eleventh MOS tubes are PMOS tubes, and the second, fourth, sixth, eighth, tenth and twelfth MOS tubes are NMOS tubes.

[0007] The sources of the first MOS tube M1, the third MOS tube M3, the fifth MOS tube M5, the seventh MOS tube M7, the ninth MOS tube M9 and the eleventh MOS tube M11 are connected with an external power supply V DD , the sources of the second MOS tube M2, the fourth MOS tube M4, the sixth MOS tube M6, the eighth MOS tube M8, the tenth MOS tube M10 and the twelfth MOS tube M12 are connected with the ground, the gates of the first MOS tube M1 and the second MOS tube M2 are connected with a differential input signal V in+ , the drains of the first MOS tube M1, the second MOS tube M2, the third MOS tube M3 and the fourth MOS tube M4 are commonly connected to form an output terminal V out- of the OTA amplifier, the drains of the fifth MOS tube M5, the sixth MOS tube M6, the seventh MOS tube M7 and the eighth MOS tube M8 are commonly connected to form another output terminal V out+ of the OTA amplifier, the gates of the third MOS tube M3, the fourth MOS tube M4, the fifth MOS tube M5 and the sixth MOS tube M6 are commonly connected and connected with the drains of the eleventh MOS tube M11 and the twelfth MOS tube M12, and the gates of the seventh MOS tube M7 and the eighth MOS tube M8 are connected with the differential input signal V in- , the bodies of the first MOS tube M1, the third MOS tube M3, the fifth MOS tube M5 and the seventh MOS tube M7 are commonly connected and connected with a first output node V bp of a PVT-compensated substrate bias circuit, the bodies of the second MOS tube M2, the fourth MOS tube M4, the sixth MOS tube M6 and the eighth MOS tube M8 are commonly connected and connected with a second output node V bn of the PVT-compensated substrate bias circuit, the gates of the ninth MOS tube M9 and the eleventh MOS tube M11 are commonly connected and connected with the drains of the ninth MOS tube M9 and the tenth MOS tube M10, and one end of the first resistor R1 and the second resistor R2 is connected with the output terminal V out- and V out+ respectively, and the other end of the first resistor R1 and the second resistor R2 is connected with the gate of the tenth MOS tube M10, and the gate of the twelfth MOS tube M12 is connected with an external reference voltage source V ref .

[0008] The substrate biasing circuit for PVT compensation comprises the thirteenth to twenty-fifth MOS tubes, the first to third capacitors and the third resistor. The thirteenth to fifteenth MOS tubes constitute a starting circuit, the sixteenth to twenty-first MOS tubes and the third resistor constitute a temperature-proportional reference current source, the twenty-second and twenty-third MOS tubes constitute a first output node circuit, and the twenty-fourth and twenty-fifth MOS tubes constitute a second output node circuit. The thirteenth, sixteenth, eighteenth, twentieth, twenty-second and twenty-fourth MOS tubes are PMOS tubes, and the fourteenth, fifteenth, seventeenth, nineteenth, twenty-first, twenty-third and twenty-fifth MOS tubes are NMOS tubes.

[0009] The sources of the thirteenth, sixteenth, eighteenth, twentieth, twenty-second and twenty-fourth MOS tubes, the bulk of the thirteenth, sixteenth and eighteenth MOS tubes, the upper plate of the first capacitor and one end of the third resistor are connected with an external power source V DD The sources and bulk of the fourteenth, fifteenth, seventeenth, nineteenth, twenty-first, twenty-third and twenty-fifth MOS tubes, the lower plates of the second and third capacitors are connected with the ground. The gates of the thirteenth, fifteenth, seventeenth, nineteenth, twenty-first and twenty-third MOS tubes are commonly connected and connected with the drain of the sixteenth and seventeenth MOS tubes. The drains of the thirteenth and fifteenth MOS tubes are commonly connected and connected with the gate of the fourteenth MOS tube. The drains of the fourteenth, eighteenth and nineteenth MOS tubes are commonly connected and connected with the gate of the sixteenth and twenty-fifth MOS tubes and the lower plate of the first capacitor. The gates of the eighteenth and twentieth MOS tubes are commonly connected and connected with the drains of the twentieth and twenty-first MOS tubes. The source and bulk of the twentieth MOS tube are connected with the other end of the third resistor. The gates of the twenty-second and twenty-fourth MOS tubes are connected with an external reference power source V cmThe drain of the twenty-second MOS transistor M22 and the twenty-third MOS transistor M23 is commonly connected and connected with the upper plate of the second capacitor C2, the first MOS transistor M1, the third MOS transistor M3, the fifth MOS transistor M5, the seventh MOS transistor M7 and the body of the twenty-second MOS transistor M22; the drain of the twenty-fourth MOS transistor M24 and the twenty-fifth MOS transistor M25 is commonly connected and connected with the upper plate of the third capacitor C3, the second MOS transistor M2, the fourth MOS transistor M4, the sixth MOS transistor M6, the eighth MOS transistor M8 and the body of the twenty-fourth MOS transistor M24.

[0010] Compared with the prior art amplifier, the PVT-compensated ultra-low-voltage fully differential OTA amplifier based on inverters of the application adopts a substrate biasing circuit to compensate the amplifier, so that the gain and bandwidth of the amplifier are stabilized when the temperature or process parameters change, the amplifier can still work normally at ultra-low voltage, and the power consumption of the amplifier is reduced. BRIEF DESCRIPTION OF DRAWINGS

[0011] Figure 1 The figure is the principle diagram of the amplifying circuit of the PVT-compensated ultra-low-voltage fully differential OTA amplifier based on inverters of the application;

[0012] Figure 2 The figure is the principle diagram of the substrate biasing circuit for compensating the amplifying circuit;

[0013] Fig. 3(a) is a diagram of the gain of the amplifier varying with temperature and process angle;

[0014] Fig. 3(b) is a diagram of the bandwidth of the amplifier varying with temperature and process angle;

[0015] Fig. 4(a) is a diagram of the gain varying with frequency;

[0016] Fig. 4(b) is a diagram of the phase varying with frequency. DETAILED DESCRIPTION

[0017] The application will be further described below in combination with the drawings.

[0018] As Figure 1 and Figure 2The application provides a circuit schematic of a PVT compensation ultra-low voltage full differential OTA amplifier based on an inverter, which comprises an inverter-based amplification circuit and a PVT compensation substrate biasing circuit; the inverter-based amplification circuit comprises a differential input pair composed of CMOS inverters whose substrates are controlled by the substrate biasing circuit, a common-mode feedback amplifier, a variable current source controlled by the common-mode feedback amplifier, and first and second resistors; the PVT compensation substrate biasing circuit comprises a starting circuit composed of MOS transistors, a temperature-proportional reference current source composed of MOS transistors and resistors, and a circuit composed of MOS transistors for simultaneously outputting body bias voltages of PMOS transistors and NMOS transistors; the working state of the substrate biasing circuit is as follows:

[0019] When the temperature or process parameters change, the temperature-proportional reference current source composed of the sixteenth to twenty-first MOS transistors and the third resistor generates a changing current, which is output to control the body voltages of the PMOS transistors and the NMOS transistors of the amplification circuit via the circuit composed of the twenty-second and twenty-third MOS transistors and the twenty-fourth and twenty-fifth MOS transistors, so as to offset the influence of the change of the temperature or process parameters on the circuit and stabilize the performance of the circuit.

[0020] The inverter-based amplification circuit comprises the first MOS transistor M1 and the second MOS transistor M2 of the inverter that constitutes the differential input pair, the seventh MOS transistor M7 and the eighth MOS transistor M8, the current source third MOS transistor M3, the fourth MOS transistor M4, the fifth MOS transistor M5 and the sixth MOS transistor M6 controlled by the common-mode feedback amplifier, and the ninth MOS transistor M9, the tenth MOS transistor M10, the eleventh MOS transistor M11 and the twelfth MOS transistor M12 that constitute the common-mode feedback amplifier, wherein the first MOS transistor M1, the third MOS transistor M3, the fifth MOS transistor M5, the seventh MOS transistor M7, the ninth MOS transistor M9 and the eleventh MOS transistor M11 are PMOS transistors, and the second MOS transistor M2, the fourth MOS transistor M4, the sixth MOS transistor M6, the eighth MOS transistor M8, the tenth MOS transistor M10 and the twelfth MOS transistor M12 are NMOS transistors.

[0021] The sources of the first MOS transistor M1, the third MOS transistor M3, the fifth MOS transistor M5, the seventh MOS transistor M7, the ninth MOS transistor M9 and the eleventh MOS transistor M11 are connected with an external power supply (V DD ), the sources of the second MOS transistor M2, the fourth MOS transistor M4, the sixth MOS transistor M6, the eighth MOS transistor M8, the tenth MOS transistor M10 and the twelfth MOS transistor M12 are connected with the ground (GND), and the gates of the first MOS transistor M1 and the second MOS transistor M2 are connected with a differential input signal (V in+) and the drain of the first MOS transistor M1, the second MOS transistor M2, the third MOS transistor M3 and the fourth MOS transistor M4 are connected to form an output terminal (V out- ) of the OTA amplifier. out+ ) of the OTA amplifier. in- ) of the OTA amplifier. bp ) of the OTA amplifier. bn ) of the OTA amplifier. out- out+ ref

[0022] The PVT-compensated substrate bias circuit comprises a start-up circuit composed of the thirteenth MOS transistor M13 to the fifteenth MOS transistor M15, a temperature-proportional reference current source composed of the sixteenth MOS transistor M16 to the twenty-first MOS transistor M21 and the third resistor R3, a first output node (V bp ) circuit composed of the twenty-second MOS transistor M22 and the twenty-third MOS transistor M23, and a second output node (V bn ) circuit composed of the twenty-fourth MOS transistor M24 and the twenty-fifth MOS transistor M25, wherein the thirteenth MOS transistor M13, the sixteenth MOS transistor M16, the eighteenth MOS transistor M18, the twentieth MOS transistor M20, the twenty-second MOS transistor M22 and the twenty-fourth MOS transistor M24 are PMOS transistors, and the fourteenth MOS transistor M14, the fifteenth MOS transistor M15, the seventeenth MOS transistor M17, the nineteenth MOS transistor M19, the twenty-first MOS transistor M21, the twenty-third MOS transistor M23 and the twenty-fifth MOS transistor M25 are NMOS transistors.

[0023] ​​​The source of the thirteenth MOS M13, the sixteenth MOS M16, the eighteenth MOS M18, the twenty-second MOS M22, the twenty-fourth MOS M24, the body of the thirteenth MOS M13, the sixteenth MOS M16, the eighteenth MOS M18, the upper plate of the first capacitor C1 and one end of the third resistor R3 are connected with an external power source (V DD ), the source and the body of the fourteenth MOS M14, the fifteenth MOS M15, the seventeenth MOS M17, the nineteenth MOS M19, the twenty-first MOS M21, the twenty-third MOS M23, the twenty-fifth MOS M25, the lower plate of the second capacitor C2 and the third capacitor C3 are connected with the ground (GND), the gate of the thirteenth MOS M13, the fifteenth MOS M15, the seventeenth MOS M17, the nineteenth MOS M19, the twenty-first MOS M21, the twenty-third MOS M23 are connected together and connected with the drain of the sixteenth MOS M16, the seventeenth MOS M17, the drain of the thirteenth MOS M13 and the fifteenth MOS M15 are connected together and connected with the gate of the fourteenth MOS M14, the drain of the fourteenth MOS M14, the eighteenth MOS M18, the nineteenth MOS M19 are connected together and connected with the gate of the sixteenth MOS M16, the twenty-fifth MOS M25, the lower plate of the first capacitor C1, the gate of the eighteenth MOS M18 and the twentieth MOS M20 are connected together and connected with the drain of the twentieth MOS M20, the twenty-first MOS M21, the source and the body of the twentieth MOS M20 are connected and connected with the other end of the third resistor R3, the gate of the twenty-second MOS M22, the twenty-fourth MOS M24 are connected with an external reference power source (V cm ), the drain of the twenty-second MOS M22, the twenty-third MOS M23 are connected together and connected with the upper plate of the second capacitor C2, the body of the first MOS M1, the third MOS M3, the fifth MOS M5, the seventh MOS M7, the twenty-second MOS M22, the drain of the twenty-fourth MOS M24, the twenty-fifth MOS M25 are connected together and connected with the upper plate of the third capacitor C3, the body of the second MOS M2, the fourth MOS M4, the sixth MOS M6, the eighth MOS M8, the twenty-fourth MOS M24.

[0024] The working principle of the present application is described as follows: when the temperature rises, the threshold voltage of the MOS tube decreases, at this time the voltage generated by the substrate bias circuit to bias the body of the PMOS tube rises, and the voltage generated by the substrate bias circuit to bias the body of the NMOS tube decreases; on the contrary, when the temperature decreases, the threshold voltage of the MOS tube rises, at this time the voltage generated by the substrate bias circuit to bias the body of the PMOS tube decreases, and the voltage generated by the substrate bias circuit to bias the body of the NMOS tube rises, thereby changing the threshold voltage of the MOS tube to offset the influence of temperature change on the performance of the circuit. The same principle applies when the process parameters change.

[0025] Figs. 3(a) and 3(b) are graphs of the characteristics of the inverter-based PVT-compensated ultra-low voltage fully differential OTA amplifier of the present application under different process corners at a voltage of 0.6 V and with temperature change. Fig. 3(a) is a graph of the amplifier gain with temperature and process corner change, and when the temperature and process parameters change, the change range of the amplifier gain is compressed to about 3 dB; Fig. 3(b) is a graph of the amplifier bandwidth with temperature and process corner change, and when the temperature and process corner change, the bandwidth change only decreases a little more at low temperature and SS process corner, and in other cases, the decrease is less than 5% compared with the nominal case.

[0026] Figs. 4(a) and 4(b) are frequency response graphs of the inverter-based PVT-compensated ultra-low voltage fully differential OTA amplifier of the present application under different process corners, at voltages of 0.54, 0.6, 0.66 V, and with temperature change from -55°C to 85°C. Fig. 4(a) is a graph of the gain with frequency change, and Fig. 4(b) is a graph of the phase with frequency change. As can be seen from Fig. 4(a), under different temperature, power voltage, and process corner conditions, the open-loop gain of the inverter-based PVT-compensated ultra-low voltage fully differential OTA amplifier of the present application is about 45 dB, and its -3 dB bandwidth is in the range of 20 MHz-50 MHz. As can be seen from Fig. 4(b), under different temperature, power voltage, and process corner conditions, the phase margin of the amplifier is close to 90°.

[0027] The embodiments of the present application are described in detail above with reference to the accompanying drawings, but the present application is not limited to the above-described embodiments, and various modifications can be made within the knowledge of those skilled in the art without departing from the spirit of the present application.

Claims

1. An inverter-based PVT-compensated ultra-low voltage fully differential OTA amplifier, characterized in that, Comprise: The inverter-based amplifier circuit and the PVT-compensated substrate biasing circuit; the inverter-based amplifier circuit comprises a differential input pair composed of CMOS inverters whose substrates are controlled by a substrate biasing circuit, a common-mode feedback amplifier, a variable current source controlled by the common-mode feedback amplifier, and first and second resistors; the PVT-compensated substrate biasing circuit comprises a start-up circuit composed of MOS transistors, a temperature-proportional reference current source composed of MOS transistors and resistors, and a circuit composed of MOS transistors for simultaneously outputting PMOS and NMOS body bias voltages; The PVT-compensated substrate biasing circuit comprises thirteenth to twenty-fifth MOS transistors, first to third capacitors, and a third resistor; the thirteenth to fifteenth MOS transistors compose a start-up circuit, the sixteenth to twenty-first MOS transistors and the third resistor compose a temperature-proportional reference current source, the twenty-second and twenty-third MOS transistors compose a first output node circuit, and the twenty-fourth and twenty-fifth MOS transistors compose a second output node circuit; wherein the thirteenth, sixteenth, eighteenth, twentieth, twenty-second, and twenty-fourth MOS transistors are PMOS transistors, and the fourteenth, fifteenth, seventeenth, nineteenth, twenty-first, twenty-third, and twenty-fifth MOS transistors are NMOS transistors. The source of the thirteenth MOS transistor M13, the sixteenth MOS transistor M16, the eighteenth MOS transistor M18, the twenty-second MOS transistor M22, the twenty-fourth MOS transistor M24, the body of the thirteenth MOS transistor M13, the sixteenth MOS transistor M16, the eighteenth MOS transistor M18, the upper plate of the first capacitor C1 and one end of the third resistor R3 are connected with an external power source V DD The source and the body of the fourteenth MOS transistor M14, the fifteenth MOS transistor M15, the seventeenth MOS transistor M17, the nineteenth MOS transistor M19, the twenty-first MOS transistor M21, the twenty-third MOS transistor M23, the twenty-fifth MOS transistor M25, the lower plate of the second capacitor C2 and the third capacitor C3 are connected with the ground, the gate of the thirteenth MOS transistor M13, the fifteenth MOS transistor M15, the seventeenth MOS transistor M17, the nineteenth MOS transistor M19, the twenty-first MOS transistor M21, the twenty-third MOS transistor M23 are commonly connected and connected with the drain of the sixteenth MOS transistor M16, the seventeenth MOS transistor M17, the drain of the thirteenth MOS transistor M13 and the fifteenth MOS transistor M15 are commonly connected and connected with the gate of the fourteenth MOS transistor M14, the drain of the fourteenth MOS transistor M14, the eighteenth MOS transistor M18, the nineteenth MOS transistor M19 are commonly connected and connected with the gate of the sixteenth MOS transistor M16, the twenty-fifth MOS transistor M25, the lower plate of the first capacitor C1, the gate of the eighteenth MOS transistor M18 and the twentieth MOS transistor M20 are commonly connected and connected with the drain of the twentieth MOS transistor M20, the twenty-first MOS transistor M21, the source and the body of the twentieth MOS transistor M20 are connected and connected with the other end of the third resistor R3, the gate of the twenty-second MOS transistor M22, the twenty-fourth MOS transistor M24 are connected with an external reference power source V cm The drain of the twenty-second MOS transistor M22, the twenty-third MOS transistor M23 are commonly connected and connected with the upper plate of the second capacitor C2, the first MOS transistor M1, the third MOS transistor M3, the fifth MOS transistor M5, the seventh MOS transistor M7, the body of the twenty-second MOS transistor M22, the drain of the twenty-fourth MOS transistor M24, the twenty-fifth MOS transistor M25 are commonly connected and connected with the upper plate of the third capacitor C3, the second MOS transistor M2, the fourth MOS transistor M4, the sixth MOS transistor M6, the eighth MOS transistor M8, the body of the twenty-fourth MOS transistor M24.

2. The inverter-based PVT-compensated ultra-low voltage fully differential OTA amplifier of claim 1, wherein, The inverter-based amplifier circuit comprises first to twelfth MOS transistors M1-M12 and first and second resistors; the first and second MOS transistors and the seventh and eighth MOS transistors compose a pair of inverters and simultaneously serve as differential inputs of the amplifier circuit; the third to sixth MOS transistors serve as a variable current source; and the ninth to twelfth MOS transistors compose a common-mode feedback amplifier; wherein the first, third, fifth, seventh, ninth, and eleventh MOS transistors are PMOS transistors, and the second, fourth, sixth, eighth, tenth, and twelfth MOS transistors are NMOS transistors.

3. The inverter-based PVT-compensated ultra-low voltage fully differential OTA amplifier of claim 2, wherein, The inverter-based amplifier circuit is specifically implemented as: The source of the first MOS M1, the third MOS M3, the fifth MOS M5, the seventh MOS M7, the ninth MOS M9 and the eleventh MOS M11 is connected with an external power source V DD The source of the second MOS M2, the fourth MOS M4, the sixth MOS M6, the eighth MOS M8, the tenth MOS M10 and the twelfth MOS M12 is connected with the ground. The gate of the first MOS M1 and the second MOS M2 is connected with a differential input signal V in+ The drain of the first MOS M1, the second MOS M2, the third MOS M3 and the fourth MOS M4 is commonly connected to form an output terminal V of the OTA amplifier. out- The drain of the fifth MOS M5, the sixth MOS M6, the seventh MOS M7 and the eighth MOS M8 is commonly connected to form another output terminal V of the OTA amplifier. out+ The gate of the third MOS M3, the fourth MOS M4, the fifth MOS M5 and the sixth MOS M6 is commonly connected and connected with the drain of the eleventh MOS M11 and the twelfth MOS M12. The gate of the seventh MOS M7 and the eighth MOS M8 is connected with the differential input signal V in- The body of the first MOS M1, the third MOS M3 and the fifth MOS M5 is commonly connected and connected with a first output node V of a PVT compensation substrate bias circuit. bp The body of the second MOS M2, the fourth MOS M4, the sixth MOS M6 and the eighth MOS M8 is commonly connected and connected with a second output node V of the PVT compensation substrate bias circuit. bn The gate of the ninth MOS M9 and the eleventh MOS M11 is commonly connected and connected with the drain of the ninth MOS M9 and the tenth MOS M10. One end of the first resistor R1 and the second resistor R2 is connected with the output terminal V out- , V out+ The other end of the first resistor R1 and the second resistor R2 is connected with the gate of the tenth MOS M10. The gate of the twelfth MOS M12 is connected with an external reference voltage source V ref .

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