A reversible single-bus interface circuit

Abstract

This invention discloses a reversible single-bus interface circuit, relating to the field of communication technology, to solve the problems of existing single-bus interfaces that can only be plugged in the forward direction and cannot be plugged in the reverse direction, and the complex packaging molds of single-bus products. The single-bus interface circuit includes at least: a first port, a second port, a level guiding circuit, and a logic processing circuit; the level guiding circuit includes at least multiple diodes; both the first port and the second port are connected to the level guiding circuit; the positive and negative power supply terminals of the logic processing circuit are both connected to the level guiding circuit; the multiple diodes are used to introduce the input signal from the communication terminal to the positive power supply terminal; the logic processing circuit is used to perform logic processing on the input signals of the first port and the second port to achieve identification of the communication terminal and the ground terminal. Thus, both forward and reverse plugging of the single-bus interface are simultaneously achieved, simplifying the design requirements of single-bus product packaging molds.

Description

Technical Field

[0001] This invention relates to the field of communication technology, and in particular to a single-bus interface circuit that can be plugged in either direction. Background Art

[0002] Existing single-bus products have two wires, a signal wire and a ground wire, and are widely used in various application environments that require fewer contacts. This is because fewer contacts result in higher connection reliability and lower product cost.

[0003] Existing single-bus products all require distinguishing between signal lines and ground lines, and currently use a reverse insertion prevention method using packaging molds.

[0004] In existing technologies, the reason why single-bus interface circuits (such as the common GX18B20 temperature sensor) cannot be reverse-connected is mainly related to circuit design and physical connection methods. For example, a single-bus interface typically includes a power supply negative terminal corresponding to GND (ground) and a data line corresponding to DQ. The functions of these pins are clear and specific. If the DQ pin is reversed, the original data line may be connected to ground, resulting in data transmission failure or a short circuit.

[0005] To meet diverse market demands, this invention proposes a circuit that eliminates the need to distinguish between signal and ground, thus simplifying the design requirements for single-bus product packaging molds. Summary of the Invention

[0006] The purpose of this invention is to provide a single-bus interface circuit that can be plugged in both forward and reverse directions, thereby simplifying the design requirements of single-bus product packaging molds and meeting the diversified needs of the market.

[0007] To achieve the above objectives, the present invention provides the following technical solution:

[0008] This invention provides a reversible single-bus interface circuit, comprising at least: a first port, a second port, a level guiding circuit, and a logic processing circuit; wherein either the first port or the second port is a ground terminal, and the other terminal is a communication terminal; the level guiding circuit comprises at least a plurality of diodes;

[0009] Both the first port and the second port are connected to the level guiding circuit; both the positive and negative power supply terminals of the logic processing circuit are connected to the level guiding circuit.

[0010] The plurality of diodes are used to introduce the input signal in the communication terminal to the positive terminal of the power supply;

[0011] The logic processing circuit is used to perform logic processing on the input signals of the first port and the second port to identify the communication terminal and the ground terminal.

[0012] Optionally, the level guiding circuit includes a first resistor, a second resistor, a first diode, a second diode, a third diode, and a fourth diode;

[0013] Wherein, the first end of the first resistor is connected to the first port;

[0014] The first terminal of the second resistor is connected to the second port.

[0015] The anode of the first diode is connected to the second terminal of the first resistor;

[0016] The cathode of the second diode is connected to the second terminal of the second resistor;

[0017] The anode of the third diode is connected to the second terminal of the second resistor;

[0018] The cathode of the fourth diode is connected to the second terminal of the first resistor;

[0019] The cathodes of the first diode and the third diode are both connected to the positive terminal of the power supply.

[0020] The anodes of the second diode and the fourth diode are both connected to the negative terminal of the power supply.

[0021] Optionally, the logic processing circuit includes at least a port signal identification sub-circuit;

[0022] The port signal identification sub-circuit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, and an eighth NMOS transistor.

[0023] Optionally, the gates of the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, and the fourth PMOS transistor are all connected to the first bias voltage terminal of the logic processing circuit; the first bias voltage terminal is connected to the second terminal of the first resistor.

[0024] The first PMOS transistor, the second PMOS transistor, the first NMOS transistor, and the second NMOS transistor are connected in series; the source of the first PMOS transistor is connected to the positive terminal of the power supply; the source of the second NMOS transistor is connected to the negative terminal of the power supply.

[0025] The drain of the first PMOS transistor and the source of the second PMOS transistor are both connected to the source of the third PMOS transistor.

[0026] The source of the first NMOS transistor and the drain of the second NMOS transistor are both connected to the source of the third NMOS transistor;

[0027] The drain of the second PMOS transistor, the drain of the first NMOS transistor, the gate of the third PMOS transistor, the gate of the third NMOS transistor, the gate of the fourth PMOS transistor, and the gate of the fourth NMOS transistor are all connected to the first node.

[0028] The source of the fourth PMOS transistor is connected to the positive terminal of the power supply, and the source of the fourth NMOS transistor is connected to the negative terminal of the power supply; the fourth PMOS transistor and the fourth NMOS transistor are connected in series.

[0029] The drain of the fourth PMOS transistor and the drain of the fourth NMOS transistor are both connected to the second node.

[0030] The gates of the fifth PMOS transistor, the sixth PMOS transistor, the seventh PMOS transistor, and the eighth PMOS transistor are all connected to the second bias voltage terminal of the logic processing circuit; the second bias voltage terminal is connected to the second terminal of the second resistor.

[0031] The fifth PMOS transistor, the sixth PMOS transistor, the fifth NMOS transistor, and the sixth NMOS transistor are connected in series; the source of the fifth PMOS transistor is connected to the positive terminal of the power supply; the source of the sixth NMOS transistor is connected to the negative terminal of the power supply.

[0032] The drain of the fifth PMOS transistor and the source of the sixth PMOS transistor are both connected to the source of the seventh PMOS transistor.

[0033] The source of the fifth NMOS transistor and the drain of the sixth NMOS transistor are both connected to the source of the seventh NMOS transistor.

[0034] The drain of the sixth PMOS transistor, the drain of the fifth NMOS transistor, the gate of the seventh PMOS transistor, the gate of the seventh NMOS transistor, the gate of the eighth PMOS transistor, and the gate of the eighth NMOS transistor are all connected to the third node.

[0035] The source of the eighth PMOS transistor is connected to the positive terminal of the power supply, and the source of the eighth NMOS transistor is connected to the negative terminal of the power supply; the eighth PMOS transistor and the eighth NMOS transistor are connected in series.

[0036] The drain of the eighth PMOS transistor and the drain of the eighth NMOS transistor are both connected to the fourth node.

[0037] Optionally, the logic processing circuit further includes a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, and a fourteenth NMOS transistor.

[0038] Optionally, the gate of the ninth PMOS transistor and the gate of the ninth NMOS transistor are both connected to the second node;

[0039] The ninth PMOS transistor, the tenth PMOS transistor, and the tenth NMOS transistor are connected in series, that is, the drain of the ninth PMOS transistor is connected to the source of the tenth PMOS transistor, and the drain of the tenth PMOS transistor is connected to the drain of the tenth NMOS transistor.

[0040] The drain of the ninth NMOS transistor is connected to the drain of the tenth NMOS transistor; the source of the ninth NMOS transistor and the source of the tenth NMOS transistor are both connected to the negative terminal VSS of the power supply.

[0041] The drain of the tenth PMOS transistor, the drain of the tenth NMOS transistor, the gate of the thirteenth NMOS transistor, the gate of the twelfth PMOS transistor, and the gate of the twelfth NMOS transistor are all connected to the fifth node.

[0042] The gates of the eleventh PMOS transistor and the eleventh NMOS transistor are both connected to the fourth node.

[0043] The eleventh PMOS transistor, the twelfth PMOS transistor, and the twelfth NMOS transistor are connected in series, that is, the drain of the eleventh PMOS transistor is connected to the source of the twelfth PMOS transistor, and the drain of the twelfth PMOS transistor is connected to the drain of the twelfth NMOS transistor.

[0044] The drain of the eleventh NMOS transistor is connected to the drain of the twelfth NMOS transistor; the source of the eleventh NMOS transistor and the source of the twelfth NMOS transistor are connected to the negative terminal VSS of the power supply.

[0045] The drain of the twelfth PMOS transistor, the source of the twelfth NMOS transistor, the gate of the ninth PMOS transistor, the gate of the tenth NMOS transistor, and the gate of the fourteenth NMOS transistor are all connected to the sixth node.

[0046] Optionally, both the thirteenth NMOS transistor and the fourteenth NMOS transistor are large-size power transistors.

[0047] Optionally, the reversible single-bus interface circuit further includes: an ESD protection circuit; the ESD protection circuit includes: a fifth diode, a sixth diode, a fifteenth NMOS transistor, a sixteenth NMOS transistor, a third resistor, and a fourth resistor;

[0048] The cathode of the fifth diode and the drain of the fifteenth NMOS transistor are both connected to the first port;

[0049] The cathode of the sixth diode and the drain of the sixteenth NMOS transistor are both connected to the second port;

[0050] The gate of the fifteenth NMOS transistor is connected to the first terminal of the third resistor; the second terminal of the third resistor is connected to the first terminal of the fourth resistor; the second terminal of the fourth resistor is connected to the gate of the sixteenth NMOS transistor.

[0051] The source of both the fifteenth NMOS transistor and the sixteenth NMOS transistor are connected to the negative terminal of the power supply.

[0052] Optionally, the logic processing circuit further includes a digital parsing circuit, wherein both the second node and the fourth node are connected to the digital parsing circuit; the digital parsing circuit is used to identify and parse the communication signal based on the level output by the second node and the level output by the fourth node.

[0053] Optionally, the reversible single-bus interface circuit also includes a seventeenth NMOS transistor and an eighteenth NMOS transistor;

[0054] The drain of the seventeenth NMOS transistor is connected to the first port; the drain of the eighteenth NMOS transistor is connected to the second port; the sources of both the seventeenth and eighteenth NMOS transistors are connected to the negative terminal of the power supply.

[0055] The gates of the seventeenth NMOS transistor and the eighteenth NMOS transistor are both connected to the digital parsing circuit.

[0056] Compared with existing technologies, this invention provides a reversible single-bus interface circuit. A level-guiding circuit and a logic processing circuit are added after the two ports. First, multiple diodes in the level-guiding circuit connect the communication signal input from one port to the positive terminal of the power supply, and the ground signal input from the other port to the negative terminal (also called the ground terminal). This solves the problem of the two ports not being able to be reversed in existing single-bus interface circuits, ensuring the safe operation of the internal electronic components under both reversible connection conditions. Then, the logic processing circuit performs logical processing on the communication signal and the ground signal, enabling the identification of the communication terminal and the ground terminal, and outputting the corresponding signal for protocol parsing. Thus, both forward and reverse connection of the single-bus interface are simultaneously achieved, simplifying the design requirements of single-bus product packaging molds and meeting diverse market demands. Attached Figure Description

[0057] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0058] Figure 1 A schematic diagram of the circuit structure of a reversible single-bus interface circuit provided in one embodiment of the present invention;

[0059] Figure 2 A schematic diagram of the circuit structure of a reversible single-bus interface circuit provided for another embodiment of the present invention;

[0060] Figure label:

[0061] 1-Level guiding circuit; 2-Logic processing circuit; 3-ESD protection circuit; 21-Port signal identification sub-circuit; 22-Digital analysis circuit. Detailed Implementation

[0062] To facilitate a clear description of the technical solutions in the embodiments of the present invention, the terms "first" and "second" are used to distinguish identical or similar items with essentially the same function and effect. For example, the first threshold and the second threshold are merely used to distinguish different thresholds and do not limit their order. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and that the terms "first" and "second" are not necessarily different.

[0063] It should be noted that in this invention, the terms "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in this invention should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0064] In this invention, "at least one" means one or more, and "more than one" means two or more. "And / or" describes the relationship between the associated objects, indicating that three relationships can exist.

[0065] like Figure 1 and Figure 2 As shown, this embodiment of the invention provides a reversible single-bus interface circuit, which includes at least: a first port (i.e., port 0), a second port (i.e., port 1), a level guiding circuit 1, and a logic processing circuit 2; wherein either the first port or the second port is a ground terminal and the other terminal is a communication terminal; the level guiding circuit 1 includes at least a plurality of diodes;

[0066] The logic processing circuit 2 is used to perform logic processing on the input signals of the first port and the second port to realize the identification of the communication terminal and the ground terminal.

[0067] Understandably, the single-bus protocol itself supports parasitic power supply mode and specifies the concrete methods for power transmission and data communication via data lines. The single-bus interface includes two ports: a ground port and a signal port. The ground port provides reference positioning, and the signal port transmits communication signals. As mentioned in the background section, the physical location of the power supply pins (e.g., the positive power terminal) of the chip housing the single-bus interface is fixed throughout the single-bus process. Furthermore, the single-bus has no external power supply; the communication signal input from the communication terminal provides power to the internal circuitry of the chip. Since the pin positions are fixed, if the communication terminal and ground port are connected in reverse, meaning the original data line might be connected to ground, data transmission will fail or the internal circuitry of the chip will short-circuit. Therefore, in existing technologies, single-bus interfaces can only be connected in the correct orientation and not in the reverse orientation. This is also why existing single-bus interfaces use a package mold. It should be noted that the main function of the single-bus interface circuit is to perform protocol parsing on the communication signal input from the communication terminal.

[0068] Existing single-bus interface circuits often include two ports and a digital parsing circuit. In this way, the communication end receives the communication signal, the ground end receives the ground signal, and then the communication signal and the ground signal enter the digital parsing circuit, which performs protocol parsing on the communication signal.

[0069] Unlike existing technologies, in order to meet diverse market demands, this invention proposes a single-bus interface circuit that eliminates the need to distinguish between the communication end and the ground end at the single-bus interface. A level-guiding circuit and a logic processing circuit are added between the two ports and the digital parsing circuit. First, multiple diodes in the level-guiding circuit connect the communication signal input from either port to the positive terminal of the power supply, and the ground signal input from the other port to the negative terminal of the power supply (also called the ground end). This solves the problem of the two ports not being able to be reversed in existing single-bus interface circuits. Then, the logic processing circuit performs logical processing on the communication signal and the ground signal, enabling the identification of the communication end and the ground end. Finally, the corresponding signal is output to the digital parsing circuit for further protocol parsing of the communication signal.

[0070] Based on the above, it can be understood that... (See also) Figure 2 The single-bus interface circuit also includes a digital parsing circuit 22, which is used to perform protocol parsing on the communication signals.

[0071] Alternatively, as Figure 1 As shown, the level guiding circuit 1 may include a first resistor R1, a second resistor R2, a first diode D1, a second diode D2, a third diode D3, and a fourth diode D4;

[0072] Among them, the first end of the first resistor R1 is connected to the first port;

[0073] The first terminal of the second resistor R2 is connected to the second port.

[0074] The anode of the first diode D1 is connected to the second terminal of the first resistor R1;

[0075] The cathode of the second diode D2 is connected to the second terminal of the second resistor R2;

[0076] The anode of the third diode D3 is connected to the second terminal of the second resistor R2;

[0077] The cathode of the fourth diode D4 is connected to the second terminal of the first resistor R1;

[0078] The cathodes of both the first diode D1 and the third diode D3 are connected to the positive terminal of the power supply.

[0079] The anodes of the second diode D2 and the fourth diode D4 are both connected to the negative terminal of the power supply.

[0080] Among them, the first resistor R1 and the second resistor R2 serve as circuit protection.

[0081] All the diodes mentioned above achieve level guidance in the following way: If port 0 is the communication terminal and port 1 is the ground terminal, that is, port 0 inputs a high level and port 1 inputs a low level, then the first diode D1 and the second diode D2 conduct. The high level at port 0 is then introduced to the positive terminal VDD of the power supply by the first diode D1, and the conduction of the second diode D2 causes the low level at port 1 to be introduced to the negative terminal VSS of the power supply.

[0082] If port 0 is ground and port 1 is communication port, meaning port 0 receives a low level and port 1 receives a high level, then diodes D3 and D4 will conduct. The high level at port 1 will be introduced to the positive terminal VDD of the power supply via diode D3, and the conduction of diode D4 will introduce the low level at port 0 to the negative terminal VSS of the power supply.

[0083] As can be seen from the above, regardless of whether the input at port 0 is high or low, or whether the input at port 1 is low or high, the positive power supply terminal VDD and the negative power supply terminal VSS remain unchanged. This ensures that the internal circuitry of the single-bus interface chip will not be burned out and can operate safely.

[0084] Alternatively, as Figure 1 or Figure 2 As shown, the logic processing circuit 2 includes at least a port signal recognition sub-circuit 21;

[0085] The port signal identification sub-circuit 21 includes a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, a fourth PMOS transistor P4, a fifth PMOS transistor P5, a sixth PMOS transistor P6, a seventh PMOS transistor P7, an eighth PMOS transistor P8, a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, a fourth NMOS transistor N4, a fifth NMOS transistor N5, a sixth NMOS transistor N6, a seventh NMOS transistor N7, and an eighth NMOS transistor N8.

[0086] The specific connection relationship of the above port signal identification sub-circuit 21 is as follows: the gates of the first PMOS transistor P1, the second PMOS transistor P2, the third PMOS transistor P3, and the fourth PMOS transistor P4 are all connected to the first bias voltage terminal of the logic processing circuit 2; the first bias voltage terminal is connected to the second terminal of the first resistor R1.

[0087] The first PMOS transistor P1, the second PMOS transistor P2, the first NMOS transistor N1, and the second NMOS transistor N2 are connected in series. That is, the drain of the first PMOS transistor P1 is connected to the source of the second PMOS transistor P2, the drain of the second PMOS transistor P2 is connected to the drain of the first NMOS transistor N1, and the source of the first NMOS transistor N1 is connected to the drain of the second NMOS transistor N2. The source of the first PMOS transistor P1 is connected to the positive terminal VDD of the power supply, and the source of the second NMOS transistor N2 is connected to the negative terminal VSS of the power supply.

[0088] The drain of the first PMOS transistor P1 and the source of the second PMOS transistor P2 are both connected to the source of the third PMOS transistor P3; the drain of the third PMOS transistor P3 is connected to the negative terminal VSS of the power supply.

[0089] The source of the first NMOS transistor N1 and the drain of the second NMOS transistor N2 are both connected to the source of the third NMOS transistor N3; the drain of the third NMOS transistor N3 is connected to the positive terminal of the power supply VDD.

[0090] The drain of the second PMOS transistor P2, the drain of the first NMOS transistor N1, the gate of the third PMOS transistor P3, the gate of the third NMOS transistor N3, the gate of the fourth PMOS transistor P4, and the gate of the fourth NMOS transistor N4 are all connected to the first node (the level signal at the first node is V1).

[0091] The source of the fourth PMOS transistor P4 is connected to the positive terminal of the power supply, and the source of the fourth NMOS transistor N4 is connected to the negative terminal of the power supply; the fourth PMOS transistor P4 and the fourth NMOS transistor N4 are connected in series.

[0092] The drain of the fourth PMOS transistor P4 and the drain of the fourth NMOS transistor N4 are both connected to the second node (the level signal output from the second node is V2).

[0093] As can be seen from the above, the first bias voltage terminal is connected to the second terminal of the first resistor R1. That is, the combination of MOSFETs P1, P2, P3, P4, N1, N2, N3, and N4 follows the input signal of port 0 (i.e., the first port). First, P1, P2, P3, N1, N2, and N3 are combined to form a first inverter, and P4 and N4 are combined to form a second inverter. The first inverter performs a logic conversion on the input signal of port 0, outputting an inverse level signal V1 at the first node (for example, if port 0 is high, then the level V1 at the first node is low). Then, the second inverter performs another logic conversion on the level V1 at the first node, obtaining the level signal V2 output at the second node, where the level signal V2 is high. The above process ensures that the level signal V2 output at the second node is consistent with the signal input at port 0.

[0094] The first inverter has a Schmitt hysteresis effect, which can filter out glitches at the input port and improve communication reliability. The second inverter has a shaping effect, making the waveform of V2 closer to a square wave, which facilitates subsequent digital circuit processing.

[0095] The gates of the fifth PMOS transistor P5, the sixth PMOS transistor P6, the seventh PMOS transistor P7, and the eighth PMOS transistor P8 are all connected to the second bias voltage terminal of the logic processing circuit 2; the second bias voltage terminal is connected to the second terminal of the second resistor R2.

[0096] The fifth PMOS transistor P5, the sixth PMOS transistor P6, the fifth NMOS transistor N5, and the sixth NMOS transistor N6 are connected in series; that is, the drain of the fifth PMOS transistor P5 is connected to the source of the sixth PMOS transistor P6, the drain of the sixth PMOS transistor P6 is connected to the drain of the fifth NMOS transistor N5, and the source of the fifth NMOS transistor N5 is connected to the drain of the sixth NMOS transistor N6; the source of the fifth PMOS transistor P5 is connected to the positive terminal of the power supply; and the source of the sixth NMOS transistor N6 is connected to the negative terminal of the power supply.

[0097] The drain of the fifth PMOS transistor P5 and the source of the sixth PMOS transistor P6 are both connected to the source of the seventh PMOS transistor P7; the negative terminal of the drain power supply of the seventh PMOS transistor P7 is connected to VSS.

[0098] The source of the fifth NMOS transistor N5 and the drain of the sixth NMOS transistor N6 are both connected to the source of the seventh NMOS transistor N7; the drain of the seventh NMOS transistor N7 is connected to the positive terminal of the power supply VDD.

[0099] The drain of the sixth PMOS transistor P6, the drain of the fifth NMOS transistor N5, the gate of the seventh PMOS transistor P7, the gate of the seventh NMOS transistor N7, the gate of the eighth PMOS transistor P8, and the gate of the eighth NMOS transistor N8 are all connected to the third node (the level signal at the third node is V3).

[0100] The source of the eighth PMOS transistor P8 is connected to the positive terminal of the power supply, and the source of the eighth NMOS transistor N8 is connected to the negative terminal of the power supply; the eighth PMOS transistor P8 and the eighth NMOS transistor N8 are connected in series.

[0101] The drain of the eighth PMOS transistor P8, the drain of the eighth NMOS transistor N8, and the digital analysis circuit 22 are all connected to the fourth node (the level signal at the fourth node is V4).

[0102] As can be seen from the above, the second bias voltage terminal is connected to the second terminal of the second resistor R2. That is, the combination of MOSFETs P5, P6, P7, P8, N5, N6, N7, and N8 follows the input signal of port 1 (i.e., the second port). First, P5, P6, P7, N5, N6, and N7 are combined to form a third inverter, and P8 and N8 are combined to form a fourth inverter. The third inverter performs a logic conversion on the input signal of port 1, outputting an inverse level signal V3 at the third node (for example, if port 1 is low, then the level V3 at the third node is high). Then, the fourth inverter performs another logic conversion on the level V3 at the third node, obtaining the level signal V4 output at the fourth node, where the level signal V4 is low. The above process ensures that the level signal V4 output at the fourth node is consistent with the signal input to port 1.

[0103] The third inverter has a Schmitt hysteresis effect, which can filter out glitches at the input port and improve communication reliability. The fourth inverter has a shaping effect, making the waveform of V4 closer to a square wave, which facilitates subsequent digital circuit processing.

[0104] Optionally, the logic processing circuit 2 further includes a ninth PMOS transistor P9, a tenth PMOS transistor P10, an eleventh PMOS transistor P11, a twelfth PMOS transistor P12, a ninth NMOS transistor N9, a tenth NMOS transistor N10, an eleventh NMOS transistor N11, a twelfth NMOS transistor N12, a thirteenth NMOS transistor N13, and a fourteenth NMOS transistor N14.

[0105] The connection relationship of the above MOS transistors is as follows: the gate of the ninth PMOS transistor P9 and the gate of the ninth NMOS transistor N9 are both connected to the second node.

[0106] The ninth PMOS transistor P9, the tenth PMOS transistor P10, and the tenth NMOS transistor N10 are connected in series. That is, the drain of the ninth PMOS transistor P9 is connected to the source of the tenth PMOS transistor P10, and the drain of the tenth PMOS transistor P10 is connected to the drain of the tenth NMOS transistor N10.

[0107] The drain of the ninth NMOS transistor N9 is connected to the drain of the tenth NMOS transistor N10; the source of the ninth NMOS transistor N9 and the source of the tenth NMOS transistor N10 are both connected to the negative terminal VSS of the power supply.

[0108] The drain of the tenth PMOS transistor P10, the drain of the tenth NMOS transistor N10, the gate of the thirteenth NMOS transistor, the gate of the twelfth PMOS transistor P12, and the gate of the twelfth NMOS transistor N12 are all connected to the fifth node (the level signal at the fifth node is V5).

[0109] The gates of the eleventh PMOS transistor P11 and the eleventh NMOS transistor N11 are both connected to the fourth node.

[0110] The eleventh PMOS transistor P11, the twelfth PMOS transistor P12, and the twelfth NMOS transistor N12 are connected in series. That is, the drain of the eleventh PMOS transistor P11 is connected to the source of the twelfth PMOS transistor P12, and the drain of the twelfth PMOS transistor P12 is connected to the drain of the twelfth NMOS transistor N12.

[0111] The drain of the eleventh NMOS transistor N11 and the drain of the twelfth NMOS transistor N12 are connected; the source of the eleventh NMOS transistor N11 and the source of the twelfth NMOS transistor N12 are connected to the negative terminal VSS of the power supply.

[0112] The drain of the twelfth PMOS transistor P12, the source of the twelfth NMOS transistor N12, the gate of the ninth PMOS transistor P9, the gate of the tenth NMOS transistor N10, and the gate of the fourteenth NMOS transistor are all connected to the sixth node (the level signal at the sixth node is V6).

[0113] The source of the thirteenth NMOS transistor N13 is connected to the negative terminal of the power supply. The drain of the thirteenth NMOS transistor N13 is connected to the source of the fourteenth NMOS transistor N14. The drain of the fourteenth NMOS transistor N14 is connected to the second terminal of the first resistor R1.

[0114] N13 and N14 are used after the internal VDD and VSS levels are initially established to: 1) provide a more reliable connection to the internal VSS to ground port, making VSS more stable, so that the internal VSS-based circuits work more reliably; 2) reduce the voltage drop of the internal VSS to ground port, so that the operating voltage range of the internal circuits is higher and closer to the level range of the signal port to ground port, so that the operating voltage margin of the internal circuits is greater.

[0115] It should be noted that both the thirteenth NMOS transistor N13 and the fourteenth NMOS transistor N14 are large-size power transistors. This allows them to handle large currents.

[0116] From the above, we can see that when port 0 is high and port 1 is ground: D1 is turned on, and port 0 supplies power to the internal VDD; D2 is turned on, and port 1 supplies power to the internal VSS; a weak voltage is generated inside the interface circuit, and logic processing circuit 2 starts to work.

[0117] A high level at port 0 causes V1 to go low and V2 to go high.

[0118] A low level at port 1 causes V3 to go high and V4 to go low;

[0119] Subsequently, V5 goes low and V6 goes high, causing N14 to turn off and N13 to turn on. N13 has a very low impedance, which can provide a larger current to VSS, and a complete voltage is established inside the circuit, allowing it to start working normally.

[0120] When port 1 is high and port 0 is ground: D3 is turned on, and port 1 supplies power to the internal VDD; D4 is turned on, and port 0 supplies power to the internal VSS; a weak voltage is generated inside the interface circuit, and logic processing circuit 2 starts to work.

[0121] A low level at port 0 causes V1 to go high and V2 to go low;

[0122] A high level at port 1 causes V3 to go low and V4 to go high.

[0123] Subsequently, V5 goes high and V6 goes low, causing N14 to conduct and N13 to turn off. N14 has a very low impedance, which can provide a larger current. A complete voltage is established inside the circuit, and it can start to work normally.

[0124] See Figure 2 The reversible single-bus interface circuit also includes: ESD protection circuit 3; ESD protection circuit 3 includes: fifth diode D5, sixth diode D6, fifteenth NMOS transistor N15, sixteenth NMOS transistor N16, third resistor and fourth resistor;

[0125] Among them, the cathode of the fifth diode D5 and the drain of the fifteenth NMOS transistor N15 are both connected to the first port;

[0126] The cathode of the sixth diode D6 and the drain of the sixteenth NMOS transistor N16 are both connected to the second port;

[0127] The gate of the fifteenth NMOS transistor N15 is connected to the first terminal of the third resistor; the second terminal of the third resistor is connected to the first terminal of the fourth resistor; the second terminal of the fourth resistor is connected to the gate of the sixteenth NMOS transistor N16.

[0128] The source of the fifteenth NMOS transistor N15 and the source of the sixteenth NMOS transistor N16 are both connected to the negative terminal of the power supply.

[0129] As can be seen from the above, ESD protection circuit 3 can protect the single bus from electrostatic discharge damage, ensuring circuit stability and reliability.

[0130] Optionally, the reversible single-bus interface circuit may also include a seventeenth NMOS transistor N17 and an eighteenth NMOS transistor N18;

[0131] The drain of the seventeenth NMOS transistor N17 is connected to the first port; the drain of the eighteenth NMOS transistor N18 is connected to the second port; the source of both the seventeenth NMOS transistor N17 and the source of the eighteenth NMOS transistor N18 are connected to the negative terminal of the power supply.

[0132] The gates of the seventeenth NMOS transistor N17 and the eighteenth NMOS transistor N18 are both connected to the digital parsing circuit 22.

[0133] As can be seen from the above, after the digital parsing circuit 22 performs protocol parsing on the communication signal, the output result is output through the seventeenth NMOS transistor N17 and the eighteenth NMOS transistor N18, and then output to other circuits outside the single-bus interface circuit.

[0134] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings, the disclosure, and the appended claims in carrying out the claimed invention. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. A single processor or other unit can implement several functions listed in the claims. While different dependent claims may recite certain measures, this does not mean that these measures cannot be combined to produce good results.

[0135] Although the invention has been described in conjunction with specific features and embodiments, it is obvious that various modifications and combinations can be made therein without departing from the spirit and scope of the invention. Accordingly, this specification and drawings are merely exemplary descriptions of the invention as defined by the appended claims, and are considered to cover any and all modifications, variations, combinations, or equivalents within the scope of the invention. Clearly, those skilled in the art can make various alterations and modifications to the invention without departing from its spirit and scope. Thus, if such modifications and modifications of the invention fall within the scope of the claims and their equivalents, the invention is also intended to include such modifications and modifications.

Claims

1. A reversible single-bus interface circuit, characterized in that, At least including: The system comprises a first port, a second port, a level guiding circuit, and a logic processing circuit; wherein either the first port or the second port is a ground terminal and the other terminal is a communication terminal; the level guiding circuit includes at least a plurality of diodes. Both the first port and the second port are connected to the level guiding circuit; both the positive and negative power supply terminals of the logic processing circuit are connected to the level guiding circuit. The plurality of diodes are used to introduce the input signal in the communication terminal to the positive terminal of the power supply; The logic processing circuit is used to perform logic processing on the input signals of the first port and the input signals of the second port to realize the identification of the communication terminal and the ground terminal; The logic processing circuit includes at least a port signal identification sub-circuit; the port signal identification sub-circuit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, and an eighth NMOS transistor; The gates of the first PMOS transistor, the second PMOS transistor, the first NMOS transistor, and the second NMOS transistor are all connected to the first bias voltage terminal of the logic processing circuit; the first bias voltage terminal is connected to the second terminal of the first resistor in the level guiding circuit; the first PMOS transistor, the second PMOS transistor, the first NMOS transistor, and the second NMOS transistor are connected in series; the source of the first PMOS transistor is connected to the positive terminal of the power supply; the source of the second NMOS transistor is connected to the negative terminal of the power supply; the drains of the first PMOS transistor and the sources of the second PMOS transistor are both connected to the source of the third PMOS transistor; the sources of the first NMOS transistor and the drains of the second NMOS transistor are both connected to the source of the third NMOS transistor; the drain of the second PMOS transistor, the drain of the first NMOS transistor, the gate of the third PMOS transistor, and the gate of the third NMOS transistor are all connected in series. The gates of the fourth PMOS transistor, the fourth NMOS transistor, and the fourth PMOS transistor are all connected to the first node; the source of the fourth PMOS transistor is connected to the positive terminal of the power supply, and the source of the fourth NMOS transistor is connected to the negative terminal of the power supply; the fourth PMOS transistor and the fourth NMOS transistor are connected in series; the drains of the fourth PMOS transistor and the fourth NMOS transistor are both connected to the second node; the gates of the fifth PMOS transistor, the sixth PMOS transistor, the fifth NMOS transistor, and the sixth NMOS transistor are all connected to the second bias voltage terminal of the logic processing circuit; the second bias voltage terminal is connected to the second terminal of the second resistor in the level guiding circuit; the fifth PMOS transistor, the sixth PMOS transistor, the fifth NMOS transistor, and the sixth NMOS transistor are connected in series; the source of the fifth PMOS transistor is connected to the first node; the gates of the fifth PMOS transistor and the fourth NMOS transistor are connected in series ... The positive terminal of the power supply is connected; the source of the sixth NMOS transistor is connected to the negative terminal of the power supply; the drain of the fifth PMOS transistor and the source of the sixth PMOS transistor are both connected to the source of the seventh PMOS transistor; the source of the fifth NMOS transistor and the drain of the sixth NMOS transistor are both connected to the source of the seventh NMOS transistor; the drain of the sixth PMOS transistor, the drain of the fifth NMOS transistor, the gate of the seventh PMOS transistor, the gate of the seventh NMOS transistor, the gate of the eighth PMOS transistor, and the gate of the eighth NMOS transistor are all connected to the third node; the source of the eighth PMOS transistor is connected to the positive terminal of the power supply, and the source of the eighth NMOS transistor is connected to the negative terminal of the power supply; the eighth PMOS transistor and the eighth NMOS transistor are connected in series; the drain of the eighth PMOS transistor and the drain of the eighth NMOS transistor are both connected to the fourth node.

2. The reversible single-bus interface circuit according to claim 1, characterized in that, The level guiding circuit includes a first resistor, a second resistor, a first diode, a second diode, a third diode, and a fourth diode; Wherein, the first end of the first resistor is connected to the first port; The first terminal of the second resistor is connected to the second port. The anode of the first diode is connected to the second terminal of the first resistor; The cathode of the second diode is connected to the second terminal of the second resistor; The anode of the third diode is connected to the second terminal of the second resistor; The cathode of the fourth diode is connected to the second terminal of the first resistor; The cathodes of the first diode and the third diode are both connected to the positive terminal of the power supply. The anodes of the second diode and the fourth diode are both connected to the negative terminal of the power supply.

3. The reversible single-bus interface circuit according to claim 2, characterized in that, The logic processing circuit also includes a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, and a fourteenth NMOS transistor.

4. The reversible single-bus interface circuit according to claim 3, characterized in that, The gate of the ninth PMOS transistor and the gate of the ninth NMOS transistor are both connected to the second node. The ninth PMOS transistor, the tenth PMOS transistor, and the tenth NMOS transistor are connected in series, that is, the drain of the ninth PMOS transistor is connected to the source of the tenth PMOS transistor, and the drain of the tenth PMOS transistor is connected to the drain of the tenth NMOS transistor. The drain of the ninth NMOS transistor is connected to the drain of the tenth NMOS transistor; the source of the ninth NMOS transistor and the source of the tenth NMOS transistor are both connected to the negative terminal of the power supply. The drain of the tenth PMOS transistor, the drain of the tenth NMOS transistor, the gate of the thirteenth NMOS transistor, the gate of the twelfth PMOS transistor, and the gate of the twelfth NMOS transistor are all connected to the fifth node. The gates of the eleventh PMOS transistor and the eleventh NMOS transistor are both connected to the fourth node. The eleventh PMOS transistor, the twelfth PMOS transistor, and the twelfth NMOS transistor are connected in series, that is, the drain of the eleventh PMOS transistor is connected to the source of the twelfth PMOS transistor, and the drain of the twelfth PMOS transistor is connected to the drain of the twelfth NMOS transistor. The drain of the eleventh NMOS transistor and the drain of the twelfth NMOS transistor are connected; the source of the eleventh NMOS transistor and the source of the twelfth NMOS transistor are connected to the negative terminal of the power supply. The drain of the twelfth PMOS transistor, the source of the twelfth NMOS transistor, the gate of the tenth PMOS transistor, the gate of the tenth NMOS transistor, and the gate of the fourteenth NMOS transistor are all connected to the sixth node.

5. The reversible single-bus interface circuit according to claim 4, characterized in that, Both the thirteenth and fourteenth NMOS transistors are large-size power transistors.

6. The reversible single-bus interface circuit according to claim 4, characterized in that, Also includes: ESD protection circuit; The ESD protection circuit includes: a fifth diode, a sixth diode, a fifteenth NMOS transistor, a sixteenth NMOS transistor, a third resistor, and a fourth resistor; The cathode of the fifth diode and the drain of the fifteenth NMOS transistor are both connected to the first port; The cathode of the sixth diode and the drain of the sixteenth NMOS transistor are both connected to the second port; The gate of the fifteenth NMOS transistor is connected to the first terminal of the third resistor; the second terminal of the third resistor is connected to the first terminal of the fourth resistor; the second terminal of the fourth resistor is connected to the gate of the sixteenth NMOS transistor. The source of both the fifteenth NMOS transistor and the sixteenth NMOS transistor are connected to the negative terminal of the power supply.

7. The reversible single-bus interface circuit according to claim 4, characterized in that, The logic processing circuit further includes a digital parsing circuit, and both the second node and the fourth node are connected to the digital parsing circuit; the digital parsing circuit is used to identify and parse the communication signal based on the level output by the second node and the level output by the fourth node.

8. The reversible single-bus interface circuit according to claim 7, characterized in that, It also includes the seventeenth and eighteenth NMOS transistors; The drain of the seventeenth NMOS transistor is connected to the first port; the drain of the eighteenth NMOS transistor is connected to the second port; the sources of both the seventeenth and eighteenth NMOS transistors are connected to the negative terminal of the power supply. The gates of the seventeenth NMOS transistor and the eighteenth NMOS transistor are both connected to the digital parsing circuit.

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