A power supply voltage identification control circuit and method in analog-to-digital conversion

Abstract

The present invention discloses a power supply voltage identification control circuit and method in analog-to-digital conversion, which belongs to the field of integrated circuit technology. The method of the present invention is applied to the scenario where the power supply voltage changes. First, a resistor string is set between the power supply voltage to be monitored and the ground for reduction processing to obtain the reduced power supply voltage; then, the reference voltage generated by the internal bandgap reference of the chip is reduced to obtain the first and second reference voltages, which are input together with the reduced power supply voltage into two comparators for comparison, and the comparison results are output to a state recognition machine; finally, the state recognition machine performs voltage judgment based on the state change of the comparison result to obtain a voltage recognition result. The present invention can monitor and automatically identify the power supply voltage in real time without the need for additional power supply, and can tolerate fluctuations in the power supply voltage within a certain range to obtain stable recognition results.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a power supply voltage identification control circuit and method in analog-to-digital conversion. Background Art

[0002] In modern integrated circuit design, especially in some variable power supply application scenarios, such as data converter interfaces and clock driver interfaces, power supply voltage changes may occur. The power supply voltage will be affected by different product requirements and show a clear "gradation" distribution. For example, it will dynamically change between 1.8V, 2.5V, 3.3V or 5V to adapt to different application requirements. This voltage change poses a challenge to chip interface design.

[0003] In existing chip interface designs, the voltage withstand characteristics of different high- and low-voltage components, typically within the same process, can vary significantly. Traditional designs typically adopt the principle of "higher voltage, not lower voltage"—designing related circuits with high-voltage components to achieve backward compatibility with supply voltages. For example, in a circuit supporting a 1.8V to 5V supply range, designers might uniformly use 5V-tolerant components to ensure proper operation at the highest voltage. However, this approach presents significant performance tradeoffs. High-voltage components often operate at lower voltages (such as 1.8V or 2.5V) due to their higher threshold voltages and limited drive capability, resulting in reduced speed and inability to fully realize their optimal performance at low voltages. On the other hand, while using low-voltage components (such as 1.8V or 2.5V components) can achieve higher speeds and lower power consumption at low voltages, their limited voltage withstand makes them incapable of withstanding higher supply voltages (such as 3.3V or 5V). This can easily lead to device breakdown or reliability issues, limiting their application and preventing proper operation at higher voltages.

[0004] Therefore, there is an urgent need for a control circuit and method that can monitor the power supply voltage in real time and automatically switch between high and low voltage modules in the circuit according to the actual voltage conditions, taking into account the voltage change requirements and the high-speed performance requirements of the circuit to optimize the performance of the circuit under different voltage conditions. Summary of the Invention

[0005] The problem to be solved by the present invention is to provide a power supply voltage identification control circuit and method in analog-to-digital conversion, which can monitor and identify the power supply voltage in real time, and then realize automatic switching control of high and low voltage modules in actual circuits.

[0006] The present invention adopts the following technical solution: a power supply voltage identification and control method in analog-to-digital conversion, comprising the following steps:

[0007] Step 1: Setting a resistor string between the power supply voltage Vdd to be monitored and the ground, reducing the power supply voltage Vdd to be monitored to obtain a reduced power supply voltage Vdd1, wherein the power supply voltage Vdd to be monitored is distributed in grades;

[0008] Step 2: Select the reference voltage Vref generated by the internal bandgap reference of the chip as a reference, perform reduction processing, and obtain the first reference voltage Vref1 and the second reference voltage Vref2 based on the voltage fluctuation range that needs to be tolerated;

[0009] Step 3: Input the reduced power supply voltage Vdd1 and the first reference voltage Vref1 into the first comparator comph, and input the reduced power supply voltage Vdd1 and the second reference voltage Vref2 into the second comparator cpmpl. After comparison, the comparison results Vo1 and Vo2 are output to the state recognition machine respectively.

[0010] Step 4: The state recognition machine performs voltage determination based on the state changes of the comparison results Vo1 and Vo2 to obtain a voltage recognition result.

[0011] Preferably, in step 1, the power supply voltage Vdd to be monitored is distributed in two or three levels, the high level voltage is Vdd_hi, and the low level voltage is Vdd_lo;

[0012] The voltage reduction factor of the resistor string is α. The reduced power supply voltage Vdd1 is output between the last two resistors at the end of the resistor string close to the ground. The value of Vdd1 is Vdd*α.

[0013] The high-end voltage after reduction is Vdd_hi*α, and the low-end voltage after reduction is Vdd_lo*α.

[0014] Preferably, in step 2, considering the actual power supply noise and error tolerance, the voltage fluctuation range that needs to be tolerated is ±10%, the high-end voltage fluctuation range is [0.9*Vdd_hi, 1.1*Vdd_hi], the low-end voltage fluctuation range is [0.9*Vdd_lo, 1.1*Vdd_lo], and 0.9*Vdd_hi-1.1*Vdd_lo is greater than 500mV.

[0015] Preferably, in step 2, the first reference voltage Vref1 is set to 1.1α*Vdd_lo, and the second reference voltage Vref2 is set to 0.9α*Vdd_lo;

[0016] The reference voltage Vref is divided by setting a resistor string to obtain a first reference voltage Vref1 and a second reference voltage Vref2.

[0017] Preferably, in step 3, the first comparator comph and the second comparator cpmpl are the same dual - end comparators;

[0018] For the first comparator comph, the first reference voltage Vref1 is input to the input terminal vip1, the reduced power supply voltage Vdd1 is input to the input terminal vin1, and the comparison result Vo1 is output from the output terminal;

[0019] For the second comparator compl, the second reference voltage Vref2 is input to the input terminal vip2, the reduced power supply voltage Vdd1 is input to the input terminal vin2, and the comparison result Vo2 is output from the output terminal.

[0020] Preferably, for the first comparator comph, the determination rule is: when Vref1 > Vdd1, Vo1 = 1; when Vref1 < Vdd1, Vo1 = 0;

[0021] For the second comparator compl, the determination rule is: when Vref2 > Vdd1, Vo2 = 1; when Vref2 < Vdd1, Vo2 = 0;

[0022] When Vref1 is close to Vdd1 and Vref2 is close to Vdd1, the first comparator comph and the second comparator cpmpl cannot accurately identify the magnitude of the input voltage, and the judgment results Vo1 and Vo2 jump between 0 and 1, presenting a metastable state.

[0023] Preferably, the state recognition machine makes a voltage determination according to the state changes of the comparison results Vo1 and Vo2, and the method is as follows:

[0024] When the power supply voltage Vdd to be monitored drops from the high - grade voltage Vdd_hi to the low - grade voltage Vdd_lo:

[0025] When Vo1 = 0 and Vo2 = 0, the recognition result is 00, and the determined voltage is Vdd_hi;

[0026] When Vo1 changes from 0 to 1 and Vo2 = 0, the recognition result is 00, and the determined voltage is Vdd_hi;

[0027] When Vo1 = 1 and Vo2 = 0, the recognition result is 00, and the determined voltage is Vdd_hi;

[0028] What is the English translation of the following text:When Vo1 = 1 and Vo2 changes from 0 to 1, the recognition result is 11, and the determined voltage is Vdd_lo; [[ID=^]]

[0029] When Vo1 = 1 and Vo2 = 1, the recognition result is 11, and the determined voltage is Vdd_lo;

[0030] When the power supply voltage Vdd to be monitored rises from the low - grade voltage Vdd_lo to the high - grade voltage Vdd_hi:

[0031] When Vo1=1 and Vo2=1, the recognition result is 11, and the voltage is determined to be Vdd_lo;

[0032] When Vo1=1 and Vo2 changes from 1 to 0, the recognition result is 11, and the voltage is determined to be Vdd_lo;

[0033] When Vo1=1 and Vo2=0, the recognition result is 11, and the voltage is determined to be Vdd_lo;

[0034] When Vo1 changes from 1 to 0 and Vo2 = 0, the recognition result is 00 and the judgment voltage is Vdd_hi;

[0035] When Vo1=0 and Vo2=0, the recognition result is 00, and the determination voltage is Vdd_hi.

[0036] The technical solution of the present invention further provides: a power supply voltage identification control circuit in analog-to-digital conversion, used to implement any of the above control methods, comprising:

[0037] A resistor string is connected between the power supply voltage to be monitored and the ground, and is used to control the power supply voltage to be reduced to obtain a reduced power supply voltage Vdd1;

[0038] a first comparator comph, configured to compare the first reference voltage Vref1 with the reduced power supply voltage Vdd1;

[0039] a second comparator compl, configured to compare the second reference voltage Vref2 with the reduced power supply voltage Vdd1;

[0040] The state recognition machine is used to perform voltage judgment on the state changes of the output results of the first comparator comph and the second comparator compl to obtain a voltage recognition result.

[0041] Compared with the prior art, the present invention adopts the above technical solution and has the following technical effects:

[0042] 1. The power supply voltage identification and control method of the present invention can monitor and identify the power supply voltage in real time, and then realize automatic switching control of high and low voltage modules in actual circuits, so as to take into account the voltage change requirements and the high-speed performance requirements of the circuit.

[0043] 2. The power supply voltage identification and control method of the present invention can achieve stable output of identification results when the power supply voltage fluctuates within a certain range. The power supply voltage fluctuation range can cover fluctuations caused by noise in conventional application conditions.

[0044] 3. The power supply voltage identification control circuit of the present invention can operate under the control of the monitored variable voltage without the need for additional power supply and is not affected by its voltage changes. It uses two identical comparators and jointly determines the specific range of the voltage to be identified based on the results of the two comparators. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 This is a structural block diagram of a power supply voltage identification control circuit according to an embodiment of the present invention;

[0046] Figure 2 This is a state diagram of a single comparator solution according to an embodiment of the present invention. DETAILED DESCRIPTION

[0047] In order to make the purpose, technical solutions and advantages of the present invention clearer, the technical solutions of the application are further elaborated in detail below with reference to the accompanying drawings. The described embodiments are only a part of the embodiments involved in the present invention. All non-innovative embodiments of other researchers in this field on this embodiment fall within the scope of protection of the present invention. At the same time, the step numbers in the embodiments of the present invention are only set for the convenience of explanation and description, and the order between the steps is not limited in any way. The execution order of each step in the embodiment can be adaptively adjusted according to the understanding of those skilled in the art.

[0048] Example 1

[0049] A power supply voltage identification control circuit in analog-to-digital conversion comprises a resistor string, a first comparator compl, a second comparator compl and a state identification machine.

[0050] A resistor string is connected between the power supply voltage to be monitored and ground, and is used to control the power supply voltage to be reduced. The voltage reduction coefficient is α, and the reduced power supply voltage Vdd1 is obtained;

[0051] a first comparator comph, configured to compare the first reference voltage Vref1 with the reduced power supply voltage Vdd1;

[0052] a second comparator compl, configured to compare the second reference voltage Vref2 with the reduced power supply voltage Vdd1;

[0053] The state recognition machine is used to perform voltage judgment on the state changes of the output results of the first comparator comph and the second comparator compl to obtain a voltage recognition result.

[0054] In actual analog circuit applications, the power supply voltage may vary, sometimes spanning different voltage standards. In this embodiment, two voltage levels to be identified are used for distinction, where the high level voltage is Vdd_hi and the low level voltage is Vdd_lo.

[0055] It's important to note that, taking into account actual power supply noise and error tolerance, analog voltages generally have an error tolerance range of approximately ±10%. This means the high-range voltage error tolerance range is in the range [0.9*Vdd_hi, 1.1*Vdd_hi], and the low-range voltage error tolerance range is in the range [0.9*Vdd_lo, 1.1*Vdd_lo]. Because the high and low voltages differ significantly, the relationship 0.9*Vdd_hi > 1.1*Vdd_lo is inevitable, and the value of 0.9*Vdd_hi - 1.1*Vdd_lo is generally greater than 500mV to ensure clear distinction between the two voltages.

[0056] On the other hand, if analog circuits need to operate at both high and low voltages, they will generally choose components with higher voltage resistance to ensure circuit safety. Therefore, the voltage identification module only needs to identify the ±10% boundary of the low-range voltage Vdd_lo mentioned above.

[0057] In this embodiment, in order to accurately identify the ±10% boundary voltage of Vdd_lo, an on-chip reference source Vref is selected as a reference, and the voltage of the on-chip reference source Vref is not affected by the power supply voltage.

[0058] In order to balance recognition accuracy and design difficulty, this embodiment selects a voltage reduction coefficient α (α<1) for preprocessing the power supply voltage Vdd and the reference voltage Vref to be monitored.

[0059] The monitored power supply voltage Vdd is divided by a resistor string to obtain a reduced power supply voltage Vdd1, where Vdd1 = Vdd*α. At the same time, the same method is used to divide Vref using a resistor string to obtain reference voltages of 1.1α*Vdd_lo and 0.9α*Vdd_lo, which are equal, respectively, as Vref1 and Vref2.

[0060] The scaled-down power supply voltage Vdd1 is compared with Vref1 and Vref2 simultaneously by two comparators comph and compl.

[0061] The first comparator comph has an input terminal vip1 inputting a first reference voltage Vref1, an input terminal vin1 inputting a reduced power supply voltage Vdd1, and an output terminal outputting a comparison result Vo1;

[0062] The second comparator compl has an input terminal vip2 inputting the second reference voltage Vref2, an input terminal vin2 inputting the reduced power supply voltage Vdd1, and an output terminal outputting a comparison result Vo2.

[0063] The two comparators will give an output result of 1 or 0 according to the high and low levels of the two input signals, and input it into the state machine recognition machine. The state machine recognition machine monitors the output results of the two comparators in real time, and then the actual working voltage can be stably determined.

[0064] Example 2

[0065] In conventional interface power supply application scenarios, the power supply voltage shows a clear "tiered" distribution due to different product requirements. Based on the actual chip implementation process, if there is a change in the interface power supply, most scenarios cover 2 levels, and very few scenarios are 3 levels, and there are obvious differences between the voltages of each level.

[0066] In this embodiment, the common switching between 1.8V and 3.3V is taken as an example to describe in detail the implementation steps of the power supply voltage identification and control method in analog-to-digital conversion of the present invention.

[0067] The first step is to "reduce" the power supply voltage Vdd by connecting a resistor string between the power supply voltage Vdd to be monitored and ground, such as Figure 1 As shown, in this embodiment, the reduction coefficient α is 1 / 4, so that the reduced voltages corresponding to 1.8V and 3.3V are 0.45V and 0.825V respectively.

[0068] It should be noted that in normal application scenarios, the power supply voltage will be provided by chips or power modules such as LDO and DCDC. Usually, filter capacitors are placed at the power supply end or decoupling capacitors are placed at the power receiving end to reduce fluctuations caused by non-ideal factors such as power supply noise and improve the stability of the power supply voltage.

[0069] However, due to the limitations of actual application conditions, power supply fluctuations cannot be filtered out to an "absolutely clean" state, and there will always be a certain amount of fluctuation interference. For example, a 3.3V powered LDO may have a peak-to-peak output fluctuation of more than ten millivolts or even close to 100mV, depending on the size of the filter capacitor.

[0070] In this embodiment, if Figure 1 As shown, the power supply voltage Vdd is compressed to 1 / 4 of its original value after being reduced by the resistor string. At this time, the corresponding maximum fluctuation amplitude is only about 20mV, which can be fully covered by the spans of the different threshold reference voltages corresponding to the two comparators.

[0071] The second step is to take the reference voltage generated by the bandgap reference inside the chip and "reduce" it by a certain ratio. The reduction range is related to the result after the power supply voltage to be tested is reduced in the first step and the fluctuation range that needs to be tolerated.

[0072] In this embodiment, for a 1.8V power supply, the safety range is generally within ±10%, approximately 1.6-2V. Considering the 1 / 4 reduction in the first step, the reduction is 0.4V-0.5V. The protection principle for 1.8V withstand voltage devices is to not exceed the upper voltage limit. Therefore, in this embodiment, 0.5V is selected as Vref1, and 0.4V, which is the reduction of the typical 1.8V operating voltage, is selected as Vref2.

[0073] Within the 1.8V device operating voltage range, the voltage generated by the bandgap reference is generally 1.2V, which can be achieved by means of a resistor string to 0.5V and 0.4V.

[0074] In the third step, Vdd / 4 and Vref1 and Vref2 are connected to two two-terminal comparators respectively to perform voltage judgment, obtain comparison results Vo1 and Vo2, and input them into the state recognition machine.

[0075] The decision rules of the two comparators are:

[0076] When Vip>Vin, Vo=1; when Vip>Vin, Vo=0.

[0077] Due to non-ideal factors such as noise and metastability in the comparator itself, as well as non-ideal factors such as noise or fluctuation in the input signal itself, when Vip and Vin are very close (for example, a difference of a few mV), the comparator will not be able to accurately identify the input size, and the judgment result will fluctuate between 0 and 1, presenting an unstable state.

[0078] If the two comparator scheme of the present invention is not adopted, and only a single comparator is used, then when the voltage to be monitored is close to the reference voltage, the power supply voltage fluctuation caused by non-ideal factors such as noise will cause the judgment result to jump between the two situations continuously, such as Figure 2 As shown, the corresponding interface circuit cannot operate under stable working conditions.

[0079] After adopting the two comparator scheme of the present invention, since the corresponding judgment references of the two comparators are significantly different, it can be ensured that one of the two comparators will have a stable output result. Then, based on the result of the other comparator, a stable and correct recognition result is given by combining the two, thereby ensuring that the corresponding interface circuit can operate stably.

[0080] Step 4: In the state recognition machine, the two comparators comph and compl, and the corresponding comparison results Vo1 and Vo2, will present different situations as the monitored power supply voltage decreases and increases. Even considering non-ideal factors such as noise described in the third step, the combination of the two comparator results is included in the situation shown in Table 1 below. Therefore, the state recognition machine can identify state changes, obtain the judgment voltage, and realize automatic switching control of the high and low voltage modules.

[0081] Table 1 Summary of the identification results of the two comparators

[0082]

[0083] From Table 1, we can see that the rules for voltage recognition by the state recognition machine are as follows:

[0084] (1) When the power supply voltage Vdd to be monitored drops from the high-end voltage Vdd_hi to the low-end voltage Vdd_lo:

[0085] When Vo1=0 and Vo2=0, the recognition result is 00, and the judgment voltage is Vdd_hi;

[0086] When Vo1 changes from 0 to 1 and Vo2 = 0, the recognition result is 00 and the judgment voltage is Vdd_hi;

[0087] When Vo1=1 and Vo2=0, the recognition result is 00, and the judgment voltage is Vdd_hi;

[0088] When Vo1=1 and Vo2 changes from 0 to 1, the recognition result is 11, and the voltage is determined to be Vdd_lo;

[0089] When Vo1=1 and Vo2=1, the recognition result is 11, and the voltage is determined to be Vdd_lo;

[0090] (2) When the power supply voltage Vdd to be monitored increases from the low-range voltage Vdd_lo to the high-range voltage Vdd_hi,

[0091] When Vo1=1 and Vo2=1, the recognition result is 11, and the voltage is determined to be Vdd_lo;

[0092] When Vo1=1 and Vo2 changes from 1 to 0, the recognition result is 11, and the voltage is determined to be Vdd_lo;

[0093] When Vo1=1 and Vo2=0, the recognition result is 11, and the voltage is determined to be Vdd_lo;

[0094] When Vo1 changes from 1 to 0 and Vo2 = 0, the recognition result is 00 and the judgment voltage is Vdd_hi;

[0095] When Vo1=0 and Vo2=0, the recognition result is 00, and the determination voltage is Vdd_hi.

[0096] In particular, although the corresponding Vdd of states 3 and 7 in Table 1 are both between 1.8V and 2V, they are identified as different judgment voltages due to different power supply change directions, which does not have an adverse effect on the circuit.

[0097] Because even in state 3, the actual voltage is between 1.8V and 2V, but the voltage determined at this time is 3.3V, then the corresponding circuit module still remains in the 3.3V device state. The actual 1.8V-2V voltage is relatively low and will not cause damage to the 3.3V device.

[0098] At the same time, it can be seen from Table 1 that although the two comparators still fluctuate between 0 and 1 when their respective input terminals are close to each other, by using the state machine to identify and monitor the respective results of the two comparators, the influence of one of the fluctuating results can be effectively eliminated, thereby achieving a stable output result.

[0099] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A power supply voltage identification and control method in analog-to-digital conversion, characterized in that: The steps include: Step 1: Setting a resistor string between the power supply voltage Vdd to be monitored and the ground, reducing the power supply voltage Vdd to be monitored to obtain a reduced power supply voltage Vdd1, wherein the power supply voltage Vdd to be monitored is distributed in grades; Step 2: Select the reference voltage Vref generated by the internal bandgap reference of the chip as a reference, perform reduction processing, and obtain the first reference voltage Vref1 and the second reference voltage Vref2 based on the voltage fluctuation range that needs to be tolerated; Step 3: Input the reduced power supply voltage Vdd1 and the first reference voltage Vref1 into the first comparator comph, and input the reduced power supply voltage Vdd1 and the second reference voltage Vref2 into the second comparator cpmpl, and compare them simultaneously, and output comparison results Vo1 and Vo2 to the state recognition machine respectively; The first comparator comph and the second comparator cpmpl are identical double-ended comparators; The first comparator comph has an input terminal vip1 inputting a first reference voltage Vref1, an input terminal vin1 inputting a reduced power supply voltage Vdd1, and an output terminal outputting a comparison result Vo1; The second comparator compl has an input terminal vip2 inputting a second reference voltage Vref2, an input terminal vin2 inputting a reduced power supply voltage Vdd1, and an output terminal outputting a comparison result Vo2; The state recognition machine performs voltage determination based on the state changes of the comparison results Vo1 and Vo2 in the following manner: When the power supply voltage Vdd to be monitored decreases from the high-range voltage Vdd_hi to the low-range voltage Vdd_lo: When Vo1=0 and Vo2=0, the recognition result is 00, and the judgment voltage is Vdd_hi; When Vo1 changes from 0 to 1 and Vo2 = 0, the recognition result is 00 and the judgment voltage is Vdd_hi; When Vo1=1 and Vo2=0, the recognition result is 00, and the judgment voltage is Vdd_hi; When Vo1=1 and Vo2 changes from 0 to 1, the recognition result is 11, and the voltage is determined to be Vdd_lo; When Vo1=1 and Vo2=1, the recognition result is 11, and the voltage is determined to be Vdd_lo; When the power supply voltage Vdd to be monitored increases from the low-range voltage Vdd_lo to the high-range voltage Vdd_hi: When Vo1=1 and Vo2=1, the recognition result is 11, and the voltage is determined to be Vdd_lo; When Vo1=1 and Vo2 changes from 1 to 0, the recognition result is 11, and the voltage is determined to be Vdd_lo; When Vo1=1 and Vo2=0, the recognition result is 11, and the voltage is determined to be Vdd_lo; When Vo1 changes from 1 to 0 and Vo2 = 0, the recognition result is 00 and the judgment voltage is Vdd_hi; When Vo1=0 and Vo2=0, the recognition result is 00, and the judgment voltage is Vdd_hi; Step 4: The state recognition machine performs voltage determination based on the state changes of the comparison results Vo1 and Vo2 to obtain a voltage recognition result.

2. The power supply voltage identification and control method in analog-to-digital conversion according to claim 1, characterized in that: The power supply voltage Vdd to be monitored is distributed in two or three levels, the high level voltage is Vdd_hi, and the low level voltage is Vdd_lo.

3. The power supply voltage identification and control method in analog-to-digital conversion according to claim 2, characterized in that: In step 1, the voltage reduction coefficient of the resistor string is α, and the reduced power supply voltage Vdd1 is output between the last two resistors at the end of the resistor string close to the ground. The value of Vdd1 is Vdd*α.

4. The power supply voltage identification and control method in analog-to-digital conversion according to claim 3, characterized in that: In step 2, considering the actual power supply noise and error tolerance, the voltage fluctuation range that needs to be tolerated is ±10%, the high-end voltage fluctuation range is [0.9*Vdd_hi, 1.1*Vdd_hi], the low-end voltage fluctuation range is [0.9*Vdd_lo, 1.1*Vdd_lo], and 0.9*Vdd_hi-1.1*Vdd_lo is greater than 500mV.

5. The power supply voltage identification and control method in analog-to-digital conversion according to claim 4, characterized in that: In step 2, the fluctuation range of the low-range voltage Vdd_lo is identified, and the first reference voltage Vref1 is set to 1.1α*Vdd_lo, and the second reference voltage Vref2 is set to 0.9α*Vdd_lo.

6. The power supply voltage identification and control method in analog-to-digital conversion according to claim 5, characterized in that: The reference voltage Vref is not affected by the power supply voltage Vdd to be monitored. The reference voltage Vref is divided by setting a resistor string to obtain a first reference voltage Vref1 and a second reference voltage Vref2.

7. The power supply voltage identification and control method in analog-to-digital conversion according to claim 5, wherein: The first comparator comph has a determination rule as follows: when Vref1> Vdd1, Vo1=1; when Vref1< Vdd1, Vo1=0; The second comparator compl has a determination rule as follows: when Vref2>Vdd1, Vo2=1; when Vref2<Vdd1, Vo2=0.

8. A power supply voltage identification control circuit in analog-to-digital conversion, used to implement the control method according to any one of claims 1 to 7, characterized in that: include: A resistor string is connected between the power supply voltage to be monitored and the ground, and is used to control the power supply voltage to be reduced to obtain a reduced power supply voltage Vdd1; a first comparator comph, configured to compare the first reference voltage Vref1 with the reduced power supply voltage Vdd1; a second comparator compl, configured to compare the second reference voltage Vref2 with the reduced power supply voltage Vdd1; The state recognition machine is used to perform voltage judgment on the state changes of the output results of the first comparator comph and the second comparator compl to obtain a voltage recognition result.

Images