Time division multiplexing I / F conversion circuit

Abstract

The invention discloses a time division multiplexing I / F conversion circuit, which comprises an integrating circuit, a threshold circuit, a control circuit, a constant current source, a switching circuit, a clock circuit and an output circuit, and is characterized in that a multi-path analog switch and an AD conversion chip are added, and a multi-path integrating circuit is respectively connected with each channel in the multi-path analog switch; the FPGA of the control circuit controls the multi-path analog switch in real time and switches each channel of the multi-path analog switch, so that the voltage at the rear end of integration and the AD front-end conditioning circuit are alternated; and the AD conversion chip can complete signal acquisition and conversion within the conduction time of the corresponding channel. According to the invention, multiple paths of voltage are sampled and fed back in a time-division dislocation manner. And the functions which can be realized by the original multi-path AD conversion chip and the signal conditioning circuit are realized, so that the cost and the complexity of the circuit are reduced.

Description

Technical Field

[0001] The present invention relates to an I / F conversion circuit, in particular to a time division multiplexing I / F conversion circuit. Background Art

[0002] I / F conversion circuits are widely used in the field of inertial navigation. They collect current signals from accelerometers and convert them into frequency signals. When the accelerometer outputs a positive current, the I / F conversion circuit outputs a positive frequency signal. When the accelerometer outputs a negative current, the I / F conversion circuit outputs a negative frequency signal. The I / F conversion circuit is highly sensitive to the accelerometer output. The faster the response, the higher the sensitivity and resolution of the I / F conversion circuit, which is crucial for the real-time performance of inertial navigation.

[0003] The I / F conversion circuit is a high-precision conversion circuit based on the principle of charge balance, converting analog current into frequency pulses. Charge integration causes the output voltage to rise or fall from zero. When the high or low threshold is reached, feedback is generated and a pulse is output. Currently, there are two main designs for I / F conversion circuits:

[0004] The first type is a traditional I / F conversion circuit, consisting of an integrator circuit, a threshold circuit, an FPGA control circuit, and a constant current source circuit. The threshold circuit has two thresholds: an upper threshold and a lower threshold. Due to the limited number of thresholds, this type of I / F conversion circuit has low resolution.

[0005] The second type of I / F conversion circuit introduces an A / D converter into the threshold circuit, subdividing the number of thresholds. This method improves the resolution of the I / F conversion circuit. However, the disadvantage is that for a common three-channel I / F conversion circuit, three A / D chips are required. To ensure the appropriate input voltage range for each of the three A / D chips, a signal conditioning circuit must be added to each of the three A / D chips' front ends, increasing the cost and complexity of the circuit. Summary of the Invention

[0006] The technical problem solved by the present invention is to provide a time-division multiplexing I / F conversion circuit, which can realize the functions that can only be realized by the original multi-channel AD conversion chip and signal conditioning circuit, and reduce the cost and complexity of the circuit.

[0007] A time-division multiplexing I / F conversion circuit includes an integration circuit, a threshold circuit, a control circuit, a constant current source, a switch circuit, a clock circuit, and an output circuit. The circuit also includes a multi-channel analog switch and an AD conversion chip. The multi-channel integration circuits are respectively connected to each channel of the multi-channel analog switch. The FPGA of the control circuit controls the multi-channel analog switch in real time, switching each channel of the multi-channel analog switch so that the integration back-end voltage and the AD front-end conditioning circuit are rotated. The AD conversion chip can complete signal acquisition and conversion within the time when the corresponding channel is turned on.

[0008] Furthermore, the multi-channel analog switch has three channels.

[0009] Furthermore, when the feedback cycle is set to 128K and the three channels need to be switched back and forth within 128K, the connection time between the AD conversion chip and the integral output of each channel is 2.6us. During this 2.6us, the AD conversion chip samples and quantizes the channel connected at this time and outputs the conversion result to the control circuit.

[0010] Furthermore, the FPGA of the control circuit implements time-division control logic, staggers and cyclically conducts the three-way integrated voltage signals; controls the AD conversion chip to implement sampling and reads the AD conversion chip sampling data; compares the voltage digital quantity sampled by the AD conversion chip with the preset threshold voltage threshold; and controls the constant current source feedback.

[0011] Furthermore, the FPGA analyzes the quantization result of the AD conversion chip and compares the voltage value with the preset threshold voltages Vth1, Vth2, Vth3, Vth4, Vth5, Vth6, Vth7, and Vth8. When the integrated voltage is lower than the currently compared threshold voltage, the output is 0; when it is higher than the currently compared threshold voltage, the output is AD(n), where n=1 to 8. At this time, the number of output pulses is the difference between the current sampling result and the previous sampling result; when the integrated voltage is higher than the threshold voltage Vth8, the circuit enters the feedback stage, keeping the value of AD(n) at 0 until the feedback stage ends; the number of output pulses is the difference between the preset threshold voltage threshold number 8 and the output of the previous AD conversion chip sampling result; and the above process is repeated in the next cycle.

[0012] The time-division multiplexing I / F conversion circuit designed in this invention utilizes time-division multiplexing technology, employing a multi-channel analog switch with an AD conversion chip and a conditioning circuit. By performing time-division staggered sampling and feedback on multiple voltage channels, it achieves functions previously only possible with multiple AD and signal conditioning circuits, reducing circuit cost and complexity. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 This is the structural block diagram of the IF conversion circuit;

[0014] Figure 2 This is a structural diagram of the present invention;

[0015] Figure 3 Schematic diagram of the relationship between the voltage range and the pulse signal in an embodiment of the present invention. DETAILED DESCRIPTION

[0016] The present invention will be further described below with reference to the accompanying drawings.

[0017] The present invention designs a time-division multiplexing I / F conversion circuit. Using only one AD conversion chip and one signal conditioning circuit, it achieves the functions that can only be achieved with multiple AD conversion chips and signal conditioning circuits by performing time-division staggered sampling and feedback on multiple voltage channels.

[0018] The I / F conversion circuit is mainly composed of an integration circuit, a threshold circuit, a control circuit, a constant current source, a switch circuit, a clock circuit, and an output circuit. The block diagram is as follows: Figure 1 shown.

[0019] According to the integral amplification output formula:

[0020]

[0021] U is the integrated voltage. When a positive current is input, U gradually decreases. When U falls below the lower threshold, the control circuit controls the negative constant current source to provide feedback on the input current. If U is still below the lower threshold after feedback, the control circuit turns on the negative constant current source again to provide feedback on the input current. If U is above the lower threshold after feedback, no feedback is provided. When a negative current is input, U gradually increases. When U is above the upper threshold, the control circuit controls the positive constant current source to provide feedback on the input current. If U is still above the upper threshold after feedback, the control circuit turns on the negative constant current source again to provide feedback on the input current. If U is above the upper threshold after feedback, no feedback is provided.

[0022] In this feedback cycle, if the voltage U is subdivided N times, the number of thresholds in each feedback cycle will be N times the current number, the number of pulses output during a single feedback will also be N times, and the scale factor will also be expanded N times accordingly. This threshold division can be completed using an AD conversion chip.

[0023] For the AD converter chip + IF solution, the threshold circuit is implemented by the conditioning circuit and the AD converter chip. For a three-channel conversion circuit, three conditioning circuits and three independent AD converter chips are required.

[0024] Now, through time division multiplexing technology, the original function can be realized by using a multi-channel analog switch with an AD conversion chip + a conditioning circuit. The system block diagram is as follows: Figure 2 As shown:

[0025] Hardware circuit design of the present invention:

[0026] After the accelerometer current signal is input, it first passes through an integrator circuit, which integrates and amplifies the input current. The voltage U behind the integrated current changes continuously with the injection of the integrated current. For the I / F conversion circuit, the integrating op amp must meet the requirements of low bias current and high bandwidth to meet the dynamic characteristics of integration and feedback.

[0027] At the same time, the FPGA of the control circuit controls the multi-channel analog switch in real time, switching the various channels of the multi-channel analog switch, so that the integral back-end voltage and the AD conversion chip front-end conditioning circuit are rotated.

[0028] The control circuit is mainly composed of FPGA, and its main functions are:

[0029] 1. Implementation of time-division control logic, staggered and cyclic conduction of three-way integrated voltage signals;

[0030] 2. Control the AD conversion chip to achieve sampling and read the AD conversion chip sampling data;

[0031] 3. Compare the voltage digital value sampled by the AD conversion chip with the preset threshold voltage threshold;

[0032] 4. Control constant current source feedback;

[0033] 5. Control pulse output.

[0034] The analog switch that controls switching needs to have a switching capability of more than 3 channels and fast turn-on and turn-off times.

[0035] The conditioning circuit needs to condition the voltage output by the integration circuit so that the output voltage range meets the input voltage range of the AD conversion chip.

[0036] The AD converter chip must feature a high sampling frequency and fast sampling time to ensure signal acquisition and conversion within the time the corresponding channel is on. If the feedback cycle is set to 128K, and the three channels need to be switched back and forth within 128K, the connection time between the AD converter chip and each channel's integral output is 1 / (128000*3)s≈2.6us. During this 2.6us, the AD converter chip samples and quantizes the currently connected channel and outputs the conversion results to the control circuit.

[0037] FPGA analyzes the quantization results of the AD conversion chip and compares the voltage value with the preset threshold voltages Vth1, Vth2, Vth3, Vth4, Vth5, Vth6, Vth7, and Vth8. When the integrated voltage is lower than the currently compared threshold voltage, the output is 0. When it is higher than the currently compared threshold voltage, the output is AD(n), where n=1 to 8. At this time, the number of output pulses is the difference between the current sampling result and the previous sampling result. When the integrated voltage is higher than the threshold voltage Vth8, the circuit enters the feedback stage, keeping the value of AD(n) at 0 until the end of the feedback stage. The number of output pulses is the output difference between the preset threshold voltage threshold number 8 and the previous AD conversion chip sampling result. The above process is repeated in the next cycle, as shown in the following example. Figure 3 shown.

[0038] The above description of the preferred embodiments of the present invention is merely illustrative in nature and is not intended to limit the present invention, its applications, or uses. Therefore, the scope of protection of the present invention is not limited to these embodiments and details. Without departing from the basic principles of the present invention, those skilled in the art will be able to modify or substitute these embodiments and details, and the modified or substituted embodiments will also fall within the scope of protection of the present invention.

Claims

1. A time-division multiplexing I / F conversion circuit, comprising an integration circuit, a threshold circuit, a control circuit, a constant current source, a switch circuit, a clock circuit, and an output circuit, characterized in that: It also includes a multi-channel analog switch and an AD conversion chip. The multi-channel integration circuits are respectively connected to the various channels in the multi-channel analog switch; the FPGA of the control circuit controls the multi-channel analog switch in real time, switches the various channels of the multi-channel analog switch, and rotates the integration back-end voltage and the AD front-end conditioning circuit; the AD conversion chip can complete signal acquisition and conversion within the time when the corresponding channel is turned on.

2. The time-division multiplexing I / F conversion circuit according to claim 1, characterized in that: The multi-way analog switch has 3 channels.

3. The time-division multiplexing I / F conversion circuit according to claim 2, characterized in that: When the feedback cycle is set to 128K, and the three channels need to be switched back and forth within 128K, the connection time between the AD conversion chip and each channel integral output is 2.6us. During this 2.6us, the AD conversion chip samples and quantizes the channels that are connected at this time, and outputs the conversion results to the control circuit.

4. The time-division multiplexing I / F conversion circuit according to claim 2, characterized in that: The FPGA of the control circuit implements the time-division control logic, performs staggered cyclic conduction on the three-way integrated voltage signals; controls the AD conversion chip to implement sampling, and reads the sampling data of the AD conversion chip; compares the voltage digital quantity sampled by the AD conversion chip with the preset threshold voltage threshold; and controls the constant current source feedback.

5. The time-division multiplexing I / F conversion circuit according to claim 4, characterized in that: FPGA analyzes the quantization result of the AD conversion chip and compares the voltage value with the preset threshold voltages Vth1, Vth2, Vth3, Vth4, Vth5, Vth6, Vth7, and Vth8. When the integrated voltage is lower than the currently compared threshold voltage, the output is 0, and when it is higher than the currently compared threshold voltage, the output is AD(n), where n=1 to 8. At this time, the number of output pulses is the difference between the current sampling result and the previous sampling result; when the integrated voltage is higher than the threshold voltage Vth8, the circuit enters the feedback stage, keeping the value of AD(n) at 0 until the feedback stage ends; the number of output pulses is the output difference between the preset threshold voltage threshold number 8 and the previous AD conversion chip sampling result; the above process is repeated in the next cycle.

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