Pipeline analog-to-digital converters and control chips, electronic equipment

Abstract

This disclosure relates to a pipelined analog-to-digital converter (ADC) and its control chip, as well as an electronic device. The pipelined ADC includes: multiple cascaded pipelined processing units. Each pipelined processing unit includes: a sub-ADC for performing analog-to-digital conversion on a received input analog signal to obtain a first digital signal; a digital-to-analog converter for performing digital-to-analog conversion on the first digital signal to obtain a first analog signal; a signal processing module for performing a subtraction operation on the input analog signal and the first analog signal to obtain a residual signal; and a first residual amplifier and a second residual amplifier, both used to amplify the residual signal. The output of the first residual amplifier is connected to the digital-to-analog converter of the next-stage pipelined processing unit, and the output of the second residual amplifier is connected to the sub-ADC of the next-stage pipelined processing unit. This disclosure can improve energy efficiency and extend settling time, thereby improving the energy efficiency of the residual amplifier circuit.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and in particular to a pipelined analog-to-digital converter and its control chip, and electronic equipment. Background Technology

[0002] A pipelined analog-to-digital converter (ADC) is a type of ADC suitable for high-speed, high-precision ADC designs, primarily used in applications such as wireless communication and radar. A pipelined ADC consists of multiple pipeline stages, each alternately performing coarse quantization and residual error generation and amplification, before sending the residual error to the next stage for further quantization. The core circuit module of a pipelined ADC is the residual error generation and amplification circuit, typically implemented using switched-capacitor circuits. The speed and accuracy of residual error amplification often determine the overall speed and accuracy of the pipelined ADC. Therefore, how to better achieve residual error amplification is a key indicator for improving the performance of a pipelined ADC.

[0003] In a traditional pipelined ADC architecture, each pipeline stage consists of a coarse quantizer ADC (usually flash, referred to as flash below, but other types of coarse quantizers are also possible), a capacitive digital-to-analog converter (DAC), and a residual amplifier. The residual is amplified by a residual amplifier and then sent to the next stage's capacitive DAC and flash ADC for sampling and coarse quantization.

[0004] This classic structure has two drawbacks:

[0005] First, the capacitor DAC and flash ADC in the later stages are driven by a single amplifier; however, their accuracy requirements are different. For example, analyzing the first stage of a 14-bit pipelined ADC, assuming an inter-stage gain of 4, the capacitor voltage in the second stage needs to be built up to 12 bits of accuracy. The second-stage flash only needs to be built up to 3-4 bits (flash is typically designed to be 3-4 bits), but it is still driven to 12 bits of accuracy, resulting in significant power wastage.

[0006] The second drawback is that coarse quantization in flash memory often produces nonlinear kickback error (due to the parasitic capacitance of transistors, changes in the source-drain voltage of transistors will in turn affect the gate voltage (usually the input port). The quantizer (comparator) can be regarded as a nonlinear amplifier. The nonlinear amplification during the comparison process will cause interference to the input terminal, which is called kickback error).

[0007] The two drawbacks mentioned above will be even more pronounced in high-speed applications. Therefore, there is an urgent need to propose a new analog-to-digital conversion scheme to improve the energy efficiency of residual amplification. Summary of the Invention

[0008] According to one aspect of this disclosure, a pipelined analog-to-digital converter (ADC) is provided, the pipelined ADC comprising: a plurality of cascaded pipelined processing units, each pipelined processing unit comprising a signal processing module, a sub-ADC, a first residual amplifier, and a second residual amplifier, wherein,

[0009] The sub-analog-to-digital converter is used to perform analog-to-digital conversion on the received input analog signal to obtain a first digital signal;

[0010] The signal processing module is used to perform digital-to-analog conversion on the first digital signal to obtain a first analog signal;

[0011] The signal processing module is used to perform a subtraction operation on the input analog signal and the first analog signal to obtain the residual signal;

[0012] Both the first and second residual amplifiers amplify the residual signal. The output of the first residual amplifier is connected to the signal processing module of the next-stage pipeline processing unit, and the output of the second residual amplifier is connected to the sub-analog-to-digital converter of the next-stage pipeline processing unit.

[0013] The first residual amplifier has a larger size than the second residual amplifier, and the bandwidth of the first residual amplifier is greater than the bandwidth of the second residual amplifier.

[0014] In this process, the first digital signal output by the sub-analog-to-digital converter in each pipeline processing unit is used as the analog-to-digital conversion result of the input analog signal.

[0015] In one possible implementation, the bandwidth ratio of the first redundant amplifier to the second redundant amplifier is the ratio of the accuracy of the first redundant amplifier to the accuracy of the second redundant amplifier.

[0016] In one possible implementation, the size ratio of the first redundant amplifier to the second redundant amplifier is the product of the bandwidth ratio of the first redundant amplifier to the second redundant amplifier and the load ratio.

[0017] In one possible implementation, each stage of the pipeline processing unit is configured to perform sampling, quantization, and residual propagation operations based on a target clock signal, wherein the target clock signal is set to a form in which a first phase and a second phase alternate periodically, wherein...

[0018] In the first phase, the Nth stage pipeline processing unit samples the received signal to obtain a sampled signal, quantizes it using the sub-analog-to-digital converter to obtain a quantization result, and obtains a residual signal using the signal processing module, where N is a positive integer;

[0019] In the second phase, the Nth stage pipeline processing unit amplifies the residual signal using the first residual amplifier and the second residual amplifier, and transmits the amplified residual signal to the signal processing module and sub-analog-to-digital converter of the N+1th stage pipeline processing unit, respectively.

[0020] In one possible implementation, in the first sub-phase of the second phase, the Nth stage pipeline processing unit transmits the residual signals amplified by the first residual amplifier and the second residual amplifier to the signal processing module and sub-analog-to-digital converter of the N+1 stage pipeline processing unit, respectively.

[0021] In the second sub-phase of the second phase, the sub-analog-to-digital converter of the (N+1)th stage pipeline processing unit performs analog-to-digital conversion on the amplified residual signal from the second residual amplifier of the Nth stage pipeline processing unit.

[0022] In the second sub-phase of the second phase, the first residual amplifier of the Nth stage pipeline processing unit continues to transmit the amplified residual signal.

[0023] The start time of the first sub-phase is earlier than the start time of the second sub-phase.

[0024] In one possible implementation, an interstage switch is provided between the first residual amplifier and the signal processing module of the next stage pipeline processing unit.

[0025] The inter-stage switch of the Nth stage pipeline processing unit is turned on during the second phase.

[0026] In one possible implementation, the sub-analog-to-digital converter includes a flash memory analog-to-digital converter, and the signal processing module includes a capacitive digital-to-analog converter.

[0027] According to one aspect of this disclosure, a control chip is provided, the control chip including the pipelined analog-to-digital converter described above.

[0028] According to one aspect of this disclosure, an electronic device is provided, the electronic device including the control chip described above.

[0029] In one possible implementation, the electronic device includes any one of a display, smartphone, smartwatch, smart bracelet, tablet, laptop, all-in-one computer, or access control device.

[0030] This embodiment of the disclosure sets the size of the first residual amplifier to be larger than that of the second residual amplifier, and the bandwidth of the first residual amplifier to be larger than that of the second residual amplifier. The residual signal is amplified by the first and second residual amplifiers respectively, and the amplified residual signal is used to drive the next-stage signal processing module and the sub-analog-to-digital converter respectively, thereby improving energy efficiency and extending the settling time, and improving the energy efficiency of the residual amplifier circuit.

[0031] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Other features and aspects of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0032] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the specification, serve to illustrate the technical solutions of this disclosure.

[0033] Figure 1a A schematic diagram of a pipelined analog-to-digital converter according to an embodiment of the present disclosure is shown.

[0034] Figure 1b A schematic diagram of a pipeline processing unit according to an embodiment of the present disclosure is shown.

[0035] Figure 2 A schematic diagram of the operating timing of the pipelined analog-to-digital converter according to an embodiment of the present disclosure is shown.

[0036] Figure 3 The pipelined processing unit 10 in the pipelined analog-to-digital converter according to an embodiment of the present disclosure is shown in the second phase. A schematic diagram of residual transfer. Detailed Implementation

[0037] Various exemplary embodiments, features, and aspects of this disclosure will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0038] In the description of this disclosure, it should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0039] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this disclosure, "a plurality of" means two or more, unless otherwise expressly specified.

[0040] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0041] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0042] In this document, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A alone, A and B simultaneously, and B alone. Furthermore, the term "at least one" in this document means any combination of at least two of any one or more elements. For example, including at least one of A, B, and C can mean including any one or more elements selected from the set consisting of A, B, and C.

[0043] Furthermore, to better illustrate this disclosure, numerous specific details are set forth in the following detailed description. Those skilled in the art will understand that this disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art have not been described in detail in order to highlight the main points of this disclosure.

[0044] Please see Figure 1a, Figure 1a A schematic diagram of a pipelined analog-to-digital converter according to an embodiment of the present disclosure is shown.

[0045] like Figure 1a As shown, the pipelined analog-to-digital converter includes: multiple cascaded pipelined processing units 10, each pipelined processing unit 10 including a signal processing module 110, a sub-analog-to-digital converter 120, a first residual amplifier 140, and a second residual amplifier 150, wherein,

[0046] The sub-analog-to-digital converter 120 is used to perform analog-to-digital conversion on the received input analog signal to obtain a first digital signal;

[0047] The signal processing module 110 is used to perform digital-to-analog conversion on the first digital signal to obtain a first analog signal;

[0048] The signal processing module 110 is used to perform a subtraction operation on the input analog signal and the first analog signal to obtain the residual signal (V). res1 );

[0049] Both the first residual amplifier 140 and the second residual amplifier 150 are used to amplify the residual signal. The output of the first residual amplifier 140 is connected to the signal processing module 110 of the next-stage pipeline processing unit 10, and the output of the second residual amplifier 150 is connected to the sub-analog-to-digital converter 120 of the next-stage pipeline processing unit 10.

[0050] The first residual amplifier 140 is larger in size than the second residual amplifier 150, and the bandwidth of the first residual amplifier 140 is greater than the bandwidth of the second residual amplifier 150.

[0051] Among them, the first digital signal (D) output by the sub-analog-to-digital converter 120 in each pipeline processing unit 10 n ~D1, where n is a positive integer representing the precision of the analog-to-digital converter, is the analog-to-digital conversion result of the input analog signal.

[0052] In the embodiments of this disclosure, the size of the residual amplifier may refer to the size of each transistor forming the residual amplifier.

[0053] This embodiment of the disclosure sets the size of the first residual amplifier 140 to be larger than the size of the second residual amplifier 150, and the bandwidth of the first residual amplifier 140 to be larger than the bandwidth of the second residual amplifier 150. The residual signal is amplified by the first residual amplifier 140 and the second residual amplifier 150 respectively, and the amplified residual signal is used to drive the next-level signal processing module 110 and the sub-analog-to-digital converter 120 respectively, thereby improving the energy efficiency of the residual amplifier circuit.

[0054] The embodiments disclosed herein do not limit the specific number of cascaded pipeline processing units 10. Those skilled in the art can set the number of units according to actual conditions and needs, for example, the number of stages can be configured according to the accuracy of analog-to-digital conversion.

[0055] The present disclosure does not limit the specific implementation of the signal processing module 110, the sub-analog-to-digital converter 120, the first redundant amplifier 140, and the second redundant amplifier 150. Those skilled in the art can implement them using relevant technologies according to actual conditions and needs.

[0056] For example, the sub-analog-to-digital converter 120 may include a coarse quantizer such as a flash analog-to-digital converter. The first residual amplifier 140 and the second residual amplifier 150 can both be implemented based on operational amplifiers, as long as the size of the first residual amplifier 140 is larger than the size of the second residual amplifier 150, and the bandwidth of the first residual amplifier 140 is greater than the bandwidth of the second residual amplifier 150.

[0057] For example, the signal processing module 110 can be implemented using a capacitive digital-to-analog converter (CDAC). Since a capacitive digital-to-analog converter is formed by a capacitor array, it can sample analog voltage signals and calculate the difference between the sampled signal and the first analog signal to obtain the residual signal. Of course, the signal processing module 110 can also be implemented in other ways, which will be described exemplarily below.

[0058] Please see Figure 1b , Figure 1b A schematic diagram of a pipeline processing unit according to an embodiment of the present disclosure is shown.

[0059] For example, such as Figure 1b As shown, the signal processing module 110 can be implemented not only by a capacitive digital-to-analog converter (CDAC), but also by a sampling circuit 1100, a conventional digital-to-analog converter 1110, and a subtractor 1120. The sampling circuit 1100 samples the input signal and transmits it to the subtractor. The digital-to-analog converter 1110 performs digital-to-analog conversion of the first digital signal to obtain a first analog signal, which is then transmitted to the subtractor 1120. The subtractor 1120 performs subtraction on the sampled signal and the first analog signal to obtain the residual signal.

[0060] Of course, the specific implementation of the sampling circuit 1100, the digital-to-analog converter 1110 and the subtractor 1120 in this embodiment is not limited. Those skilled in the art can implement them using relevant technologies according to actual conditions and needs.

[0061] As an example, the signal processing module 110 can sample the input signal (wherein, the input signal of the first-stage pipeline processing unit is an analog signal that needs to be converted from analog to digital, and the input signals of the other pipeline processing units are the residual signals amplified by the first residual amplifier 140 of the previous stage) to obtain a sampled signal; on the other hand, the signal processing module 110 can perform digital-to-analog conversion on the first digital signal output by the sub-analog-to-digital converter 120 to obtain a first analog signal, and can also perform a subtraction operation between the sampled signal and the first analog signal to obtain a residual signal. The embodiments of this disclosure do not limit the specific implementation method and working process of sampling, quantization, and residual generation. Those skilled in the art can refer to relevant technologies to implement them according to actual conditions and needs.

[0062] In one possible implementation, the bandwidth ratio of the first redundant amplifier 140 to the second redundant amplifier 150 can be the ratio of the accuracy of the first redundant amplifier 140 to the accuracy of the second redundant amplifier 150.

[0063] In one possible implementation, the size ratio of the first redundant amplifier 140 to the second redundant amplifier 150 can be the product of the bandwidth ratio of the first redundant amplifier 140 to the second redundant amplifier 150 and the load ratio.

[0064] This embodiment of the disclosure allows the two paths containing the first redundant amplifier 140 and the second redundant amplifier 150 to be established to appropriate accuracy by setting the bandwidth of the first redundant amplifier 140 and the second redundant amplifier 150, thereby maximizing energy efficiency.

[0065] In this embodiment, the first residual amplifier 140 (main amplifier) ​​driving the signal processing module 110 of the next-stage pipeline processing unit has a larger size and higher bandwidth, enabling it to achieve higher accuracy. The second residual amplifier 150 (auxiliary amplifier) ​​driving the sub-analog-to-digital converter 120 has a smaller size and lower bandwidth, requiring only that the sub-analog-to-digital converter 120 be driven to the minimum required accuracy.

[0066] Of course, the accuracy of the first residual amplifier 140 and the second residual amplifier 150 can be adapted to the actual situation and needs. This embodiment does not limit this. For example, the accuracy of the first residual amplifier 140 and the second residual amplifier 150 can be configured according to the accuracy of the analog-to-digital converter.

[0067] For example, for a 14-bit precision pipelined ADC, assuming each stage has a quantization precision of 3 bits and an interstage gain of 4, the main amplifier (the first residual amplifier 140) needs to be built up to 12 bits of precision, while the auxiliary amplifier (the second residual amplifier 150) only needs to be built up to 3 bits of precision. Therefore, the bandwidth of the auxiliary amplifier only needs to be set to 1 / 4 of that of the main amplifier (bandwidth ratio = precision ratio).

[0068] For example, assuming that the capacitive load of the two paths (the paths where the first redundant amplifier 140 and the second redundant amplifier 150 are located) is 1 / 2 of the main path, then the size of the auxiliary amplifier only needs to be 1 / 8 of the first redundant amplifier 140 (size ratio = bandwidth ratio * load ratio). Of course, the specific load size is set according to the actual situation and needs, and this disclosure does not limit it.

[0069] For example, in a conventional method using a single amplifier, the output of the error amplifier is directly connected to the digital-to-analog converter (DAC) and sub-DAC of the next-stage pipeline processing unit. In this conventional method, both paths (the two paths from the error amplifier to the DAC and sub-DAC) are established to 12-bit precision, which is equivalent to the auxiliary amplifier being half the size of the main amplifier (with consistent bandwidth, the size ratio being the load ratio). However, by adopting the technical solution of the embodiments of this disclosure, the size of the auxiliary amplifier can be significantly reduced. For example, in one example, the total size can be reduced from 1.5 to 1.125, thereby significantly improving energy efficiency.

[0070] It is worth mentioning that in the pipelined analog-to-digital converter of this embodiment, the mismatch between the two amplifiers of the current stage pipeline processing unit 10 can be digested by the inter-stage redundancy of the subsequent pipeline processing unit 10, and will not affect the performance of the pipelined ADC.

[0071] Furthermore, due to the use of dual-path amplification, the kickback error of the sub-analog-to-digital converter 120 is isolated from the capacitor input, so it does not affect the sampling accuracy. Therefore, the sampling time of the capacitor DAC path in the N+1th pipeline processing unit 10 (from the first residual amplifier 140 of the Nth stage to the signal processing module 110 of the N+1th stage) can be delayed until after the FlashADC path (from the second residual amplifier 150 of the Nth stage to the sub-analog-to-digital converter 120 of the N+1th stage) is activated, which further extends the settling time and improves the settling accuracy.

[0072] The mismatch between the two amplifiers causes the signal seen by the coarse quantizer (sub-analog-to-digital converter 120) in the subsequent pipeline processing unit 10 to be inconsistent with the signal sampled by the sampling capacitor in the signal processing module 110. This difference results in the signal not being quantized correctly, leading to a larger actual conversion steady-state error range than the ideal steady-state error range. Typically, the steady-state error range generated by the pipeline processing unit 10 is larger than the ideal steady-state error range (usually 2 or 4 times larger, corresponding to 1 or 2 bits of redundancy). Therefore, as long as the increase in the steady-state error range caused by the mismatch does not exceed the redundancy range, it will not affect subsequent conversions.

[0073] The following is an exemplary description of how the pipelined analog-to-digital converter works.

[0074] Please see Figure 2 , Figure 2 A schematic diagram of the operating timing of the pipelined analog-to-digital converter according to an embodiment of the present disclosure is shown.

[0075] For example, such as Figure 2 As shown, the target clock signal is set to the first phase. Second phase The form is a periodic alternation, in which different phases can correspond to different control signals to control the operation of corresponding components. For example, in the first phase... The first control signal is high and the second control signal is low. The first control signal controls the corresponding components to perform sampling and quantization operations; in the second phase... The second control signal is high and the first control signal is low. The second control signal controls the corresponding components to perform residual amplification and residual propagation operations. Of course, it can also sample and quantize the received signal at the same time.

[0076] In one possible implementation, each stage of the pipeline processing unit 10 is configured to perform sampling, quantization, and residual propagation operations based on a target clock signal.

[0077] For example, such as Figure 1a and Figure 2 As shown, in the first phase The Nth-stage pipeline processing unit 10 samples the received signal to obtain a sampled signal (e.g., the sampling capacitor in the digital-to-analog converter 1110), quantizes it using the sub-analog-to-digital converter 120 to obtain a quantization result, and uses the signal processing module to obtain the residual signal (V). res1 ), where N is a positive integer;

[0078] In the second phase, the Nth stage pipeline processing unit 10 amplifies the residual signal using the first residual amplifier 140 and the second residual amplifier 150, and transmits the amplified residual signal to the signal processing module 110 and the sub-analog-to-digital converter 120 of the N+1th stage pipeline processing unit 10, respectively.

[0079] Figure 2 Taking N=1 as an example, the first-stage pipeline processing unit and the second-stage pipeline processing unit are introduced, such as... Figure 2 As shown, in the first phase The signal processing module 110 of the first-stage pipeline processing unit samples the received signal to obtain a sampled signal, quantizes it using the sub-analog-to-digital converter 120 to obtain a quantization result, and obtains the residual signal (V) using the signal processing module 110. res1 ), in the second phase The first-stage pipeline processing unit amplifies the residual signal using the first residual amplifier 140 and the second residual amplifier 150, and transmits the amplified residual signal to the signal processing module 110 and the sub-analog-to-digital converter 120 of the second-stage pipeline processing unit, respectively. At this time (in the second phase) The signal processing module 110 of the second-stage pipeline processing unit 10 samples the residual signal received from the first-stage pipeline processing unit 10 to obtain a sampled signal, performs quantization using the sub-analog-to-digital converter 120 to obtain a quantization result, and obtains the residual signal of the second-stage pipeline processing unit 10 using the signal processing module 110.

[0080] This disclosure describes the first phase. Second phase The specific duration is not limited; for example, the first phase... Second phase The durations can be equal.

[0081] This disclosure does not limit the generation method of control signals such as the target clock signal, the first control signal, and the second control signal. For example, a pipelined analog-to-digital converter (ADC) may include a control module that generates the corresponding target clock signal and controls the various components of the pipelined ADC to operate at the corresponding phase. For example, the control module may include a processing component. In one example, the processing component includes, but is not limited to, a separate processor, discrete components, or a combination of a processor and discrete components. The processor may include a controller in an electronic device with instruction execution capabilities. The processor can be implemented in any suitable manner, for example, by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components. Within the processor, the executable instructions can be executed by hardware circuits such as logic gates, switches, application-specific integrated circuits (ASICs), programmable logic controllers, and embedded microcontrollers.

[0082] This disclosure embodiment can be in the second phase The amplified residual signals generated by the first residual amplifier 140 and the second residual amplifier 150 are transmitted in different sub-phases to isolate the sampling and amplification operations of the next-stage pipeline processing unit 10, avoid interference of quantization operations on sampling operations, and improve signal establishment accuracy.

[0083] Please see Figure 3 , Figure 3 The pipelined processing unit 10 in the pipelined analog-to-digital converter according to an embodiment of the present disclosure is shown in the second phase. A schematic diagram of residual transfer.

[0084] In one possible implementation, such as Figure 2 and Figure 3 As shown, in the second phase First sub-phase The Nth stage pipeline processing unit 10 transmits the amplified residual signals from the first residual amplifier 140 and the second residual amplifier 150 to the signal processing module 110 and the sub-analog-to-digital converter 120 of the N+1th stage pipeline processing unit 10, respectively.

[0085] In the second phase The second subphase The sub-analog-to-digital converter 120 of the N+1 stage pipeline processing unit 10 performs analog-to-digital conversion on the amplified residual signal from the second residual amplifier 150 of the Nth stage pipeline processing unit.

[0086] In the second phase The second subphase The first residual amplifier 140 of the Nth stage pipeline processing unit continues to transmit the amplified residual signal.

[0087] Among them, the first sub-phase The start time is earlier than the second sub-phase The start time.

[0088] This disclosure embodiment relates to the first sub-phase Second sub-phase The end time is not limited, as long as it is the second phase. The end time can be limited, for example, the second sub-phase. The end time can be the second phase The end time of the first sub-phase The end time can be in the second sub-phase start time, second sub-phase Between the end times. That is, embodiments of this disclosure can adjust the first sub-phase as needed. The effective duration is controlled to improve sampling accuracy; that is, the embodiments of this disclosure have the flexibility to adjust the extension time, such as... Figure 3 As shown, by setting the first sub-phase The end time can be in the second sub-phase start time, second sub-phase Between the end times, embodiments of this disclosure are able to convert the voltage (V) of the two paths. in,c V in,f The error is controlled within the tolerable range and has high precision.

[0089] As an example, the first sub-phase The end time can be the second sub-phase The start time to the second phase At any time between the end times (including the boundary), the second sub-phase The end time can be the second phase The end time.

[0090] For example, as previously described, in the first phase In the Nth stage pipeline processing unit 10, the signal is sampled and quantized, and then in the second phase... The stage amplifies the residual and passes it to the (N+1)th stage pipeline processing unit 10. The (N+1)th stage pipeline processing unit 10 also needs to be processed in the second phase. Within the time period, two operations are completed: sampling and quantization of the residual signal of the Nth stage pipeline processing unit 10. For example, Figure 3 As shown, the first sub-phase This indicates that the N+1th stage pipeline processing unit 10 is in the second phase. The residual signal of the Nth stage pipeline processing unit 10 is sampled (sampling capacitor C in signal processing module 110). S The phase period of the second sub-phase. This indicates that the N+1th stage pipeline processing unit 10 is in the second phase. The phase period during which the residual signal of the Nth stage pipeline processing unit 10 is quantized. Then, in the next first phase... The stage transmits the residual signal of the N+1th stage pipeline processing unit 10 to the N+2th stage pipeline processing unit 10.

[0091] In traditional methods, since the next-stage signal processing module 110 and the sub-analog-to-digital converter 120 are driven by a single error amplifier, the two paths are connected. To avoid interference from quantization on sampling, related techniques require ending sampling before quantization. However, the dual-path amplification structure proposed in this embodiment isolates the two operations, allowing sampling to be performed later. A longer sampling time results in higher signal establishment accuracy. Therefore, this embodiment can further improve establishment accuracy.

[0092] In one possible implementation, an interstage switch is provided between the first residual amplifier 140 and the signal processing module 110 of the next stage pipeline processing unit 10.

[0093] Specifically, the interstage switch of the Nth stage pipeline processing unit 10 is turned on during the second phase. Thus, in the second sub-phase of the second phase, when the sub-analog-to-digital converter of the N+1th stage pipeline processing unit performs analog-to-digital conversion on the amplified residual signal from the second residual amplifier of the Nth stage pipeline processing unit, the first residual amplifier of the Nth stage pipeline processing unit can continue to transmit the amplified residual signal, free from interference from the sub-analog-to-digital converter, thereby allowing for a longer transmission time.

[0094] This disclosure does not limit the specific type of interstage switch. Those skilled in the art can select appropriate devices as needed. For example, the interstage switch may include any one of the following: relay, reed switch, thyristor, switching diode, switching transistor, electronic bidirectional switch, optocoupler, transistor, etc. The transistor may be a metal-oxide-semiconductor field-effect transistor (MOSFET) or an insulated gate bipolar transistor (IGBT). The transistor may be based on silicon carbide (SiC) or gallium nitride (GaN) to improve performance.

[0095] The pipelined analog-to-digital converter of the present disclosure has two main advantages:

[0096] 1. Improved the energy efficiency of the residual amplifier circuit.

[0097] 2. The problem of kickback error in the sub-quantizer and the main signal path has been solved, thereby further extending the settling time and improving the settling accuracy.

[0098] According to one aspect of this disclosure, a control chip is provided, the control chip including the pipelined analog-to-digital converter described above.

[0099] According to one aspect of this disclosure, an electronic device is provided, the electronic device including the control chip described above.

[0100] In one possible implementation, the electronic device includes any one of a display, smartphone, smartwatch, smart bracelet, tablet, laptop, all-in-one computer, or access control device.

[0101] Of course, electronic devices can also be terminal devices. Terminal devices can be user equipment (UE), mobile devices, user terminals, terminals, handheld devices, computing devices, or in-vehicle devices, etc. Examples of terminals include: mobile phones, tablets, laptops, PDAs, mobile internet devices (MID), wearable devices, virtual reality (VR) devices, augmented reality (AR) devices, wireless terminals in industrial control, wireless terminals in self-driving, wireless terminals in remote medical surgery, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, wireless terminals in smart homes, and wireless terminals in vehicle-to-everything (V2X) networks. For example, a server can be a local server or a cloud server.

[0102] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or improvement of the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A pipelined analog-to-digital converter, characterized by The pipeline analog-to-digital converter comprises a plurality of cascaded pipeline processing units, each pipeline processing unit comprising a signal processing module, a sub-analog-to-digital converter, a first residual error amplifier, and a second residual error amplifier, wherein The sub-analog-to-digital converter is configured to perform analog-to-digital conversion on a received input analog signal to obtain a first digital signal. The signal processing module is configured to perform digital-to-analog conversion on the first digital signal to obtain a first analog signal. The signal processing module is further configured to perform subtraction operation on the input analog signal and the first analog signal to obtain a residual error signal. The first residual error amplifier and the second residual error amplifier are both configured to amplify the residual error signal, and the output end of the first residual error amplifier is connected to the signal processing module of the next-stage pipeline processing unit, and the output end of the second residual error amplifier is connected to the sub-analog-to-digital converter of the next-stage pipeline processing unit. The size of the first residual error amplifier is greater than the size of the second residual error amplifier, and the bandwidth of the first residual error amplifier is greater than the bandwidth of the second residual error amplifier. The first digital signal output by the sub-analog-to-digital converter in each pipeline processing unit is taken as the analog-to-digital conversion result of the input analog signal.

2. The pipelined analog-to-digital converter of claim 1, wherein, The ratio of the bandwidths of the first residual error amplifier and the second residual error amplifier is equal to the ratio of the precisions of the first residual error amplifier and the second residual error amplifier.

3. The pipelined analog-to-digital converter of claim 1 or 2, wherein, The ratio of the sizes of the first residual error amplifier and the second residual error amplifier is equal to the product of the ratio of the bandwidths and the ratio of the loads of the first residual error amplifier and the second residual error amplifier.

4. The pipelined analog-to-digital converter of claim 1, wherein, Each pipeline processing unit is configured to perform sampling, quantization, and residual error transfer based on a target clock signal, which is set to periodically alternate between a first phase and a second phase. In the first phase, the Nth pipeline processing unit samples a received signal to obtain a sampling signal, quantizes the sampling signal using the sub-analog-to-digital converter to obtain a quantization result, and obtains a residual error signal using the signal processing module, where N is a positive integer. In the second phase, the Nth pipeline processing unit amplifies the residual error signal using the first residual error amplifier and the second residual error amplifier, and transfers the amplified residual error signal to the signal processing module and the sub-analog-to-digital converter of the (N+1)th pipeline processing unit, respectively.

5. The pipeline analog-to-digital converter of claim 4, wherein In a first sub-phase of the second phase, the Nth pipeline processing unit transfers the amplified residual error signal of the first residual error amplifier and the second residual error amplifier to the signal processing module and the sub-analog-to-digital converter of the (N+1)th pipeline processing unit, respectively. In a second sub-phase of the second phase, the sub-analog-to-digital converter of the (N+1)th pipeline processing unit performs analog-to-digital conversion on the amplified residual error signal transmitted by the second residual error amplifier of the Nth pipeline processing unit. In the second sub-phase of the second phase, the first residual error amplifier of the Nth pipeline processing unit continues to transfer the amplified residual error signal. The start time of the first sub-phase is earlier than the start time of the second sub-phase.

6. The pipelined analog-to-digital converter of claim 5, wherein, An inter-stage switch is arranged between the first residual error amplifier and a signal processing module of a next stage pipeline processing unit, The inter-stage switch of the Nth stage pipeline processing unit is turned on during the second phase.

7. The pipelined analog-to-digital converter of claim 1, wherein, The sub-analog-to-digital converter comprises a flash analog-to-digital converter, and the signal processing module comprises a capacitive digital-to-analog converter.

8. A control chip, characterized by The control chip comprises the pipeline analog-to-digital converter according to any one of claims 1-7.

9. An electronic device, comprising: The electronic device comprises the control chip according to claim 8.

10. The electronic device of claim 9, wherein, The electronic device comprises any one of a display, a smart phone, a smart watch, a smart bracelet, a tablet computer, a notebook computer, an all-in-one computer, and an access control device.

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