Receiver front-end circuit

Abstract

The present disclosure provides a receiver front-end circuit including: first and second input units that alternately operate according to a common mode voltage of a differential input signal and output a differential output signal; a variable resistance unit that adjusts a differential load resistance supplied to the differential output signal according to the variable resistance control signal; and a control unit generating a variable resistance control signal according to a common mode voltage of the differential input signal. According to the receiver front-end circuit disclosed by the invention, the receiving of the differential input signal with a wider common-mode voltage range can be realized under low power supply voltage, and the output amplitude of the generated differential output signal does not change greatly along with the change of the common-mode voltage of the differential input signal; therefore, the compatibility of the receiver is improved, and the power consumption is reduced.

Description

Technical Field

[0001] The present disclosure relates to the technical field of electronic circuits, and in particular, to a receiver front-end circuit. Background Art

[0002] With the continuous development of semiconductor technology, integrated circuits are developing towards low power consumption, high compatibility and high integration. In order to be compatible with differential input signals of various common mode voltage ranges, receivers for wired data communication usually include rail-to-rail front-end circuits. The receiver front-end circuit may include two parallel differential input stages for respectively receiving differential input signals with common mode voltages of different intervals.

[0003] However, the existing receiver front-end circuit has at least two defects. First, when the power supply voltage of the receiver front-end circuit is less than the common-mode voltage of the differential input signal, the receiver front-end circuit usually cannot work properly. Furthermore, when the common-mode voltage of the differential input signal changes greatly, the amplitude of the differential output signal of the receiver front-end circuit will also change greatly, so it is necessary to incorporate a variable gain amplifier to adjust the amplitude of the output of the receiver front-end circuit, resulting in an increase in chip power consumption and area.

[0004] In order to solve the above problems, a receiver front-end circuit is needed that at least overcomes the above defects, that is, the receiver front-end circuit can operate under a low power supply voltage and support a wide input common-mode voltage range, that is, the amplitude of the output voltage does not change significantly with the change of the common-mode voltage of the input signal.

[0005] The above information disclosed in this Background section is only for understanding the background of the present disclosure concept and therefore it may contain information that does not constitute prior art. Summary of the invention

[0006] In order to solve the above problems existing in the prior art, the present disclosure proposes a novel receiver front-end circuit.

[0007] According to one aspect of the present disclosure, a receiver front-end circuit is provided, comprising: a first input unit and a second input unit, which operate alternately according to the common-mode voltage of a differential input signal and output a differential output signal; a variable resistance unit, which adjusts the differential load resistance provided to the differential output signal according to a variable resistance control signal; and a control unit, which generates a variable resistance control signal according to the common-mode voltage of the differential input signal.

[0008] The receiver front-end circuit according to the present disclosure uses two input units connected in parallel and working alternately and a variable resistance unit capable of adjusting the differential load resistance according to the common-mode voltage of the differential input signal. It is capable of receiving a differential input signal with a wider common-mode voltage range at a low power supply voltage, and the output amplitude of the generated differential output signal does not change significantly with the change of the common-mode voltage of the differential input signal, thereby improving the compatibility of the receiver and reducing power consumption.

[0009] However, the effects of the present disclosure are not limited to the above effects, and various extensions can be made without departing from the spirit and scope of the present disclosure. It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory, and are intended to provide further explanation of the present disclosure claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the disclosure and together with the description serve to explain the concepts of the disclosure.

[0011] Figure 1 is a schematic block diagram showing a receiver front-end circuit according to an embodiment of the present disclosure.

[0012] Figure 2 is a schematic circuit diagram illustrating a first input unit according to an embodiment of the present disclosure.

[0013] Figure 3 is a schematic circuit diagram illustrating a second input unit according to an embodiment of the present disclosure.

[0014] Figure 4 is a schematic circuit diagram illustrating a variable resistance unit according to an embodiment of the present disclosure.

[0015] Figure 5 is a schematic circuit diagram showing a control unit according to an embodiment of the present disclosure.

[0016] Figure 6 is a schematic circuit diagram showing a receiver front end circuit according to an embodiment of the present disclosure.

[0017] Figure 7 is a schematic circuit diagram showing a receiver front end circuit according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0018] In the following description, for the purpose of illustration, many specific details are set forth in order to provide a thorough understanding of each exemplary embodiment of the present disclosure. As used herein, an "embodiment" is a non-limiting example of a device or method using one or more inventive concepts disclosed herein. However, it is apparent that each exemplary embodiment can be implemented without these specific details or with one or more equivalent configurations. In addition, each exemplary embodiment can be different, but does not have to be exclusive. For example, without departing from the concept of the present disclosure, specific features of other exemplary embodiments can be used or implemented in some exemplary embodiments.

[0019] Unless otherwise specified, the exemplary embodiments described should be understood as providing exemplary features of varying details of some ways in which the disclosed concept can be implemented in practice. Therefore, unless otherwise specified, the features, components, units, regions and / or aspects of each embodiment (hereinafter individually or collectively referred to as "elements") can be combined, separated, interchanged and / or reconfigured without departing from the disclosed concept.

[0020] For the purpose of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0021] Although the terms "first", "second", etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Therefore, without departing from the teachings of the present disclosure, the first element discussed below may be referred to as the second element.

[0022] The terms used herein are for the purpose of describing specific embodiments and are not intended to be restrictive. As used herein, the singular forms "a", "an" and "the" are intended to also include the plural forms, unless the context clearly indicates otherwise. In addition, when used in this specification, the terms "include" and / or "comprise" mean the presence of stated features, steps, operations, elements, parts and / or their groups, but do not exclude the presence or addition of one or more other features, steps, operations, elements, parts and / or their groups.

[0023] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and should not be interpreted in an idealized or overly formal sense, unless explicitly defined herein.

[0024] The various embodiments of the present disclosure will now be described more fully below with reference to the accompanying drawings. However, the present disclosure can be implemented in many different ways and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be exhaustive and complete, and will fully convey the scope of the present disclosure to those skilled in the art. The same reference numerals throughout the text represent the same components.

[0025] Embodiments of the present disclosure will be described below with reference to the accompanying drawings.

[0026] Figure 1 1 is a schematic block diagram showing a receiver front-end circuit 10 according to an embodiment of the present disclosure. Figure 1 As shown, according to an embodiment of the present disclosure, the receiver front-end circuit 10 may include a first input unit 201 , a second input unit 202 , a variable resistance unit 300 , and a control unit 400 .

[0027] like Figure 1 As shown, according to an embodiment of the present disclosure, the receiver front-end circuit 10 can be used to receive differential input signals 11, 12, which include a positive input signal 11 and a negative input signal 12, and generate differential output signals 31, 32, which include a positive output signal 31 and a negative output signal 32, and transmit the differential output signals 31, 32 to other circuits of the receiver.

[0028] like Figure 1 As shown, according to an embodiment of the present disclosure, the input terminals of the first input unit 201 and the second input unit 202 connected in parallel receive differential input signals 11 and 12 and output differential output signals 31 and 32 from the output terminals. Figure 1 As shown, according to an embodiment of the present disclosure, the differential input signals 11 and 12 are also input to the control unit 400. In addition, the output terminals of the first input unit 201 and the second input unit 202 connected in parallel are also connected to the input terminal of the variable resistance unit 300. According to an embodiment of the present disclosure, the variable resistance unit 300 can provide an adjustable differential load resistance for the differential output signals 31 and 32. Figure 1 As shown, according to an embodiment of the present disclosure, the control unit 400 may output a variable resistance control signal 41 to the variable resistance unit 300 for adjusting the resistance value of the differential load resistance.

[0029] The circuit implementation scheme of the first input unit 201, the second input unit 202, the variable resistance unit 300 and the control unit 400 is described below in conjunction with specific implementations.

[0030] Figure 2 is a schematic circuit diagram showing a first input unit 201 according to an embodiment of the present disclosure. Figure 2 As shown, the first input unit 201 may include a first input transistor M21 and a second input transistor M22 as a differential input pair and a current source IA. Figure 2 As shown, according to an embodiment of the present disclosure, the first input transistor M21 and the second input transistor M22 may both be P-type MOS (metal oxide semiconductor) transistors.

[0031] like Figure 2 As shown, according to an embodiment of the present disclosure, one end of the current source IA can be connected to the power supply voltage VDD, and the other end can be connected to the source of the first input transistor M21 and the source of the second input transistor M22, thereby generating a bias current from the power supply IA to the first input transistor M21 and the second input transistor M22.

[0032] like Figure 2 As shown, according to an embodiment of the present disclosure, the gate of the first input transistor M21 can receive a positive input signal 11, and the drain can output a negative output signal 32. Similarly, Figure 2 As shown, according to an embodiment of the present disclosure, the gate of the second input transistor M22 can receive a negative input signal 12 , and the drain can output a positive output signal 31 .

[0033] According to an embodiment of the present disclosure, the power supply voltage VDD of the receiver front-end circuit 10 may be lower than the highest common-mode voltage of the differential input signals 11 and 12. For example, the power supply voltage may be 1.8 V, and the common-mode voltage range of the differential input signals 11 and 12 may be 0-2.4 V. In other words, the power supply voltage 1.8 V is lower than the highest common-mode voltage 2.4 V of the differential input signals 11 and 12.

[0034] Therefore, when the common-mode voltage of the differential input signals 11 and 12 is low, the first input transistor M21 and the second input transistor M22 are turned on, so that the first input unit 201 is in an operating state, that is, the first input transistor M21 and the second input transistor M22 perform common-source amplification on the differential input signals 11 and 12, thereby outputting differential output signals 31 and 32 at the drains of the first input transistor M21 and the second input transistor M22. On the contrary, when the common-mode voltage of the differential input signals 11 and 12 is high, the first input transistor M21 and the second input transistor M22 are turned off, so that the first input unit 201 does not operate on the differential input signals 11 and 12.

[0035] According to an embodiment of the present disclosure, the first threshold voltage VTP may be pre-set for the common mode voltage of the differential input signals 11 and 12. According to an embodiment of the present disclosure, the first input transistor M21 and the second input transistor M22 of the first input unit 201 may be formed by the same P-type MOS transistor and have the same threshold voltage. According to an embodiment of the present disclosure, the threshold voltage of the first input transistor M21 and the second input transistor M22 may be set to the first threshold voltage VTP.

[0036] According to an embodiment of the present disclosure, when the common-mode voltage of the differential input signals 11 and 12 is less than the first threshold voltage VTP, the first input transistor M21 and the second input transistor M22 of the first input unit 201 can perform common-source amplification on the differential input signals 11 and 12 and output differential output signals 31 and 32; and when the common-mode voltage of the differential input signals 11 and 12 is greater than or equal to the first threshold voltage VTP, the first input unit 201 does not operate on the differential input signals 11 and 12.

[0037] Figure 3 is a schematic circuit diagram showing the second input unit 202 according to an embodiment of the present disclosure. Figure 3 As shown, according to an embodiment of the present disclosure, the second input unit 202 may include a third input transistor M23 and a fourth input transistor M24. Figure 3 As shown, according to an embodiment of the present disclosure, the third input transistor M23 and the fourth input transistor M24 may both be N-type MOS transistors.

[0038] like Figure 3 As shown, according to an embodiment of the present disclosure, the gate of the third input transistor M23 can receive a positive input signal 11, the drain can be connected to the power supply voltage VDD, and the source can output a positive output signal 31. Similarly, Figure 3As shown, according to an embodiment of the present disclosure, the gate of the fourth input transistor M24 can receive a negative input signal 12 , the drain can be connected to the power supply voltage VDD, and the source outputs a negative output signal 32 .

[0039] Therefore, when the common mode voltage of the differential input signals 11 and 12 is high, the third input transistor M23 and the fourth input transistor M24 are turned on, so that the second input unit 202 is in an operating state, that is, the third input transistor M23 and the fourth input transistor M24 perform source follower amplification on the differential input signals 11 and 12, thereby outputting differential output signals 31 and 32 at the sources of the third input transistor M23 and the fourth input transistor M24. On the contrary, when the common mode voltage of the differential input signals 11 and 12 is low, the third input transistor M23 and the fourth input transistor M24 are turned off, so that the second input unit 202 does not operate on the differential input signals 11 and 12.

[0040] According to an embodiment of the present disclosure, the second threshold voltage VTN may be preset for the common mode voltage of the differential input signals 11 and 12. According to an embodiment of the present disclosure, the second threshold voltage VTN may be preset for the common mode voltage of the differential input signals 11 and 12. According to an embodiment of the present disclosure, the third input transistor M23 and the fourth input transistor M24 of the second input unit 202 may be formed by the same N-type MOS transistor and have the same threshold voltage. According to an embodiment of the present disclosure, the threshold voltage of the third input transistor M23 and the fourth input transistor M24 may be set to the second threshold voltage VTN.

[0041] According to an embodiment of the present disclosure, when the common-mode voltage of the differential input signals 11 and 12 is greater than the second threshold voltage VTN, the third input transistor M23 and the fourth input transistor M24 of the second input unit 202 can perform source-follower amplification on the differential input signals 11 and 12 and output differential output signals 31 and 32; and when the common-mode voltage of the differential input signals 11 and 12 is less than or equal to the second threshold voltage VTN, the second input unit 202 does not operate on the differential input signals 11 and 12.

[0042] Reference Figure 2 and Figure 3 According to an embodiment of the present disclosure, by adjusting parameters, such as sizes, of the first input transistor M21, the second input transistor M22, the third input transistor M23, and the fourth input transistor M24, the first threshold voltage VTP can be made equal to the second threshold voltage VTN, which is marked as the threshold voltage VT.

[0043] Therefore, refer to Figure 2 and Figure 3According to the embodiment of the present disclosure, when the common-mode voltage of the differential input signals 11 and 12 is less than the threshold voltage VT, the first input transistor M21 and the second input transistor M22 are turned on, and the third input transistor M23 and the fourth input transistor M24 are turned off, so that the first input unit 201 works and the second input unit 202 does not work, that is, the first input transistor M21 and the second input transistor M22 perform common-source amplification on the differential input signals 11 and 12, thereby outputting differential output signals 31 and 32 at the drains of the first input transistor M21 and the second input transistor M22. In addition, since the common-mode voltage of the differential input signals 11 and 12 is relatively low, according to the principle of common-source amplification, the common-mode voltage of the differential output signals 31 and 32 is also relatively low.

[0044] Accordingly, refer to Figure 2 and Figure 3 According to the embodiment of the present disclosure, when the common mode voltage of the differential input signals 11 and 12 is greater than or equal to the threshold voltage VT, the first input transistor M21 and the second input transistor M22 are turned off, and the third input transistor M23 and the fourth input transistor M24 are turned on, so that the first input unit 201 does not work and the second input unit 202 works, that is, the third input transistor M23 and the fourth input transistor M24 perform source follower amplification on the differential input signals 11 and 12, thereby outputting differential output signals 31 and 32 at the sources of the third input transistor M23 and the fourth input transistor M24. In addition, since the common mode voltage of the differential input signals 11 and 12 is relatively high, according to the principle of source follower amplification, the common mode voltage of the differential output signals 31 and 32 is relatively low.

[0045] Therefore, according to the embodiment of the present disclosure, by setting the first threshold voltage VTP equal to the second threshold voltage VTN, the first input transistor M21 and the second input transistor M22 can be alternately turned on and off relative to the third input transistor M23 and the fourth input transistor M24. That is, at any time, only one of the first input unit 201 and the second input unit 202 amplifies the differential input signals 11 and 12, and outputs the differential output signals 31 and 32 accordingly, and the common mode voltages of the differential output signals 31 and 32 are similar.

[0046] Figure 4 is a schematic circuit diagram showing a variable resistance unit 300 according to an embodiment of the present disclosure. Figure 4 As shown, according to an embodiment of the present disclosure, the variable resistance unit 300 may include a first load resistor R31, a second load resistor R32, a third load resistor R33, a fourth load resistor R34 and a load switch transistor M31.

[0047] like Figure 4As shown, according to an embodiment of the present disclosure, the first load resistor R31 and the third load resistor R33 can be connected in series between the positive output signal 31 and the ground voltage GND, and the second load resistor R32 and the fourth load resistor R34 can be connected in series between the negative output signal 32 and the ground voltage GND. According to an embodiment of the present disclosure, in order to ensure the symmetry of the differential circuit, the resistance value of the first load resistor R31 and the resistance value of the second load resistor R32 can be the same, that is, R31=R32, and the resistance value of the third load resistor R33 and the resistance value of the fourth load resistor R34 can be the same, that is, R33=R34.

[0048] like Figure 4 As shown, according to an embodiment of the present disclosure, the source of the load switch transistor M31 is connected to a node between the first load resistor R31 and the third load resistor R33, the drain is connected to a node between the second load resistor R32 and the fourth load resistor R34, and the gate receives a variable resistance control signal 41.

[0049] like Figure 4 As shown, according to an embodiment of the present disclosure, the load switch transistor M31 may be an N-type MOS transistor. Therefore, according to an embodiment of the present disclosure, when the variable resistance control signal 41 is at a low level, the load switch transistor M31 is turned off, the first load resistor R31 and the third load resistor R33 are connected in series, and the second load resistor R32 and the fourth load resistor R34 are connected in series, so that the differential load resistances of the differential output signals 31 and 32 are R31+R33 and R32+R34, respectively.

[0050] In addition, according to an embodiment of the present disclosure, when the variable resistance control signal 41 is at a high level, the load switch transistor M31 is turned on, and the third load resistor R33 and the fourth load resistor R34 are connected in parallel, so that the third load resistor R33 and the fourth load resistor R34 no longer have an effect on the differential output, so that the differential load resistances of the differential output signals 31 and 32 are R31 and R32, respectively.

[0051] It can be seen that according to the embodiment of the present disclosure, when the variable resistance control signal 41 is at a low level, the differential load resistance provided by the variable resistance unit 300 is large, and when the variable resistance control signal 41 is at a high level, the differential load resistance provided by the variable resistance unit 300 is small. That is, according to the embodiment of the present disclosure, the variable resistance unit 300 can adjust the differential load resistance provided to the differential output signals 31 and 32 according to the variable resistance control signal 41.

[0052] Figure 5 is a schematic circuit diagram showing a control unit 400 according to an embodiment of the present disclosure. Figure 5 As shown, according to an embodiment of the present disclosure, the control unit 400 may include a first terminal resistor R41 , a second terminal resistor R42 , and an inverter 401 .

[0053] like Figure 5 As shown, according to an embodiment of the present disclosure, the first terminal resistor R41 and the second terminal resistor R42 can be connected in series between the positive input signal 11 and the negative input signal 12. According to an embodiment of the present disclosure, the resistance values ​​of the first terminal resistor R41 and the second terminal resistor R42 can be the same, that is, R41 = R42. Therefore, according to an embodiment of the present disclosure, the voltage at the node between the first terminal resistor R41 and the second terminal resistor R42 can be the common mode voltage of the differential input signals 11 and 12.

[0054] like Figure 5 As shown, according to an embodiment of the present disclosure, the input end of the inverter 401 can be connected to the node between the first terminal resistor R41 and the second terminal resistor R42, that is, the inverter 401 can receive the common mode voltage of the differential input signals 11 and 12. In addition, according to an embodiment of the present disclosure, the inverter 401 can output the variable resistance control signal 41.

[0055] Specifically, according to an embodiment of the present disclosure, when the common mode voltage of the differential input signals 11 and 12 is low, for example, less than the common mode voltage of the differential input signals 11 and 12, Figure 2 and Figure 3 When the threshold voltage VT is described, the inverter 401 receives the common mode voltage with a low level and thus outputs the variable resistance control signal 41 with a high level. Accordingly, according to an embodiment of the present disclosure, when the common mode voltage of the differential input signals 11, 12 is high, for example, greater than the threshold voltage VT, the inverter 401 receives the common mode voltage with a high level and thus outputs the variable resistance control signal 41 with a low level.

[0056] Figure 6 is a schematic circuit diagram showing a receiver front end circuit 10 according to an embodiment of the present disclosure.

[0057] Reference Figure 6 According to an embodiment of the present disclosure, when the common-mode voltage of the differential input signals 11 and 12 is less than the threshold voltage VT, the first input transistor M21 and the second input transistor M22 in the first input unit 201 are turned on, and the third input transistor M23 and the fourth input transistor M24 in the second input unit 202 are turned off, and a common-source differential amplifier consisting of the first input transistor M21 and the second input transistor M22 is formed in the receiver front-end circuit 10, and the differential input signals 11 and 12 are common-source amplified, and differential output signals 31 and 32 are output.

[0058] According to an embodiment of the present disclosure, when the common mode voltage of the differential input signals 11 and 12 is less than the threshold voltage VT, the differential gain is determined by the transconductance of the common source amplifier composed of the first input transistor M21 and the second input transistor M22 and the resistance value of the differential load resistor of the variable resistance unit 300. According to the principle of common source amplification, the transconductance of the common source amplifier is relatively large.

[0059] In addition, since the common mode voltage of the differential input signals 11 and 12 is less than the threshold voltage VT, a low level voltage is input to the control unit 400 (inverter 401), and the variable resistance control signal 41 outputted by it is high level, so that the load switch transistor M31 in the variable resistance unit 300 is turned on, and the differential load resistance provided by the variable resistance unit is small (R31 / R32). Therefore, when the common mode voltage of the differential input signals 11 and 12 is less than the threshold voltage VT, although the transconductance of the common source amplifier is large, the differential load resistance of the variable resistance unit 300 is small, so the overall differential gain changes relatively little.

[0060] On the other hand, refer to Figure 6 According to an embodiment of the present disclosure, when the common-mode voltage of the differential input signals 11 and 12 is greater than or equal to the threshold voltage VT, the first input transistor M21 and the second input transistor M22 in the first input unit 201 are turned off, and the third input transistor M23 and the fourth input transistor M24 in the second input unit 202 are turned on, and a differential source follower amplifier consisting of the third input transistor M23 and the fourth input transistor M24 is formed in the receiver front-end circuit 10, and the differential input signals 11 and 12 are source-follower amplified, and differential output signals 31 and 32 are output.

[0061] According to an embodiment of the present disclosure, when the common mode voltage of the differential input signals 11 and 12 is greater than or equal to the threshold voltage VT, the differential gain is determined by the transconductance of the source follower amplifier composed of the third input transistor M23 and the fourth input transistor M22 and the resistance value of the differential load resistor of the variable resistance unit 300. According to the principle of source follower amplification, the transconductance of the source follower amplifier is small.

[0062] In addition, since the common-mode voltage of the differential input signals 11 and 12 is greater than or equal to the threshold voltage VT, a high level is input to the control unit 400 (inverter 401), and the variable resistance control signal 41 outputted by it is a low level, so that the load switch transistor M31 in the variable resistance unit 300 is turned off, and the differential load resistance provided by the variable resistance unit is relatively large (R31+R33 / R32+R44). Therefore, when the common-mode voltage of the common-mode voltage of the differential input signals 11 and 12 is greater than or equal to the threshold voltage VT, although the transconductance of the source follower amplifier is small, the resistance value of the differential load resistance of the variable resistance unit 300 is large, so the overall differential gain changes relatively little.

[0063] Therefore, refer to Figure 6 According to the embodiment of the present disclosure, regardless of whether the common-mode voltage of the differential input signals 11 and 12 is greater than or equal to the threshold voltage VT or less than the threshold voltage VT, the overall differential gain changes relatively little, that is, the amplitude of the differential output signals 31 and 32 will not change significantly with the change of the common-mode voltage of the differential input signals 11 and 12.

[0064] Although the circuit implementation scheme of the receiver front-end circuit 10 is described above in conjunction with specific examples, the present disclosure is not limited thereto. For example, although the first input unit 201 and the second input unit 202 are implemented using P-type MOS transistors and N-type MOS transistors, respectively, those skilled in the art should recognize that, according to the teachings of the present disclosure, other methods can also be used to implement the first input unit 201 and the second input unit 202 having the same functions, such as using N-type MOS transistors and P-type MOS transistors to implement the first input unit 201 and the second input unit 202, respectively. At this time, the load switch transistor M31 included in the variable resistance unit 300 can be implemented using a P-type MOS transistor accordingly. All these variations should be included in the scope of the present disclosure.

[0065] Figure 7 is a schematic circuit diagram showing a receiver front end circuit 10 ′ according to another embodiment of the present disclosure.

[0066] Different from Figure 6 ,like Figure 7 As shown, according to an alternative embodiment of the present disclosure, the first input transistor M21 and the second input transistor M22 may both be N-type MOS transistors. At this time, one end of the current source IA may be connected to the ground voltage VSS, and the other end may be connected to the source of the first input transistor M21 and the source of the second input transistor M22, thereby generating a bias current from the first input transistor M21 and the second input transistor M22 to the power source IA. Figure 7As shown, according to an alternative embodiment of the present disclosure, the gate of the first input transistor M21 can receive a positive input signal 11, and the drain can output a negative output signal 32; the gate of the second input transistor M22 can receive a negative input signal 12, and the drain can output a positive output signal 31.

[0067] In addition, unlike Figure 6 ,like Figure 7 As shown, according to an alternative embodiment of the present disclosure, the third input transistor M23 and the fourth input transistor M24 may both be P-type MOS transistors. Figure 7 As shown, according to an alternative embodiment of the present disclosure, the gate of the third input transistor M23 can receive the positive input signal 11, the drain can be connected to the ground voltage VSS, and the source can output the positive output signal 31. In addition, as Figure 7 As shown, according to an alternative embodiment of the present disclosure, the gate of the fourth input transistor M24 can receive the negative input signal 12 , the drain can be connected to the ground voltage VSS, and the source outputs the negative output signal 32 .

[0068] In addition, unlike Figure 6 ,like Figure 7 As shown, according to an alternative embodiment of the present disclosure, the load switch transistor M31 of the variable resistance unit 300 can be a P-type MOS transistor, whose source is connected to a node between the first load resistor R31 and the third load resistor R33, whose drain is connected to a node between the second load resistor R32 and the fourth load resistor R34, and whose gate receives the variable resistance control signal 41.

[0069] Figure 7 The working principle of the receiver front-end circuit 10' shown is similar to Figure 6 The operating principle of the receiver front-end circuit 10 shown is basically the same.

[0070] Specifically, in Figure 7 In the receiver front-end circuit 10' shown, when the common-mode voltage of the differential input signals 11, 12 is less than the threshold voltage VT, the first input transistor M21 and the second input transistor M22 in the first input unit 201 are turned off, and the third input transistor M23 and the fourth input transistor M24 in the second input unit 202 are turned on, and a differential source follower amplifier consisting of the third input transistor M23 and the fourth input transistor M24 is formed in the receiver front-end circuit 10, and the differential input signals 11, 12 are source-follower amplified, and differential output signals 31, 32 are output.

[0071] According to an alternative embodiment of the present disclosure, when the common mode voltage of the differential input signals 11 and 12 is less than the threshold voltage VT, the differential gain is determined by the transconductance of the source follower amplifier composed of the third input transistor M23 and the fourth input transistor M22 and the resistance value of the differential load resistor of the variable resistance unit 300. According to the principle of source follower amplification, the transconductance of the source follower amplifier is small.

[0072] In addition, since the common-mode voltage of the differential input signals 11 and 12 is less than the threshold voltage VT, a low-level voltage is input to the control unit 400 (inverter 401), and the variable resistance control signal 41 outputted by it is high-level, so that the load switch transistor M31 in the variable resistance unit 300 is turned off, and the differential load resistance provided by the variable resistance unit is relatively large (R31+R33 / R32+R44). Therefore, when the common-mode voltage of the common-mode voltage of the differential input signals 11 and 12 is less than the threshold voltage VT, although the transconductance of the source follower amplifier is small, the resistance value of the differential load resistance of the variable resistance unit 300 is large, so the overall differential gain changes relatively little.

[0073] On the other hand, Figure 7 In the receiver front-end circuit 10' shown, when the common-mode voltage of the differential input signals 11, 12 is greater than or equal to the threshold voltage VT, the first input transistor M21 and the second input transistor M22 in the first input unit 201 are turned on, and the third input transistor M23 and the fourth input transistor M24 in the second input unit 202 are turned off, and a common-source differential amplifier consisting of the first input transistor M21 and the second input transistor M22 is formed in the receiver front-end circuit 10, and the differential input signals 11, 12 are common-source amplified, and differential output signals 31, 32 are output.

[0074] According to an alternative embodiment of the present disclosure, when the common mode voltage of the differential input signals 11 and 12 is greater than or equal to the threshold voltage VT, the differential gain is determined by the transconductance of the common source amplifier composed of the first input transistor M21 and the second input transistor M22 and the resistance value of the differential load resistor of the variable resistance unit 300. According to the principle of common source amplification, the transconductance of the common source amplifier is relatively large.

[0075] In addition, since the common mode voltage of the differential input signals 11 and 12 is greater than or equal to the threshold voltage VT, a high level is input to the control unit 400 (inverter 401), and the variable resistance control signal 41 outputted by it is a low level, so that the load switch transistor M31 in the variable resistance unit 300 is turned on, and the differential load resistance provided by the variable resistance unit is small (R31 / R32). Therefore, when the common mode voltage of the differential input signals 11 and 12 is greater than or equal to the threshold voltage VT, although the transconductance of the common source amplifier is large, the differential load resistance of the variable resistance unit 300 is small, so the overall differential gain changes relatively little.

[0076] Therefore, refer to Figure 7 According to an alternative embodiment of the present disclosure, regardless of whether the common-mode voltage of the differential input signals 11 and 12 is greater than or equal to the threshold voltage VT or less than the threshold voltage VT, the overall differential gain changes relatively little, that is, the amplitude of the differential output signals 31 and 32 will not change significantly with the change of the common-mode voltage of the differential input signals 11 and 12.

[0077] The receiver front-end circuit according to the present disclosure uses two input units connected in parallel and working alternately and a variable resistance unit capable of adjusting the differential load resistance according to the common-mode voltage of the differential input signal. It is capable of receiving a differential input signal with a wider common-mode voltage range at a low power supply voltage, and the output amplitude of the generated differential output signal does not change significantly with the change of the common-mode voltage of the differential input signal, thereby improving the compatibility of the receiver and reducing power consumption.

[0078] For the purpose of illustration, a limited number of possible embodiments of the present disclosure have been given above. Although the present disclosure has been described with reference to the embodiments of the present disclosure, it will be appreciated by those skilled in the art that various modifications and changes may be made to the various embodiments of the present disclosure without departing from the spirit and scope of the present disclosure disclosed in the appended claims.

[0079] Although this document contains many details, these details should not be interpreted as limitations on the scope of the present disclosure or what may be claimed, but rather should be interpreted as descriptions of features that may be specific to a particular embodiment. Certain features described herein in the context of discrete embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented in multiple embodiments separately or in any suitable sub-combination. In addition, although features may be described above as working in certain combinations, and even initially stated as such, in some cases, one or more features in the combination may be deleted from the claimed combination, and the claimed combination may involve sub-combinations or variations of sub-combinations.

Claims

1. A receiver front-end circuit, comprising: The first input unit and the second input unit are configured to operate alternately according to the common mode voltage of the differential input signal and output a differential output signal; a variable resistance unit configured to adjust a differential load resistance provided to the differential output signal according to a variable resistance control signal; as well as The control unit is configured to generate the variable resistance control signal according to the common mode voltage of the differential input signal.

2. The receiver front-end circuit according to claim 1, wherein: The common mode voltage of the differential input signal is greater than the power supply voltage of the receiver front-end circuit.

3. The receiver front-end circuit according to claim 1 or 2, in, When the common mode voltage of the differential input signal is less than a threshold voltage, one of the first input unit and the second input unit operates and the other does not operate, and Wherein, when the common mode voltage of the differential input signal is greater than or equal to a threshold voltage, the other of the first input unit and the second input unit operates and the one of the first input unit does not operate.

4. The receiver front-end circuit according to claim 3, in, When the common mode voltage of the differential input signal is less than the threshold voltage, the one of the first input unit and the second input unit operates and has a small transconductance, and When the common mode voltage of the differential input signal is greater than or equal to the threshold voltage, the other one of the first input unit and the second input unit works and has a large transconductance.

5. The receiver front-end circuit according to claim 4, in, When the common mode voltage of the differential input signal is less than the threshold voltage, the one of the first input unit and the second input unit forms a source follower amplifier, and When the common mode voltage of the differential input signal is greater than or equal to the threshold voltage, the other one of the first input unit and the second input unit forms a common source amplifier.

6. The receiver front-end circuit according to claim 4, in, When the common mode voltage of the differential input signal is less than the threshold voltage, the control unit generates the variable resistance control signal having a first level, and When the common mode voltage of the differential input signal is greater than or equal to the threshold voltage, the control unit generates the variable resistance control signal having a second level different from the first level.

7. The receiver front-end circuit according to claim 6, in, The variable resistance unit makes a differential load resistance large according to the variable resistance control signal having the first level, and makes a differential load resistance small according to the variable resistance control signal having the second level.

8. The receiver front-end circuit according to claim 3, in, The first input unit and the second input unit include a P-type MOS transistor and an N-type MOS transistor, respectively, or include an N-type MOS transistor or a P-type MOS transistor, respectively.

9. The receiver front-end circuit according to claim 8, in, The threshold voltage is determined according to threshold voltages of the P-type MOS transistor and the N-type MOS transistor.

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