An LVDS transmitter with slew control

Abstract

The present invention relates to the field of integrated circuit technology, and more particularly to an LVDS transmitter with slew control. The present invention utilizes the characteristics of resistor and capacitor delay to output a portion of the data signal output by the LVDS circuit after a delay controlled by slew control resistors (RD1 and RD2) and the parasitic capacitance of the gate of the switch tube (M3 and M4). This process absorbs the external load resistor R L The reflection of the output signal (OUTN and OUTP) is then controlled to control the voltage swing of the output signal. On the one hand, the introduction of the slew control circuit does not increase the extra power consumption of the circuit. On the other hand, the introduction of the slew control circuit can improve the ringing phenomenon of the signal at the inversion point. Secondly, due to the use of a much larger than R L RCM1 and RCM2 thus avoid increasing the current flowing through the internal matching resistor, thereby reducing the power consumption of the transmitter. Ultimately, the present invention solves the ringing phenomenon while reducing the power consumption of the LVDS transmitter.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to an LVDS transmitter with slew control. Background Art

[0002] LVDS (Low Voltage Differential Signaling) uses extremely low voltage swings to transmit data differentially at high speed, enabling point-to-point or point-to-multipoint connections. It features low power consumption, low bit error rate, low crosstalk, and low radiation.

[0003] During signal transmission, square wave pulses experience ringing at the inversion point. This ringing phenomenon is particularly pronounced when transmitting high-frequency signals (GHz-level). This can cause severe distortion in the system's output signal, potentially reducing the transmitter's transmission rate. Conventional technology addresses this ringing by connecting a resistor of equal magnitude to the load in parallel within the LVDS transmitter's main driver circuit. This, however, results in increased power consumption for the LVDS transmitter. Summary of the Invention

[0004] In view of the above problems or deficiencies, the present invention provides an LVDS transmitter with slew control, which aims to solve the ringing phenomenon and reduce the power consumption of the LVDS transmitter.

[0005] An LVDS transmitter with slew control comprises an LVDS circuit and a slew control circuit.

[0006] The LVDS circuit includes a first switch tube M1, a second switch tube M2, a first current source tube M5, a second current source tube M6, a first common-mode feedback resistor RCM1, a second common-mode feedback resistor RCM2, a current source and an operational amplifier;

[0007] The gate terminal of the first switch tube M1 is connected to the positive input signal IN+, and the source terminal is connected to the current source; the drain terminal of the first switch tube M1 is connected to the drain terminal of the fourth switch tube M4, the drain terminal of the first current source tube M5 and one end of the first slew control resistor RD1, and serves as a reverse signal output terminal, outputting the signal OUTN.

[0008] The gate terminal of the second switch tube M2 is connected to the positive input signal IN-, and the source terminal is connected to the current source; the drain terminal of the second switch tube M2 is connected to the drain terminal of the third switch tube M3, the drain terminal of the second current source tube M6, and one end of the second slew control resistor RD2, and serves as the positive signal output terminal, outputting the signal OUTP.

[0009] The first common-mode feedback resistor RCM1 and the second common-mode feedback resistor RCM2 are connected in series and connected between the forward signal output terminal and the reverse signal output terminal. The connection point between the first common-mode feedback resistor RCM1 and the second common-mode feedback resistor RCM2 is also connected to the positive input terminal of the operational amplifier.

[0010] The first switch tube M1 , the second switch tube M2 , the third switch tube M3 and the fourth switch tube M4 are NMOS tubes, and the first current source tube M5 and the second current source tube M6 are PMOS tubes.

[0011] The current source is connected to the source terminals of the first switch tube M1 , the second switch tube M2 , the third switch tube M3 and the fourth switch tube M4 .

[0012] Source terminals of the first current source transistor M5 and the second current source transistor M6 are both connected to the power supply voltage VDD, and gate terminals of both are connected to the output terminal of the operational amplifier.

[0013] The negative input of the operational amplifier is connected to a fixed voltage V ref .

[0014] The slew control circuit includes a third switch tube M3, a fourth switch tube M4, a first slew control resistor RD1 and a second slew control resistor RD2.

[0015] The gate terminal of the third switch tube M3 is connected to the other end of the first slew control resistor RD1, and the gate terminal of the fourth switch tube M4 is connected to the other end of the second slew control resistor RD1; the source terminal of the third switch tube M3 is connected to the source terminal of the fourth switch tube M4, and is connected to the current source; the resistance values ​​of the first slew control resistor RD1 and the second slew control resistor RD2 are equal, and the sum of the two is equal to the external load resistor R L The resistance value is 100Ω.

[0016] Furthermore, the slew control circuit further includes a capacitor, one end of which is connected to the gate terminal of M3 and the other end of which is connected to the gate terminal of M4, so as to compensate for the insufficient parasitic capacitance of the MOS tubes M3 and M4.

[0017] Furthermore, the slew control circuit also includes two capacitors C1 and C2; one end of one capacitor C1 is connected to the gate terminal of M3, and the other end is connected to the power ground GND; one end of the other capacitor C2 is connected to the gate terminal of M4, and the other end is connected to the power ground GND, so as to compensate for the insufficient parasitic capacitance of the MOS tubes M3 and M4.

[0018] Furthermore, the first common-mode feedback resistor RCM1 and the second common-mode feedback resistor RCM2 detect the output common-mode voltage V comAnd form a negative feedback control loop with the operational amplifier, the first current source tube M5 and the second current source tube M6; the sum of the resistances of resistors RCM1 and RCM2 is ≥1000Ω, which is much larger than the external load resistance R L The resistance value is 100Ω.

[0019] Furthermore, the first switch tube M1 , the second switch tube M2 , the third switch tube M3 and the fourth switch tube M4 operate in the linear region, and the first current source tube M5 and the second current source tube M6 operate in the saturation region.

[0020] In summary, the present invention utilizes the characteristics of resistor and capacitor delay to output a portion of the data signal output by the LVDS circuit after a delay controlled by the slew control resistors (RD1 and RD2) and the gate parasitic capacitance of the switch tubes (M3 and M4). This process will absorb the external load resistor R L The reflection of the output signal (OUTN and OUTP) is then controlled to control the voltage swing of the output signal. On the one hand, the introduction of the slew control circuit does not increase the extra power consumption of the circuit. On the other hand, the introduction of the slew control circuit can improve the ringing phenomenon of the signal at the inversion point. L RCM1 and RCM2 thus avoid increasing the current flowing through the internal matching resistors. Compared to a circuit without a slew control circuit, the present invention improves output signal quality, reduces signal distortion, and increases the transmitter's signal transmission rate. Compared to conventional circuit structures designed to mitigate ringing, the LVDS transmitter of this application can reduce power consumption by half. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a module block diagram of the present invention;

[0022] Figure 2 Schematic diagram of the circuit structure of the embodiment;

[0023] Figure 3 This is a simulation comparison diagram of an LVDS transmitter with and without a slew control circuit;

[0024] Figure 4 Schematic diagram of the circuit structure of an operational amplifier of an embodiment;

[0025] Figure 5 Schematic diagram of the LVDS circuit structure in the prior art. DETAILED DESCRIPTION

[0026] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0027] The structure of the existing LVDS circuit is as follows Figure 5 As shown, the feedback resistor RCM is set to a value equal to the receiving resistor (external load resistor RL ) value to solve the "ringing" phenomenon caused by impedance mismatch. However, this circuit solution is achieved at the expense of the overall power consumption of the transmitter. Due to the existence of internal matching resistors, the power consumption of the overall circuit is four times the output current.

[0028] This embodiment provides an LVDS transmitter with slew control, referring to Figure 1 and Figure 2 :

[0029] Reference Figure 1 The LVDS circuit includes a forward signal input terminal, a forward signal output terminal, a reverse signal input terminal, and a reverse signal output terminal. The forward signal input terminal (IN+) and the reverse signal input terminal (IN-) are used to receive input data signals IN+ and IN-, and the forward signal output terminal (OUTP) and the reverse signal output terminal (OUTN) are used to output data signals OUTP and OUTN.

[0030] In this embodiment, the LVDS circuit is provided with switch tubes M1 and M2, which are turned on or off according to the high or low levels of the received data signals IN+ and IN-, so that an output current in a positive or negative direction flows between the forward signal output terminal and the reverse signal output terminal, thereby realizing high-level or low-level transmission.

[0031] When the input data signal is high, the level signal connected to the positive signal input terminal (IN+) is high, and the level signal connected to the negative signal input terminal (NI-) is low. At this time, M2 is turned off, causing the current to flow out of the positive output terminal and flow through the external load resistor R L Then return; M1 is turned on, so that the current flows in from the reverse signal output terminal, forming a complete current loop. In this process, the current flows out from the positive signal output terminal through the external load resistor R L Then it flows into the reverse signal output terminal, so the level difference between the forward signal output terminal and the reverse signal output terminal is positive, and high-level transmission is achieved.

[0032] When the input data signal is low, the level signal connected to the positive signal input terminal (IN+) is low, and the level signal connected to the negative signal input terminal (NI-) is high. At this time, M1 is turned off, causing the current to flow out of the negative output terminal and flow through the external load resistor R L Then return; M2 is turned on, so that the current flows in from the positive signal output terminal, forming a complete current loop. In this process, the current flows out from the reverse signal output terminal through the external load resistor R L Then it flows into the positive signal output terminal, so the level difference between the positive signal output terminal and the reverse signal output terminal is negative, thus realizing low level transmission.

[0033] Among them, M1, M2, M3, and M4 are NMOS transistors, and M5 and M6 are PMOS transistors. M1, M2, M3, and M4 operate in the linear region, while M5 and M6 operate in the saturation region. RCM1 and RCM2 detect the output common-mode voltage and form a negative feedback control loop with the operational amplifier, M5, and M6.

[0034] In this embodiment, the operational amplifier structure used in the negative feedback control loop is as follows: Figure 4 As shown, V ip is the positive input terminal of the operational amplifier, V in is the inverting input terminal of the operational amplifier, V out_ap is the output terminal of the operational amplifier. When the common mode voltage V com When the voltage is reduced, the operational amplifier outputs a higher voltage, thereby reducing the gate voltage of M5 and M6, and the common-mode voltage V com Therefore, it is reduced, forming a negative feedback control loop to achieve the common mode voltage V com stability.

[0035] To this end, a slew control circuit is provided in this embodiment. The slew control circuit utilizes the fast changing characteristics of the high-frequency output data signal jump edge output by the LVDS circuit to short the slew control resistors RD1 and RD2 to ground through the parasitic capacitance of the gate terminals of M3 and M4, and the sum of the resistances of the slew control resistors RD1 and RD2 is equal to the external load resistor R L , thereby eliminating the ringing phenomenon caused by impedance mismatch.

[0036] In this embodiment, when the positive input signal IN+ transitions from negative to positive and the negative input signal IN- transitions from positive to negative, the positive output signal OUTP transitions from negative to positive and the negative output signal OUTN transitions from positive to negative. The output current flows from the positive signal output terminal to the negative signal output terminal. Before the delay time, M3 is on and M4 is off. During this time, the slew control circuit absorbs a portion of the output current (data current signal) and the reflected current signal caused by impedance mismatch. After the delay time, M3 turns off and M4 turns on, restoring full output current.

[0037] Conversely, when the positive input signal IN+ transitions from positive to negative and the negative input signal IN- transitions from negative to positive, the positive output signal OUTP transitions from positive to negative and the negative output signal OUTN transitions from negative to positive. The output current flows from the negative signal output terminal to the positive signal output terminal. Before the delay time, M3 turns off and M4 turns on. During this time, the slew control circuit absorbs a portion of the output current and the reflected current signal caused by the impedance mismatch. After the delay time, M3 turns on and M4 turns off, restoring full output current. Adjusting the size of M3 and M4 adjusts the magnitude of the absorbed output current signal and the reflected current signal. The delay time is determined by the slew control resistors (RD1 and RD2) and the parasitic capacitance of the gate terminals of the switches (M3 and M4).

[0038] Figure 3 The LVDS transmitter with slew control according to the embodiment of the present invention is specifically Figure 5 The simulation comparison diagram of the circuit without voltage swing control (existing technology) is shown in the figure. The test condition is a 1GHz random data signal. It can be seen that the output waveform of the circuit without voltage swing control is due to the external load resistor R L Reflections from the LVDS transmitter cause ringing, resulting in more severe signal distortion, poorer signal quality, and a lower achievable frequency limit. However, the output waveform of the slew control circuit is significantly improved. Furthermore, the power consumption of this LVDS transmitter with slew control is twice the output current, a 50% reduction compared to traditional structures that address ringing.

[0039] Through the above embodiments and comparative examples, it can be seen that the present invention utilizes the characteristics of resistor and capacitor delay to output a portion of the data signal output by the LVDS circuit after a delay controlled by the slew control resistors (RD1 and RD2) and the gate parasitic capacitance of the switch tubes (M3 and M4). This process will absorb the external load resistor R L The reflection of the output signal (OUTN and OUTP) is then controlled to control the voltage swing of the output signal. On the one hand, the introduction of the slew control circuit does not increase the extra power consumption of the circuit. On the other hand, the introduction of the slew control circuit can improve the ringing phenomenon of the signal at the inversion point. Secondly, due to the use of a much larger than R L RCM1 and RCM2 thus avoid increasing the current flowing through the internal matching resistor, thereby reducing the power consumption of the transmitter. Ultimately, the present invention solves the ringing phenomenon while reducing the power consumption of the LVDS transmitter.

Claims

1. An LVDS transmitter with slew control, characterized in that: Including LVDS circuit and slew control circuit; The LVDS circuit includes a first switch tube M1, a second switch tube M2, a first current source tube M5, a second current source tube M6, a first common-mode feedback resistor RCM1, a second common-mode feedback resistor RCM2, a current source and an operational amplifier; The gate terminal of the first switch tube M1 is connected to the positive input signal IN+, and the source terminal is connected to the current source; Its drain terminal is connected to the drain terminal of the fourth switch tube M4, the drain terminal of the first current source tube M5 and one end of the first slew control resistor RD1, and serves as a reverse signal output terminal to output a signal OUTN; The gate terminal of the second switch tube M2 is connected to the reverse input signal IN-, and the source terminal is connected to the current source; Its drain terminal is connected to the drain terminal of the third switch tube M3, the drain terminal of the second current source tube M6 and one end of the second slew control resistor RD2, and serves as a positive signal output terminal to output the signal OUTP; A first common-mode feedback resistor RCM1 and a second common-mode feedback resistor RCM2 are connected in series and are connected between the positive signal output terminal and the negative signal output terminal. The connection point between the first common-mode feedback resistor RCM1 and the second common-mode feedback resistor RCM2 is also connected to the positive input terminal of the operational amplifier. The first switch tube M1, the second switch tube M2, the third switch tube M3 and the fourth switch tube M4 are NMOS tubes, and the first current source tube M5 and the second current source tube M6 are PMOS tubes. The current source is connected to the source terminals of the first switch tube M1, the second switch tube M2, the third switch tube M3 and the fourth switch tube M4; The source terminals of the first current source transistor M5 and the second current source transistor M6 are both connected to the power supply voltage VDD, and the gate terminals of both are connected to the output terminal of the operational amplifier; The negative input of the operational amplifier is connected to a fixed voltage V ref ; The slew control circuit includes a third switch tube M3, a fourth switch tube M4, a first slew control resistor RD1 and a second slew control resistor RD2; The gate terminal of the third switch tube M3 is connected to the other end of the first slew control resistor RD1, and the gate terminal of the fourth switch tube M4 is connected to the other end of the second slew control resistor RD1; the source terminal of the third switch tube M3 is connected to the source terminal of the fourth switch tube M4, and is connected to the current source; the resistance values ​​of the first slew control resistor RD1 and the second slew control resistor RD2 are equal, and the sum of the two is equal to the external load resistor R L The resistance value is 100Ω.

2. The LVDS transmitter with slew control according to claim 1, wherein: The slew control circuit further includes a capacitor, one end of which is connected to the gate terminal of M3, and the other end of which is connected to the gate terminal of M4.

3. The LVDS transmitter with slew control according to claim 1, wherein: The slew control circuit further includes two capacitors C1 and C2; one end of one capacitor C1 is connected to the gate of M3, and the other end is connected to the power ground GND; one end of the other capacitor C2 is connected to the gate of M4, and the other end is connected to the power ground GND.

4. The LVDS transmitter with slew control according to claim 1, wherein: The first common mode feedback resistor RCM1 and the second common mode feedback resistor RCM2 detect the output common mode voltage V com and forms a negative feedback control loop with the operational amplifier, the first current source tube M5 and the second current source tube M6; the sum of the resistances of the resistors RCM1 and RCM2 is ≥1000Ω.

5. The LVDS transmitter with slew control according to claim 1, wherein: The first switch tube M1 , the second switch tube M2 , the third switch tube M3 and the fourth switch tube M4 operate in a linear region, and the first current source tube M5 and the second current source tube M6 operate in a saturation region.

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