Reconfigurable OFDM (Orthogonal Frequency Division Multiplexing) baseband processor

Abstract

The invention provides a reconfigurable OFDM (Orthogonal Frequency Division Multiplexing) baseband processor. The reconfigurable OFDM baseband processor comprises a control path, a data path and a shared memory unit, wherein the control access is connected with an interrupt signal of a host CPU (Central Processing Unit) and receives interrupt control of the host CPU; the control access is also connected with a slave bus interface of the host CPU and receives state control of the host CPU; the data path is connected with a main bus interface of the host CPU and is used for receiving and transmitting OFDM original data in the host CPU; the data path converts an externally received OFDM time domain signal into OFDM original data and sends the OFDM original data to the host CPU, or receives the OFDM original data sent by the host CPU, converts the OFDM original data into an OFDM time domain signal and sends the OFDM time domain signal to the outside; the data path is also connected with a slave bus interface of the host CPU and is used for the host CPU to configure the data path; and the shared memory unit is used for providing a storage space for the data path in a shared memory mode.

Description

Technical Field

[0001] The invention relates to a baseband processor, in particular to a reconfigurable OFDM baseband processor. Background Art

[0002] This section merely provides background information related to the present disclosure and is not necessarily prior art.

[0003] In modern communication systems, with the rapid development of wireless communication technology, especially the widespread application of OFDM (Orthogonal Frequency Division Multiplexing) technology, the data transmission efficiency, signal processing capability and anti-interference performance of communication systems have been significantly improved. OFDM divides data into multiple subcarriers for parallel transmission, which can make full use of spectrum resources and has strong anti-multipath interference capability. Therefore, it has been widely used in 4G, 5G mobile communications, Wi-Fi, wireless LAN and other fields.

[0004] However, as communication standards continue to be updated and iterated, communication protocols and algorithms have become more complex, and existing processor architectures have shown some shortcomings in the face of these challenges:

[0005] Instruction-based processors (such as CPUs or DSPs): These processors are highly flexible and can support a variety of communication protocols through software programming. However, they are not optimized for specific signal processing and communication algorithms, which results in the inability to maximize the processor's performance when executing specific modulation, coding and other signal processing algorithms.

[0006] ASIC (Application Specific Integrated Circuit): ASIC processors usually have extremely high energy efficiency and performance because they are customized for specific tasks and application scenarios. However, the disadvantage of ASIC is that it is not flexible enough. Once the design is completed, the hardware functions are fixed and it is difficult to adapt to future communication standard updates. If new standards or algorithms need to be supported, the chip must be redesigned, which will significantly increase development costs and time.

[0007] FPGA (Field Programmable Gate Array): FPGA provides a solution between CPU and ASIC, with good flexibility and programmability, suitable for supporting multiple communication standards. However, the cost of FPGA is relatively high, especially in large-scale mass production, the cost performance of FPGA is not ideal. In addition, the energy efficiency of FPGA is not as good as ASIC, and the power consumption is high, which makes it face challenges in energy-sensitive applications.

[0008] In summary, existing communication processor architectures face many challenges in terms of flexibility, energy efficiency, and cost. Especially when dealing with highly similar communication algorithms such as OFDM, traditional processor architectures are difficult to simultaneously meet the requirements of high performance, high energy efficiency, and flexibility. Therefore, there is an urgent need for a low-cost, high-energy-efficiency, and high-flexibility processor architecture to cope with the rapidly evolving communication standards and complex communication algorithm requirements.

[0009] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0010] Purpose of the invention: The technical problem to be solved by the present invention is to provide a reconfigurable OFDM baseband processor in view of the deficiencies in the prior art.

[0011] In order to solve the above technical problems, the present invention discloses a reconfigurable OFDM baseband processor, comprising:

[0012] control path, data path and shared memory unit; wherein,

[0013] The control path is connected to the interrupt signal of the host CPU and receives the interrupt control of the host CPU; the control path is also connected to the slave bus interface of the host CPU and receives the state control of the host CPU;

[0014] The data path is connected to the main bus interface of the host CPU and is used to send and receive OFDM original data in the host CPU; the data path converts OFDM time domain signals received from the outside into OFDM original data and sends them to the host CPU, or receives OFDM original data sent by the host CPU and converts them into OFDM time domain signals and sends them to the outside;

[0015] The data path is also connected to the slave bus interface of the host CPU, so that the host CPU can configure the data path;

[0016] The shared memory unit is used to provide storage space for the data path in a shared memory manner.

[0017] Furthermore, the data path includes:

[0018] A data packet management module connected to the main bus interface of the host CPU, used for sending and receiving the OFDM original data;

[0019] The data packet management module is connected to the data processing module, and the data processing module is used to convert the OFDM original data and the OFDM time domain signal into each other;

[0020] The data path also includes a data transmission bus and a register configuration bus; the data processing module uses the shared memory unit through the data transmission bus, and the control path controls the data processing module through the register configuration bus.

[0021] Furthermore, the data processing module is divided into three types of processing units according to the OFDM data processing process, namely:

[0022] A block processing unit, a symbol processing unit and a sampling point processing unit, wherein:

[0023] The block processing unit data is connected to the data packet management module, and is used to send and receive OFDM original data of the data packet management module, and to perform mutual conversion between OFDM original data and data blocks;

[0024] The symbol processing unit is used to convert data blocks and symbol data into each other;

[0025] The sampling point processing unit is used to perform symbol data conversion and mutual conversion of sampling point signals;

[0026] The data interaction among the block processing unit, the symbol processing unit and the sampling point processing unit is performed through the data transmission bus and the shared memory unit.

[0027] Furthermore, the block processing unit includes:

[0028] Block processing unit DMA submodule, block processing unit register, block processing unit state machine, verification unit and encoding and decoding unit; wherein,

[0029] The block processing unit DMA submodule is used to perform data interaction with the shared memory unit through the data transmission bus;

[0030] The block processing unit register is used to configure the block processing unit through the register configuration bus;

[0031] The block processing unit state machine is used to control the working state of the block processing unit according to the control path;

[0032] The verification unit is used for data integrity check;

[0033] The encoding and decoding unit is used to perform error correction encoding and decoding of data.

[0034] Furthermore, the symbol processing unit converts data blocks in the form of bit data and symbol data in the form of carrier data, including:

[0035] Symbol processing unit DMA submodule, symbol processing unit register, symbol processing unit state machine, modulation and demodulation submodule, interleaving submodule and fast Fourier transform FFT or inverse fast Fourier transform IFFT processing submodule; wherein,

[0036] A symbol processing unit DMA submodule, used for performing data interaction with the shared memory unit via the data transmission bus;

[0037] a symbol processing unit register, used to configure the symbol processing unit via the register configuration bus;

[0038] A symbol processing unit state machine, used to control the working state of the symbol processing unit according to the control path;

[0039] The modulation and demodulation submodule maps the coded data block into symbol data through a modulator, or converts the symbol data into a data block through demodulation;

[0040] The interleaving submodule performs an interleaving operation before or after modulation;

[0041] The fast Fourier transform FFT or inverse fast Fourier transform IFFT processing submodule is used to realize the conversion of signals between the frequency domain and the time domain.

[0042] Furthermore, the sampling point processing unit comprises:

[0043] Sampling point processing unit DMA submodule, sampling point processing unit register, sampling point processing unit state machine, signal interpolation and extraction submodule, and filtering and enhancement submodule; wherein,

[0044] A sampling point processing unit DMA submodule, used for performing data interaction with the shared memory unit through the data transmission bus;

[0045] A sampling point processing unit register, used to configure the sampling point processing unit through the register configuration bus;

[0046] A sampling point processing unit state machine, used to control the working state of the sampling point processing unit according to the control path;

[0047] The signal interpolation and decimation submodule performs interpolation and decimation operations according to the sampling rate and channel conditions of different transmission channels;

[0048] The filtering and enhancement submodule uses filters to remove noise or interference from the data signal and performs signal enhancement operations.

[0049] Furthermore, the control path includes:

[0050] Reconfigurable state machine, control path registers and interrupt control module, where:

[0051] The reconfigurable state machine is used to control the state machines in the block processing unit, the symbol processing unit and the sampling point processing unit;

[0052] The control path register is connected to the register configuration bus and is used to control the processing unit or read its status through the register in the processing unit;

[0053] The interrupt control module is used to transmit interrupt signals to the host CPU for transaction-level communication.

[0054] Furthermore, the shared memory unit is divided into N independent data storage blocks according to the number of processing units in the data processing module.

[0055] Furthermore, a two-layer reconstruction strategy is used for configuration.

[0056] Furthermore, the two-layer reconstruction strategy includes:

[0057] Hardware generation and runtime configuration, where

[0058] The hardware generation, i.e., generating hardware configuration according to requirements and determining the maximum processing capacity of the OFDM baseband processor, specifically includes:

[0059] When performing OFDM baseband processing, the set of FFT points that need to be supported, the maximum processing order, the maximum symbol length, the maximum windowing length, the maximum cyclic prefix length, the maximum interleaving depth, the maximum lookup table length, the maximum throughput of the processing unit, and the shared memory unit size;

[0060] The runtime configuration, after the hardware generation is completed, adjusts the OFDM baseband processor through the configuration register, specifically including:

[0061] When performing OFDM baseband processing, the current number of FFT points, the current filter chain order and corresponding coefficients, the current symbol length, the current windowing length and corresponding coefficients, the current cyclic prefix length, the current interleaving depth, and the current lookup table size and its contents.

[0062] Beneficial effects:

[0063] The present invention proposes a novel reconfigurable OFDM baseband processor architecture to provide sufficient flexibility while maintaining high energy efficiency, adapt to a variety of communication protocols and standards, and reduce design and production costs. Specifically:

[0064] 1. Enhanced flexibility: In order to solve the problem of insufficient flexibility of ASIC, the present invention adopts a reconfigurable architecture design so that the processor can be configured to support existing and future communication standards. Through the coordinated configuration of hardware and software, it can quickly adapt to the update of communication protocols and reduce the cost and time of redesigning hardware.

[0065] 2. Energy efficiency is guaranteed: The processor architecture of the present invention optimizes the execution efficiency of the OFDM communication algorithm through a dedicated signal processing acceleration unit, while achieving efficient parallel processing and maintaining low power consumption, thereby ensuring overall energy efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0066] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments, and the above and / or other advantages of the present invention will become more clear.

[0067] Figure 1 It is a schematic diagram of the overall architecture of the present invention.

[0068] Figure 2 The schematic diagram of the architecture of an embodiment is shown in FIG. DETAILED DESCRIPTION

[0069] The overall idea of ​​the present invention is as follows:

[0070] By analyzing the deficiencies of CPU / DSP, ASIC, and FPGA architectures in the prior art, the present invention adopts a design of different processing units divided based on the characteristics of OFDM data structure, and combined with a two-layer reconstruction strategy, it can effectively solve the balance problem between flexibility, energy efficiency and cost. Traditional CPU / DSP has high flexibility but low energy efficiency, while ASIC is efficient but poor in flexibility, and FPGA is high in cost and insufficient in energy efficiency. Specifically, the system architecture of the present invention optimizes processing for different data levels through the division of sampling point processing units, symbol processing units, and block processing units, and at the same time, through a two-layer reconstruction strategy, ensures that the processor can flexibly adapt to multiple communication standards without large-scale hardware changes.

[0071] Therefore, the present invention not only significantly improves the flexibility of the system, but also ensures signal processing efficiency and energy efficiency, so that it can effectively cope with the evolving communication standards.

[0072] The specific technical solutions of the present invention are as follows:

[0073] (1) Overall structure and basis for unit division

[0074] Overall architecture:

[0075] The architecture of the baseband processor is as follows Figure 1As shown. The entire baseband communicates with the host CPU through the master bus interface, slave bus interface and interrupt signal. The master bus interface is mainly responsible for interacting with the data packet management module. The slave interface is connected to the register configuration bus and the data transmission bus, which facilitates the CPU to configure the registers of each functional unit or read the data in the shared memory unit to realize their configuration and monitoring. This system ensures that the CPU can efficiently control and monitor the various processing modules in the baseband processor.

[0076] The processor consists of multiple functional units that manage the various stages of OFDM processing data. Depending on the type of data being processed, these functional units are divided into three categories: sample point processing units, symbol processing units, and block processing units. Each type of functional unit is optimized for its specific buffer size and throughput. This organization ensures efficient processing of data and maximizes performance at each stage of the processing chain.

[0077] Data exchange between functional units is performed through shared memory, which is divided into N independent banks. This design reduces memory access conflicts and ensures efficient flow of data within the system. Access to shared memory units is performed through the data transfer bus, and each functional unit is equipped with its own dedicated DMA subunit.

[0078] The control path is separated from the data path, and the control signal of each functional unit is related to the finite state machine (FSM) of the current OFDM baseband processor data protocol. Figure 1 The FSM itself can be reconfigured by reloading specific CSRs (Control and status registers), thereby enhancing the flexibility of the system to support different communication protocols.

[0079] The division basis of sampling point processing unit, symbol processing unit and block processing unit is:

[0080] In the OFDM system, the data stream goes through a series of layers of processing, including different processing steps from sampling points to symbols and then to physical blocks. Since the data characteristics and processing requirements of each layer are different, it is necessary to divide the system into reasonable units in order to efficiently process various types of data in the data stream. The following is an analysis of the data structure in the OFDM system:

[0081] ●1.1 Sampling point structure

[0082] Sampling point: OFDM symbols are usually processed through sampling points, and each symbol contains multiple sampling points. Sampling points are the representation of symbols in the time domain, and they play a key role, especially at the physical level. The processing of sampling points usually includes operations such as interpolation and decimation, and the data rate is high, which places high requirements on throughput.

[0083] Features: The number of sampling points is very large, the data rate is extremely high, and the processor must have extremely high throughput and real-time processing capabilities. Sampling-level processing is critical to high-speed data processing and signal conversion at the physical layer.

[0084] ●1.2 Symbol structure

[0085] OFDM symbol: After the data block is encoded, the data is modulated into symbols. OFDM symbol is a signal transmitted over a period of time, representing the modulated data. Each symbol contains many modulated subcarriers, which are interleaved, modulated (such as QAM, PSK) and other operations to improve transmission efficiency and signal robustness.

[0086] Features: Symbol-level data represents the physical signal unit of transmission. Symbol processing involves modulation, interleaving, FFT and other operations. The data rate is moderate.

[0087] ●1.3 Block structure

[0088] Data block: In OFDM systems, the initial input data is processed in the form of blocks. Each block is usually composed of a group of bits or bytes, which are encoded (such as Turbo coding, convolutional coding, etc.) to enhance the robustness of the data. The focus of block-level data processing before transmission is error correction coding and data packaging.

[0089] Features: The block-level data volume is large, and it needs to process complex encoding and error correction algorithms, and the data rate is relatively low.

[0090] (2) Unit function design

[0091] Sampling point processing unit:

[0092] The sampling point processor is responsible for processing the sampling point data after symbol processing, mainly focusing on the data transmission part of the physical layer. Due to the high data rate, the function of the sampling point processor mainly involves high-speed signal processing and optimization.

[0093] Signal interpolation and extraction: In order to ensure the transmission quality of the signal under different sampling rates and channel conditions, the sampling point processor performs interpolation and extraction operations so that the signal can be converted within different frequency ranges to adapt to the requirements of the transmission channel.

[0094] Filtering and enhancement: The sampling point processor usually includes filters to remove noise or other interference from the signal. In addition, it can also perform signal enhancement to ensure that the received signal maintains sufficient signal strength and quality for subsequent symbol demodulation and data recovery.

[0095] Symbol Processing Unit:

[0096] The symbol processor processes the data packaged and encoded by the block processor and converts it into symbols for further modulation and transmission. It plays the role of mapping bit data into carrier data in the data transmission link.

[0097] Modulation / Demodulation: The symbol processor maps the coded bits into OFDM symbols (such as BPSK, QPSK, 16-QAM, etc.) through the modulator. At the receiving end, the symbol processor performs the demodulation function and converts the received symbols into a bit stream.

[0098] Interleaving: The symbol processor performs an interleaving operation before or after modulation to ensure that adjacent symbols are shuffled during transmission, thereby improving anti-interference capabilities and preventing burst errors from affecting consecutive symbols.

[0099] FFT / IFFT processing: In OFDM systems, the symbol processor performs conversion between the frequency domain and the time domain, and achieves modulation and demodulation of the signal through fast Fourier transform (FFT) or inverse fast Fourier transform (IFFT). IFFT is used to convert frequency domain signals into time domain signals for transmission, and FFT is used for demodulation at the receiving end.

[0100] Block Processing Unit:

[0101] The block processor is responsible for processing the input data block. Its main functions include data verification, encoding and decoding. It is the first layer of processing after the data enters the system, ensuring that the data has strong anti-interference ability in subsequent transmission. Specifically, it can include but is not limited to the following processing units:

[0102] ●CRC check unit: responsible for generating and appending cyclic redundancy check (CRC) code for data transmission integrity check. The receiving end can determine whether the data is correct by verifying the CRC.

[0103] ●Codec unit: Enhances the robustness of data by implementing error correction coding (such as Turbo coding, convolutional coding, Reed-Solomon coding, etc.), so that even if part of the data is interfered with during transmission, the original data can be restored through decoding.

[0104] Control unit: The control unit is responsible for the scheduling and process management of the entire system, ensuring that each processing unit works synchronously on time. It manages the transmission of data flow, the start and stop of processing units, coordinates the efficient operation of all modules, and ensures the stability and reliability of the entire system.

[0105] Shared memory unit: The shared memory unit is used for data exchange between processing units, providing efficient data storage and reading functions. It avoids bottleneck problems that may occur during data transmission and ensures that data can be quickly and accurately transferred from one processing unit to the next.

[0106] (3) Two-layer reconstruction strategy

[0107] In terms of reconfigurability, the present invention adopts a two-layer reconfiguration strategy to achieve a balance between the system's hardware capabilities and runtime flexibility. The strategy includes two main levels:

[0108] Hardware generation layer:

[0109] At this level, the system generates a hardware configuration based on the target application requirements and determines the maximum processing capability of the accelerator.

[0110] These configurations include but are not limited to:

[0111] The set of FFT points that need to be supported, the maximum processing order, the maximum symbol length, the maximum windowing length, the maximum cyclic prefix length, the maximum interleaving depth, the maximum lookup table length of the encoding and decoding unit, the maximum throughput of each processing unit, and the shared memory unit size.

[0112] For example, for the FFT accelerator, the system presets the upper limit of the FFT points (such as 4096 points) during the hardware generation phase and determines the symbol time, buffer size, and number of butterfly operation units associated with it. This level ensures that the accelerator can meet the highest performance requirements in different scenarios.

[0113] Runtime configuration layer:

[0114] After the hardware is generated, the system can fine-tune the accelerator at runtime through the configuration registers. These configurations include but are not limited to:

[0115] The current number of FFT points, the current filter chain order and the corresponding coefficients, the current symbol length, the current windowing length and the corresponding coefficients, the current cyclic prefix length, the current interleaving depth, the lookup table size of the current codec unit and its contents.

[0116] For example, the actual number of FFT points can be controlled through registers to dynamically adapt to the specific needs of different protocols or applications. The design of this layer provides runtime flexibility, allowing the system to work efficiently under different communication protocols.

[0117] This two-layer reconfigurable strategy not only guarantees maximum performance support in hardware, but also allows dynamic adjustments at runtime, ensuring that the system has sufficient flexibility and scalability when facing diverse protocols and applications.

[0118] Example:

[0119] like Figure 2 As shown, according to the technical solution of the present invention, in a specific embodiment, taking the data protocol of the current OFDM baseband processor as a HPLC-like protocol as an example, a reconfigurable OFDM processor is designed, an HPLC protocol state machine designed for the HPLC-like protocol; an acceleration unit such as a Turbo codec / interleaver integrated in the processing unit for the HPLC-like protocol; the number of shared memory banks is concretized as 2, and the specific solution of this embodiment is as follows:

[0120] a) Division of submodules within a unit

[0121] In this embodiment, the system is divided into three main computing units: sampling point processing unit, symbol processing unit and block processing unit. Each unit contains multiple sub-modules, each of which performs different functions:

[0122] ●Block processing unit: includes data packaging module, Turbo encoding and decoding module, convolutional code encoding and decoding module and verification module.

[0123] ●Symbol processing unit: includes interleaving module, constellation mapping module and FFT accelerator. The interleaving module scrambles the bit order to enhance anti-interference capability, the constellation mapping module maps bits into modulation symbols, and the FFT accelerator realizes the conversion between time domain and frequency domain.

[0124] ● Sampling point processing unit: includes filter chain, windowing, cyclic prefix, and gain control. These modules work together to process the sampling and channel compensation of the received signal to ensure efficient transmission of the signal at the physical layer.

[0125] b) Interaction between the computing unit and the control unit

[0126] Each processing unit (sampling point processing, symbol processing, and block processing) is scheduled and managed by the control unit. The control unit dynamically configures the operating parameters of each processing unit according to the timing requirements of data processing and the requirements of the current communication protocol. The control unit interacts with each computing unit through configuration registers to ensure that they can work synchronously and complete their respective tasks on time. For example, the control unit can dynamically adjust the number of FFT points in the symbol processing unit or the interpolation ratio in the sampling point processing unit through registers.

[0127] In a specific implementation, the present application provides a computer storage medium and a corresponding data processing unit, wherein the computer storage medium can store a computer program, and when the computer program is executed by the data processing unit, the invention content of a reconfigurable OFDM baseband processor provided by the present invention and some or all of the steps in each embodiment can be executed. The storage medium can be a disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc.

[0128] Those skilled in the art can clearly understand that the technical solutions in the embodiments of the present invention can be implemented by means of computer programs and their corresponding general hardware platforms. Based on such an understanding, the technical solutions in the embodiments of the present invention can be essentially or partly contributed to the prior art in the form of computer programs, i.e., software products, which can be stored in a storage medium and include several instructions for enabling a device including a data processing unit (which can be a personal computer, a server, a single-chip microcomputer, an MCU or a network device, etc.) to execute the methods described in various embodiments of the present invention or certain parts of the embodiments.

[0129] The present invention provides a concept and method for a reconfigurable OFDM baseband processor. There are many methods and approaches to implement the technical solution. The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention. These improvements and modifications should also be regarded as the protection scope of the present invention. All components not specified in this embodiment can be implemented by existing technologies.

Claims

1. A reconfigurable OFDM baseband processor, characterized in that: include: control path, data path and shared memory unit; wherein, The control path is connected to the interrupt signal of the host CPU and receives the interrupt control of the host CPU; the control path is also connected to the slave bus interface of the host CPU and receives the state control of the host CPU; The data path is connected to the main bus interface of the host CPU and is used to send and receive OFDM original data in the host CPU; the data path converts OFDM time domain signals received from the outside into OFDM original data and sends them to the host CPU, or receives OFDM original data sent by the host CPU and converts them into OFDM time domain signals and sends them to the outside; The data path is also connected to the slave bus interface of the host CPU, so that the host CPU can configure the data path; The shared memory unit is used to provide storage space for the data path in a shared memory manner.

2. A reconfigurable OFDM baseband processor according to claim 1, characterized in that: The data path comprises: A data packet management module connected to the main bus interface of the host CPU, used for sending and receiving the OFDM original data; The data packet management module is connected to the data processing module, and the data processing module is used to convert the OFDM original data and the OFDM time domain signal into each other; The data path also includes a data transmission bus and a register configuration bus; the data processing module uses the shared memory unit through the data transmission bus, and the control path controls the data processing module through the register configuration bus.

3. A reconfigurable OFDM baseband processor according to claim 2, characterized in that: The data processing module is divided into three types of processing units according to the OFDM data processing process, namely: A block processing unit, a symbol processing unit and a sampling point processing unit, wherein: The block processing unit data is connected to the data packet management module, and is used to send and receive OFDM original data of the data packet management module, and to perform mutual conversion between OFDM original data and data blocks; The symbol processing unit is used to convert data blocks and symbol data into each other; The sampling point processing unit is used to perform symbol data conversion and mutual conversion of sampling point signals; The data interaction among the block processing unit, the symbol processing unit and the sampling point processing unit is performed through the data transmission bus and the shared memory unit.

4. The reconfigurable OFDM baseband processor according to claim 3, characterized in that: The block processing unit comprises: Block processing unit DMA submodule, block processing unit register, block processing unit state machine, verification unit and encoding and decoding unit; wherein, The block processing unit DMA submodule is used to perform data interaction with the shared memory unit through the data transmission bus; The block processing unit register is used to configure the block processing unit through the register configuration bus; The block processing unit state machine is used to control the working state of the block processing unit according to the control path; The verification unit is used for data integrity check; The encoding and decoding unit is used to perform error correction encoding and decoding of data.

5. A reconfigurable OFDM baseband processor according to claim 4, characterized in that: The symbol processing unit converts data blocks in the form of bit data and symbol data in the form of carrier data, including: Symbol processing unit DMA submodule, symbol processing unit register, symbol processing unit state machine, modulation and demodulation submodule, interleaving submodule and fast Fourier transform FFT or inverse fast Fourier transform IFFT processing submodule; wherein, A symbol processing unit DMA submodule, used for performing data interaction with the shared memory unit via the data transmission bus; a symbol processing unit register, used to configure the symbol processing unit via the register configuration bus; A symbol processing unit state machine, used to control the working state of the symbol processing unit according to the control path; The modulation and demodulation submodule maps the coded data block into symbol data through a modulator, or converts the symbol data into a data block through demodulation; The interleaving submodule performs an interleaving operation before or after modulation; The fast Fourier transform FFT or inverse fast Fourier transform IFFT processing submodule is used to realize the conversion of signals between the frequency domain and the time domain.

6. The reconfigurable OFDM baseband processor according to claim 5, characterized in that: Sampling point processing unit, including: Sampling point processing unit DMA submodule, sampling point processing unit register, sampling point processing unit state machine, signal interpolation and extraction submodule, and filtering and enhancement submodule; wherein, A sampling point processing unit DMA submodule, used for performing data interaction with the shared memory unit through the data transmission bus; A sampling point processing unit register, used to configure the sampling point processing unit through the register configuration bus; A sampling point processing unit state machine, used to control the working state of the sampling point processing unit according to the control path; The signal interpolation and decimation submodule performs interpolation and decimation operations according to the sampling rate and channel conditions of different transmission channels; The filtering and enhancement submodule uses filters to remove noise or interference from the data signal and performs signal enhancement operations.

7. The reconfigurable OFDM baseband processor according to claim 6, characterized in that: The control path comprises: Reconfigurable state machine, control path registers and interrupt control module, where: The reconfigurable state machine is used to control the state machines in the block processing unit, the symbol processing unit and the sampling point processing unit; The control path register is connected to the register configuration bus and is used to control the processing unit or read its status through the register in the processing unit; The interrupt control module is used to transmit interrupt signals to the host CPU for transaction-level communication.

8. The reconfigurable OFDM baseband processor according to claim 7, characterized in that: The shared memory unit is divided into N independent data storage blocks according to the number of processing units in the data processing module.

9. The reconfigurable OFDM baseband processor according to claim 8, characterized in that: Use a two-tier reconstruction strategy for configuration.

10. The reconfigurable OFDM baseband processor according to claim 9, characterized in that: The two-layer reconstruction strategy includes: Hardware generation and runtime configuration, where The hardware generation, i.e., generating hardware configuration according to requirements and determining the maximum processing capacity of the OFDM baseband processor, specifically includes: When performing OFDM baseband processing, the set of FFT points that need to be supported, the maximum processing order, the maximum symbol length, the maximum windowing length, the maximum cyclic prefix length, the maximum interleaving depth, the maximum lookup table length, the maximum throughput of the processing unit, and the shared memory unit size; The runtime configuration, after the hardware generation is completed, adjusts the OFDM baseband processor through the configuration register, specifically including: When performing OFDM baseband processing, the current number of FFT points, the current filter chain order and corresponding coefficients, the current symbol length, the current windowing length and corresponding coefficients, the current cyclic prefix length, the current interleaving depth, and the current lookup table size and its contents.

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