Image sensor for suppressing flicker

Abstract

An image sensor for suppressing flicker includes: a photodiode configured to reset in each frame period to accumulate a charge corresponding to incident light in one frame period and output an output voltage corresponding to the accumulated charge; and a holding capacitor configured to accumulate a charge corresponding to an output signal of the photodiode. An output signal of the photodiode in one frame is integrated, the integrated output signal is accumulated in the holding capacitor, and a first signal is output. After the holding capacitor is refreshed, a voltage corresponding to the output voltage of the photodiode is held in the holding capacitor, and a second signal is output.

Description

Technical Field

[0001] The present disclosure relates to an image sensor using a photodiode that can perform suitable operations under both low illumination and high illumination. Background Art

[0002] The image sensor includes a photodiode in each of pixel circuits, and detects an amount of charge generated based on light entering each of the photodiodes.

[0003] Figure 1 is a graph showing the VI characteristics of a photodiode. As shown in the figure, the VI characteristics of the photodiode have a logarithmic region (under high illumination) in which the photodiode operates with a forward bias and a linear region (under low illumination) in which the photodiode operates with a portion of a reverse bias and a forward bias.

[0004] Therefore, the operation of the photodiode is different between high illumination conditions and low illumination conditions. Therefore, the nature of the noise mixed when performing detection is also different between high illumination conditions and low illumination conditions. Therefore, it is desirable to appropriately remove noise under both high illumination and low illumination.

[0005] Examples have disclosed integrating the output of a photodiode in order to remove flicker caused by light-emitting diode (LED) illumination, but kTC noise has not been discussed. Summary of the invention

[0006] An image sensor according to the present disclosure includes: a photodiode configured to be reset in each frame period to accumulate charges corresponding to incident light in one frame period and output an output voltage corresponding to the accumulated charges; and a holding capacitor configured to accumulate charges corresponding to an output signal of the photodiode. The output signal of the photodiode in one frame period is integrated, the integrated output signal is accumulated in the holding capacitor, and a first signal is output. After the holding capacitor is refreshed, a voltage corresponding to the output voltage of the photodiode is held in the holding capacitor, and a second signal is output.

[0007] According to the present disclosure, the first signal and the second signal can be obtained during one frame period. This can make it possible to obtain a flicker-suppressed output in both low light and high light. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Embodiments of the present disclosure will be described based on the following figures, in which:

[0009] Figure 1 It is a graph showing the VI characteristics of a photodiode.

[0010] Figure 2 is a diagram showing a configuration of a pixel circuit of an image sensor according to an embodiment.

[0011] Figure 3 It is shown Figure 2 A timing diagram of the operation of the circuit.

[0012] Figure 4 It is a diagram showing a state in which flicker occurs.

[0013] Figure 5 1 is a diagram showing the amplitude of the signal Isig which is the output of the photodiode (PD) 10 and the frequency of occurrence of flicker in the PH-injection signal and the PH-SF signal.

[0014] Figure 6 is a diagram showing an image sensor 200 in which pixels according to the embodiment are two-dimensionally arranged.

[0015] Figure 7 is a timing chart showing the operation of the image sensor 200 .

[0016] Figure 8 is a timing chart showing the operation according to Modification 1.

[0017] Fig. 9 is a diagram showing a circuit configuration according to Modification 2.

[0018] Fig.10 is a timing chart showing the operation according to Modification 2.

[0019] Fig.11 is a diagram showing a result obtained by comparing outputs of three signals in a case where a constant amount of light enters during one frame period. DETAILED DESCRIPTION

[0020] Embodiments of the present disclosure are described below with reference to the accompanying drawings. The following embodiments do not limit the present disclosure, and configurations obtained by selectively combining a plurality of examples are also included in the present disclosure.

[0021] Circuit Configuration

[0022] Figure 21 is a diagram showing the configuration of a pixel circuit of an image sensor according to an embodiment. A photodiode (PD) 10 accumulates charge (in this case, electrons) based on incident light. The cathode of the photodiode (PD) 10 serves as an output terminal, and the anode is connected to a power supply (e.g., ground). Therefore, the output voltage Vpd of the photodiode (PD) 10 becomes an output signal. In this embodiment, a field effect transistor (FET) is used as a transistor.

[0023] One end (drain) of a reset transistor (RST) 12 is connected to the cathode of the photodiode (PD) 10, and the other end (source) of the reset transistor (RST) 12 is connected to a power source (e.g., ground) through a reset power source 14. In this example, the reset transistor (RST) 12 is an n-channel transistor.

[0024] The cathode of the photodiode (PD) 10 is connected to the gate of a peak hold transistor (PH) 16. The peak hold transistor (PH) 16 is a p-channel transistor. The source of the peak hold transistor (PH) 16 is connected to a power supply.

[0025] The source of the switching transistor (SWsig) 24 is connected to the drain of the peak holding transistor (PH) 16. One end of the holding capacitor (Csig) 26 is connected to the drain of the switching transistor (SWsig) 24. The other end of the holding capacitor (Csig) 26 is connected to a power supply (e.g., ground). The switching transistor (SWsig) 24 is a p-channel transistor.

[0026] The drain of the switch transistor (SWsig) 24 is connected to the gate of a source follower transistor (SF) 30. The drain of the source follower transistor (SF) 30 is connected to a power supply, and the source is connected to the drain of a selection transistor (SEL) 32. The source of the selection transistor (SEL) is connected to an output line 40.

[0027] Furthermore, the drain of peak hold transistor (PH) 16 is connected to a power source (eg, ground) through bias transistor (BIAS) 44 and load transistor (LOAD) 48. Bias transistor (BIAS) 44 and load transistor (LOAD) 48 are p-channel transistors.

[0028] The gate voltage of the load transistor (LOAD) 48 is set to a DC voltage for the peak hold transistor (PH) 16 to perform a source follower operation. To inject holes into the hold capacitor (Csig) 26, a negative pulse is applied to the bias transistor (BIAS) 44.

[0029] A row selection signal is supplied to the gate of the selection transistor (SEL) 32. When the row selection signal becomes an H level, a signal corresponding to the gate voltage of the source follower transistor (SF) 30 is output to the output line 40.

[0030] The source follower transistor (SF) 30 and the select transistor (SEL) 32 are n-channel transistors. The source follower transistor (SF) 30 is referred to as an output transistor, and the gate of the source follower transistor (SF) 30 is referred to as a control terminal.

[0031] Figure 3 It is shown Figure 2 1. A timing diagram of the operation of the circuit in FIG. Charge (holes) is injected into the holding capacitor (Csig) by turning on the reset transistor (RST) 12 to reset the photodiode (PD) 10 and then turning on the bias transistor (BIAS) 44 and the switch transistor (SWsig).

[0032] Thereafter, the bias transistor (BIAS) is turned off to discharge the excess charge through the peak hold transistor (PH) 16. Therefore, the holding capacitor (Csig) 26 is placed in a reset state. In this state, the signal supplied from the peak hold transistor (PH) 16 is accumulated in the holding capacitor (Csig) 26 through the switching transistor (SWsig) within one frame period. As described above, the output voltage corresponding to the accumulated charge of the photodiode (PD) 10 is supplied to the gate of the peak hold transistor (PH) 16. Therefore, the charge corresponding to the incident light amount of the photodiode (PD) 10 within one frame period is accumulated in the holding capacitor (Csig) 26.

[0033] When the switch transistor (SWsig) is off and the select transistor (SEL) 32 is on, a voltage signal corresponding to the charge accumulated in the holding capacitor (Csig) 26 is read out to the output line 40. In this example, the readout signal is referred to as a PH-injection signal or a first signal.

[0034] Thereafter, in a state where the bias transistor is turned on, the peak hold transistor (PH) 16 is operated as a source follower circuit, and a signal corresponding to the output voltage of the photodiode (PD) 10 is accumulated in the holding capacitor (Csig) 26. In other words, a charge corresponding to the output voltage of the photodiode (PD) 10 at this time is accumulated in the holding capacitor (Csig) 26. Thereafter, the switch transistor (SWsig) 24 is turned off, the selection transistor (SEL) 32 is turned on, and the signal accumulated in the holding capacitor (Csig) 26 is read out to the output line 40. The signal is referred to as a PH-SF signal or a second signal.

[0035] Flickering occurs

[0036] Figure 4 The flickering state is shown. The previous stage shows the input current corresponding to the incident light amount. In this example, three incidents at different timings are shown, that is, A incident during the first 1 / 3 of a frame period, B incident during the middle 1 / 3 of a frame period, and C incident during the last 1 / 3 of a frame period.

[0037] The middle stage shows the output of the photodiode (PD) 10 and the output of the peak hold transistor (PH) 16 (the voltage PH accumulated in the holding capacitor (Csig) 26 ) in a case where the illuminance is relatively high and the incident light amount is high (high light).

[0038] As shown in the figure, in the case of high light, the output voltage of the photodiode (PD) 10 has the same behavior as the intensity of the incident light. Therefore, the output voltage of the photodiode (PD) 10 at the end of one frame changes with the incident timing. On the other hand, even if light enters at any timing in one frame, the value integrated in the peak hold (PH) circuit is fixed.

[0039] The latter stage shows the output of the photodiode (PD) and the output of the peak hold transistor (PH) 16 (the voltage PH accumulated in the holding capacitor (Csig) 26 ) in a case where the incident light amount is relatively small (low light).

[0040] As shown in the figure, in the case of low light, integration is performed in the photodiode (PD) 10. Therefore, flicker does not occur in the output of the photodiode (PD) 10. However, flicker occurs when integration is performed again in the peak hold circuit. In other words, in the case where light enters at the beginning of a frame, the voltage is maintained even if the incident light disappears after the signal integration, and the integrated signal increases. In contrast, in the case where light enters at the end of a frame, the signal is not integrated at the beginning of a frame, and is only integrated at the end of a frame. In the latter stage, the signal of the light entering at the end of a frame is small.

[0041] Figure 5 1 is a diagram showing the amplitude of the signal Isig which is the output of the photodiode (PD) 10 and the frequency of occurrence of flicker in the PH-injection signal and the PH-SF signal.

[0042] As shown in the figure, in the PH-injection signal, flicker occurs due to double integration in the linear region where the signal Isig is small, while flicker is suppressed by integration in the peak hold (PH) circuit in the logarithmic region where the signal Isig is large. On the other hand, in the case where the PH-SF signal causes the peak hold (PH) circuit to operate as a source follower (SF) circuit, flicker occurs due to changes in the output in the logarithmic region where the signal is large, but flicker does not occur in the linear region where the signal is small because a signal corresponding to the output of the photodiode PD is output.

[0043] In this embodiment, flicker caused by double integration is suppressed by using a PH-injection signal in a logarithmic region where the signal is large and a PH-SF signal in a linear region where the signal is small. This makes it possible to suppress flicker in all regions.

[0044] Image sensor configuration

[0045] Figure 6 2 is a diagram showing an image sensor 200 in which pixels according to an embodiment are arranged two-dimensionally. The pixel array 210 includes the above-mentioned pixels P arranged in m columns*n rows (m*n), that is, m pixels in the horizontal direction and n pixels in the vertical direction. A vertical scanning circuit (vertical scan circuit, V-Scan) 212 sequentially selects rows of pixels P in the vertical direction. The pixels in each column are connected to an analog-to-digital converter (analog-to-digital converter, ADC) 214 through a readout line in the vertical direction. A horizontal scanning circuit (horizontal scan circuit, H-Scan) 216 is connected to the analog-to-digital converter (ADC) 214, and the image signals of the corresponding pixels are sequentially output from the horizontal scanning circuit (H-Scan) 216.

[0046] Figure 7 is a timing chart showing the operation of the image sensor 200 .

[0047] In the (k-1)th row, after the two readouts are completed, the reset transistor (RST) 12 is turned on to reset the photodiode (PD) 10. Reset is performed for each vertical period (1V). Exposure starts after one reset. In addition, the first readout of the signal is performed shortly before the next reset. The readout is performed in the above manner, so that the selection transistor (SEL) 32 is turned on, and the PH-injection signal accumulated in the holding capacitor (Csig) 26 is read out to the analog-to-digital converter (ADC) 214 through the output line 40. The analog-to-digital converter (ADC) 214 converts the PH-injection signal into a digital signal. Here, for simplicity, the analog-to-digital converter (ADC) 214 is omitted. Figure 3 Bias pulse and SWsig pulse in.

[0048] Next, as described above, a PH-SF signal is formed in the holding capacitor (Csig) 26, the selection transistor (SEL) 32 is turned on to read the PH-SF signal to the analog-to-digital converter (ADC) 214, and the PH-SF signal is converted into a digital signal.

[0049] The analog-to-digital converter (ADC) 214 selects the PH-injection signal or the PH-SF signal based on the amplitude of the signal. For example, either the PH-injection signal and the PH-SF signal are compared with a predetermined threshold. In the case where the signal is greater than the predetermined threshold, the PH-SF signal is selected. In the case where the signal is less than the predetermined threshold, the PH-injection signal is selected. A signal that is the sum of the PH-injection signal and the PH-SF signal may also be used.

[0050] As described above, in the case of preparing signals of corresponding pixels, the horizontal scanning circuit (H-Scan) 216 sequentially outputs signals of m pixels.

[0051] Next, in the k-th row, the same operation is performed by shifting the horizontal period by 1 H. The signals of all m*n pixels can be read out by repeating the operation n times.

[0052] It should be noted that the selection of the PH-injection signal or the PH-SF signal may be performed by the above-mentioned ADC 214. Alternatively, the two signals may be output from the image sensor 200 to the outside, and the operation may be performed by an external circuit.

[0053] Modified form 1

[0054] According to the circuit configuration of modification 1, Figure 2 As shown in the general. Figure 8 is a timing chart showing the operation according to Modification 1.

[0055] The gate voltage of the load transistor 48 is set to a DC voltage for the peak hold transistor (PH) 16 to perform a source follower operation.

[0056] In the modification 1, after the first readout of the PH-injection signal is completed, the switch transistor (SWsig) is turned on, and in this state, the bias transistor (bias) 44 is set to the H level in a short period. The peak holding transistor (PH) 16 performs a source follower operation, injects holes into the holding capacitor (Csig) through the switch transistor (SWsig) 24, and discharges excess holes. Therefore, the peak holding circuit is refreshed, and the holding capacitor (Csig) 26 is refreshed to a voltage corresponding to the output voltage of the photodiode (PD) 10.

[0057] Thereafter, the switch transistor (SWsig) 24 is turned off and the selection transistor (SEL) 32 is turned on to read out the signal. The signal is referred to as a PH-refresh signal. In addition, the PH-refresh signal is also referred to as a second signal.

[0058] Modified form 2

[0059] Fig. 9 is a diagram showing a circuit configuration according to Modification 2. As shown in the figure, the source of the peak hold transistor (PH) 16 is connected to the injection power supply 18 , and only the source of the switch transistor (SWsig) is connected to the drain of the peak hold transistor (PH) 16 .

[0060] In Modification 2, holes can be injected into and discharged from the holding capacitor (Csig) 26 by applying a pulse voltage to the drain of the peak hold transistor (PH).

[0061] Fig.10 is a timing chart showing the operation according to Modification 2. After the photodiode (PD) 10 is reset, the injection power source 18 is set to the H level, and holes are injected into the holding capacitor (Csig) 26 through the peak holding transistor (PH) 16 and the switching transistor (SWsig) 24. Thereafter, the injection power source 18 is set to the L level, and excess holes are discharged through the peak holding transistor (PH) 16.

[0062] Thereafter, the switch transistor (SWsig) 24 is turned on and the select transistor (SEL) 32 is turned on to read out the PH-injection signal.

[0063] Subsequently, the injection power supply 18 is set to the H level in a short period to inject holes. The PH circuit is refreshed by releasing the excess holes, and the signal is stored in the holding capacitor (Csig). The voltage of the holding capacitor (Csig) 26 after the refresh corresponds to the gate voltage of the peak holding transistor (PH) 16, that is, the output voltage of the photodiode (PD) 10 at this time. Therefore, the switch transistor (SWsig) 24 is turned off and the selection transistor (SEL) 32 is turned on, which makes it possible to read the signal. The signal read out is called the PH-refresh signal.

[0064] As explained above, in Modification 2, the PH circuit is made to operate as a refresh circuit at the time of the second readout. In the case of the PH-refresh signal, flicker occurs in the logarithmic region where the signal is large, but flicker is eliminated in the linear region where the signal is small.

[0065] Therefore, when the PH-refresh signal is used in the linear region and the PH-injection signal is used in the logarithmic region, flickering in all regions can be suppressed.

[0066] Other Effects

[0067] In general, double integration of a signal reduces the signal level. More specifically, in the case where incident light enters at the beginning of a frame, the signal is integrated. Therefore, even after the incident light disappears, the voltage is maintained and the integrated signal increases. In contrast, in the case where incident light enters at the end of a frame, the signal is not integrated from the beginning of a frame, and the signal corresponds to the PD signal at the end of a frame. This indicates that the incident light entering at the end of a frame is Figure 4 The signal level of light C in the image will decrease.

[0068] Fig.11 PH-SF signal and PH-refresh signal have the same characteristics in the entire range. On the other hand, it is found that the output of the PH-injection signal deteriorates by about 0.66 times in the linear region compared with the PH-SF signal and the PH-refresh signal.

[0069] According to the present embodiment, the PH-SF signal or the PH-refresh signal is used in the linear region, so that the influence of the degradation of the PH-injection signal in the linear region can be avoided.

Claims

1. An image sensor, comprising: a photodiode configured to be reset in each frame period to accumulate charges corresponding to incident light in one frame period and output an output voltage corresponding to the accumulated charges; as well as a holding capacitor configured to accumulate charge corresponding to an output signal of the photodiode, wherein Integrating the output signal of the photodiode within one frame period, accumulating the integrated output signal in the holding capacitor, and outputting a first signal of the holding capacitor, and After the holding capacitor is refreshed, a voltage corresponding to the output voltage of the photodiode is held in the holding capacitor, and a second signal of the holding capacitor is output. 2 . The image sensor according to claim 1 , wherein the photodiode generates charges corresponding to the incident light and is capable of operating in both a linear region and a logarithmic region. 3 . The image sensor according to claim 1 , further comprising a reset transistor configured to reset the accumulated charge of the photodiode.

4. The image sensor according to claim 1, further comprising: a peak holding transistor configured to receive the output signal of the photodiode through a control terminal and output charges from a power supply; a switching transistor configured to control supply of the output of the peak hold transistor to the hold capacitor; as well as a bias transistor configured to cause the peak hold transistor to perform a source follower operation, wherein In a state where the switching transistor is turned on, the output signal of the photodiode in one frame period is integrated, the integrated output signal is accumulated in the holding capacitor, and then the switching transistor is turned off to output the first signal of the holding capacitor, and The switching transistor is turned on and the bias transistor is turned on to refresh the holding capacitor and the peak holding transistor performs the source follower operation, and after the second signal of the holding capacitor corresponding to the output voltage of the photodiode is held in the holding capacitor, the switching transistor is turned off to output the second signal of the holding capacitor.

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