Method for producing power semiconductor device having contact metallization and edge passivation, and power semiconductor device

Abstract

The invention relates to a method for producing a power semiconductor device having a contact metallization and an edge passivation, and to a power semiconductor device. The power semiconductor device has a semiconductor body having a first doping with a front side and a rear side; a basin-shaped region in the semiconductor body at the center of the front side thereof; a second doped edge structure on the front side and in an edge region of the power semiconductor device surrounding the basin-shaped region in a ring shape, the edge region being directly coupled to the basin-shaped region; a first silicon oxide layer in the edge region wherein an outer section of the basin region is also covered; an aluminum alloy having aluminum and at least one additional metal or semimetal; and a passivation, preferably a polyimide passivation, on the outer section of the basin-shaped region and on the edge region.

Description

Technical Field

[0001] The present invention describes a manufacturing method and a power semiconductor device, which has: a first doped semiconductor body having a front side and a rear side; a central tub-shaped area in the semiconductor body on its front side; a second doped edge structure annularly surrounding the tub-shaped area on the front side and in the edge area of ​​the power semiconductor device, wherein the edge area is directly connected to the tub-shaped area; and a contact metallization. Background Art

[0002] DE 10 2014 200 242 A1 discloses a semiconductor component having a semiconductor chip with a semiconductor component region, an aluminum-containing metal layer on the semiconductor component region, and at least one additional metal layer on the aluminum-containing metal layer, which additional metal layer is harder than the aluminum-containing metal layer.

[0003] An inherent disadvantage in such power semiconductor components is the stability with respect to different ambient conditions, even if the power semiconductor components are installed in a power semiconductor module. Summary of the invention

[0004] In the above-mentioned context, the object of the present invention is to specify a method for producing a power semiconductor component and a power semiconductor component which is stable with respect to environmental influences, in particular in offshore use.

[0005] According to the invention, this object is achieved by a method for producing a power semiconductor component in a wafer composite, the method comprising the following production steps:

[0006] a) providing a first doped semiconductor body having a front side and a back side;

[0007] b) forming a central, tub-shaped region of a second doping in the semiconductor body from the front side;

[0008] c) forming a second doped edge structure annularly surrounding the tub-shaped region from the front side and in an edge region of the power semiconductor component, wherein the edge region is directly connected to the tub-shaped region;

[0009] d) forming a first silicon oxide layer in the edge region, wherein an outer section of the tub-shaped region is also covered;

[0010] e) applying an aluminum alloy comprising aluminum and at least one further metal or semi-metal;

[0011] f) Applying a passivation, preferably a polyimide passivation, to the outer section of the trough-shaped region and to the edge region.

[0012] Although the complete production naturally takes place as a wafer composite and the power semiconductor components are only present individually later by singulation of the wafer, the production method is still relevant here with respect to the power semiconductor components.

[0013] It may be advantageous if steps b) and c) are carried out simultaneously and, moreover, if the steps are carried out in the order indicated.

[0014] It may be preferred to construct the edge structure as a plurality of field rings separated from one another. It may be preferred that the first silicon oxide layer has a first window in the region of the field rings. It may also be preferred that the first silicon oxide layer has a further section which is arranged in an outer section of the expansion of the tub-shaped region.

[0015] Alternatively, it may be preferred to design the edge structure as a variable doping region directly adjoining the tub-shaped region, wherein the doping concentration decreases towards the outside.

[0016] It may be particularly advantageous to deposit the aluminum alloy simultaneously on the rear side. It may be preferred here to achieve the deposition of the aluminum alloy by sputtering.

[0017] It is particularly advantageous if the layer thickness of the aluminum alloy is 1 μm to 10 μm, preferably 2 μm to 8 μm and particularly preferably 3 μm to 5 μm.

[0018] Preferably, the aluminum alloy contains at least one element of silicon, magnesium or manganese.

[0019] It may be advantageous that, between steps d) and e), in step d1), polysilicon is deposited on the outer section of the tub-shaped region, in the region of the first window of the annular edge structure and on one or two sections of the first silicon oxide layer that respectively surround these windows. It may be preferred that, following step d1), in step d2), a second silicon oxide layer is produced on the outer section of the tub-shaped region and on the edge region. The second silicon oxide layer is advantageously deposited from tetraethyl orthosilicate (TEOS) by a chemical vapor deposition (CVD) method. Alternatively and by way of example, the second silicon oxide layer can also be deposited as a so-called high-temperature oxide by means of an LPCVD method.

[0020] Furthermore, it may be advantageous if, following step d2), in step e), an aluminum alloy is also applied to the accessible first section of the annular edge structure.

[0021] It is particularly advantageous to deposit a nickel layer on the accessible surface of the aluminum alloy, preferably electrolessly or electroplatingly, and preferably to deposit a palladium layer on the nickel layer. Preferably, the nickel layer has a layer thickness of 0.5 μm to 10 μm, preferably 1 μm to 5 μm, particularly preferably 2 μm to 4 μm, and, if present, the palladium layer has a layer thickness of 0.1 μm to 2 μm, preferably 0.5 μm to 1 μm, particularly preferably 0.7 μm to 0.9 μm.

[0022] Furthermore, it is particularly advantageous if, using the respective layers simultaneously, the nickel layer is deposited on the front side and, if present, the palladium layer is also deposited on the rear side.

[0023] The object is also achieved by a power semiconductor component, which has: a first doped semiconductor body, the semiconductor body having a front side and a rear side; a central tub-shaped region in the semiconductor body on its front side; a second doped edge structure annularly surrounding the tub-shaped region on the front side and in an edge region of the power semiconductor device, wherein the edge region is directly connected to the tub-shaped region; a first silicon oxide layer in the edge region, wherein an outer section of the tub-shaped region is also covered; an aluminum alloy, which has aluminum and at least one further metal or semimetal; a passivation, preferably a polyimide passivation, on an outer section of the tub-shaped region and on the edge region.

[0024] It is understood that the features mentioned above and below within the scope of the method may also be present in the power semiconductor component. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Further explanations, advantageous details and features of the invention are given in the following description of the invention. Figures 1 to 4 The description of the schematically illustrated embodiments or their respective parts is obtained.

[0026] Figures 1 to 4 Four different designs of a power semiconductor device according to the invention produced by means of the method according to the invention are shown in each non-scale illustration. In this case, the designs are based on a single power semiconductor device, although the power semiconductor device is present as a wafer composite during the entire production process and all production steps involve the wafer composite. DETAILED DESCRIPTION

[0027] Figure 1A first embodiment of a power semiconductor device according to the invention is shown, which has a silicon semiconductor body 1 with a first doping, here an n-doping, having a front side 10 and a rear side 12 (the rear side here forms the cathode of the diode). A tub-shaped region 2 with a second doping, here a p-doping, is formed on the front side 10. The tub-shaped region forms the anode of the diode with its metallization, which is also described later, and is arranged centrally on the front side 10 of the diode. The tub-shaped region 2 in its spatial design usually follows the outer contour, i.e. the edge of the diode, in a top view. Thus, in a round power semiconductor device, the tub-shaped region is designed as a circle in a top view, while in a square or rectangular power semiconductor device, the tub-shaped region is designed as such a square or rectangular region in a top view (however, usually with rounded corners).

[0028] The pot-shaped region 2 is surrounded in an annular manner by an edge region 14 of the power semiconductor device or semiconductor body 1, which is directly connected to the pot-shaped region 2 and extends to the outer edge of the power semiconductor device. An edge structure 3 is usually formed in this edge region 14, which has two field rings 30 without limiting the generality. A third doped region 9 is also arranged near the edge of the power semiconductor device, which is a highly n-type doped region in this case.

[0029] A first silicon oxide layer 4 is arranged on the edge region 14 and up to an outer section 20 of the tub-shaped region 2 directly connected to the edge region 14, the first silicon oxide layer having a first window in the center above the field ring 30. The first window is therefore arranged circumferentially around the tub-shaped region 2 and spaced apart from the tub-shaped region. The first window interrupts the first silicon oxide layer 4 only in the center when viewed from the side, but does not interrupt the first silicon oxide layer 4 at the edge of the field ring 30.

[0030] In these windows, a polysilicon layer 6 is arranged, which in this embodiment covers the silicon oxide layer 4 located outside in the lateral direction in sections at the inner field ring of the two field rings 30. The polysilicon layer 6 of the outer field ring of the two field rings 30 covers the first silicon oxide layer 4, covering the inner section and the outer section respectively when viewed in the lateral direction. The thickness of the polysilicon layer 6 is about 500 nm here.

[0031] The accessible sections of the first silicon oxide layer 4 and the polysilicon layer 6 are covered with a deposited second silicon oxide layer 7 which has a layer thickness of approximately 700 nm.

[0032] The accessible region of the tub-shaped region 2 is covered with a sputter-coated aluminum alloy 50 (as contact metallization) with a thickness of 4 μm, which in addition to aluminum as the main component also contains silicon, magnesium or manganese. Preferred mass proportions are 0.7% to 1.3% silicon, 0.6% to 1.2% magnesium and 0.4% to 1.0% manganese.

[0033] A particularly advantageous alternative aluminum alloy contains only magnesium and manganese. Preferred mass proportions for this embodiment are 3.5% to 4.5% magnesium and 0.2% to 0.7% manganese.

[0034] The edge regions of the second silicon oxide layer 7 and the aluminum alloy 50 are covered with a passivation 8 , here a polyimide layer 80 .

[0035] Preferably and in this configuration, the accessible region of the aluminum alloy is covered with a 3 μm thick nickel layer and the nickel layer is covered with a 0.8 μm thick palladium layer. Both layers are deposited here purely by way of example electroplating.

[0036] The rear side 12 of the power semiconductor component also has a layer sequence consisting of an aluminum alloy layer 500 , a nickel layer 520 and a palladium layer 540 , which have the same parameters as the corresponding layers of the front side 10 .

[0037] Figure 2 A second embodiment of a power semiconductor device according to the invention is shown. The second embodiment differs from the first embodiment in that an additional section 40 of the first silicon layer 4 is arranged only on the expanded outer section 22 of the tub-shaped region 2 (which adjoins the outer section 20 when viewed laterally outward).

[0038] In the first window between the additional section 40 and the laterally following section, a polysilicon layer 4 is again arranged. A second silicon oxide layer 7 is arranged on the still accessible surface of the additional section.

[0039] Figure 3 A third embodiment of a power semiconductor device according to the invention is shown, which has a silicon semiconductor body 1 with a first doping, here n-doping, having a front side 10 and a rear side 12 (the rear side forming the cathode of the diode in this case). A second doping, here p-doping, tub-shaped region 2 is again formed on the front side 1.

[0040] The tub-shaped region 2 is surrounded in an annular manner by an edge region 14 of the power semiconductor device, which is directly connected to the tub-shaped region 2 in the lateral direction and extends to the outer edge of the power semiconductor device. An edge structure 3 is usually constructed in this region, which is constructed as a variable doping region 32 here. The doping that decreases outward is shown by a schematic diagram of the doping concentration 320. The variable doping region 32 is directly connected to the tub-shaped region 2 and is advantageously manufactured simultaneously with it. A third doping region 9 is arranged near the edge of the power semiconductor device, which is a highly doped n-type region here.

[0041] An uninterrupted first silicon oxide layer 4 is arranged on the edge region 14 and as far as an outer section 20 of the trough-shaped region 2 directly adjoining the edge region 14 .

[0042] A polysilicon layer 6 is arranged on each of the inner and outer edges of the first silicon oxide layer 4 in a lateral view. The respective polysilicon layer 6 also covers adjacent sections of the first silicon oxide layer 4 .

[0043] The accessible sections of the first silicon oxide layer 4 and the polysilicon layer 6 are covered with a deposited second silicon oxide layer 7 .

[0044] The accessible area of ​​the tub-shaped region 2 is covered with a sputtered aluminum alloy 50 with a thickness of 4 μm, which contains silicon, magnesium and manganese in addition to aluminum as the main component. The aluminum alloy also covers the polysilicon layer 6 and the second silicon oxide layer 7 in the outer section of the tub-shaped region and adjacent thereto.

[0045] The edge regions of the second silicon oxide layer 7 and the aluminum alloy 50 are covered with a passivation layer 8 , here a polyimide layer 80 .

[0046] The accessible regions of the aluminum alloy 50 are covered with a 3 μm thick nickel layer 52, and the nickel layer is covered with a 0.8 μm thick palladium layer 54. Both layers are deposited here purely by way of example in an electroless manner.

[0047] Figure 4 A fourth design solution of a power semiconductor device according to the present invention is shown. The fourth design solution is different from the third design solution in that it does not have a polysilicon layer.

[0048] Of course, similarly to the first configuration, in the fourth configuration, nickel and palladium layers can advantageously be arranged. The rear sides of the third and fourth configurations can also be designed similarly to the first configuration.

Claims

1. A method for producing a power semiconductor component using a wafer composite, the method comprising the following production steps: a) providing a first doped semiconductor body (1) having a front side (10) and a back side (12); b) forming a central, tub-shaped region (2) of a second doping in the semiconductor body from the front side (10); c) forming a second doped edge structure (3) annularly surrounding the tub-shaped region (2) from the front side (10) and in the edge region (14) of the power semiconductor component, wherein: The edge region (14) is directly connected to the basin-shaped region (2); d) forming a first silicon oxide layer (4) in the edge region (14), wherein an outer section (20) of the tub-shaped region (2) is also covered; e) applying an aluminum alloy (50) comprising aluminum and at least one further metal or semi-metal; f) Applying a passivation (8), preferably a polyimide passivation (80), to the outer section (20) of the trough-shaped region (2) and to the edge region (14).

2. The method according to claim 1, wherein: Steps b) and c) are performed simultaneously.

3. The method according to claim 2, wherein: The edge structure (3) is constructed as a plurality of mutually separated field rings (30).

4. The method according to claim 2, wherein: The edge structure (3) is configured as a variable doping region (32) directly connected to the tub-shaped region, wherein the doping concentration (320) decreases gradually toward the outside.

5. The method according to claim 3, wherein: The first silicon oxide layer (4) has a first window in the region of the field ring (30).

6. The method according to any one of claims 1 to 4, wherein: The first silicon oxide layer (4) has a further section (40) which is arranged in an expanded outer section (22) of the tub-shaped region (2).

7. The method according to any one of claims 1 to 4, wherein: The aluminum alloy is deposited simultaneously on the rear side (12).

8. The method according to any one of claims 1 to 4, wherein: The aluminum alloy (50) is deposited by means of sputtering.

9. The method according to any one of claims 1 to 4, wherein: The layer thickness of the aluminum alloy ( 50 ) is 1 μm to 10 μm, preferably 2 μm to 8 μm, and particularly preferably 3 μm to 5 μm.

10. The method according to any one of claims 1 to 4, wherein: The aluminum alloy (50) contains at least one element of silicon, magnesium or manganese.

11. The method according to any one of claims 1 to 4, wherein: Between steps d) and e), in step d1), a polysilicon layer (6) is deposited on an outer section (20) of the tub-shaped region (2), in the region of a window of the annular edge structure (3) and on one or two sections of the first silicon oxide layer (4) respectively surrounding the window.

12. The method according to claim 11, wherein: Following step d1), in step d2), a second silicon oxide layer (7) is produced on the outer section (20) of the trough-shaped region (2) and on the edge region (14).

13. The method according to claim 12, wherein: Following step d2), in step e), the aluminum alloy is also applied to a central section of the annular edge structure (3) that is accessible via the second window.

14. The method according to any one of claims 1 to 4, wherein: A nickel layer (52) is deposited on the accessible surface of the aluminum alloy (50), preferably in an electroless manner or in an electrolytic manner, and a palladium layer (54) is preferably deposited on the nickel layer.

15. The method according to claim 14, wherein: The nickel layer has a layer thickness of 0.5 to 10 μm, preferably 1 to 5 μm, particularly preferably 2 to 4 μm, and the palladium layer, if present, has a layer thickness of 0.1 to 2 μm, preferably 0.5 to 1 μm, particularly preferably 0.7 to 0.9 μm.

16. The method according to claim 14, wherein: Simultaneously, using the respective layers, a nickel layer (520) is deposited on the front side (10) and, if present, a palladium layer (540) is also deposited on the rear side (12).

17. A power semiconductor device, comprising: a first doped semiconductor body (1), the semiconductor body having a front side (10) and a rear side (12); a central tub-shaped region (2) in the semiconductor body on its front side (10); a second doped edge structure (3) on the front side (10) and in an edge region (14) of the power semiconductor device, the second doped edge structure (3) surrounding the tub-shaped region (2) in an annular manner, wherein: The edge region (14) is directly connected to the tub-shaped region (2); a first silicon oxide layer (4) in the edge region (14), wherein an outer section (20) of the tub-shaped region (2) is also covered; an aluminum alloy (50), the aluminum alloy comprising aluminum and at least one other metal or semi-metal; a passivation (8), preferably a polyimide passivation (80), on the outer section (20) of the tub-shaped region (2) and on the edge region (14).

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