Power semiconductor device and preparation method thereof

Abstract

The invention relates to a power semiconductor device and a preparation method thereof. The power semiconductor device comprises a substrate, a main junction structure, a plurality of field ring structures, a first insulating layer and an electrode layer, the substrate comprises a cellular area and a terminal area, the main junction structure is located in the cellular area, the field ring structures are located in the terminal area, the field ring structures are arranged in an isolated mode in the first direction, and the first direction is the direction from the cellular area to the terminal area; the plurality of field ring structures comprise at least one first field limiting ring and at least one cut-off ring, the cut-off ring is located on one side of the first field limiting ring along the first direction, the first insulating layer is located on one side of the main junction structure and the field ring structures far away from the substrate, and the electrode layer is located on one side of the first insulating layer far away from the substrate and comprises a first field plate; the first field plate covers the part, close to the field ring structure, of the main junction structure and at least one first field limiting ring close to the main junction structure, and the first field plate is electrically connected with the main junction structure. According to the technical scheme, the voltage endurance capability and the dielectric breakdown reliability of the device can be improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a power semiconductor device and a preparation method thereof. Background Art

[0002] Among the related technologies, power semiconductor devices, as one of the core and basic devices of electronic power technology, play a vital role in the fields of energy, manufacturing, transportation, consumer electronics, etc. Insulated Gate Bipolar Transistor (IGBT) is a typical power semiconductor device, with the advantages of low on-state voltage drop, high input impedance, fast switching speed, and low switching loss. It is widely used in energy, transportation, information, medical and other fields. For example, in today's popular electric vehicles, IGBT is the core module of the drive system, accounting for about 10% of the cost of the whole vehicle. Even its charging piles are dominated by IGBT, accounting for about 20% of the cost.

[0003] IGBT is often used in high-voltage applications, so it needs to meet certain voltage levels and reliability. The cylindrical junction or planar junction of the IGBT cell has insufficient curvature, concentrated electric field, and is prone to electrical breakdown. Therefore, field limiting rings are often added to the terminal to reduce the phenomenon of electric field concentration. At the same time, the electric field distribution in the terminal area can improve the overall withstand voltage and meet the use requirements.

[0004] In the related technology, the field limiting rings commonly used will form spherical junctions at the corners of the layout. The electric field strength is much greater than that of the cylindrical junction. In addition, the main junction structure and the first field limiting ring have the smallest radius of curvature among all field limiting rings, and are most likely to break down at the corners, causing device failure. Generally, the field limiting rings are used with field plates (polysilicon (poly) field plates or metal field plates) to optimize the electric field.

[0005] The field limiting ring-field plate used in the related art will change the surface electric field distribution due to the change of interface states (defects, charges, etc.) in the actual use of the device, especially the curved junction at the edge of the main junction structure forms a spherical junction at the corner of the layout with the smallest curvature radius, which is prone to breakdown, resulting in device failure. In addition, using additional processes to solve the problem of dielectric breakdown reliability will increase the process cycle and cost. Summary of the invention

[0006] The purpose of the present application is to provide a power semiconductor device and a method for preparing the same, which can improve the voltage resistance and dielectric breakdown reliability of the device during use by optimizing the structure of the field plate.

[0007] According to a first aspect of an embodiment of the present application, there is provided a power semiconductor device, including: A substrate, wherein the substrate is divided into a cell region and a terminal region, and the terminal region is located at the periphery of the cell region; A main junction structure, located on the first side of the substrate and within the cell region; A plurality of field ring structures are located on a first side of the substrate and in the terminal region, the plurality of field ring structures are isolated and arranged along a first direction, the first direction is a direction from the cell region to the terminal region, the plurality of field ring structures include at least one first field limiting ring and at least one cut-off ring, the cut-off ring is located on one side of at least one first field limiting ring along the first direction; A first insulating layer is located on a side of the main junction structure and the plurality of field ring structures away from the substrate; An electrode layer is located on a side of the first insulating layer away from the substrate, the electrode layer includes a first field plate, the first field plate covers a portion of the main junction structure close to the field ring structure and at least one first field limiting ring close to the main junction structure, and the first field plate is electrically connected to the main junction structure.

[0008] In one implementation, the number of the first field limiting rings covered by the first field plate is determined according to a minimum withstand voltage value of the power semiconductor device.

[0009] In one implementation, the first field plate covers one of the first field limiting rings; or, the first field plate covers two of the first field limiting rings.

[0010] In one embodiment, the plurality of field ring structures further include: at least one second field limiting ring, located between the first field limiting ring and the cut-off ring, and isolatedly arranged along a first direction; The electrode layer further comprises: At least one second field plate is located on a side of the first insulating layer away from the substrate, the first field plate and the at least one second field plate are insulated and arranged along a first direction, the number of the second field plates is the same as the number of the second field limiting rings, at least one second field plate is electrically connected to at least one second field limiting ring in a one-to-one correspondence, and for the electrically connected second field plates and second field limiting rings, the second field plate at least covers a portion of the second field limiting ring.

[0011] In one embodiment, the electrode layer further comprises: At least one third field plate is located on a side of the first insulating layer away from the substrate, the first field plate, at least one of the second field plates and at least one of the third field plates are insulated and arranged along a first direction, the number of the third field plates is the same as the number of the cut-off rings, at least one of the third field plates is electrically connected to at least one of the cut-off rings in a one-to-one correspondence, and for the electrically connected third field plates and the cut-off rings, the third field plate at least covers a portion of the cut-off rings.

[0012] In one embodiment, the power semiconductor device further includes: A plurality of through-hole structures penetrate the first insulating layer, the through-hole structures comprising a first through-hole, at least one second through-hole and at least one third through-hole, the first field plate contacts the main junction structure through the first through-hole, at least one of the second field plates contacts different second field limiting rings through different second through-holes, and at least one of the third field plates contacts different cut-off rings through different third through-holes.

[0013] In one embodiment, the first insulating layer comprises: There are multiple silicon local oxidation isolation structures and multiple punched portions, the silicon local oxidation isolation structures and the punched portions are alternately arranged, there is one silicon local oxidation isolation structure between the main junction structure and two adjacent structures in the multiple field ring structures, there is one punched portion on each of the main junction structure and the multiple field ring structures, and the multiple through-hole structures respectively penetrate different punched portions.

[0014] In one embodiment, the power semiconductor device further includes: The second insulating layer is located on a side of the first insulating layer away from the substrate, the second insulating layer includes a plurality of insulating portions, and one insulating portion exists between two adjacent field plates among the first field plate, at least one of the second field plates, and at least one of the third field plates.

[0015] According to a second aspect of an embodiment of the present application, a method for preparing a power semiconductor device is provided, for preparing the above-mentioned power semiconductor device, the method comprising: providing the substrate; forming the main junction structure and a plurality of the field ring structures on a surface of the first side of the substrate; forming the first insulating layer on a side of the main junction structure and the plurality of field ring structures away from the substrate; The electrode layer is formed on a side of the first insulating layer away from the substrate.

[0016] In one embodiment, when the power semiconductor device includes a plurality of the through-hole structures and the first insulating layer includes a plurality of perforated portions, after the first insulating layer is formed on a side of the main junction structure and the plurality of the field ring structures away from the substrate and before the electrode layer is formed on a side of the first insulating layer away from the substrate, the method further includes: Punching holes on the punching portion using a punching process to form a plurality of openings; Depositing metal material in the plurality of openings to form the plurality of through-hole structures; wherein depositing metal material in the plurality of openings to form the plurality of through-hole structures and forming the electrode layer on a side of the first insulating layer away from the substrate belong to the same process.

[0017] Compared with the prior art, the beneficial effects of the present application are as follows: since the power semiconductor device includes: a substrate, a main junction structure, a plurality of field ring structures, a first insulating layer and an electrode layer, the substrate is divided into a cell region and a terminal region, the terminal region is located at the periphery of the cell region, the main junction structure is located at a first side of the substrate and is located in the cell region, the plurality of field ring structures are located at a first side of the substrate and are located in the terminal region, the plurality of field ring structures are isolated and arranged along a first direction, the first direction is the direction from the cell region to the terminal region, the plurality of field ring structures include at least one first field limiting ring and at least one cut-off ring, the cut-off ring is located on one side of the at least one first field limiting ring along the first direction, the first insulating layer is located on a side of the main junction structure and the plurality of field ring structures away from the substrate, the electrode layer is located on a side of the first insulating layer away from the substrate, and the electrode layer includes The first field plate covers a portion of the main junction structure close to the field ring structure and at least one first field limiting ring close to the main junction structure. The first field plate is electrically connected to the main junction structure but not to the first field limiting ring covered by it. In this way, during the use of the device, the electric potential of the field plate on the first field limiting ring is the electric potential of the field plate on the main junction structure, that is, 0 volts. This is equivalent to applying a higher negative voltage to the bias field plate (the first field plate), which can further reduce the peak electric field on the surface close to the main junction. Moreover, since the first field plate covers a larger area, the effective area acting on the substrate surface is also increased, resulting in more carriers being repelled, thereby reducing the peak electric field on the surface close to the main junction. At the same time, the electric field strength inside the substrate will be increased, thereby improving the voltage resistance of the device as a whole.

[0018] Moreover, since the main junction structure and the field limiting ring close to the cell are close to the cell, the electric field at the edge of the main junction structure and the field limiting ring at the corner in the layout is larger, the distortion is stronger, and destructive breakdown is more likely to occur. In the present application, the maximum surface electric field peak is transferred from the edge of the main junction structure to the first field limiting ring, the second field limiting ring or other field limiting rings, which can increase the distance between the maximum surface electric field peak and the cell, increase the curvature radius of the corner at the maximum surface electric field peak, and further reduce the maximum electric field peak at the device corner, which can reduce the occurrence of dielectric breakdown and improve the reliability of device dielectric breakdown.

[0019] In summary, the technical solution provided in the present application can improve the voltage resistance and dielectric breakdown reliability of the device during use by optimizing the structure of the field plate.

[0020] Moreover, the process flow for preparing the power semiconductor device provided in the present application is not increased and is the same as the process flow for preparing the power semiconductor device in the related art, which does not increase the process cycle and cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 The diagram is a schematic structural diagram of a power semiconductor device according to an exemplary embodiment.

[0022] Figure 2 It is a schematic structural diagram of a power semiconductor device according to the related art.

[0023] Figure 3 Yes Figure 1 The power semiconductor devices shown are Figure 2 Schematic diagram of one-dimensional electric field distribution comparison of insulated gate bipolar transistors shown.

[0024] Figure 4 is a schematic structural diagram of a power semiconductor device according to another exemplary embodiment.

[0025] Figure 5 Yes Figure 4 The power semiconductor devices shown are Figure 2 Schematic diagram of one-dimensional electric field distribution comparison of insulated gate bipolar transistors shown.

[0026] Figure 6 is a flow chart of a method for preparing a power semiconductor device according to another exemplary embodiment.

[0027] Figure 7 is a flow chart of a method for preparing a power semiconductor device according to another exemplary embodiment.

[0028] Description of reference numerals: 11: substrate, 12: main junction structure, 13: field ring structure, 131: first field limiting ring, 132: second field limiting ring, 134: cut-off ring, 14: first insulating layer, 141: silicon local oxidation isolation structure, 142: punching portion, 15: electrode layer, 151: first field plate, 152: second field plate, 153: third field plate, 16: cut-off layer, 17: collector region, 18: through-hole structure, 181: first through-hole, 182: second through-hole, 183: third through-hole, 19: second insulating layer. DETAILED DESCRIPTION

[0029] Unless otherwise defined, the technical terms or scientific terms used in this specification and claims shall have the usual meanings understood by persons with ordinary skills in the technical field to which the invention belongs. The specific embodiments of the present invention will be described below in conjunction with the accompanying drawings. It should be noted that in the specific description of these embodiments, in order to provide a concise description, it is impossible for this specification to provide a detailed description of all the features of the actual embodiments. Without departing from the spirit and scope of the present invention, those skilled in the art may modify and replace the embodiments of the present invention, and the resulting embodiments are also within the scope of protection of the present invention.

[0030] An embodiment of the present application provides a power semiconductor device. The power semiconductor device may be an insulated gate bipolar transistor, but is not limited thereto. Figure 1 As shown, the power semiconductor device may include: a substrate 11 , a main junction structure 12 , a plurality of field ring structures 13 , a first insulating layer 14 and an electrode layer 15 .

[0031] like Figure 1 As shown, the substrate 11 is divided into a cell region and a terminal region, and the terminal region is located at the periphery of the cell region.

[0032] In one embodiment, the conductivity type of the substrate 11 may be a first conductivity type (eg, N type), but is not limited thereto. The substrate 11 is used to provide a drift region of the first conductivity type.

[0033] In one embodiment, Figure 1 As shown, the substrate 11 may include a cutoff layer 16 and a collector region 17. The cutoff layer 16 is also known as a field stop layer (FS layer for short). The conductivity type of the cutoff layer 16 may be a first conductivity type (e.g., N type), and the doping concentration is greater than the doping concentration of the substrate 11, that is, the cutoff layer 16 is an N+ type cutoff layer. The conductivity type of the collector region 17 may be a second conductivity type (e.g., P type), but is not limited thereto.

[0034] In one embodiment, Figure 1As shown, the main junction structure 12 is located on the first side of the substrate 11 and is located in the cell region. The conductivity type of the main junction structure 12 may be the second conductivity type (e.g., P type), and the main junction structure 12 may be a P+ type main junction structure 12, which is generally obtained by injecting P type doping into the substrate 11, and the P type doping may be boron ions or gallium (Ga) ions, but is not limited thereto. The main junction structure 12 may be connected to the emitter through a metal electrode.

[0035] In one embodiment, Figure 1 As shown, a plurality of field ring structures 13 are located on the first side of the substrate 11 and in the terminal region. The plurality of field ring structures 13 are isolated and arranged along a first direction, which is a direction from the cell region to the terminal region.

[0036] like Figure 1 As shown, the plurality of field ring structures 13 include at least one first field limiting ring 131 and at least one cut-off ring 134 , and the cut-off ring is located on one side of the at least one first field limiting ring 131 along the first direction.

[0037] In one embodiment, Figure 1 As shown, the plurality of field ring structures 13 include a first field limiting ring 131 and a cut-off ring 134. The first field limiting ring 131 and the cut-off ring 134 are arranged in isolation along a first direction.

[0038] In one embodiment, Figure 1 As shown, the first insulating layer 14 is located on a side of the main junction structure 12 and the plurality of field ring structures 13 away from the substrate 11. The material of the first insulating layer 14 may be silicon oxide, but is not limited thereto.

[0039] In one embodiment, Figure 1 As shown, the first insulating layer 14 includes: a plurality of silicon local oxidation isolation structures 141 and a plurality of perforated portions 142 .

[0040] like Figure 1 As shown, the silicon local oxidation isolation structure 141 and the perforated portion 142 are alternately arranged, and the thickness of the silicon local oxidation isolation structure 141 is greater than the thickness of the perforated portion 142. There is a silicon local oxidation isolation structure 141 between the main junction structure 12 and two adjacent structures in the plurality of field ring structures 13, and the silicon local oxidation isolation structure 141 is used to isolate the two adjacent structures. There is a perforated portion 142 on each structure of the main junction structure 12 and the plurality of field ring structures 13.

[0041] In one embodiment, the local oxidation of silicon isolation structure 141 may be prepared by a local oxidation of silicon isolation (LOCOS) process. The surface of the local oxidation of silicon isolation structure 141 away from the substrate 11 may be a plane. Figure 1The silicon local oxidation isolation structure 141 is obtained by preparing an initial isolation structure by using a silicon local oxidation isolation process, and then performing chemical mechanical planarization (CMP) on the initial isolation structure to make it flat.

[0042] In another embodiment, the silicon local oxidation isolation structure 141 may be an initial isolation structure prepared by a silicon local oxidation isolation process, and may be a complete initial isolation structure without undergoing CMP.

[0043] In one embodiment, after the silicon local oxidation isolation structure 141 is formed by a silicon local oxidation isolation process, the perforated portion 142 may be formed by a deposition process.

[0044] In one embodiment, the conductivity type of the first field limiting ring 131 may be the second conductivity type (eg, P type), but is not limited thereto.

[0045] In one embodiment, the conductivity type of the cutoff ring 134 may be a first conductivity type (eg, N type), but is not limited thereto.

[0046] In one embodiment, Figure 1 As shown, the electrode layer 15 is located on a side of the first insulating layer 14 away from the substrate 11. The material of the electrode layer 15 may include a metal material, but is not limited thereto.

[0047] In one embodiment, Figure 1 As shown, the electrode layer 15 includes a first field plate 151, which covers a portion of the main junction structure 12 close to the field ring structure 13 and at least one first field limiting ring 131 close to the main junction structure 12, and the first field plate 151 is electrically connected to the main junction structure 12. The first field limiting ring 131 covered by the first field plate 151 is not electrically connected to the first field plate 151.

[0048] In one embodiment, the material of the electrode layer 15 may include copper-aluminum alloy, which is deposited by using an aluminum alloy target and a PVD (Physical Vapor Deposition) process. However, the material of the electrode layer 15 is not limited to copper-aluminum alloy.

[0049] It should be noted that the more first field limiting rings 131 are covered by the first field plates 151, the lower the withstand voltage of the device. Therefore, the number of first field limiting rings 131 covered by the first field plates 151 can be determined according to the lowest withstand voltage value of the power semiconductor device.

[0050] In one embodiment, Figure 1As shown, the first field plate 151 covers a portion of the main junction structure 12 close to the field ring structure 13 and a first field limiting ring 131 close to the main junction structure 12 .

[0051] In one embodiment, Figure 1 As shown, the plurality of field ring structures 13 further include: at least one second field limiting ring 132 , for example, may include two second field limiting rings 132 .

[0052] It should be noted that the first field limiting ring 131 and the second field limiting ring 132 are identical in structure and manufacturing process. For ease of description, the field limiting ring covered by the first field plate 151 is named the first field limiting ring 131 , and the field limiting ring not covered by the first field plate 151 is named the second field limiting ring 132 .

[0053] In one embodiment, Figure 1 As shown, at least one second field limiting ring 132 is located between the first field limiting ring 131 and the cut-off ring 134 and is isolated and arranged along the first direction. The first field limiting ring 131, the second field limiting ring 132, and the cut-off ring 134 are isolated and arranged along the first direction.

[0054] In one embodiment, the conductivity type of the second field limiting ring 132 may be the second conductivity type (eg, P type), but is not limited thereto.

[0055] In one embodiment, Figure 1 As shown, the electrode layer 15 further includes: at least one second field plate 152 and at least one third field plate 153. For example, the electrode layer 15 may include: two second field plates 152 and one third field plate 153.

[0056] like Figure 1 As shown, at least one second field plate 152 is located on a side of the first insulating layer 14 away from the substrate 11. The first field plate 151 and at least one second field plate 152 are insulated and arranged along the first direction, the number of the second field plates 152 is the same as the number of the second field limiting rings, at least one second field plate 152 is electrically connected to at least one second field limiting ring 132 in a one-to-one correspondence, and for the electrically connected second field plate 152 and second field limiting ring 132, the second field plate 152 at least covers a portion of the second field limiting ring 132. For example, the first field plate 151 and two second field plates 152 are insulated and arranged along the first direction, and the two second field plates 152 are electrically connected to the two second field limiting rings 132 in a one-to-one correspondence.

[0057] like Figure 1As shown, the third field plate 153 is located on a side of the first insulating layer 14 away from the substrate 11. The first field plate 151, at least one second field plate 152 and at least one third field plate 153 are insulated and arranged along the first direction, the number of the third field plates 153 is the same as the number of the cut-off rings 134, at least one third field plate 153 is electrically connected to at least one cut-off ring 134 in a one-to-one correspondence, and for the electrically connected third field plate 153 and the cut-off ring 134, the third field plate 153 at least covers a portion of the cut-off ring 134. For example, the first field plate 151, two second field plates 152 and one third field plate 153 are insulated and arranged along the first direction, one third field plate 153 is electrically connected to one cut-off ring 134, and the third field plate 153 at least covers a portion of the cut-off ring 134.

[0058] In one embodiment, Figure 1 As shown, the power semiconductor device further includes: a plurality of through-hole structures 18 .

[0059] like Figure 1 As shown, a plurality of through-hole structures 18 penetrate the first insulating layer 14. Specifically, the plurality of through-hole structures 18 respectively penetrate different perforated portions 142. The through-hole structure 18 includes a first through-hole 181, at least one second through-hole 182, and at least one third through-hole 183. For example, the through-hole structure 18 includes a first through-hole 181, two second through-holes 182, and a third through-hole 183.

[0060] like Figure 1 As shown, the first field plate 151 contacts the main junction structure 12 through the first through hole 181. The orthographic projection of the first through hole 181 on the substrate 11 is located within the orthographic projection of the main junction structure 12 on the substrate 11, and is also located within the orthographic projection of the first field plate 151 on the substrate 11.

[0061] like Figure 1 As shown, at least one second field plate 152 contacts different field limiting rings through different second through holes 182 , for example, two second field plates 152 contact different second field limiting rings 132 through different second through holes 182 .

[0062] like Figure 1 As shown, at least one third field plate 153 contacts different cut-off rings 134 through different third through holes 183 , respectively. For example, one third field plate 153 contacts the cut-off ring 134 through the third through hole 183 .

[0063] In one embodiment, Figure 1 As shown, the power semiconductor device further includes: a second insulating layer 19 .

[0064] like Figure 1As shown, the second insulating layer 19 is located on the side of the first insulating layer 14 away from the substrate 11 , and the second insulating layer 19 includes a plurality of insulating portions 191 . An insulating portion 191 exists between two adjacent field plates among the first field plate 151 , at least one second field plate 152 and at least one third field plate 153 .

[0065] In one embodiment, the second insulating layer 19 may include a passivation layer and a protective layer, wherein the passivation layer is located on a side of the first insulating layer 14 away from the substrate 11, and the protective layer is located on a side of the passivation layer away from the substrate 11. The second insulating layer 19 may not be limited to a combination of a passivation layer and a protective layer.

[0066] In one embodiment, the material of the passivation layer may include silicon nitride, and the passivation layer may be prepared by a PECVD (Plasma-Enhanced Chemical Vapor Deposition) process. The material of the passivation layer is not limited to silicon nitride.

[0067] In one embodiment, the material of the protective layer may include polyimide, and the protective layer may be prepared by a coating process. The material of the protective layer may not be limited to polyimide.

[0068] In the embodiment of the present application, since the electrode layer 15 includes the first field plate 151, the first field plate 151 covers the portion of the main junction structure 12 close to the field ring structure 13 and at least one first field limiting ring 131 close to the main junction structure 12, and the first field plate 151 is electrically connected to the main junction structure 12, but not to the first field limiting ring 131 covered by it. In this way, during the use of the device, the potential of the field plate on the first field limiting ring 131 is the potential of the field plate on the main junction structure 12, that is, 0 volts, which is equivalent to applying a higher negative voltage to the bias field plate (the first field plate 151), which can further reduce the peak electric field on the surface close to the main junction. Moreover, since the first field plate 151 covers a larger area, the effective area acting on the surface of the substrate 11 is also increased, resulting in more carriers being repelled, thereby reducing the peak electric field on the surface close to the main junction. At the same time, the electric field strength inside the substrate 11 will be increased, thereby improving the withstand voltage capability of the device as a whole.

[0069] Moreover, since the main junction structure 12 and the field limiting ring close to the cell are close to the cell, the electric field at the edge of the main junction structure 12 and the field limiting ring at the corner in the layout is larger, the distortion is stronger, and destructive breakdown is more likely to occur. In the present application, the maximum surface electric field peak is transferred from the edge of the main junction structure 12 to the first field limiting ring, the second field limiting ring or other field limiting rings in the first direction, which can increase the distance between the maximum surface electric field peak and the cell, increase the curvature radius of the corner at the maximum surface electric field peak, and further reduce the maximum electric field peak at the corner of the device, which can reduce the occurrence of dielectric breakdown and improve the reliability of dielectric breakdown of the device.

[0070] Figure 2 It is a schematic diagram of the structure of an insulated gate bipolar transistor (IGBT) in the related art. Figure 2 As shown, the insulated gate bipolar transistor may include: a P-type main junction 100, a plurality of fourth field limiting rings 101, a plurality of fourth through holes 102, a silicon local oxidation isolation portion 103, an N-type cutoff ring 104, a thin oxide layer 105, an insulating dielectric layer 106, a metal field plate 107, an N-type drift region 108, an N+ type cutoff layer 109 and a P-type collector region 110. The metal field plate 107 connected to the P-type main junction 100 does not cover the fourth field limiting ring 101, and there is a metal field plate 107 electrically connected to each fourth field limiting ring 101, and there is also a metal field plate 107 electrically connected to the N-type cutoff ring 104. There is a thick oxide layer (silicon local oxidation isolation portion 103) under the metal field plate 107 to weaken the electric field strength to prevent the device from breaking down under the high electric field of the field plate, resulting in device failure.

[0071] Figure 3 Yes Figure 1 The power semiconductor devices shown are Figure 2 The one-dimensional electric field distribution comparison diagram of the insulated gate bipolar transistor shown in FIG. Figure 2 The electric field distribution curve of the insulated gate bipolar transistor shown in FIG. 2 is Figure 1 The electric field distribution curve of the power semiconductor device shown. Figure 3 In FIG. 1 , the horizontal axis is the length along the lateral direction of the device, the origin is the main junction structure 12, and the unit is micrometer, and the vertical axis is the electric field strength, and the unit is volt per centimeter (V / cm).

[0072] In the right Figure 1 When simulating the electric field of the power semiconductor device shown, the fact that the first insulating layer 14 (oxide layer) is charged has been taken into account. Figure 3 It can be seen that Figure 1 The surface electric field ratio of the power semiconductor device in this application is shown Figure 2The electric field strength of the insulated gate bipolar transistor in the related art shown is reduced, and the maximum electric field strength appears at the second electric field peak (counting from left to right), that is, it is transferred from the curved junction at the edge of the P-type main junction 100 in the related art to the first field limiting ring 131 (the first field ring structure 13). While reducing the maximum electric field strength, the curvature radius of the corner at the maximum surface electric field peak is increased, further reducing the maximum electric field peak at the corner of the device, further reducing the breakdown risk, and enhancing the dielectric breakdown reliability.

[0073] in addition, Figure 2 The withstand voltage of the insulated gate bipolar transistor in the related art shown is 1192V, while Figure 1 The structural withstand voltage of the power semiconductor device shown in the present application is 1317V, which improves the withstand voltage level while enhancing reliability.

[0074] In summary, the technical solution provided in the present application can, without increasing the area of ​​the power semiconductor device, change the potential and electric field flux distribution by optimizing the structure of the field plate, so as to redistribute the surface electric field and improve the voltage resistance and dielectric breakdown reliability of the device during use.

[0075] Another embodiment of the present application provides a power semiconductor device. Figure 4 As shown, Figure 1 The difference from the embodiment shown is that in this embodiment, in the power semiconductor device, the first field plate 151 covers the portion of the main junction structure 12 close to the field ring structure 13 and the two first field limiting rings 131 close to the main junction structure 12. The first field plate 151 contacts the main junction structure 12 through the first through hole 181, and the two first field limiting rings 131 covered by the first field plate 151 are not electrically connected to the first field plate 151.

[0076] Figure 5 Yes Figure 4 The power semiconductor devices shown are Figure 2 The one-dimensional electric field distribution comparison diagram of the insulated gate bipolar transistor in the related art is shown. Among them, curve 1 is Figure 2 The electric field distribution curve of the insulated gate bipolar transistor shown in FIG. 3 is Figure 4 The electric field distribution curve of the power semiconductor device shown. Figure 5 In FIG. 1 , the horizontal axis is the length along the lateral direction of the device, the origin is the main junction structure 12, and the unit is micrometer, and the vertical axis is the electric field strength, and the unit is volt per centimeter (V / cm).

[0077] In the right Figure 4 When simulating the electric field of the power semiconductor device shown, the fact that the first insulating layer 14 (oxide layer) is charged has been taken into account. Figure 5 It can be seen that Figure 4The surface electric field ratio of the power semiconductor device in this application is shown Figure 2 The electric field strength of the insulated gate bipolar transistor in the related technology shown is reduced, and the maximum electric field strength appears at the fourth electric field peak (counting from left to right), that is, it is transferred from the curved junction at the edge of the P-type main junction 100 in the related technology to the second field limiting ring (the third field ring structure 13). While reducing the maximum electric field strength, the curvature radius of the corner at the maximum surface electric field peak is increased, further reducing the maximum electric field peak at the corner of the device, further reducing the breakdown risk, and enhancing the dielectric breakdown reliability.

[0078] In addition, the withstand voltage of the insulated gate bipolar transistor in the related art is 1192V, while Figure 4 The structural withstand voltage of the power semiconductor device shown in the present application is 1300V, which improves the withstand voltage level while enhancing reliability.

[0079] In addition, since the main junction structure 12 is prone to drift and gather carriers, the high electric field here is prone to thermal breakdown and device failure. The technical solution provided by the present application disperses the electric field strength at the main junction structure 12 and enhances the electric field strength of the field limiting ring far away from the main junction structure 12, thereby ensuring both reliability and voltage resistance.

[0080] In summary, the technical solution provided in this application can optimize the structure of the field plate, change the potential and electric field flux distribution, and redistribute the surface electric field, thereby further improving the voltage resistance and dielectric breakdown reliability of the device during use.

[0081] Another exemplary embodiment of the present application further provides a method for preparing a power semiconductor device, which is used to prepare the power semiconductor device of any of the above embodiments. Figure 6 As shown, the method for preparing the power semiconductor device may include the following steps S601 to S604: Step S601, providing a substrate.

[0082] In this step, a substrate 11 of a first conductive type (eg, N-type) may be provided. The substrate 11 is divided into a cell region and a terminal region, and the terminal region is located at the periphery of the cell region.

[0083] Step S602 , forming a main junction structure and a plurality of field ring structures on a surface of a first side of the substrate.

[0084] The plurality of field ring structures 13 include a first field limiting ring 131 , a second field limiting ring 132 and a cut-off ring 134 .

[0085] In this step, a photolithography process may be used to define a main junction region where the main junction structure 12 is located on the surface of the first side of the substrate 11 , and then an ion implantation process may be used to implant ions into the main junction region to form the main junction structure 12 .

[0086] In this step, a field ring mask can be used to define a field ring region where the field ring structure 13 is located on the N-type substrate 11. The field ring region includes a first field limiting ring region where the first field limiting ring 131 is located, a second field limiting ring region where the second field limiting ring 132 is located, and a stop ring region where the stop ring 134 is located.

[0087] Then, an ion implantation process is used to implant P-type doping into the first field limiting ring region and the second field limiting ring region, and a thermal process is performed to form the first field limiting ring 131 and the second field limiting ring 132. An ion implantation process is used to implant N-type doping into the stop ring region to form a stop ring 134. For example, the P-type doping may be boron ions or gallium (Ga) ions, but is not limited thereto. The N-type doping may be phosphorus (P) ions, arsenic (As) ions, or antimony (Sb) ions, but is not limited thereto.

[0088] Step S603 , forming a first insulating layer on a side of the main junction structure and the plurality of field ring structures away from the substrate.

[0089] The first insulating layer 14 includes: a plurality of silicon local oxidation isolation structures 141 and a plurality of perforated portions 142. The plurality of silicon local oxidation isolation structures 141 are used to isolate two adjacent structures of the main junction structure 12 and the plurality of field ring structures 13. A perforated portion 142 exists on each of the main junction structure 12 and the plurality of field ring structures 13. A portion of the perforated portions 142 is used to set a through-hole structure 18.

[0090] In one embodiment, a plurality of silicon local oxidation isolation structures 141 may be prepared by a silicon local oxidation isolation process, and then a plurality of punching portions 142 may be prepared by a deposition process, thereby obtaining the first insulating layer 14 .

[0091] In one embodiment, Figure 1 As shown, when the surface of the silicon local oxidation isolation structure 141 away from the substrate 11 is planar, the initial isolation structure can be prepared by a silicon local oxidation isolation process, and then the initial isolation structure is subjected to chemical mechanical planarization (CMP) to obtain a flattened silicon local oxidation isolation structure 141.

[0092] In another embodiment, the silicon local oxidation isolation structure 141 may be an initial isolation structure prepared by a silicon local oxidation isolation process, and may be a complete initial isolation structure without undergoing CMP.

[0093] In one embodiment, after forming the first insulating layer 14, as Figure 7 As shown, the following steps S701 to S702 may also be included: Step S701 , punching the punching portion 142 by using a punching process to form a plurality of openings.

[0094] In this step, it is only necessary to punch holes 142 on the main junction structure 12, the second field limiting ring 142, and the cut-off ring 134 to form a plurality of openings. Different from the related art, the positions of the holes are different, and the process used is the same, so no additional process is required.

[0095] Step S702 , depositing metal material in the plurality of openings to form a plurality of through-hole structures.

[0096] In the present application, the process of preparing the plurality of through-hole structures 18 is the same as the process of preparing the plurality of through-hole structures 18 in the related art, and therefore, no additional process is required.

[0097] Step S604: forming an electrode layer on a side of the first insulating layer away from the substrate.

[0098] In this step, a field plate mask may be used to deposit a metal material on a side of the first insulating layer 14 away from the substrate 11 to form the electrode layer 15 .

[0099] In the present application, the process of forming the electrode layer 15 is the same as the process of forming the metal field plate in the related art, except that the field plate mask used is different, so no additional process is required.

[0100] In one embodiment, step S702 and step S604 belong to the same process, that is, a deposition process is used to deposit metal material in the plurality of openings to form a plurality of through-hole structures 18 , and at the same time, an electrode layer 15 is formed on a side of the first insulating layer 14 away from the substrate 11 .

[0101] In one embodiment, after the electrode layer 15 is formed, a second insulating layer 19 is formed on a side of the first insulating layer 14 away from the substrate 11 .

[0102] In one embodiment, when the second insulating layer 19 includes the above-mentioned passivation layer and protective layer, a PECVD (Plasma-Enhanced Chemical Vapor Deposition) process can be first used to form a passivation layer on the side of the first insulating layer 14 away from the substrate 11, and then a coating process can be used to form a protective layer on the side of the passivation layer away from the substrate 11.

[0103] In the present application, the process for preparing the power semiconductor device is simple and can be prepared using a traditional preparation process without requiring any additional process and without increasing the process cycle and cost.

[0104] In the present invention, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance. The term "plurality" refers to two or more than two, unless otherwise clearly defined.

[0105] The above description of the embodiments is to facilitate those skilled in the art to understand and apply the present application. It is obvious that those skilled in the art can easily make various modifications to these embodiments and apply the general principles described herein to other embodiments without having to pay creative labor. Therefore, the present application is not limited to the embodiments herein, and improvements and modifications made by those skilled in the art based on the contents disclosed in the present application without departing from the scope and spirit of the present application are within the scope of the present application.

Claims

1. A power semiconductor device, characterized in that: include: A substrate, wherein the substrate is divided into a cell region and a terminal region, and the terminal region is located at the periphery of the cell region; A main junction structure, located on the first side of the substrate and within the cell region; A plurality of field ring structures are located on a first side of the substrate and in the terminal region, the plurality of field ring structures are isolated and arranged along a first direction, the first direction is a direction from the cell region to the terminal region, the plurality of field ring structures include at least one first field limiting ring and at least one cut-off ring, the cut-off ring is located on one side of at least one first field limiting ring along the first direction; A first insulating layer is located on a side of the main junction structure and the plurality of field ring structures away from the substrate; An electrode layer is located on a side of the first insulating layer away from the substrate, the electrode layer includes a first field plate, the first field plate covers a portion of the main junction structure close to the field ring structure and at least one of the first field limiting rings close to the main junction structure, and the first field plate is electrically connected to the main junction structure.

2. The power semiconductor device according to claim 1, characterized in that: The number of the first field limiting rings covered by the first field plate is determined according to the lowest withstand voltage value of the power semiconductor device.

3. The power semiconductor device according to claim 2, characterized in that: The first field plate covers one of the first field limiting rings; or, the first field plate covers two of the first field limiting rings.

4. The power semiconductor device according to claim 1, characterized in that: The plurality of field ring structures further include: at least one second field limiting ring, located between the first field limiting ring and the cut-off ring, and isolatedly arranged along a first direction; The electrode layer further comprises: At least one second field plate is located on a side of the first insulating layer away from the substrate, the first field plate and the at least one second field plate are insulated and arranged along a first direction, the number of the second field plates is the same as the number of the second field limiting rings, at least one second field plate is electrically connected to at least one second field limiting ring in a one-to-one correspondence, and for the electrically connected second field plates and second field limiting rings, the second field plate at least covers a portion of the second field limiting ring.

5. The power semiconductor device according to claim 4, characterized in that: The electrode layer further comprises: At least one third field plate is located on a side of the first insulating layer away from the substrate, the first field plate, at least one of the second field plates and at least one of the third field plates are insulated and arranged along a first direction, the number of the third field plates is the same as the number of the cut-off rings, at least one of the third field plates is electrically connected to at least one of the cut-off rings in a one-to-one correspondence, and for the electrically connected third field plates and the cut-off rings, the third field plate at least covers a portion of the cut-off rings.

6. The power semiconductor device according to claim 5, characterized in that: Also includes: A plurality of through-hole structures penetrate the first insulating layer, the through-hole structures comprising a first through-hole, at least one second through-hole and at least one third through-hole, the first field plate contacts the main junction structure through the first through-hole, at least one of the second field plates contacts different second field limiting rings through different second through-holes, and at least one of the third field plates contacts different cut-off rings through different third through-holes.

7. The power semiconductor device according to claim 6, characterized in that: The first insulating layer comprises: There are multiple silicon local oxidation isolation structures and multiple punched portions, the silicon local oxidation isolation structures and the punched portions are alternately arranged, there is one silicon local oxidation isolation structure between the main junction structure and two adjacent structures in the multiple field ring structures, there is one punched portion on each of the main junction structure and the multiple field ring structures, and the multiple through-hole structures respectively penetrate different punched portions.

8. The power semiconductor device according to claim 5, characterized in that: Also includes: The second insulating layer is located on a side of the first insulating layer away from the substrate, the second insulating layer includes a plurality of insulating portions, and one insulating portion exists between two adjacent field plates among the first field plate, at least one of the second field plates, and at least one of the third field plates.

9. A method for preparing a power semiconductor device, characterized in that: For preparing a power semiconductor device according to any one of claims 1 to 8, the method comprises: providing the substrate; forming the main junction structure and a plurality of the field ring structures on a surface of the first side of the substrate; forming the first insulating layer on a side of the main junction structure and the plurality of field ring structures away from the substrate; The electrode layer is formed on a side of the first insulating layer away from the substrate.

10. The method for preparing a power semiconductor device according to claim 9, characterized in that: When the power semiconductor device includes a plurality of through-hole structures and the first insulating layer includes a plurality of perforated portions, after the first insulating layer is formed on a side of the main junction structure and the plurality of field ring structures away from the substrate and before the electrode layer is formed on a side of the first insulating layer away from the substrate, the method further includes: Punching holes on the punching portion using a punching process to form a plurality of openings; Depositing metal material in the plurality of openings to form the plurality of through-hole structures; wherein depositing metal material in the plurality of openings to form the plurality of through-hole structures and forming the electrode layer on a side of the first insulating layer away from the substrate belong to the same process.

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