Groove type insulated gate bipolar transistor and preparation method thereof

Abstract

The invention relates to a groove type insulated gate bipolar transistor and a preparation method thereof. The trench type insulated gate bipolar transistor comprises a substrate, a trench gate structure, an oxide isolation buried layer and an electrode, the substrate comprises a first body region, a second body region, a first active region and a second active region, and the second body region is located on the upper side of the first body region; the trench gate structure comprises a first emitter trench gate structure, a first active trench gate structure, a second active trench gate structure and a second emitter trench gate structure which are arranged in sequence, and the oxide isolation buried layer is located at the junction of the first body region and the second body region. And a plurality of electrodes disposed between the first active trench gate structure and the second active trench gate structure, the plurality of electrodes including a first emitter disposed between the first active trench gate structure and the second active trench gate structure. According to the technical scheme of the invention, low saturation voltage and switching loss can be ensured, turn-off loss can be reduced, and the probability of heating failure of the device can be reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a trench-type insulated gate bipolar transistor and a preparation method thereof. Background Art

[0002] In the related technologies, the Insulated Gate Bipolar Transistor (IGBT) has the characteristics of high input impedance, low on-state voltage drop, fast switching speed and low loss, and is widely used in new energy, transportation, power grid and industry. These applications often require IGBT to have high current and high withstand voltage level, while having low switching loss.

[0003] In the related technology, the turn-on loss and turn-off loss of IGBT are in a mutually restrained relationship and it is difficult to reduce them at the same time. However, in the application, the switching loss of IGBT is required to be as low as possible, which is not only beneficial to the stability of the device, but also can improve the working efficiency and service life of the device.

[0004] In the related art, there are IGBTs with low turn-on loss and IGBTs with low turn-off loss. For IGBTs with low turn-on loss, the outflow of carriers during turn-on is controlled, and the saturation voltage is low. However, when turned off, the outflow of carriers is also slow, so the turn-on loss is low and the turn-off loss is high. For IGBTs with low turn-off loss, more carriers will flow out through the emitter when turned on, the saturation voltage is high, and the turn-on loss is high; when turned off, the stored carriers flow out faster and the turn-off loss is smaller. These two types of IGBTs have their own advantages and disadvantages, but neither can guarantee low saturation voltage, low turn-on loss, and low turn-off loss at the same time. Summary of the invention

[0005] The purpose of the present application is to provide a trench insulated gate bipolar transistor and a method for preparing the same, which can reduce turn-off losses while ensuring low saturation voltage and switching losses, reduce the probability of device failure due to thermal generation, extend the device's service life and improve the device's reliability.

[0006] According to a first aspect of an embodiment of the present application, there is provided a trench insulated gate bipolar transistor, comprising: A substrate, comprising a cell region; the substrate comprises a first body region of a first conductivity type, a second body region of a second conductivity type, a first active region and a second active region of the first conductivity type, the first body region and the second body region are located in the cell region, the second body region is located on an upper side of the first body region, and the first active region and the second active region are located in the second body region on a side away from the first body region; a plurality of trench gate structures, penetrating the second body region along a first direction and extending into the first body region, the first direction being perpendicular to the substrate, the plurality of trench gate structures comprising a first emitter trench gate structure, a first active trench gate structure, a second active trench gate structure and a second emitter trench gate structure sequentially arranged along a second direction, the second direction being perpendicular to the first direction, the first active region being located between the first emitter trench gate structure and the first active trench gate structure, and the second active region being located between the second active trench gate structure and the second emitter trench gate structure; an oxide isolation buried layer, located at the junction of the first body region and the second body region, and between the first active trench gate structure and the second active trench gate structure; A plurality of electrodes extend along the first direction into the second body region and protrude from the second body region. The plurality of electrodes include a first active gate, a first emitter and a second active gate. The first active gate penetrates the first active region and extends into the second body region. The second active gate penetrates the second active region and extends into the second body region. The first emitter is located between the first active trench gate structure and the second active trench gate structure in the second direction.

[0007] In one embodiment, the oxide isolation buried layer is at least partially located in the second body region.

[0008] In one embodiment, the length of the buried oxide isolation layer in the second direction is positively correlated with the doping concentration of the second body region, and there are gaps between the buried oxide isolation layer and the first active trench gate structure and the second active trench gate structure.

[0009] In one embodiment, a projection of the first emitter on the substrate is located within a projection of the oxide isolation buried layer on the substrate, and a gap exists between the first emitter and the oxide isolation buried layer.

[0010] In one embodiment, the material of the oxide isolation buried layer is silicon oxide.

[0011] In one embodiment, an upper surface of the first active region, an upper surface of the second active region, and an upper surface of the second body region are flush.

[0012] In one embodiment, the trench insulated gate bipolar transistor further comprises a first interlayer dielectric layer; The first interlayer dielectric layer is located at a side of the second body region away from the first body region, and the plurality of electrodes penetrate the first interlayer dielectric layer and extend into the second body region; The substrate further includes a carrier storage layer, a first field stop layer and a first collector region. The carrier storage layer is located between the first body region and the second body region. The first field stop layer is located between the first body region and the first collector region.

[0013] In one embodiment, the trench insulated gate bipolar transistor further includes a first conductive layer and a second conductive layer; The first conductive layer is located on a side of the first interlayer dielectric layer away from the second body region and is electrically connected to the plurality of electrodes; The second conductive layer is located on a side of the first collector region away from the first field stop layer.

[0014] According to a second aspect of an embodiment of the present application, a method for preparing a trench-type insulated gate bipolar transistor is provided, which is used to prepare the above-mentioned trench-type insulated gate bipolar transistor, and the method comprises: Providing a substrate of a first conductivity type; the substrate is used to provide the first body region; implanting oxygen ions into designated positions in the substrate to form an oxygen ion buried layer; Using a high temperature process to form the oxide isolation buried layer from the oxygen ion buried layer; forming a plurality of the trench gate structures on the substrate; forming the second body region, the first active region and the second active region in the substrate by an ion implantation process; forming a first interlayer dielectric layer on a side of the second body region away from the first body region; A plurality of contact holes are formed by an etching process, wherein the plurality of contact holes penetrate the first interlayer dielectric layer and extend into the second body region; positions of the plurality of contact holes correspond one-to-one to positions of the plurality of electrodes; Conductive material is deposited in the plurality of contact holes to form a plurality of electrodes.

[0015] In one embodiment, when the substrate further includes a carrier storage layer, before the step of injecting oxygen ions into a designated position in the substrate to form an oxygen ion buried layer, the step further includes: Implanting doping ions of a first conductivity type into the substrate to form a doping layer; A high temperature process is used to form the carrier storage layer from the doped layer; wherein, the process of forming the carrier storage layer from the doped layer using a high temperature process and the process of forming the oxide isolation buried layer from the oxygen ion buried layer using a high temperature process belong to the same process.

[0016] Compared with the prior art, the beneficial effect of the present application is that: since the trench-type insulated gate bipolar transistor includes, in addition to the above-mentioned substrate, multiple trench gate structures and multiple electrodes, it also includes an oxide isolation buried layer, the oxide isolation buried layer is located at the junction of the first body region and the second body region, and is located between the first active trench gate structure and the second active trench gate structure, the first emitter is located between the first active trench gate structure and the second active trench gate structure in the second direction, and since the doping concentration near the position of the oxide isolation buried layer is low, when a voltage is applied to the first active trench gate structure and the second active trench gate structure to turn on the trench-type insulated gate bipolar transistor, the position of the oxide isolation buried layer is easily inverted to form an electronic region to prevent holes from flowing out. At this time, coupled with the ability of the oxide isolation buried layer to block the outflow of carriers, the first emitter between the first active trench gate structure and the second active trench gate structure can be prevented from extracting carriers when the transistor is turned on, thereby maintaining a low saturation voltage and a small turn-on loss. When the transistor is turned off, no voltage is applied to the first active trench gate structure and the second active trench gate structure, and the ability to invert the second body region is lost. Therefore, the position of the oxide isolation buried layer allows carriers to be extracted from it by the first emitter between the first active trench gate structure and the second active trench gate structure, thereby accelerating the shutdown and reducing the shutdown loss. In summary, the technical solution provided by the present application can achieve low saturation voltage and small turn-on loss while reducing the turn-off loss of the device, which can reduce the probability of device failure due to heating, extend the service life of the device and improve the reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a schematic structural diagram of a trench-type insulated gate bipolar transistor according to the related art.

[0018] Figure 2 It is a schematic structural diagram of another trench insulated gate bipolar transistor according to the related art.

[0019] Figure 3 It is a schematic structural diagram of a trench insulated gate bipolar transistor according to an exemplary embodiment.

[0020] Figure 4 yes Figure 1 The simulation diagram of the trench IGBT in the turned-on state is shown.

[0021] Figure 5 yes Figure 2 The simulation diagram of the trench IGBT in the turned-on state is shown.

[0022] Figure 6 yes Figure 3 The simulation diagram of the trench IGBT in the turned-on state is shown.

[0023] Figure 7 The present invention is a flow chart of a method for manufacturing a trench insulated gate bipolar transistor according to an exemplary embodiment.

[0024] Figure 8 is a flow chart of a method for preparing a trench insulated gate bipolar transistor according to another exemplary embodiment.

[0025] Description of reference numerals: 31: substrate, 311: first body region, 312: second body region of second conductivity type, 313: first active region, 314: second active region, 315: first field stop layer, 316: first collector region, 32: multiple trench gate structures, 321: first emitter trench gate structure, 322: first active trench gate structure, 323: second active trench gate structure, 324: second emitter trench gate structure, 33: oxide isolation buried layer, 34: first interlayer dielectric layer, 35: electrode, 351: first active gate, 352: first emitter, 353: second active gate, 36: first conductive layer, 37: second conductive layer. DETAILED DESCRIPTION

[0026] Unless otherwise defined, the technical terms or scientific terms used in this specification and claims shall have the usual meanings understood by persons with ordinary skills in the technical field to which the invention belongs. The specific embodiments of the present invention will be described below in conjunction with the accompanying drawings. It should be noted that in the specific description of these embodiments, in order to provide a concise description, it is impossible for this specification to provide a detailed description of all the features of the actual embodiments. Without departing from the spirit and scope of the present invention, those skilled in the art may modify and replace the embodiments of the present invention, and the resulting embodiments are also within the scope of protection of the present invention.

[0027] In related technologies, such as Figure 1 The IGBT shown controls the outflow of carriers when turned on, and the saturation voltage is low, but when turned off, the outflow of carriers is also slow, so the turn-on loss is low and the turn-off loss is high. Figure 1 The IGBT shown includes a first electrode lead-out layer 11, a second interlayer dielectric layer 12, two third active regions 13, two third active gates 14, two second emitter trench gate structures 15, two second active gate trench gate structures 16, a third body region 17, a fourth body region 18, a second field stop layer 19, a second collector region 110 and a first collector electrode 111. The material of the first electrode lead-out layer 11 and the first collector electrode 111 is metal, the two third active regions 13 are N+ type active regions, the third body region 17 is a P type body region, the fourth body region 18 is an N type body region, and the second collector region 110 is a P+ type collector region.

[0028] like Figure 2 The IGBT shown in the figure has more metals connected, and when turned on, more carriers will flow out through the second emitter 212, resulting in a high saturation voltage and high turn-on loss; when turned off, the stored carriers flow out faster and the turn-off loss is smaller. Figure 2 The IGBT shown includes a second electrode lead-out layer 21, a third interlayer dielectric layer 22, two fourth active regions 23, two fourth active gates 24, a second emitter 212, two third emitter trench gate structures 25, two third active gate trench gate structures 26, a fifth body region 27, a sixth body region 28, a third field stop layer 29, a third collector region 210 and a second collector 211. The second electrode lead-out layer 21 and the second collector 211 are made of metal, the two fourth active regions 23 are N+ type active regions, the fifth body region 27 is a P type body region, the sixth body region 28 is an N type body region, and the third collector region 210 is a P+ type collector region.

[0029] The above two IGBT structures have their own advantages and disadvantages, but neither can guarantee low saturation voltage, low turn-on loss and low turn-off loss at the same time.

[0030] In order to solve the above technical problems, the present application proposes a trench insulated gate bipolar transistor and a preparation method thereof, which can reduce the turn-off loss while ensuring low saturation voltage and switching loss, reduce the probability of device thermal failure, extend the service life of the device and improve the reliability of the device.

[0031] An embodiment of the present application provides a trench-type insulated gate bipolar transistor. Figure 3 As shown, the trench insulated gate bipolar transistor may include: a substrate 31 , a plurality of trench gate structures 32 , an oxide isolation buried layer 33 , a first interlayer dielectric layer 34 , a plurality of electrodes 35 , a first conductive layer 36 and a second conductive layer 37 .

[0032] In one embodiment, the substrate 31 includes a cell region (not shown) and a terminal region (not shown), and the terminal region is located at the periphery of the cell region. The technical solution provided in this application only involves the structural improvement of the cell region, so the terminal region is not introduced.

[0033] In one embodiment, the conductivity type of the substrate 31 is the first conductivity type, such as N type, but not limited thereto. The substrate 31 can be used to provide a first body region of the first conductivity type, and the first body region can be a drift region.

[0034] In one embodiment, Figure 3As shown, the substrate 31 may include a first body region 311 of a first conductivity type, a second body region 312 of a second conductivity type, a first active region 313 of a first conductivity type, a second active region 314 of a first conductivity type, a first field stop layer 315 and a first collector region 316 .

[0035] In one embodiment, the first conductivity type may be N type, and the second conductivity type may be P type, but is not limited thereto.

[0036] like Figure 3 As shown, the first body region 311 and the second body region 312 are located in the cell region, the second body region 312 is located on the upper side of the first body region 311, and the first active region 313 and the second active region 314 are located on the side of the second body region 312 away from the first body region 311. The upper surface of the first active region 313 and the upper surface of the second active region 314 may be flush with the upper surface of the second body region 312.

[0037] For the convenience of expression, it is agreed in this article that Figure 3 The first direction is an upward direction, the upper surface of the component is the surface of the component in the first direction, and the back surface of the component is the surface in the opposite direction of the first direction.

[0038] In one embodiment, the first body region 311 may be a drift region, and the second body region 312 may be an emitter region.

[0039] In one embodiment, Figure 3 As shown, the first field stop layer 315 is located between the first body region 311 and the first collector region 316. The conductivity type of the first collector region 316 is the second conductivity type. The first collector region 316 may be a P+ type collector region.

[0040] In one embodiment, the substrate 31 may further include a carrier storage layer (not shown), and the carrier storage layer may be located between the first body region 311 and the second body region 312 .

[0041] In one embodiment, Figure 3 As shown, a plurality of trench gate structures 32 penetrate the second body region 312 along a first direction and extend into the first body region 311 , and the first direction is perpendicular to the substrate 31 .

[0042] In one embodiment, Figure 3 As shown, the plurality of trench gate structures 32 may include a first emitter trench gate structure 321 , a first active trench gate structure 322 , a second active trench gate structure 323 and a second emitter trench gate structure 324 arranged in sequence along a second direction, and the second direction is perpendicular to the first direction.

[0043] In one embodiment, the materials of the first emitter trench gate structure 321 and the second emitter trench gate structure 324 may include polysilicon and an oxide layer, and are connected to a zero potential.

[0044] In one embodiment, the materials of the first active trench gate structure 322 and the second active trench gate structure 323 may include polysilicon and an oxide layer, and may be connected to a gate pad to control device switching.

[0045] like Figure 3 As shown, the first active region 313 is located between the first emitter trench gate structure 321 and the first active trench gate structure 322 , and the second active region 314 is located between the second active trench gate structure 323 and the second emitter trench gate structure 324 .

[0046] like Figure 3 As shown, the oxide isolation buried layer 33 is located at the junction of the first body region 311 and the second body region 312 , and is located between the first active trench gate structure 322 and the second active trench gate structure 323 .

[0047] In one embodiment, the oxide isolation buried layer 33 is at least partially located in the second body region 312. In one embodiment, the oxide isolation buried layer 33 may be partially located in the second body region 312 and another partially located in the first body region 311. In another embodiment, the oxide isolation buried layer 33 may be entirely located in the second body region 312.

[0048] In one embodiment, the material of the oxide isolation buried layer 33 may be silicon oxide.

[0049] In one embodiment, the length of the oxide isolation buried layer 33 in the second direction is positively correlated with the doping concentration of the second body region 312 . The greater the doping concentration of the second body region 312 , the greater the length of the oxide isolation buried layer 33 .

[0050] In one embodiment, Figure 3 As shown, there are gaps between the oxide isolation buried layer 33 and the first active trench gate structure 322 and the second active trench gate structure 323 .

[0051] In one embodiment, Figure 3 As shown, the first interlayer dielectric layer 34 is located on a side of the second body region 312 away from the first body region 311. The material of the first interlayer dielectric layer 34 may be silicon oxide for electrical isolation.

[0052] In one embodiment, Figure 3 As shown, the plurality of electrodes 35 penetrate the first interlayer dielectric layer 34 along a first direction, extend into the second body region 312 , and protrude from the second body region 312 .

[0053] like Figure 3 As shown, the multiple electrodes 35 include a first active gate 351, a first emitter 352 and a second active gate 353. The first active gate 351 penetrates the first active region 313 and extends into the second body region 312. The second active gate 353 penetrates the second active region 314 and extends into the second body region 312. The first emitter 352 is located between the first active trench gate structure 322 and the second active trench gate structure 323 in the second direction.

[0054] In one embodiment, the material of the electrode 35 may be a metal material, but is not limited thereto and may be other conductive materials.

[0055] In one embodiment, Figure 3 As shown, the projection of the first emitter 352 on the substrate 31 is located within the projection of the oxide isolation buried layer 33 on the substrate 31 , and there is a gap between the first emitter 352 and the oxide isolation buried layer 33 .

[0056] In one embodiment, Figure 3 As shown, the first conductive layer 36 is located on a side of the first interlayer dielectric layer 34 away from the second body region 312 and is electrically connected to the plurality of electrodes 35. The material of the first conductive layer 36 can be metal, and is used to lead out the electrodes 35 and electrically connect to external devices.

[0057] In one embodiment, Figure 3 As shown, the second conductive layer 37 is located on a side of the first collector region 316 away from the first field stop layer 315. The second conductive layer 37 may be a collector electrode. The material of the second conductive layer 37 may be metal.

[0058] In the present application, since the oxide isolation buried layer 33 is located at the junction of the first body region 311 and the second body region 312, and is located between the first active trench gate structure and the second active trench gate structure, the first emitter 352 is located between the first active trench gate structure and the second active trench gate structure in the second direction, and since the doping concentration near the position of the oxide isolation buried layer 33 is low, when a voltage is applied to the first active trench gate structure and the second active trench gate structure to turn on the trench insulated gate bipolar transistor, the position of the oxide isolation buried layer 33 is easily inverted to form an electronic region to prevent holes from flowing out. At this time, coupled with the ability of the oxide isolation buried layer 33 to block the outflow of carriers, the first emitter 352 between the first active trench gate structure and the second active trench gate structure can be prevented from extracting carriers when the transistor is turned on, thereby maintaining a low saturation voltage and a small turn-on loss. When the transistor is turned off, no voltage is applied to the first active trench gate structure and the second active trench gate structure, and the ability to invert the second body region 312 is lost. Therefore, the position of the oxide isolation buried layer 33 allows carriers to be extracted from it by the first emitter 352 between the first active trench gate structure and the second active trench gate structure, thereby accelerating the shutdown and reducing the shutdown loss.

[0059] IGBT devices often switch between on and off during application, which will cause energy loss and heat generation, affecting the stability of the device. In addition, the voltage of the device during operation is the saturation voltage. The smaller the voltage, the smaller the energy loss and heat generated during operation, which is a great advantage for application.

[0060] Figure 4 yes Figure 1 The simulation diagram of a conventional IGBT in the on state is shown in FIG. Figure 5 yes Figure 2 The simulation diagram of a conventional IGBT in the on state is shown in FIG. Figure 6 yes Figure 3 The simulation diagram of the IGBT of the present application in the on state is shown, wherein red represents more holes and blue represents less holes.

[0061] For conventional IGBTs, if you want to reduce turn-on losses, you must ensure a low saturation voltage. To do this, you must ensure that the internal carriers are not extracted by the electrodes when the device is turned on. To reduce turn-off losses, on the contrary, the internal carriers must be extracted quickly. Increasing the electrodes in the cell can reduce turn-off losses, but it will also increase the saturation voltage, increase heat generation during use, and increase energy loss during turn-on. If you do not increase the electrodes, you can ensure a low saturation voltage and turn-on losses, but you cannot reduce turn-off losses, which is very unfavorable for high-frequency applications.

[0062] The advantage of the IGBT provided by the present application is that when the device is turned on, the first active trench gate structure and the second active trench gate structure have an inversion effect, depleting the P-type region on its surface and matching the oxide isolation buried layer 33, which can prevent holes from being drawn away by the first emitter 352 when the device is turned on, thereby maintaining a low saturation voltage and a small turn-on loss. When the device is turned off, the first active trench gate structure and the second active trench gate structure do not have an inversion effect, and the P-type region on its surface cannot be depleted, and a potential barrier cannot be formed to block holes inside the device, so when the device is turned off, the holes can be drawn away by the first emitter 352, thereby reducing the turn-off loss of the device.

[0063] In summary, the IGBT provided in the present application can achieve low saturation voltage and small turn-on loss while reducing the turn-off loss of the device, which can reduce the probability of device failure due to thermal generation, extend the service life of the device and improve the reliability of the device, which is beneficial to the application of the device.

[0064] Another exemplary embodiment of the present application also provides a method for preparing a trench-type insulated gate bipolar transistor. In this embodiment, the method for preparing a trench-type insulated gate bipolar transistor is used to prepare a trench-type insulated gate bipolar transistor that does not include a carrier storage layer. Figure 7 As shown, the trench insulated gate bipolar transistor may include the following steps S701 to S710: Step S701, providing a substrate of a first conductivity type; the substrate is used to provide a first body region.

[0065] In this step, a substrate 31 of a first conductive type is provided, for example, an N-type substrate 31 is provided. The substrate 31 is used to provide a first body region 311 , and the first body region 311 may be a drift region.

[0066] Step S702, implanting oxygen ions into designated positions in the substrate to form an oxygen ion buried layer.

[0067] In this step, a first mask may be used to achieve positioned high-energy oxygen ion implantation, and oxygen ions may be implanted into designated locations in the substrate 31 to form an oxygen ion buried layer. The first mask is used to define the ion implantation area.

[0068] Step S703: using a high temperature process to form an oxide isolation buried layer from the oxygen ion buried layer.

[0069] In this step, a high temperature process is used to perform high temperature annealing on the intermediate structure prepared in step S702, so that the oxygen ion buried layer forms an oxide isolation buried layer 33.

[0070] Step S704: forming a plurality of trench gate structures on the substrate.

[0071] In this step, an etching process may be used to form multiple trenches on the substrate 31, an oxide layer may be deposited or grown in the trenches to form a gate oxide layer, and then polysilicon may be deposited in the multiple trenches to form the above-mentioned multiple trench gate structures.

[0072] Step S705 , forming a second body region, a first active region, and a second active region in the substrate by using an ion implantation process.

[0073] In this step, an ion implantation process may be used to implant doping ions of the second conductivity type into the substrate 31 to form a second body region 312 in the substrate 31. The doping ions of the second conductivity type may be boron ions, but are not limited thereto. The step of preparing the second body region 312 may be before step S704.

[0074] After the second body region 312 is prepared, the first conductive type doping ions are implanted on the upper surface of the substrate 31 using a second mask to form a first active region 313 and a second active region 314 in the substrate 31. The second mask is used to define the shapes of the first active region 313 and the second active region 314. The first conductive type doping ions may be phosphorus ions, but are not limited thereto.

[0075] Step S706: forming a first interlayer dielectric layer on a side of the second body region away from the first body region.

[0076] In this step, a first interlayer dielectric layer 34 is formed on a side of the second body region 312 away from the first body region 311 . The first interlayer dielectric layer 34 may be silicon oxide and may be prepared by a deposition process.

[0077] Step S707, forming a plurality of contact holes by using an etching process, wherein the plurality of contact holes penetrate the first interlayer dielectric layer and extend into the second body region; positions of the plurality of contact holes correspond one-to-one to positions of the plurality of electrodes.

[0078] In this step, an etching process can be used to etch the first interlayer dielectric layer 34 on the intermediate structure prepared in step S706 to form a plurality of contact holes. The plurality of contact holes penetrate the first interlayer dielectric layer 34 and extend into the second body region 312. The positions of the plurality of contact holes correspond one-to-one to the positions of the plurality of electrodes mentioned above.

[0079] Step S708 , depositing a conductive material in the plurality of contact holes to form a plurality of electrodes, and depositing a conductive material on a side of the first interlayer dielectric layer away from the second body region to form a first conductive layer.

[0080] In this step, a conductive material is deposited in the multiple contact holes to form multiple electrodes 35, and a conductive material is deposited on the side of the first interlayer dielectric layer 34 away from the second body region 312 to form a first conductive layer 36. The conductive material can be metal, but is not limited thereto.

[0081] Step S709: forming a first field stop layer and a first collector region in the substrate by using an ion implantation process, wherein the first field stop layer is located between the first body region and the first collector region.

[0082] In this step, doping ions of the second conductivity type may be implanted into the back surface of the substrate 31 to form the first collector region 316. The doping ions of the second conductivity type may be boron ions, but are not limited thereto.

[0083] Then, doping ions of the first conductivity type are implanted into the back surface of the substrate 31 to form a first field stop layer 315 . The doping ions of the first conductivity type may include hydrogen (H) ions or phosphorus ions.

[0084] Step S710: depositing a conductive material on a side of the substrate away from the first conductive layer to form a second conductive layer.

[0085] In this step, a deposition process may be used to deposit a conductive material on a side of the substrate 31 away from the first conductive layer 36 to form the second conductive layer 37. The conductive material may be a metal.

[0086] In this embodiment, the first mask is used to achieve the positioning of high-energy oxygen ion injection, and high-temperature annealing is used to form silicon oxide in the area where the oxygen ion buried layer is located, that is, the oxide isolation buried layer 33. High-temperature annealing is a mature process and is simple to prepare.

[0087] Another exemplary embodiment of the present application also provides a method for preparing a trench-type insulated gate bipolar transistor. Different from the above-mentioned embodiment, in this embodiment, the method for preparing a trench-type insulated gate bipolar transistor is used to prepare a trench-type insulated gate bipolar transistor including a carrier storage layer. Figure 8 As shown, in this embodiment, the method for preparing the trench insulated gate bipolar transistor may include the following steps S801 to S811: Step S801, providing a substrate of a first conductivity type; the substrate is used to provide a first body region.

[0088] This step is similar to the above-mentioned step S701 and will not be described again.

[0089] Step S802 , implanting doping ions of the first conductivity type into the substrate to form a doping layer.

[0090] In this step, an ion process is used to implant doping ions of the first conductivity type into the substrate 31 to form a doping layer. The doping ions of the first conductivity type may be phosphorus ions, but are not limited thereto.

[0091] Step S803, injecting oxygen ions into designated positions in the substrate to form an oxygen ion buried layer.

[0092] This step is similar to the above-mentioned step S702 and will not be described again.

[0093] Step S804: using a high temperature process to form the doped layer into a carrier storage layer, and to form the oxygen ion buried layer into an oxide isolation buried layer.

[0094] In this step, a high temperature process is used to form the carrier storage layer from the doped layer, and the oxide isolation buried layer 33 is formed from the oxygen ion buried layer. That is, the high temperature process used to form the carrier storage layer from the doped layer and the high temperature process used to form the oxide isolation buried layer 33 from the oxygen ion buried layer belong to the same process. The high temperature annealing process can utilize the existing thermal process in the IGBT preparation process, without adding additional processes, and is simple to prepare.

[0095] Step S805 , forming a plurality of trench gate structures on the substrate.

[0096] This step is similar to the above-mentioned step S704 and will not be described again.

[0097] Step S806: forming a second body region, a first active region, and a second active region in the substrate by using an ion implantation process.

[0098] This step is similar to the above-mentioned step S705 and will not be described again.

[0099] Step S807 , forming a first interlayer dielectric layer on a side of the second body region away from the first body region.

[0100] This step is similar to the above-mentioned step S706 and will not be described again.

[0101] Step S808, forming a plurality of contact holes by using an etching process, wherein the plurality of contact holes penetrate the first interlayer dielectric layer and extend into the second body region; positions of the plurality of contact holes correspond one-to-one to positions of the plurality of electrodes.

[0102] This step is similar to the above-mentioned step S707 and will not be described again.

[0103] Step S809 , depositing a conductive material in the plurality of contact holes to form a plurality of electrodes, and depositing a conductive material on a side of the first interlayer dielectric layer away from the second body region to form a first conductive layer.

[0104] This step is similar to the above-mentioned step S708 and will not be described again.

[0105] Step S810: forming a first field stop layer and a first collector region in the substrate by using an ion implantation process, wherein the first field stop layer is located between the first body region and the first collector region.

[0106] This step is similar to the above-mentioned step S709 and will not be repeated here.

[0107] Step S811, depositing a conductive material on a side of the substrate away from the first conductive layer to form a second conductive layer.

[0108] This step is similar to the above-mentioned step S710 and will not be described again.

[0109] In this embodiment, the first mask is used to achieve the positioning of high-energy oxygen ion injection, and high-temperature annealing is used to form silicon oxide in the area where the oxygen ion buried layer is located, that is, the oxide isolation buried layer 33. The high-temperature annealing can utilize the original thermal process in the IGBT preparation process, without the need for additional steps, and the preparation is simple.

[0110] In the present invention, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance. The term "plurality" refers to two or more than two, unless otherwise clearly defined.

[0111] The above description of the embodiments is to facilitate those skilled in the art to understand and apply the present application. It is obvious that those skilled in the art can easily make various modifications to these embodiments and apply the general principles described herein to other embodiments without having to pay creative labor. Therefore, the present application is not limited to the embodiments herein, and improvements and modifications made by those skilled in the art based on the contents disclosed in the present application without departing from the scope and spirit of the present application are within the scope of the present application.

Claims

1. A trench insulated gate bipolar transistor, characterized in that: include: A substrate, comprising a cell region; the substrate comprises a first body region of a first conductivity type, a second body region of a second conductivity type, a first active region and a second active region of the first conductivity type, the first body region and the second body region are located in the cell region, the second body region is located on an upper side of the first body region, and the first active region and the second active region are located in the second body region on a side away from the first body region; a plurality of trench gate structures, penetrating the second body region along a first direction and extending into the first body region, the first direction being perpendicular to the substrate, the plurality of trench gate structures comprising a first emitter trench gate structure, a first active trench gate structure, a second active trench gate structure and a second emitter trench gate structure sequentially arranged along a second direction, the second direction being perpendicular to the first direction, the first active region being located between the first emitter trench gate structure and the first active trench gate structure, and the second active region being located between the second active trench gate structure and the second emitter trench gate structure; an oxide isolation buried layer, located at the junction of the first body region and the second body region, and between the first active trench gate structure and the second active trench gate structure; A plurality of electrodes extend along the first direction into the second body region and protrude from the second body region. The plurality of electrodes include a first active gate, a first emitter and a second active gate. The first active gate penetrates the first active region and extends into the second body region. The second active gate penetrates the second active region and extends into the second body region. The first emitter is located between the first active trench gate structure and the second active trench gate structure in the second direction.

2. The trench insulated gate bipolar transistor according to claim 1, wherein: The oxide isolation buried layer is at least partially located in the second body region.

3. The trench insulated gate bipolar transistor according to claim 1, wherein: The length of the buried oxide isolation layer in the second direction is positively correlated with the doping concentration of the second body region, and there are gaps between the buried oxide isolation layer and the first active trench gate structure and the second active trench gate structure.

4. The trench insulated gate bipolar transistor according to claim 1, wherein: The projection of the first emitter on the substrate is located within the projection of the oxide isolation buried layer on the substrate, and there is a gap between the first emitter and the oxide isolation buried layer.

5. The trench insulated gate bipolar transistor according to claim 1, wherein: The material of the oxide isolation buried layer is silicon oxide.

6. The trench insulated gate bipolar transistor according to claim 1, wherein: An upper surface of the first active region, an upper surface of the second active region, and an upper surface of the second body region are flush.

7. The trench insulated gate bipolar transistor according to claim 1, wherein: Also included is a first interlayer dielectric layer; The first interlayer dielectric layer is located at a side of the second body region away from the first body region, and the plurality of electrodes penetrate the first interlayer dielectric layer and extend into the second body region; The substrate further includes a carrier storage layer, a first field stop layer and a first collector region. The carrier storage layer is located between the first body region and the second body region. The first field stop layer is located between the first body region and the first collector region.

8. The trench insulated gate bipolar transistor according to claim 7, wherein: Also includes a first conductive layer and a second conductive layer; The first conductive layer is located on a side of the first interlayer dielectric layer away from the second body region and is electrically connected to the plurality of electrodes; The second conductive layer is located on a side of the first collector region away from the first field stop layer.

9. A method for preparing a trench insulated gate bipolar transistor, characterized in that: For preparing a trench insulated gate bipolar transistor according to any one of claims 1 to 8, the method comprising: Providing a substrate of a first conductivity type; the substrate is used to provide the first body region; implanting oxygen ions into designated positions in the substrate to form an oxygen ion buried layer; Using a high temperature process to form the oxide isolation buried layer from the oxygen ion buried layer; forming a plurality of the trench gate structures on the substrate; forming the second body region, the first active region and the second active region in the substrate by an ion implantation process; forming a first interlayer dielectric layer on a side of the second body region away from the first body region; A plurality of contact holes are formed by an etching process, wherein the plurality of contact holes penetrate the first interlayer dielectric layer and extend into the second body region; positions of the plurality of contact holes correspond one-to-one to positions of the plurality of electrodes; Conductive material is deposited in the plurality of contact holes to form a plurality of electrodes.

10. The method according to claim 9, characterized in that When the substrate further includes a carrier storage layer, before injecting oxygen ions into a designated position in the substrate to form an oxygen ion buried layer, the method further includes: Implanting doping ions of a first conductivity type into the substrate to form a doping layer; A high temperature process is used to form the carrier storage layer from the doped layer; wherein, the process of forming the carrier storage layer from the doped layer using a high temperature process and the process of forming the oxide isolation buried layer from the oxygen ion buried layer using a high temperature process belong to the same process.

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