Semiconductor structure, memory and manufacturing method thereof, and electronic equipment

Abstract

The embodiment of the invention provides a semiconductor structure, a memory, a manufacturing method of the memory and electronic equipment. The semiconductor structure comprises an isolation column, a first semiconductor layer, a first gate insulation layer and a first gate electrode. The isolation column extends in the first direction perpendicular to the substrate, the first semiconductor layer is arranged on the periphery of the isolation column, the first semiconductor layer comprises a first drain region, a first channel region and a first source region which are sequentially away from the substrate, and the first gate insulation layer and the first gate electrode are sequentially arranged on the periphery of the first channel region in a surrounding mode. According to the embodiment of the invention, the integrity of the first semiconductor layer is ensured, the problem of electric leakage caused by consumption of the first semiconductor layer is avoided, and the performance of the first transistor is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology. Specifically, the present application relates to a semiconductor structure, a memory and a manufacturing method thereof, and an electronic device. Background Art

[0002] At present, semiconductor memory technology is developing in the direction of increasing integration and reducing component size. In order to reduce product costs as much as possible, people hope to make as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet people's needs for current products. Summary of the invention

[0003] The present application aims at at least one disadvantage of the existing method and proposes a semiconductor structure, a memory and a manufacturing method thereof, and an electronic device.

[0004] In a first aspect, an embodiment of the present application provides a semiconductor structure, including: a first transistor disposed on one side of a substrate, the first transistor including:

[0005] An isolation column extending along a first direction perpendicular to the substrate;

[0006] A first semiconductor layer, the first semiconductor layer is arranged at the periphery of the isolation column, and the first semiconductor layer includes a first drain region, a first channel region and a first source region which are sequentially away from the substrate;

[0007] A first gate insulating layer and a first gate electrode are sequentially arranged around the periphery of the first channel region.

[0008] In a second aspect, an embodiment of the present application provides a memory, comprising: a plurality of semiconductor structures provided in the first aspect;

[0009] Along a second direction parallel to the substrate, the memory includes a plurality of rows of first transistors, and the first gate electrodes of the first transistors in each row are connected to form a write word line.

[0010] In a third aspect, an embodiment of the present application provides an electronic device, comprising: a memory as provided in the second aspect.

[0011] In a fourth aspect, an embodiment of the present application provides a method for manufacturing a memory, comprising:

[0012] Manufacturing first sacrificial semiconductor pillars arranged in an array on one side of the substrate, so that a first groove extending along the second direction is formed between two adjacent columns of the first sacrificial semiconductor pillars arranged along a third direction, and a first dielectric layer is provided between two adjacent rows of the first sacrificial semiconductor pillars arranged along the second direction, and the third direction has a designed angle with the second direction and is parallel to the substrate;

[0013] Manufacturing a second dielectric layer along the sidewall of the first trench; Manufacturing a third dielectric layer in the first trench;

[0014] The first dielectric layer and the second dielectric layer on the periphery of the first sacrificial drain and the first sacrificial channel region of the first sacrificial semiconductor column are removed; a first gate insulating layer and a first gate electrode are sequentially manufactured on the periphery of the first sacrificial channel region so that the first gate electrodes located in the same row along the second direction are connected to form a write word line; a fourth dielectric layer is manufactured on the periphery of the first sacrificial drain;

[0015] The first sacrificial semiconductor column is removed to form a first groove arranged in an array; a first semiconductor layer and an isolation column are sequentially manufactured along the first groove to form a first transistor arranged in an array, so that the isolation column fills the first groove.

[0016] The beneficial technical effects brought about by the technical solution provided by the embodiment of the present application include:

[0017] The first semiconductor layer is arranged at the periphery of the isolation column, and the first semiconductor layer can be manufactured after the first gate electrode is manufactured, which can ensure the integrity of the first semiconductor layer and avoid leakage caused by consumption of the first semiconductor layer, which is beneficial to improving the performance of the first transistor.

[0018] Moreover, the first transistor adopts a Gate-All-Around FET mode, which can increase the control capability of the first gate electrode, reduce the operating voltage, and improve the energy efficiency ratio.

[0019] Additional aspects and advantages of the present application will be partially given in the following description, which will become apparent from the following description, or will be understood through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0021] Figure 1 A schematic diagram of a semiconductor structure provided in an embodiment of the present application;

[0022] Figure 2 A schematic diagram of another semiconductor structure provided in an embodiment of the present application;

[0023] Figure 3 A schematic diagram of another semiconductor structure provided in an embodiment of the present application;

[0024] Figure 4 A schematic top view of a memory provided in an embodiment of the present application;

[0025] Figure 5 for Figure 4 A schematic diagram of a cross-sectional structure of a memory at AA;

[0026] Figure 6 for Figure 4 A schematic diagram of a cross-sectional structure at BB of a memory;

[0027] Figure 7 for Figure 4 A schematic diagram of a cross-sectional structure of a memory at CC;

[0028] Figure 8 for Figure 4 A schematic cross-sectional structure diagram of a memory at DD;

[0029] Fig. 9 A schematic diagram of a cross-sectional structure at AA of another memory provided in an embodiment of the present application;

[0030] Fig.10 A schematic diagram of a cross-sectional structure at BB of another memory provided in an embodiment of the present application;

[0031] Fig.11 A schematic diagram of a cross-sectional structure at CC of another memory provided in an embodiment of the present application;

[0032] Fig.12 A schematic diagram of a cross-sectional structure at DD of another memory provided in an embodiment of the present application;

[0033] Fig.13 A schematic diagram of a cross-sectional structure at AA of another memory provided in an embodiment of the present application;

[0034] Fig.14 A schematic diagram of a cross-sectional structure at BB of another memory provided in an embodiment of the present application;

[0035] Fig.15 A schematic diagram of a cross-sectional structure at CC of another memory provided in an embodiment of the present application;

[0036] Fig.16 A schematic cross-sectional structure diagram of a memory device at DD provided in an embodiment of the present application;

[0037] Fig.17A schematic diagram of a process for manufacturing a memory provided in an embodiment of the present application;

[0038] Figures 18 to 47 Schematic diagrams of various structures obtained by expanding the method in the flowchart of a method for manufacturing a memory provided in an embodiment of the present application;

[0039] Fig.48 A schematic diagram of a flow chart of manufacturing a second transistor in a method for manufacturing a memory provided in an embodiment of the present application;

[0040] Figures 49 to 74 Schematic diagrams of various structures obtained in the process of manufacturing a second transistor in the method expanded in the flowchart of a method for manufacturing a memory provided in an embodiment of the present application;

[0041] Fig.75 A schematic diagram of a flow chart of manufacturing another second transistor in an expanded method of a flow chart of a method for manufacturing a memory provided in an embodiment of the present application;

[0042] Figure 76 to Figure 92 The flowchart of a method for manufacturing a memory provided in an embodiment of the present application is a schematic diagram of various structures obtained in the process of manufacturing another second transistor in the method.

[0043] Description of reference numerals:

[0044] 1- substrate;

[0045] 2-first transistor; 21-isolation column; 22-first semiconductor layer; 221-first drain region; 222-first channel region; 223-first source region; 23-first gate insulating layer; 24-first gate electrode;

[0046] 3-second transistor; 31-vertical column; 311-second gate electrode; 312-second gate insulating layer; 313-second semiconductor layer; 32-second source region; 33-second drain region; 34-back gate electrode; 35-back gate insulating layer;

[0047] 4- first isolation layer;

[0048] 51-write word line; 52-write bit line; 53-read bit line; 54-read word line / source line; 55-source layer;

[0049] 61-first sacrificial semiconductor column; 611-first sacrificial drain; 612-first sacrificial channel region; 62-first trench; 63-first dielectric layer; 631-initial first dielectric layer; 64-second dielectric layer; 65-third dielectric layer; 66-fourth dielectric layer; 67-first groove;

[0050] 71 - initial first isolation layer; 72 - second sacrificial semiconductor layer; 73 - second trench; 74 - third trench; 75 - fourth trench; 76 - fifth trench; 77 - sixth trench;

[0051] 81-second sacrificial semiconductor column; 811-second sacrificial source; 812-second sacrificial channel region; 82-second groove; 83-initial read bit line; 84-second isolation layer; 85-third isolation layer; 86-read word line layer / source line layer; 87-fourth isolation layer; 88-write bit line layer; 89-first sacrificial semiconductor layer;

[0052] 91 - fifth isolation layer; 92 - sixth isolation layer. DETAILED DESCRIPTION

[0053] The embodiments of the present application are described below in conjunction with the drawings in the present application. It should be understood that the implementation methods described below in conjunction with the drawings are exemplary descriptions for explaining the technical solutions of the embodiments of the present application and do not constitute a limitation on the technical solutions of the embodiments of the present application.

[0054] Those skilled in the art will appreciate that, unless expressly stated otherwise, the singular forms "a", "an", "said" and "the" used herein may also include plural forms. It should be further understood that the term "comprising" used in the specification of the present application refers to the presence of the features, integers, steps, operations, elements and / or components, but does not exclude the implementation of other features, information, data, steps, operations, elements, components and / or combinations thereof supported by the technical field. The term "and / or" used herein refers to at least one of the items defined by the term, for example, "A and / or B" may be implemented as "A", or as "B", or as "A and B".

[0055] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below in conjunction with the accompanying drawings.

[0056] The research and development ideas of this application include: In the related art, when the material of the semiconductor column is silicon, there are problems of excessive semiconductor column consumption and source-gate leakage in the process of manufacturing word lines. In addition, the drain contact area is small, and voids are formed during the metal filling process, which will cause the bit line to have a higher contact resistance and instability of the interconnection resistance. In addition, in the 1T1C (1 transistor 1 capacitor) structure, the capacitor volume is large, and the high aspect ratio increases the process difficulty.

[0057] The following is a detailed description of the technical solution of the present application and how the technical solution of the present application solves the above technical problems with specific embodiments. It should be noted that the following implementations can refer to, draw on or combine with each other, and the same terms, similar features and similar implementation steps in different implementations will not be described repeatedly.

[0058] The present application embodiment provides a semiconductor structure. The schematic diagram of the semiconductor structure is as follows: Figure 1 As shown, it includes: a first transistor 2 arranged on one side of a substrate 1. The first transistor 2 includes: an isolation column 21, a first semiconductor layer 22, a first gate insulating layer 23 and a first gate electrode 24.

[0059] The isolation column 21 extends along a first direction perpendicular to the substrate 1 .

[0060] The first semiconductor layer 22 is disposed on the periphery of the isolation column 21 , and includes a first drain region 221 , a first channel region 222 , and a first source region 223 which are sequentially away from the substrate 1 .

[0061] The first gate insulating layer 23 and the first gate electrode 24 are sequentially disposed around the periphery of the first channel region 222 .

[0062] In the related art, after manufacturing the silicon pillars, in the process of manufacturing the gate electrodes, too many silicon pillars are easily consumed, resulting in serious leakage.

[0063] In this embodiment, the first semiconductor layer 22 is arranged on the periphery of the isolation column 21, and the first semiconductor layer 22 can be manufactured after the first gate electrode 24 is manufactured, which can ensure the integrity of the first semiconductor layer 22 and avoid leakage problems caused by consumption of the first semiconductor layer 22, which is beneficial to improving the performance of the first transistor 2.

[0064] Moreover, the first transistor 2 adopts a gate-all-around FET mode, which can increase the control capability of the first gate electrode 24, reduce the operating voltage, improve the energy efficiency, and enhance the performance of the memory by increasing the driving current.

[0065] Optionally, the material of the first channel region 222 may be indium gallium zinc oxide (InGaZnO), and the leakage current of the first transistor 2 is small, thereby improving the working performance of the memory.

[0066] In some embodiments, the material of the first channel region 222 may further include one or more of the following: indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium tungsten oxide (InWO, IWO), titanium oxide ( The materials used may include TiO2, zinc oxynitride (ZnON), magnesium zinc oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), zirconium zinc tin oxide (ZrZnSnO), etc. As long as the leakage current of the transistor can meet the requirements, the specific adjustment can be made according to the actual situation.

[0067] The material of the first channel region 222 mentioned above only emphasizes the element type of the material, and does not emphasize the atomic ratio in the material and the film quality of the material.

[0068] Optionally, refer to Figure 2 The semiconductor structure further includes: a second transistor 3 disposed on a side of the first transistor 2 away from the substrate 1 . The second transistor 3 includes a vertical column 31 .

[0069] The vertical column 31 extends in a direction perpendicular to the substrate 1 . The vertical column 31 includes a second gate electrode 311 , a second gate insulating layer 312 and a second semiconductor layer 313 sequentially surrounding the second gate electrode 311 . The second gate electrode 311 is connected to the first source region 223 .

[0070] In this embodiment, the second transistor 3 is stacked above the first transistor 2, that is, a 2T0C (2 transistors 0 capacitor) structure is adopted, which omits a larger capacitor structure, can increase integration, and reduce the size and cost of the memory.

[0071] Moreover, the second transistor 3 adopts a vertical channel-all-around (CAA) transistor mode, which has good thermal stability and reliability.

[0072] In one embodiment, reference Figure 2 The second transistor 3 further includes a second source region 32 and a second drain region 33 .

[0073] The second drain region 33 surrounds an outer periphery of an end of the second semiconductor layer 313 close to the substrate 1 , and the second source region 32 surrounds an outer periphery of an end of the second semiconductor layer 313 away from the substrate 1 .

[0074] In this embodiment, the second semiconductor layer 313 between the second drain region 33 and the second source region 32 is an effective second semiconductor layer 313 (channel region). During the operation of the second transistor 3 , the second drain region 33 and the second source region 32 are connected through the effective second semiconductor layer 313 .

[0075] In another embodiment, the second transistor 3 of the present application can also be a transistor controlled by a dual-gate structure, referring to Figure 3 The second transistor 3 further includes a second source region 32 , a second drain region 33 , a back gate electrode 34 and a back gate insulating layer 35 .

[0076] The second source region 32 surrounds the periphery of one end of the second semiconductor layer 313 close to the substrate 1 , and is used for grounding. The second drain region 33 surrounds the periphery of one end of the second semiconductor layer 313 away from the substrate 1 .

[0077] The back gate insulating layer 35 and the back gate electrode 34 are sequentially disposed on the periphery of the second semiconductor layer 313 , and the back gate insulating layer 35 and the back gate electrode 34 are disposed between the second source region 32 and the second drain region 33 .

[0078] In this embodiment, the second transistor 3 can be a dual-gate controlled transistor, which can enhance the control capability of the second transistor 3 .

[0079] Optionally, refer to Figure 2 and Figure 3 The semiconductor structure further includes a first isolation layer 4 disposed between the first transistor 2 and the second transistor 3 .

[0080] In this embodiment, the material of the first isolation layer 4 can be a material with a high dielectric constant, which can isolate the first transistor 2 from the second transistor 3 and also increase the charge storage capacity.

[0081] Based on the same inventive concept, the embodiment of the present application provides a memory, the structural diagram of which is as follows: Figures 4 to 8 As shown, it includes a plurality of semiconductor structures provided in the above embodiments arranged in an array.

[0082] Along a second direction parallel to the substrate 1 , the memory includes a plurality of rows of first transistors 2 , and the first gate electrodes 24 of the first transistors 2 in each row are connected to form a write word line 51 .

[0083] In this embodiment, the first semiconductor layer 22 in the first transistor 2 is arranged on the periphery of the isolation column 21, and the first semiconductor layer 22 can be manufactured after the first gate electrode 24 is manufactured, which can ensure the integrity of the first semiconductor layer 22 and avoid consuming the first semiconductor layer 22, which is beneficial to improving the performance of the first transistor 2.

[0084] Optionally, refer to Figure 5 Along the third direction, the memory includes a plurality of columns of first transistors 2, the first drain region 221 of each first transistor 2 in each column is connected to a write bit line 52, and the third direction is parallel to the substrate 1 and has a designed angle with the second direction.

[0085] In this embodiment, by sharing one write bit line 52, the integration level of the memory can be improved.

[0086] In a feasible embodiment, Figures 9 to 12 Along the second direction, the memory further includes a plurality of rows of second transistors 3 arranged on a side of the first transistor 2 away from the substrate 1 , and the second drain regions 33 of the second transistors 3 in each row are connected to the same read bit line 53 .

[0087] Along the third direction, the memory further includes a plurality of columns of second transistors 3 , and the second source regions 32 of the second transistors 3 in each column are connected to the same source line 54 .

[0088] In this embodiment, the second transistor 3 is stacked above the first transistor 2, eliminating a relatively large capacitor structure, thereby increasing integration and reducing the size and cost of the memory.

[0089] In another feasible embodiment, Figures 13 to 16 The memory further includes a source layer 55 for connecting to a reference power source (eg, ground), and the source layer 55 is connected to the second source region 32 of the second transistor 3 of each semiconductor structure.

[0090] Along the second direction, the memory further includes a plurality of rows of second transistors 3 , and the back gate electrodes 35 of the second transistors 3 in each row are connected to form a read word line 54 .

[0091] Along the third direction, the memory further includes a plurality of columns of second transistors 3 , and the second drain regions 33 of the second transistors 3 in each column are connected to the same read bit line 53 .

[0092] In this embodiment, the second transistor 3 can be a dual-gate controlled transistor, which can enhance the control capability of the second transistor 3 .

[0093] Based on the same inventive concept, an embodiment of the present application provides an electronic device, which includes any memory provided in the above embodiments.

[0094] In this embodiment, since the electronic device adopts any one of the memories provided in the aforementioned embodiments, its principles and technical effects can be referred to in the aforementioned embodiments and will not be described in detail here.

[0095] Optionally, the electronic device may include a smart phone, a computer, a tablet computer, artificial intelligence, a wearable device or a smart mobile terminal.

[0096] It should be noted that electronic devices are not limited to the above-mentioned ones. Those skilled in the art can set any one of the memories provided in the above-mentioned embodiments of the present application in different devices according to actual application requirements, so as to obtain the electronic device provided in the embodiments of the present application.

[0097] Based on the same inventive concept, the present application embodiment provides a method for manufacturing a memory, and the flowchart of the manufacturing method is as follows: Fig.17 As shown, the method comprises steps S1 to S4:

[0098] S1: An array of first sacrificial semiconductor columns 61 is manufactured on one side of a substrate 1, so that a first groove 62 extending along the second direction is formed between two adjacent columns of the first sacrificial semiconductor columns 61 arranged along a third direction, and a first dielectric layer 63 is provided between two adjacent rows of the first sacrificial semiconductor columns 61 arranged along the second direction, and the third direction has a designed angle with the second direction and is parallel to the substrate 1.

[0099] After step S1, the obtained structural diagram is as follows Figure 28 to Figure 31 shown.

[0100] In this embodiment, the material of the first sacrificial semiconductor column 61 may be polysilicon. As a sacrificial structure, the first sacrificial semiconductor column 61 has a relatively high etching selectivity and is easy to remove later. The material of the first dielectric layer 63 may be silicon dioxide.

[0101] S2 : forming a second dielectric layer 64 along the sidewall of the first trench 62 ; forming a third dielectric layer 65 in the first trench 62 .

[0102] After step S2, the obtained structural diagram is as follows Figure 32 to Figure 35 shown.

[0103] In this embodiment, the material of the second dielectric layer 64 may be silicon dioxide, and the material of the third dielectric layer 65 may be silicon nitride. The second dielectric layer 64 and the third dielectric layer 65 have a significant etching ratio, and the write line 51 is subsequently manufactured by removing the second dielectric layer 64, and the third dielectric layer 65 can play a role in isolating the write line 51.

[0104] Optionally, the second dielectric layer 64 and the third dielectric layer 65 may be obtained by using a deposition process such as ALD (Atomic Layer Deposition).

[0105] S3: Remove the first dielectric layer 63 and the second dielectric layer 64 around the first sacrificial drain 611 and the first sacrificial channel region 612 of the first sacrificial semiconductor column 61; sequentially manufacture the first gate insulating layer 23 and the first gate electrode 24 around the first sacrificial channel region 612, so that the first gate electrodes 24 located in the same row along the second direction are connected to form a write line 51; and manufacture the fourth dielectric layer 66 around the first sacrificial drain 611.

[0106] After removing the first sacrificial drain 611 of the first sacrificial semiconductor column 61 and the first dielectric layer 63 and the second dielectric layer 64 around the first sacrificial channel region 612 in step S3, the obtained structure diagram is as follows: Figure 36 to Figure 38 shown.

[0107] After step S3, the first gate insulating layer 23 and the first gate electrode 24 are sequentially manufactured around the first sacrificial channel region 612 so that the first gate electrodes 24 in the same row along the second direction are connected to form the write word line 51, the obtained structural schematic diagram is as follows: Figure 39 to Figure 41 .

[0108] After the fourth dielectric layer 66 is manufactured on the periphery of the first sacrificial drain 611 in step S3, the obtained structural schematic diagram is as follows: Figure 42 to Figure 44 shown.

[0109] S4: removing the first sacrificial semiconductor pillars 61 to form first grooves 67 arranged in an array; manufacturing the first semiconductor layer 22 and the isolation pillars 21 in sequence along the first grooves 67 to form first transistors 2 arranged in an array, so that the isolation pillars 21 fill the first grooves 67 .

[0110] After the first sacrificial semiconductor pillars 61 are removed in step S4 to form the first grooves 67 arranged in an array, the obtained structural schematic diagram is as follows: Figure 45 to Figure 47 shown.

[0111] After step S4, the first semiconductor layer 22 and the isolation column 21 are sequentially manufactured along the first groove 67 to form the first transistor 2 arranged in an array, so that the isolation column 21 fills the first groove 67. The obtained structural schematic diagram is as follows: Figures 5 to 8 shown.

[0112] In the present embodiment, by setting the first sacrificial semiconductor column 61, the first semiconductor layer 22 can be manufactured first; then the first sacrificial semiconductor column 61 is removed and then the first semiconductor layer 22 is manufactured, which can ensure the integrity of the first semiconductor layer 22 and avoid consuming the first semiconductor layer 22, which is beneficial to avoid serious leakage caused by excessive consumption of the first semiconductor layer 22, thereby improving the performance of the memory.

[0113] Optionally, in step S1, before manufacturing the first sacrificial semiconductor pillars 61 arranged in an array on one side of the substrate 1, the manufacturing method further includes:

[0114] A write bit line layer 88 and a first sacrificial semiconductor layer 89 are sequentially manufactured on one side of the substrate 1. The schematic diagram of the structure obtained in this step is as follows: Figures 18 to 21 shown.

[0115] The write bit line layer 88 and the first sacrificial semiconductor layer 89 are patterned to obtain the write bit line 52 and the sixth groove 77, so that the write bit line 52 and the sixth groove 77 extend along the third direction and are arranged at intervals along the second direction. Figure 22 to Figure 24 shown.

[0116] An initial first dielectric layer 631 is fabricated in the sixth trench 77. The schematic diagram of the structure obtained in this step is as follows Figure 25 to Figure 27 shown.

[0117] Optionally, a deposition process such as CVD (Chemical Vapor Deposition), PVD (Physical Vapor Deposition) or ALD (Atomic Layer Deposition) may be used to deposit the write bit line layer 88 and the first sacrificial semiconductor layer 89 on one side of the substrate 1 .

[0118] Optionally, after manufacturing the initial first dielectric layer 631 in the sixth trench 77 and before manufacturing the first sacrificial semiconductor pillars 61 arranged in an array on one side of the substrate 1, the manufacturing method further includes:

[0119] The first sacrificial semiconductor layer 89 and the initial first dielectric layer 631 are patterned to obtain a first sacrificial semiconductor pillar 61 and a first dielectric layer 63 .

[0120] In this embodiment, the first sacrificial semiconductor layer 89 and the initial first dielectric layer 631 are patterned, specifically: the first sacrificial semiconductor layer 89 is grooved along the second direction to obtain a first groove 62, to form an array of first sacrificial semiconductor columns 61, and to form a first dielectric layer 63 between two adjacent rows of first sacrificial semiconductor columns 61 arranged along the second direction.

[0121] In one practicable manner, after the first semiconductor layer 22 and the isolation column 21 are sequentially manufactured along the first groove 67 in step S4, the manufacturing method further includes steps S101 to S106. The flow chart of steps S101 to S106 is as follows: Fig.48 shown.

[0122] S101 : manufacturing an initial first isolation layer 71 on a side of the first transistor 2 away from the substrate 1 ; manufacturing second sacrificial semiconductor pillars 81 arranged in an array on the initial first isolation layer 71 .

[0123] Optionally, in step S101, manufacturing second sacrificial semiconductor pillars 81 arranged in an array on the initial first isolation layer 71 includes:

[0124] A second sacrificial semiconductor layer 72 is fabricated on the initial first isolation layer 71. The schematic diagram of the structure after this step is as shown in FIG. Fig.49 and Fig.50 shown.

[0125] The second sacrificial semiconductor layer 72 is patterned to obtain an array of second sacrificial semiconductor pillars 81, as well as second trenches 73 extending along the third direction and arranged at intervals along the second direction, and third trenches 74 arranged at intervals along the third direction and extending along the second direction. The schematic diagram of the structure after this step is as follows: Fig.51 and Fig.52 shown.

[0126] S102: manufacturing a plurality of read bit lines 53, such that the read bit lines 53 are disposed at the periphery of each second sacrificial semiconductor pillar 81 located in the same row along the second direction close to one end of the substrate 1, and the plurality of read bit lines 53 are arranged at intervals along the third direction and extend along the second direction.

[0127] Optionally, in step S102, manufacturing the read bit line 53 includes:

[0128] The initial read bit line 83 is manufactured at the bottom of the second trench 73 and the third trench 74. The schematic diagram of the structure after this step is as follows: Fig.53 and Fig.54 shown.

[0129] A second isolation layer 84 is manufactured in the second trench 73 and the third trench 74. The schematic diagram of the structure after this step is as follows Fig.55 and Fig.56 shown.

[0130] The second isolation layer 84 and the initial read bit line 83 are patterned to obtain the read bit line 53 and the fourth trench 75, so that the read bit line 53 and the fourth trench 75 are arranged at intervals along the third direction and extend along the second direction. Fig.57 and Fig.58 shown.

[0131] The third isolation layer 85 is manufactured in the fourth trench 75. The schematic diagram of the structure after this step is as follows Fig.59 and Fig.60 shown.

[0132] S103: manufacturing a plurality of source lines 54 so that the source lines 54 are disposed at the periphery of the second sacrificial channel regions 812 of the second sacrificial semiconductor pillars 81 located in the same column along the third direction, and the source lines 54 extend along the third direction and are arranged at intervals along the second direction.

[0133] Optionally, in step S103, manufacturing the source line 54 includes:

[0134] Remove the dielectric corresponding to the second sacrificial source 811 of the second sacrificial semiconductor column 81. The schematic diagram of the structure after this step is as follows: Fig.61 and Fig.62 shown.

[0135] The source line layer 86 is manufactured so that the source line layer 86 surrounds the outer periphery of the second sacrificial source electrode 811 of the second sacrificial semiconductor column 81. The schematic diagram of the structure after this step is as follows: Fig.63 and Fig.64 shown.

[0136] The source line layer 86 is patterned to obtain the source line 54 and the fifth groove 76, so that the source line 54 and the fifth groove 76 extend along the third direction and are arranged at intervals along the second direction. Fig.65 and Fig.66 shown.

[0137] A fourth isolation layer 87 is fabricated in the fifth trench 76. The schematic diagram of the structure after this step is as follows: Fig.67 and Fig.68 shown.

[0138] S104 : removing the second sacrificial semiconductor pillars 81 to form second grooves 82 arranged in an array; and sequentially manufacturing a second semiconductor layer 313 and a second gate insulating layer 312 along the sidewalls of the second grooves 82 .

[0139] After the second sacrificial semiconductor pillars 81 are removed in step S104 to form the second grooves 82 arranged in an array, the obtained structural schematic diagram is as follows: Fig.69 and Fig.70 shown.

[0140] After the second semiconductor layer 313 and the second gate insulating layer 312 are sequentially manufactured along the side wall of the second groove 82 in step S104, the obtained structure schematic diagram is as follows: Fig.71 and Fig.72 shown.

[0141] S105 : removing the initial first isolation layer 71 above the isolation column 21 and the isolation column 21 corresponding to the first source region 223 to expose the sidewall of the first source region 223 , thereby obtaining a first isolation layer 4 formed by the initial first isolation layer 71 .

[0142] After step S105, the obtained structural diagram is as follows: Fig.73 and Fig.74 shown.

[0143] S106 : manufacturing a second gate electrode 311 in the second groove 82 , so that the second gate electrode 311 is connected to the first source region 223 .

[0144] After step S106, the obtained structural diagram is as follows: Figures 9 to 12 shown.

[0145] In another feasible manner, after the first semiconductor layer 22 and the isolation column 21 are sequentially manufactured along the first groove 67 in step S4, the manufacturing method further includes steps S201 to S207. The flow chart of steps S201 to S207 is as follows: Fig.75 shown.

[0146] S201 : manufacturing an initial first isolation layer 71 on a side of the first transistor 2 away from the substrate 1 ; manufacturing second sacrificial semiconductor pillars 81 arranged in an array on the initial first isolation layer 71 .

[0147] S202 : manufacturing a source layer 55 , so that the source layer 55 surrounds the outer periphery of each second sacrificial semiconductor pillar 81 close to one end of the substrate 1 , and the source layer 55 is used for grounding.

[0148] After steps S201 and S202, the obtained structural diagram is as follows: Figure 76 to Figure 77 shown.

[0149] After step S202 and before step S203, the manufacturing method further includes:

[0150] The second isolation layer 84 around the second sacrificial source 811 and the second sacrificial channel region 812 is removed. The schematic diagram of the structure obtained in this step is as follows Fig.78 and Fig.79 shown.

[0151] S203: Manufacture a back gate insulating layer 35 and a back gate electrode 34 so that the back gate insulating layer 35 and the back gate electrode 34 are sequentially located at the periphery of the second sacrificial channel region 812 of the second sacrificial semiconductor column 81, and the back gate electrodes 34 located in the same row are connected to form a read word line 54, and the read word lines 54 are arranged at intervals along the third direction.

[0152] After step S203, the obtained structural diagram is as follows: Figure 83 to Figure 84 shown.

[0153] In this embodiment, two adjacent columns of read word lines 54 along the third direction are isolated by a dielectric.

[0154] Optionally, in step S203, manufacturing the back gate electrode 34 includes:

[0155] A back gate insulating layer 35 and a read word line layer 86 are sequentially formed around the second sacrificial channel region 812 .

[0156] A fifth isolation layer 91 is fabricated above the gate insulating layer 35 and the read word line layer 86. After this step, the resulting structure is shown in FIG. Figure 80 to Figure 82 shown.

[0157] The read word line layer 86 and the fifth isolation layer 91 are patterned to obtain the read word line 54 and trenches (not labeled), such that the trenches are arranged at intervals along the third direction and extend along the second direction.

[0158] The sixth isolation layer 92 is manufactured in the groove. Fig.83 and Fig.84 .

[0159] S204 : manufacturing the read bit lines 53 so that the read bit lines 53 are disposed on the periphery of the second sacrificial source electrodes 811 of the second sacrificial semiconductor pillars 81 in the same column along the third direction, and the read bit lines 53 extend along the third direction and are arranged at intervals along the second direction.

[0160] After step S204, the obtained structural diagram is as follows: Figure 85 to Figure 86 shown.

[0161] S205 : removing the second sacrificial semiconductor pillars 81 to form second grooves 82 arranged in an array; and sequentially manufacturing a second semiconductor layer 313 and a second gate insulating layer 312 along the sidewalls of the second grooves 82 .

[0162] After the second sacrificial semiconductor pillars 81 are removed in step S205 to form the second grooves 82 arranged in an array, the obtained structure diagram is as follows: Fig.87 and Fig.88 shown.

[0163] After the second semiconductor layer 313 and the second gate insulating layer 312 are sequentially manufactured along the sidewall of the second groove 82 in step S205, the obtained structure schematic diagram is as follows: Fig.89 and Fig.90 shown.

[0164] S206 : removing the initial first isolation layer 71 above the isolation column 21 and the isolation column 21 corresponding to the first source region 223 to expose the sidewall of the first source region 223 , thereby obtaining a first isolation layer 4 formed by the initial first isolation layer 71 .

[0165] After step S201, the obtained structural diagram is as follows: Figure 91 to Figure 92 shown.

[0166] S207 : manufacturing a second gate electrode 311 in the second groove 82 , so that the second gate electrode 311 is connected to the first source region 223 .

[0167] After step S207, the obtained structural diagram is as follows: Figures 13 to 16 shown.

[0168] By applying the embodiments of the present application, at least the following beneficial effects can be achieved:

[0169] In the embodiment of the present application, the first semiconductor layer is arranged on the periphery of the isolation column, and the first semiconductor layer can be manufactured after the first gate electrode is manufactured, which can ensure the integrity of the first semiconductor layer and avoid leakage problems caused by consumption of the first semiconductor layer, which is beneficial to improving the performance of the first transistor.

[0170] Those skilled in the art will appreciate that the various operations, methods, steps, measures, and schemes in the processes discussed in this application may be alternated, altered, combined, or deleted. Further, other steps, measures, and schemes in the various operations, methods, and processes discussed in this application may also be alternated, altered, rearranged, decomposed, combined, or deleted. Further, the steps, measures, and schemes in the prior art that are similar to those disclosed in this application may also be alternated, altered, rearranged, decomposed, combined, or deleted.

[0171] In the description of the present application, the directions or positional relationships indicated by words such as "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside" and "outside" are based on the exemplary directions or positional relationships shown in the accompanying drawings. They are for the convenience of describing or simplifying the description of the embodiments of the present application, and do not indicate or imply that the referred device or component must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they should not be understood as limitations on the present application.

[0172] The terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise specified, "plurality" means two or more.

[0173] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0174] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0175] It should be understood that, although the various steps in the flowchart of the accompanying drawings are displayed in sequence according to the indication of the arrows, the order of implementation of these steps is not limited to the order indicated by the arrows. Unless there is a clear description herein, in some implementation scenarios of the embodiments of the present application, the steps in each process can be performed in other orders according to demand. Moreover, some or all of the steps in each flow chart may include multiple sub-steps or multiple stages based on actual implementation scenarios. Some or all of these sub-steps or stages may be executed at the same time, or may be executed at different times in different scenarios at the execution time, and the execution order of these sub-steps or stages may be flexibly configured according to demand, and the embodiments of the present application do not limit this.

[0176] The above is only a partial implementation method of the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the technical concept of the scheme of the present application, other similar implementation methods based on the technical ideas of the present application are also within the protection scope of the embodiments of the present application.

Claims

1. A semiconductor structure, characterized in that: include: A first transistor is provided on one side of the substrate, wherein the first transistor comprises: An isolation column extending along a first direction perpendicular to the substrate; A first semiconductor layer, the first semiconductor layer is arranged at the periphery of the isolation column, and the first semiconductor layer includes a first drain region, a first channel region and a first source region which are sequentially away from the substrate; A first gate insulating layer and a first gate electrode are sequentially arranged around the periphery of the first channel region.

2. The semiconductor structure according to claim 1, characterized in that: Also includes: A second transistor is disposed on a side of the first transistor away from the substrate; the second transistor comprises: A vertical column extends in a direction perpendicular to the substrate, the vertical column comprises a second gate electrode, a second gate insulating layer and a second semiconductor layer sequentially surrounding the outer periphery of the second gate electrode, and the second gate electrode is connected to the first source region.

3. The semiconductor structure according to claim 2, characterized in that: The second transistor further includes: a second source region and a second drain region; The second drain region surrounds an outer periphery of an end of the second semiconductor layer close to the substrate, and the second source region surrounds an outer periphery of an end of the second semiconductor layer far from the substrate.

4. The semiconductor structure according to claim 2, characterized in that: The second transistor further includes: a second source region and a second drain region, wherein the second source region surrounds an outer periphery of an end of the second semiconductor layer close to the substrate, and the second source region is used for grounding; and the second drain region surrounds an outer periphery of an end of the second semiconductor layer away from the substrate; A back gate electrode and a back gate insulating layer, wherein the back gate insulating layer and the back gate electrode are sequentially arranged at the periphery of the second semiconductor layer, and the back gate insulating layer and the back gate electrode are arranged between the second source region and the second drain region.

5. The semiconductor structure according to claim 3 or 4, characterized in that: Also included is a first isolation layer disposed between the first transistor and the second transistor.

6. A memory, characterized in that: A semiconductor structure according to any one of claims 1 to 5 comprising a plurality of array-arranged semiconductor structures; Along a second direction parallel to the substrate, the memory includes a plurality of rows of first transistors, and the first gate electrodes of the first transistors in each row are connected to form a write word line.

7. The memory according to claim 6, characterized in that: Along a third direction, the memory includes a plurality of columns of first transistors, and the first drain regions of the first transistors in each column are connected to a write bit line. The third direction is parallel to the substrate and has a designed angle with the second direction.

8. The memory according to claim 7, characterized in that: Along the second direction, the memory further comprises a plurality of rows of second transistors arranged on a side of the first transistor away from the substrate, and the second drain regions of the second transistors in each row are connected to the same read bit line; Along the third direction, the memory further includes a plurality of columns of second transistors, and the second source regions of the second transistors in each column are connected to the same source line.

9. The memory according to claim 7, characterized in that: The memory further comprises a source layer for connecting to a reference power source, wherein the source layer is connected to the second source region of the second transistor of each semiconductor structure; Along the second direction, the memory further comprises a plurality of rows of second transistors, and the back gate electrodes of the second transistors in each row are connected to form a read word line; Along the third direction, the memory further includes a plurality of columns of second transistors, and the second drain regions of the second transistors in each column are connected to the same read bit line.

10. An electronic device, characterized in that: include: A memory as claimed in any one of claims 6 to 9.

11. A method for manufacturing a memory, characterized in that: include: Manufacturing first sacrificial semiconductor pillars arranged in an array on one side of the substrate, so that a first groove extending along the second direction is formed between two adjacent columns of the first sacrificial semiconductor pillars arranged along a third direction, and a first dielectric layer is provided between two adjacent rows of the first sacrificial semiconductor pillars arranged along the second direction, and the third direction has a designed angle with the second direction and is parallel to the substrate; Manufacturing a second dielectric layer along the sidewall of the first trench; Manufacturing a third dielectric layer in the first trench; The first dielectric layer and the second dielectric layer on the periphery of the first sacrificial drain and the first sacrificial channel region of the first sacrificial semiconductor column are removed; a first gate insulating layer and a first gate electrode are sequentially manufactured on the periphery of the first sacrificial channel region so that the first gate electrodes located in the same row along the second direction are connected to form a write word line; a fourth dielectric layer is manufactured on the periphery of the first sacrificial drain; The first sacrificial semiconductor column is removed to form a first groove arranged in an array; a first semiconductor layer and an isolation column are sequentially manufactured along the first groove to form a first transistor arranged in an array, so that the isolation column fills the first groove.

12. The method for manufacturing a memory according to claim 11, characterized in that: After the first semiconductor layer and the isolation column are sequentially manufactured along the groove, the method further includes: Manufacturing an initial first isolation layer on a side of the first transistor away from the substrate; manufacturing second sacrificial semiconductor pillars arranged in an array on the initial first isolation layer; Manufacturing a plurality of read bit lines, such that the read bit lines are arranged at the periphery of each of the second sacrificial semiconductor pillars located in the same row along the second direction and close to one end of the substrate, and the plurality of read bit lines are arranged at intervals along the third direction and extend along the second direction; Manufacturing a plurality of source lines, such that the source lines are arranged at the periphery of the second sacrificial channel regions of the second sacrificial semiconductor pillars located in the same column along the third direction, and the source lines extend along the third direction and are arranged at intervals along the second direction; The second sacrificial semiconductor pillars are removed to form second grooves arranged in an array; a second semiconductor layer and a second gate insulating layer are sequentially manufactured along the sidewalls of the second grooves; Removing the initial first isolation layer above the isolation column and the isolation column corresponding to the first source region to expose the side wall of the first source region, thereby obtaining a first isolation layer formed by the initial first isolation layer; A second gate electrode is manufactured in the second groove, so that the second gate electrode is connected to the first source region.

13. The manufacturing method according to claim 12, characterized in that: The method comprises manufacturing an array of second sacrificial semiconductor pillars on the initial first isolation layer, comprising: fabricating a second sacrificial semiconductor layer on the initial first isolation layer; The second sacrificial semiconductor layer is patterned to obtain second sacrificial semiconductor pillars arranged in an array, second trenches extending along the third direction and arranged at intervals along the second direction, and third trenches arranged at intervals along the third direction and extending along the second direction.

14. The manufacturing method according to claim 13, characterized in that: Fabricate the read bit line, including: fabricating an initial read bit line at the bottom of the second trench and the third trench; manufacturing a second isolation layer in the second trench and the third trench; Patterning the second isolation layer and the initial read bit line to obtain a read bit line and a fourth trench, so that the read bit line and the fourth trench are arranged at intervals along the third direction and extend along the second direction; A third isolation layer is fabricated in the fourth trench.

15. The manufacturing method according to claim 14, characterized in that: Manufacturing source lines, including: removing the medium corresponding to the second sacrificial source electrode of the second sacrificial semiconductor column; Manufacturing a source line layer so that the source line layer surrounds the outer periphery of the second sacrificial source electrode of the second sacrificial semiconductor column; Patterning the source line layer to obtain source lines and fifth grooves, so that the source lines and the fifth grooves extend along the third direction and are arranged at intervals along the second direction; A fourth isolation layer is fabricated in the fifth trench.

16. The manufacturing method according to claim 11, characterized in that: Before manufacturing the first sacrificial semiconductor pillars arranged in an array on one side of the substrate, the method further includes: A write bit line layer and a first sacrificial semiconductor layer are sequentially manufactured on one side of the substrate; Patterning the write bit line layer and the first sacrificial semiconductor layer to obtain a write bit line and a sixth groove, so that the write bit line and the sixth groove both extend along the third direction and are arranged at intervals along the second direction; An initial first dielectric layer is fabricated in the sixth trench.

17. The manufacturing method according to claim 11, characterized in that: After the first semiconductor layer and the isolation column are sequentially manufactured along the first groove, the method further includes: Manufacturing an initial first isolation layer on a side of the first transistor away from the substrate; manufacturing second sacrificial semiconductor pillars arranged in an array on the initial first isolation layer; Manufacturing a source layer so that the source layer surrounds the outer periphery of each of the second sacrificial semiconductor pillars close to one end of the substrate, and the source layer is used to connect to a reference power supply; Manufacturing a back gate insulating layer and a back gate electrode, so that the back gate insulating layer and the back gate electrode are sequentially located at the periphery of the second sacrificial channel region of the second sacrificial semiconductor column, the back gate electrodes located in the same row are connected to form a read word line, and the read word lines are arranged at intervals along the third direction; Manufacturing a read bit line so that the read bit line is disposed at the periphery of the second sacrificial source of each of the second sacrificial semiconductor pillars located in the same column along the third direction, and the read bit line extends along the third direction and is arranged at intervals along the second direction; The second sacrificial semiconductor pillars are removed to form second grooves arranged in an array; a second semiconductor layer and a second gate insulating layer are sequentially manufactured along the sidewalls of the second grooves; Removing the initial first isolation layer above the isolation column and the isolation column corresponding to the first source region to expose the side wall of the first source region, thereby obtaining a first isolation layer formed by the initial first isolation layer; A second gate electrode is manufactured in the second groove, so that the second gate electrode is connected to the first source region.

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