A transistor, a manufacturing method thereof, and an electronic device

Abstract

The present invention discloses a transistor, a manufacturing method thereof, and an electronic device. The superjunction layer includes at least one of a P-type buffer structure and an N-type buffer structure. The P-type buffer structure is disposed between the P-column and the drift layer, and the N-type buffer structure is disposed between the N-column and the drift layer. Thus, the P-type buffer structure can equivalently longitudinally expand the contact surface between the P-column and the drift layer, and the N-type buffer structure can equivalently longitudinally expand the contact surface between the N-column and the drift layer, avoiding the generation of local hot spots between the superjunction layer and the drift layer, thereby avoiding transistor damage and failure and improving the reliability of the transistor.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a transistor, a manufacturing method thereof, and an electronic device. Background Art

[0002] Transistors such as Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) generally include a substrate and an epitaxial layer disposed on the substrate. The epitaxial layer includes a buffer layer, a drift layer, a superjunction layer, and a P-well layer that are sequentially stacked. When the MOSFET is irradiated by rays in the external environment or a relatively high voltage is applied to the drain voltage, etc., electric field aggregation occurs between the superjunction layer and the drift layer, resulting in an increase in the impact ionization level at this position and generating local hot spots, leading to a temperature increase. If the temperature at this position rises to the sublimation temperature or failure temperature of the manufacturing material of the epitaxial layer, it will cause damage and failure of the MOSFET. Summary of the Invention

[0003] Embodiments of the present invention provide a transistor, a manufacturing method thereof, and an electronic device, so as to avoid generating local hot spots between the superjunction layer and the drift layer, thereby avoiding damage and failure of the transistor and improving the reliability of the transistor.

[0004] In a first aspect, an embodiment of the present invention provides a transistor, including: a first electrode layer, a buffer layer, a drift layer, and a superjunction layer that are sequentially stacked; the superjunction layer includes a plurality of P-columns and a plurality of N-columns, the extending directions of the P-columns and the N-columns are parallel to the stacking direction, the P-columns and the N-columns are alternately arranged along a first direction, and the first direction is perpendicular to the stacking direction;

[0005] The superjunction layer further includes at least one of a P-type buffer structure and an N-type buffer structure, the P-type buffer structure is disposed between the P-column and the drift layer, and the N-type buffer structure is disposed between the N-column and the drift layer.

[0006] In a second aspect, an embodiment of the present invention provides a manufacturing method of a transistor, including:

[0007] Forming a stacked buffer layer and drift layer in sequence;

[0008] Forming at least one of a P-type buffer structure and an N-type buffer structure on a surface of the drift layer facing away from the buffer layer;

[0009] Forming a superjunction layer;

[0010] Among them, the superjunction layer includes a plurality of P-columns and a plurality of N-columns. The extending directions of the P-columns and the N-columns are parallel to the stacking direction. The P-columns and the N-columns are arranged alternately along a first direction, and the first direction is perpendicular to the stacking direction. A P-type buffer structure is disposed between the P-column and the drift layer, and the P-type buffer structure includes at least one P-type buffer layer. An N-type buffer structure is disposed between the N-column and the drift layer.

[0011] In a third aspect, an embodiment of the present invention provides an electronic device, including the transistor as provided in the embodiment of the present invention.

[0012] The beneficial effects of the present invention are as follows:

[0013] A transistor, a manufacturing method thereof, and an electronic device provided in an embodiment of the present invention. The superjunction layer includes at least one of a P-type buffer structure and an N-type buffer structure. The P-type buffer structure is disposed between the P-column and the drift layer, and the N-type buffer structure is disposed between the N-column and the drift layer. In this way, the P-type buffer structure can equivalently longitudinally expand the contact surface between the P-column and the drift layer, and the N-type buffer structure can equivalently longitudinally expand the contact surface between the N-column and the drift layer, so that the electric field is dispersed in the P-type buffer structure and the N-type buffer structure, avoiding the generation of local hot spots between the superjunction layer and the drift layer, thereby avoiding transistor damage and failure and improving the reliability of the transistor. Description of the Drawings

[0014] Figure 1 It is a schematic structural diagram of a transistor provided in an embodiment of the present invention;

[0015] Figure 2 It is a schematic structural diagram of another transistor provided in an embodiment of the present invention;

[0016] Figure 3 It is a schematic structural diagram of yet another transistor provided in an embodiment of the present invention;

[0017] Figure 4 It is a schematic structural diagram of still another transistor provided in an embodiment of the present invention;

[0018] Figure 5 It is a schematic structural diagram of still another transistor provided in an embodiment of the present invention;

[0019] Figure 6 It is a schematic structural diagram of an N-type doping portion provided in an embodiment of the present invention;

[0020] Figure 7 It is a simulation diagram provided in an embodiment of the present invention;

[0021] Figure 8 It is a flowchart of a manufacturing method of a transistor provided in an embodiment of the present invention;

[0022] Figure 9 Schematic structural diagram of an electronic device provided in an embodiment of the present invention.

[0023] Explanation of reference numerals:

[0024] 10 - First electrode layer, 20 - Buffer layer, 30 - Drift layer, 40 - Superjunction layer, 41 - P column, 42 - N column, 43 - P-type buffer structure, 43a - First P-type buffer layer, 43b - Second P-type buffer layer, 43c - Third P-type buffer layer, 43d - Fourth P-type buffer layer, 44 - N-type buffer structure, 44a - First N-type buffer layer, 44b - Second N-type buffer layer, 44c - Third N-type buffer layer, 44d - Fourth N-type buffer layer, 45 - N-type doping part, 50 - P-well layer, 60 - Interlayer dielectric layer, 70 - Second electrode layer, 80 - Hole recombination structure, 81 - N+ doping part, 82 - N- doping part, 91 - Third electrode, 92 - Gate oxide layer, 93 - P+ contact area, 94 - N+ electrode contact area, 95 - Trench, 96 - P+ shielding layer, 101 - Substrate, 102 - P+ doping layer, m1 - Epitaxial layer. Detailed implementation manners

[0025] Next, with reference to the accompanying drawings, the detailed implementation manners of a transistor, its manufacturing method, and an electronic device provided in an embodiment of the present invention will be described in detail. It should be noted that the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0026] An embodiment of the present invention provides a transistor, as Figure 1 and Figure 2 shown, the transistor may include: a first electrode layer 10, a buffer layer 20, a drift layer 30, and a superjunction layer 40 that are sequentially stacked; the superjunction layer 40 includes a plurality of P columns 41 and a plurality of N columns 42, and the extending directions of the P columns 41 and the N columns 42 are parallel to the stacking direction, and the stacking direction may be the Figure 1 and Figure 2 z direction shown in, the P columns 41 and the N columns 42 are alternately arranged along a first direction, the first direction is perpendicular to the stacking direction, and the first direction may be the Figure 1 and Figure 2 x direction shown in or a direction perpendicular to the Figure 1 and Figure 2 plane of the paper shown; and Figure 1 and Figure 2 only show a partial number of P columns 41 and a partial number of N columns 42, and the set numbers of the P columns 41 and the N columns 42 may be set according to actual needs, and no specific limitation is made here.

[0027] The superjunction layer 40 further includes at least one of a P-type buffer structure 43 and an N-type buffer structure 44. For example, the superjunction layer 40 includes the P-type buffer structure 43 but does not include the N-type buffer structure 44, or the superjunction layer 40 does not include the P-type buffer structure 43 but includes the N-type buffer structure 44, or the superjunction layer 40 includes both the P-type buffer structure 43 and the N-type buffer structure 44. The P-type buffer structure 43 is disposed between the P-column 41 and the drift layer 30, and the N-type buffer structure 44 is disposed between the N-column 42 and the drift layer 30.

[0028] In this way, even if the transistor is irradiated by rays in the external environment or a relatively high voltage is applied to the drain voltage, the P-type buffer structure 43 can equivalently extend the contact surface between the P-column 41 and the drift layer 30 longitudinally, avoiding electric field concentration between the P-column 41 and the drift layer 30. The N-type buffer structure 44 can equivalently extend the contact surface between the N-column 42 and the drift layer 30 longitudinally, avoiding electric field concentration between the N-column 42 and the drift layer 30, so that the electric field is dispersed in the P-type buffer structure 43 and the N-type buffer structure 44, avoiding the generation of local hot spots between the superjunction layer 40 and the drift layer 30, reducing the temperature at the interface between the superjunction layer 40 and the drift layer 30, and further avoiding the sublimation or failure of the materials at the interface between the superjunction layer 40 and the drift layer 30, thereby avoiding the damage and failure of the transistor and improving the reliability of the transistor.

[0029] Optionally, the doping concentration of the P-type buffer structure 43 can be less than the doping concentration of the P-column 41 and greater than the doping concentration of the drift layer 30. In this way, the difference in doping concentration at the interface between the superjunction layer 40 and the drift layer 30 can be alleviated. Since the greater the difference in doping concentration, the greater the peak temperature may be, the reduction of the difference in doping concentration can reduce the peak temperature at the interface, thereby avoiding the generation of local hot spots.

[0030] Further, the P-type buffer structure 43 includes at least one P-type buffer layer. For example, there can be one P-type buffer layer. As Figure 1 shown, there is one P-type buffer layer, and this P-type buffer layer can be called the first P-type buffer layer 43a. In this way, the contact surface between the P-column 41 and the drift layer 30 can be extended through one P-type buffer layer. Or, there can be multiple P-type buffer layers. As Figure 3 shown, there are four P-type buffer layers. Along the direction from the superjunction layer 40 to the drift layer 30, these four P-type buffer layers can be the first P-type buffer layer 43a, the second P-type buffer layer 43b, the third P-type buffer layer 43c, and the fourth P-type buffer layer 43d respectively. Along the direction from the drift layer 30 to the superjunction layer 40, that is Figure 3In the z direction, the doping concentration of each P-type buffer layer gradually increases, which can further reduce the doping concentration difference at the interface between the superjunction layer 40 and the drift layer 30, further reduce the peak temperature at the interface, and thus further eliminate local hot spots. Of course, when there are multiple P-type buffer layers, along the direction from the superjunction layer 40 to the drift layer 30, the doping concentration of each P-type buffer layer can also decrease step by step, as long as a decreasing trend can be presented.

[0031] Alternatively, the doping concentration of the P-type buffer structure 43 can also be set to be greater than the doping concentration of the P pillar 41 or less than the doping concentration of the drift layer 30. In this way, the contact surface between the P pillar 41 and the drift layer 30 can also be longitudinally extended. However, compared with the doping concentration setting method introduced above, the degree of reduction in the peak temperature at the interface will be smaller, but the peak temperature at the interface can still be reduced to a certain extent.

[0032] Optionally, the doping concentration of the N-type buffer structure 44 is less than the doping concentration of the N pillar 42 and greater than the doping concentration of the drift layer 30. This can slow down the doping concentration difference at the interface between the superjunction layer 40 and the drift layer 30. Since the greater the doping concentration difference, the greater the peak temperature may be, the reduction of the doping concentration difference can reduce the peak temperature at the interface, thus avoiding the generation of local hot spots.

[0033] Furthermore, the N-type buffer structure 44 includes at least one N-type buffer layer. For example, one N-type buffer layer can be provided. As shown in Figure 2 One N-type buffer layer shown, and this N-type buffer layer can be called the first N-type buffer layer 44a. In this way, the contact surface between the N pillar 42 and the drift layer 30 can be extended through one N-type buffer layer. Or, multiple N-type buffer layers can be provided. As shown in Figure 3 Four N-type buffer layers shown. Along the direction from the superjunction layer 40 to the drift layer 30, these four N-type buffer layers can be the first N-type buffer layer 44a, the second N-type buffer layer 44b, the third N-type buffer layer 44c, and the fourth N-type buffer layer 44d respectively. Along the direction from the drift layer 30 to the superjunction layer 40, that is, Figure 3 In the z direction shown, the doping concentration of each N-type buffer layer gradually increases, which can further reduce the doping concentration difference at the interface between the superjunction layer 40 and the drift layer 30, further reduce the peak temperature at the interface, and thus further eliminate local hot spots. Of course, when there are multiple N-type buffer layers, along the direction from the superjunction layer 40 to the drift layer 30, the doping concentration of each N-type buffer layer can also decrease step by step, as long as a decreasing trend can be presented.

[0034] Alternatively, the doping concentration of the N-type buffer structure 44 can also be set to be greater than the doping concentration of the N-column 42 or less than the doping concentration of the drift layer 30. In this way, the contact surface between the N-column 42 and the drift layer 30 can also be longitudinally extended. Only compared with the doping concentration setting method introduced above, the degree of reduction in the peak temperature at the interface will be smaller, but the peak temperature at the interface can still be reduced to a certain extent.

[0035] Furthermore, when multiple P-type buffer layers and N-type buffer layers are provided, the number of layers of the P-type buffer layer and the N-type buffer layer is the same and they are arranged in one-to-one correspondence. The doping concentration of the i-th P-type buffer layer and the doping concentration of the i-th N-type buffer layer satisfy the charge balance relationship. In this way, the P-type buffer layer and the N-type buffer layer can participate in the reverse breakdown voltage of the transistor, thereby improving the breakdown voltage performance of the transistor. Especially when the thickness of the buffer layer 20 is relatively large, the improvement of the breakdown voltage performance of the transistor is more obvious.

[0036] For example, as Figure 3 shown in Figure 3 there are four P-type buffer layers and four N-type buffer layers shown. To avoid the drawing from being too complex, Figure 3 only the superjunction layer 40 and the drift layer 30 are shown in

[0037] The first P-type buffer layer 43a corresponds to the first N-type buffer layer 44a, and the first P-type buffer layer 43a and the first N-type buffer layer 44a satisfy the charge balance relationship; the second P-type buffer layer 43b corresponds to the second N-type buffer layer 44b, and the second P-type buffer layer 43b and the second N-type buffer layer 44b satisfy the charge balance relationship; the third P-type buffer layer 43c corresponds to the third N-type buffer layer 44c, and the third P-type buffer layer 43c and the third N-type buffer layer 44c satisfy the charge balance relationship; the fourth P-type buffer layer 43d corresponds to the fourth N-type buffer layer 44d, and the fourth P-type buffer layer 43d and the fourth N-type buffer layer 44d satisfy the charge balance relationship.

[0037] And the charge balance relationship can be expressed by Formula 1. Formula 1 is: Pi×2W1 = Ni×W2, where Pi represents the doping concentration of the i-th P-type buffer layer, Ni represents the doping concentration of the i-th N-type buffer layer, W1 represents the width of the P-column along Figure 3 the x direction in Figure 3 and W2 represents the width of the N-column along Figure 3 the x direction in ; that is, the first P-type buffer layer 43a and the first N-type buffer layer 44a, the second P-type buffer layer 43b and the second N-type buffer layer 44b, the third P-type buffer layer 43c and the third N-type buffer layer 44c, and the fourth P-type buffer layer 43d and the fourth N-type buffer layer 44d all satisfy Formula 1.

[0038] Of course, Formula 1 can also be: Pi×2W1≈Ni×W2, that is, the left side of the equation is not necessarily completely equal to the right side of the equation, and some gaps are allowed, but they are considered to be approximately equal, which also satisfies the charge balance relationship.

[0039] The thickness of each P-type buffer layer can be set to be the same or different, and can be set according to actual needs, which is not specifically limited here. The thickness of any P-type buffer layer can be set to be greater than 0 and not less than 10μm, and can be further set to 1μm-4μm, such as but not limited to: 1μm, 2μm, 3μm, 4μm and other values, which are not limited here. Similarly, the thickness of each N-type buffer layer can be set to be equal or different, and the thickness of any N-type buffer layer is the same as the thickness of the corresponding P-type buffer layer, which is not only convenient for manufacturing, but also conducive to achieving charge balance, thereby improving the voltage resistance performance of the transistor.

[0040] Optionally, the transistor may further include: an epitaxial layer m1, an interlayer dielectric layer 60, a second electrode layer 70, a gate oxide layer 92 and a third electrode 91, the epitaxial layer m1 includes a buffer layer 20, a drift layer 30, a super junction layer 40 and a P-well layer 50; wherein the manufacturing material of the epitaxial layer m1 may include: silicon carbide, silicon, gallium nitride and other semiconductor materials, which are not limited here.

[0041] The interlayer dielectric layer 60 and the second electrode layer 70 are both arranged on the side of the epitaxial layer m1 away from the first electrode layer 10. Figure 4 and Figure 5 shown.

[0042] The gate oxide layer 92 and the third electrode 91 are both disposed on the side of the epitaxial layer m1 away from the first electrode layer 10. Figure 4 As shown, the third electrode 91 is located between the gate oxide layer 92 and the interlayer dielectric layer 60, and the structure of the third electrode 91 is planar; or, a groove 95 is provided on the side of the epitaxial layer m1 away from the first electrode layer 10, as shown in FIG. Figure 5As shown, the third electrode 91 and the gate oxide layer 92 are both disposed within the trench 95. The gate oxide layer 92 isolates the P-well layer 50 and the third electrode 91, as well as the superjunction layer 40 and the third electrode 91 respectively. That is to say, the gate oxide layer 92 can isolate the epitaxial layer m1 and the third electrode 91. At this time, the structure of the third electrode 91 is a channel type. At this time, the epitaxial layer m1 may further include a P+ shielding layer 96, and the P+ shielding layer 96 is disposed at the bottom of the trench 95 to protect the gate oxide layer 92 at the bottom of the trench and improve the reliability of the gate oxide layer 92. Among them, if the transistor is a metal-oxide-semiconductor field-effect transistor, the third electrode 91 may be a gate. At this time, a drain (or source) is disposed within the first electrode layer 10, and a source (or drain) is disposed within the second electrode layer 70. A substrate 101 may be disposed between the first electrode layer 10 and the buffer layer 20. If the transistor is an insulated-gate bipolar transistor, the third electrode 91 is a base. At this time, a collector (or emitter) is disposed within the first electrode layer 10, and an emitter (or collector) is disposed within the second electrode layer 70. A P+ doped layer 102 (or N+ doped layer) may be disposed between the first electrode layer 10 and the buffer layer 20, and the P+ doped layer 102 (or N+ doped layer) may be a part of the epitaxial layer m1.

[0043] The P-well layer 50 is located on the side of the superjunction layer 40 away from the drift layer 30. Generally, a P+ contact region 93 and an N+ electrode contact region 94 are disposed within the P-well layer 50. The N+ electrode contact region 94 is disposed closer to the third electrode 91 than the P+ contact region 93, as Figure 4 and Figure 5 shown, the depths of both the P+ contact region 93 and the N+ electrode contact region 94 are less than the depth d1 of the P-well layer 50.

[0044] At this time, as Figure 4 and Figure 5 shown, a hole recombination structure 80 may further be disposed within the P-well layer 50. The positive projection of the P pillar 41 onto the P-well layer 50 overlaps with the hole recombination structure 80. It should be understood that the positive projection of the P pillar 41 onto the P-well layer 50 overlapping with the hole recombination structure 80 can be understood as the hole recombination structure 80 being disposed on top of the P pillar 41 and corresponding thereto. Since impact ionization causes holes to diffuse vertically upward along the P pillar 41, the holes are likely to accumulate near the gate oxide layer 92, which will increase the internal electric field of the gate oxide layer 92 and easily lead to the failure of the gate oxide layer 92. By providing the hole recombination structure 80, the recombination of holes with the excess electrons within the hole recombination structure 80 at this location can be enhanced, and at the same time, the extraction effect of the hole current diffusing vertically upward along the P pillar 41 within the transistor towards the second electrode layer 70 can be accelerated, avoiding the increase of the internal electric field of the gate oxide layer 92, thereby improving the reliability of the transistor.

[0045] Among them, at least a part of the hole recombination structure 80 is disposed within the P+ contact region 93, and along Figure 4In the x direction, the width of the hole recombination structure 80 does not exceed the width of the P+ contact region 93, so the hole recombination structure 80 will not contact the N+ electrode contact region 94, thus avoiding affecting the function of the hole recombination structure 80 in extracting holes.

[0046] Moreover, the depth d2 of the hole recombination structure 80 can be set as:

[0047] The depth d2 of the hole recombination structure 80 is less than the depth d1 of the P- well layer 50. No illustration is given. For example, the depth d2 of the hole recombination structure 80 is less than the depth of the P+ contact region 93, or the depth d2 of the hole recombination structure 80 is greater than the depth of the P+ contact region 93 and less than the depth d1 of the P- well layer 50. At this time, the hole recombination structure 80 is not in direct contact with the P pillar 41, but this can still accelerate the extraction of holes to a certain extent;

[0048] Or, the depth d2 of the hole recombination structure 80 is equal to the depth d1 of the P- well layer 50. As Figure 4 shown, at this time, the hole recombination structure 80 is in direct contact with the P pillar 41, which can effectively accelerate the extraction of holes;

[0049] Or, the depth d2 of the hole recombination structure 80 is greater than the depth d1 of the P- well layer 50. No illustration is given. At this time, the hole recombination structure 80 will penetrate through the P- well layer 50 and extend into the interior of the P pillar 41, which can accelerate the extraction of holes faster and earlier.

[0050] Based on this, as the depth d2 of the hole recombination structure 80 increases, the extraction effect on holes will also increase. Therefore, the depth d2 of the hole recombination structure 80 can be set according to actual needs and is not specifically limited here.

[0051] Exemplarily, as Figure 4 shown, the hole recombination structure 80 may include an N+ doped portion 81. The depth d2 of the hole recombination structure 80 is the depth of the N+ doped portion 81. There are excess electrons in the N+ doped portion 81, and holes can recombine with the excess electrons in the N+ doped portion 81, thereby achieving the effect of extracting holes.

[0052] Or, as Figure 5 shown, the hole recombination structure 80 may include: an N+ doped portion 81 and an N- doped portion 82. The N- doped portion 82 is provided on the side of the N+ doped portion 81 away from the P pillar 41. So along Figure 5In the z direction shown in the figure, an N+ doping portion 81 and an N- doping portion 82 are successively provided on the top of the P pillar 41 to form a heterojunction of N+ and N-, forming a built-in drift electric field vertically upward. When the hole current generated by heavy ion irradiation reaches the hole recombination structure 80, part of the holes recombine with the electrons in the N+ doping portion 81, and the remaining holes will drift toward the second electrode layer 70 under the action of the built-in drift electric field, enhancing the hole extraction effect in the P pillar 41 and avoiding affecting the gate oxide layer 92, thereby further improving the reliability of the transistor.

[0053] It should be understood that whether the structure of the third electrode 91 is planar or channel type has no direct relation to the specific implementation structure of the hole recombination structure 80. Figure 4 In the figure, only the planar third electrode 91 is taken as an example to show the hole recombination structure 80. Figure 5 In the figure, only the channel-type third electrode 91 is taken as an example to show the hole recombination structure 80. Similarly, Figure 1 and Figure 2 in the figure, whether the structure of the third electrode 91 is planar or channel type also has no direct relation to the structure of the superjunction layer 40. Figure 1 In the figure, only the planar third electrode 91 is taken as an example to show the superjunction layer 40. Figure 2 In the figure, only the channel-type third electrode 91 is taken as an example to show the superjunction layer 40.

[0054] Optionally, the transistor may further include an N-type doping portion 45, and the N-type doping portion 45 is provided in a partial area between the P pillar 41 and the P-well layer 50, such as Figure 4 and Figure 6 shown. Figure 6 is a top view of the surface (i.e., the top surface) of the P pillar 41 when looking along the thick black arrow in Figure 4 the figure. For each P pillar 41 and the P-well layer 50, an N-type doping portion 45 is provided, and the projection of the N-type doping portion 45 on the top surface of the P pillar 41 only occupies a partial area of the top surface of the P pillar 41. In this way, the N-type doping portion 45 only separates the P pillar 41 from the P-well layer 50 in a partial area. The N-type doping portion 45 and the P pillar 41 can form a PN junction, which can accelerate the extraction effect of the hole current diffusing vertically upward along the P pillar 41 in the transistor toward the second electrode layer 70, avoiding affecting the gate oxide layer 92, thereby further improving the reliability of the transistor. Moreover, the N-type doping portion 45 does not completely separate the P pillar 41 from the P-well layer 50, so the function of the superjunction layer 40 can still be ensured to be effective, improving the breakdown voltage performance of the transistor.

[0055] Among them, for the thickness and size of the N-type doping portion 45, they can be designed according to actual needs, and one N-type doping portion 45 can be provided between the P pillar 41 and the P-well layer 50, such as Figure 6As shown in (b) thereof, or a plurality of N-type doping portions 45 may be provided between the P pillar 41 and the P-well layer 50, as Figure 6 shown in (a) thereof, and the arrangement of the plurality of N-type doping portions 45 can be designed according to actual needs, and no specific limitations are made here.

[0056] Moreover, it can be set that: an N-type doping portion 45 is provided between each P pillar 41 and the P-well layer 50, or an N-type doping portion 45 is provided between some P pillars 41 and the P-well layer 50, which can be specifically designed according to the actual situation to meet the requirements of different scenarios and improve the flexibility of the design.

[0057] Taking the transistor including four P-type buffer layers and four N-type buffer layers as an example, the transistor is simulated. When simulating, the source-drain voltage Vds applied is 1500V, the thicknesses of the four P-type buffer layers are all 1μm, and along the direction from the P pillar 41 to the drift layer 30, the doping concentrations of the four P-type buffer layers are respectively: 5.2e16 / cm 3 、4.4e16 / cm 3 、3.6e16 / cm 3 、2.8e16 / cm 3 , the thicknesses of the four N-type buffer layers are all 1μm, and along the direction from the N pillar 42 to the drift layer 30, the doping concentrations of the four N-type buffer layers are respectively: 2.6e16 / cm 3 、2.2e16 / cm 3 、1.8e16 / cm 3 、1.4e16 / cm 3 , the doping concentration of the P pillar 41 is 6e16 / cm 3 , the doping concentration of the N pillar 42 is 3e16 / cm 3 , the doping concentration of the drift layer 30 is 5e15 / cm 3 . The simulation results are as Figure 7 shown, Figure 7 in which the curve 1 represents the peak temperature at the interface between the superjunction layer 40 and the drift layer 30 when no P-type buffer layer and N-type buffer layer are provided, and the curve 2 represents the peak temperature at the interface between the superjunction layer 40 and the drift layer 30 when P-type buffer layer and N-type buffer layer are provided. By comparing the curve 1 and the curve 2, it can be found that the peak temperature decreases when the P-type buffer layer and the N-type buffer layer are provided, which indicates that the P-type buffer layer and the N-type buffer layer reduce the local temperature at the interface between the superjunction layer 40 and the drift layer 30, thereby avoiding transistor damage and failure and improving the reliability of the transistor.

[0058] It should be understood that, taking Figure 4 and Figure 5 shown as an example, Figure 4 and Figure 5Shown is the structure of a transistor. When multiple such transistors are provided, the structure shown in Figure 4 or Figure 5 can be repeatedly set.

[0059] Based on the same inventive concept, an embodiment of the present invention provides a method for manufacturing a transistor. This manufacturing method can manufacture the above-mentioned transistor provided by the embodiment of the present invention. As Figure 8 shown, this manufacturing method may include:

[0060] S801. Sequentially form a stacked buffer layer and a drift layer;

[0061] S802. Form at least one of a P-type buffer structure and an N-type buffer structure on the surface of the drift layer facing away from the buffer layer;

[0062] S803. Form a superjunction layer;

[0063] Among them, the superjunction layer includes a plurality of P-columns and a plurality of N-columns. The extending directions of the P-columns and the N-columns are parallel to the stacking direction. The P-columns and the N-columns are alternately arranged along a first direction, and the first direction is perpendicular to the stacking direction; the P-type buffer structure is disposed between the P-column and the drift layer, and the N-type buffer structure is disposed between the N-column and the drift layer.

[0064] In this way, through the P-type buffer structure, the contact surface between the P-column and the drift layer can be equivalently extended longitudinally. Through the N-type buffer structure, the contact surface between the N-column and the drift layer can be equivalently extended longitudinally, so that the electric field is dispersed in the P-type buffer structure and the N-type buffer structure, avoiding the generation of local hot spots between the superjunction layer and the drift layer, thereby avoiding transistor damage and failure and improving the reliability of the transistor.

[0065] Optionally, taking the formation of the P-type buffer structure and the N-type buffer structure as an example, the implementation process of the above S802 may include:

[0066] Step 1. Adopt an epitaxial growth technique to form an epitaxial layer;

[0067] Step 2. Adopt an ion implantation technique to perform N-type doping on the epitaxial layer, so that the epitaxial layer is converted into an N-type doped layer;

[0068] Step 3. Continue to adopt an ion implantation technique to perform P-type doping on some positions in the N-type doped layer, so that P-type doped regions are formed in some positions, and the remaining positions are N-type doped regions. At this time, the P-type doped region serves as the P-type buffer layer, and the N-type doped region serves as the N-type buffer layer;

[0069] After that, continue to repeat Step 1 to Step 3 to obtain a plurality of P-type buffer layers and a plurality of N-type buffer layers, thereby obtaining the P-type buffer structure and the N-type buffer structure.

[0070] Thus, through multiple epitaxy and ion implantation techniques, a P-type buffer structure and an N-type buffer structure can be obtained, which can reduce the ion implantation energy, lower the cost, reduce the damage to other film layers, and improve the manufacturing yield of the transistor.

[0071] Based on the same inventive concept, an embodiment of the present invention provides an electronic device, such as Figure 9 shown. The electronic device may include the above-mentioned transistor provided by the embodiment of the present invention. Among them, the electronic device may be any type of device including the transistor, such as but not limited to a chip, etc. The electronic device can be applied to scenarios such as high-voltage inverters for high-speed railways, power grids (such as distribution grids, microgrids, etc.), high-voltage photovoltaics, etc., so as to meet the withstand voltage requirements. Of course, in addition to including transistors, the electronic device may also include other structures, such as but not limited to other passive devices or active devices such as capacitors, resistors, inductors, etc., which can be specifically set according to actual needs and are not limited here.

[0072] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention also intends to include these changes and modifications.

Claims

1. A transistor, characterized in that: include: A first electrode layer, a buffer layer, a drift layer and a super junction layer are stacked in sequence; the super junction layer comprises a plurality of P columns and a plurality of N columns, the extension directions of the P columns and the N columns are parallel to the stacking direction, the P columns and the N columns are alternately arranged along a first direction, and the first direction is perpendicular to the stacking direction; The super junction layer further includes at least one of a P-type buffer structure and an N-type buffer structure, wherein the P-type buffer structure is disposed between the P column and the drift layer, and the N-type buffer structure is disposed between the N column and the drift layer; The transistor also includes: a P-well layer located on the side of the superjunction layer away from the drift layer, a hole recombination structure is provided in the P-well layer, and the orthographic projection of the P column to the P-well layer overlaps with the hole recombination structure; the hole recombination structure includes: an N+ doped part and an N- doped part arranged along the stacking direction, and the N- doped part is provided on the side of the N+ doped part away from the P column.

2. The transistor according to claim 1, wherein The doping concentration of the P-type buffer structure is less than the doping concentration of the P column and greater than the doping concentration of the drift layer.

3. The transistor according to claim 2, characterized in that The P-type buffer structure includes at least one P-type buffer layer; When a plurality of P-type buffer layers are provided, the doping concentration of each P-type buffer layer gradually increases along a direction from the drift layer to the super junction layer.

4. The transistor according to claim 1, wherein The doping concentration of the N-type buffer structure is less than the doping concentration of the N column and greater than the doping concentration of the drift layer.

5. The transistor according to claim 4, characterized in that The N-type buffer structure includes at least one N-type buffer layer; When a plurality of N-type buffer layers are provided, the doping concentration of each N-type buffer layer gradually increases along a direction from the drift layer to the super junction layer.

6. The transistor according to claim 1, wherein The super junction layer includes a P-type buffer structure and an N-type buffer structure. The P-type buffer structure includes a plurality of P-type buffer layers, and the N-type buffer structure includes a plurality of N-type buffer layers. The number of layers of the P-type buffer layer is the same as that of the N-type buffer layer.

7. The transistor according to claim 1, wherein The depth of the hole recombination structure is not less than the depth of the P-well layer.

8. The transistor according to any one of claims 1 to 7, characterized in that: The transistor further includes: a P-well layer and an N-type doping portion, wherein the P-well layer is disposed on a side of the superjunction layer away from the drift layer, and the N-type doping portion is disposed in a partial region between the P column and the P-well layer.

9. A method for manufacturing a transistor, characterized in that: include: sequentially forming a stacked buffer layer and a drift layer; forming at least one of a P-type buffer structure and an N-type buffer structure on a surface of the drift layer facing away from the buffer layer; forming a superjunction layer; forming a P-well layer on the super junction layer; forming a hole recombination structure in the P-well layer; Among them, the super junction layer includes multiple P columns and multiple N columns, the extension directions of the P columns and the N columns are parallel to the stacking direction, the P columns and the N columns are alternately arranged along the first direction, and the first direction is perpendicular to the stacking direction; the P-type buffer structure is arranged between the P column and the drift layer, and the N-type buffer structure is arranged between the N column and the drift layer; the orthographic projection of the P column to the P-well layer overlaps with the hole recombination structure; the hole recombination structure includes: an N+ doped part and an N- doped part arranged along the stacking direction, and the N- doped part is arranged on the side of the N+ doped part away from the P column.

10. An electronic device, characterized in that: Comprising a transistor as claimed in any one of claims 1 to 8.

Images