Method for adjusting grid height and semiconductor structure

Abstract

The invention provides a method for adjusting the height of a grid electrode and a semiconductor structure, and belongs to the field of semiconductors. The method of adjusting gate height includes providing a semiconductor substrate. And etching back the hard mask layer in the NMOS region to reduce the thickness of the hard mask layer in the NMOS region. And after back etching, gate structures are respectively formed in the PMOS region and the NMOS region. And filling a dielectric layer, wherein the dielectric layer covers the gate structure of the NMOS region. And patterning a groove, etching the groove in the PMOS region, and when the groove is etched in the PMOS region, the thickness lost by the hard mask layer in the PMOS region is basically equal to the thickness lost by etching the hard mask layer in the NMOS region. By depositing the hard mask layer and etching the hard mask layer, the thickness of the hard mask layer in the PMOS region is basically equal to that of the hard mask layer in the NMOS region, so that the height of the formed grid electrode in the PMOS region is basically equal to that of the grid electrode in the NMOS region, and the performance of the device can be improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for adjusting gate height and a semiconductor structure. Background Art

[0002] With the advancement of nano-scaling, high density, high integration and multi-layer metal interconnection of integrated circuit devices, semiconductor technology nodes are becoming more and more advanced, and more new requirements are put forward for multiple key links in actual manufacturing. The high uniformity of high-k dielectric (HK) metal gates at 28nm and below is crucial to device performance and process integration.

[0003] When the embedded SiGe device etches the PMOS device to form a sigma trench, the height of the PMOS device gate is lost to a certain extent, resulting in the height of the NMOS device gate being greater than the height of the PMOS device gate, affecting the performance of the SiGe device.

[0004] It should be noted that the information disclosed in the background technology section of the invention is only intended to deepen the understanding of the general background technology of the invention, and should not be regarded as an admission or suggestion in any form that the information constitutes prior art already known to those skilled in the art. Summary of the invention

[0005] The object of the present invention is to provide a method for adjusting gate height and a semiconductor structure to solve the problem of inconsistent gate heights between different devices.

[0006] In order to solve the above technical problems, the present invention provides a method for adjusting the gate height, comprising:

[0007] Providing a semiconductor substrate, the semiconductor substrate comprising a PMOS region and an NMOS region;

[0008] forming a hard mask layer on a surface of the semiconductor substrate;

[0009] Etching back the hard mask layer of the NMOS region to reduce the thickness of the hard mask layer of the NMOS region;

[0010] After etching back, forming gate structures in the PMOS region and the NMOS region respectively;

[0011] Filling a dielectric layer, wherein the dielectric layer covers the gate structure of the NMOS region;

[0012] A groove is patterned and a groove is etched in the PMOS region. When the groove is etched in the PMOS region, the thickness of the hard mask layer lost in the PMOS region is substantially equal to the thickness of the hard mask layer lost in the NMOS region.

[0013] Preferably, before providing a semiconductor substrate, the method for adjusting the gate height further comprises:

[0014] The height lost by the gate structure in the PMOS region when the trench is etched is obtained.

[0015] The step of etching back the hard mask layer of the NMOS region to reduce the thickness of the hard mask layer of the NMOS region includes:

[0016] Based on the height loss of the gate structure in the PMOS region, the hard mask layer in the NMOS region is etched back so that the reduced thickness of the hard mask layer in the NMOS region is substantially equal to the height loss of the gate structure in the PMOS region.

[0017] Preferably, the semiconductor substrate comprises a substrate, and a gate structure layer formed on the substrate;

[0018] The gate structure layers are gate oxide compound, high-K dielectric layer, titanium nitride layer and A-Si layer in order from the substrate upward.

[0019] Preferably, etching back the hard mask layer of the NMOS region to reduce the thickness of the hard mask layer of the NMOS region includes:

[0020] forming a photoresist on the surface of the hard mask layer in the PMOS region;

[0021] The hard mask layer of the NMOS region is etched back by dry etching, and the dry etching gas is CF 4 ;

[0022] The photoresist in the PMOS region is removed.

[0023] Preferably, the material of the hard mask layer includes silicon dioxide or silicon oxynitride or a combination thereof.

[0024] Preferably, after etching back, forming gate structures in the PMOS region and the NMOS region respectively comprises:

[0025] forming an anti-reflective structure layer and a photoresist on the surface of the hard mask layer;

[0026] Exposing and developing the photoresist to pattern the gate structures of the PMOS region and the NMOS region;

[0027] The anti-reflection structure layer and the semiconductor substrate are etched to form gate structures in the PMOS region and the NMOS region respectively.

[0028] Preferably, the filling dielectric layer, wherein the dielectric layer covers the gate structure of the NMOS region, comprises:

[0029] Filling a dielectric layer between the gate structures, wherein the height of the dielectric layer is higher than the height of the gate structure;

[0030] forming a photoresist on the surface of the dielectric layer;

[0031] Exposing and developing the photoresist to expose the dielectric layer in the PMOS region;

[0032] The dielectric layer in the PMOS region is removed by etching, and the remaining dielectric layer covers the gate structure in the NMOS region.

[0033] Preferably, after patterning the grooves and etching the grooves in the PMOS region, the method for adjusting the gate height further comprises:

[0034] The trench is a sigma trench, which is filled to form a source and a drain in the PMOS region. The materials filled in the sigma trench are germanium silicon and silicon nickel metal compound in order from the substrate upward.

[0035] Preferably, shallow trench isolation is provided between adjacent PMOS regions and NMOS regions.

[0036] Based on the same inventive concept, the present invention also provides a semiconductor structure, comprising:

[0037] The method for adjusting the gate height is used for preparation.

[0038] Compared with the prior art, the method for adjusting the gate height of the present invention has the following advantages:

[0039] The present invention deposits a hard mask layer and performs back etching on the hard mask layer, thereby reducing the thickness of the hard mask layer in the NMOS region. After the subsequent process sigma trench etching, the thickness of the hard mask layer in the PMOS region is substantially equal to that of the hard mask layer in the NMOS region, so that the height of the gate in the PMOS region is substantially equal to that of the gate in the NMOS region, which can improve the performance of the device.

[0040] The semiconductor structure provided by the present invention and the method for adjusting the gate height provided by the present invention belong to the same inventive concept. Therefore, the semiconductor structure provided by the present invention has at least all the advantages of the method for adjusting the gate height provided by the present invention. The height of the gate of the PMOS transistor is basically equal to the height of the gate of the NMOS transistor, which can improve the performance of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 It is a schematic diagram of a semiconductor structure;

[0042] Figure 2 Yes Figure 1Schematic diagram of the structure formed after the semiconductor structure in FIG. 1 is etched with grooves;

[0043] Figure 3 is a schematic diagram of a semiconductor structure with different gate heights;

[0044] Figure 4 is Figure 3 A schematic diagram of a structure in which an insulating material is filled in a semiconductor structure;

[0045] Figure 5 Yes Figure 4 Schematic diagram of the structure formed after the semiconductor structure in FIG. 1 is ground for the first time;

[0046] Figure 6 Yes Figure 5 A schematic diagram of a structure formed after etching the semiconductor structure in FIG.

[0047] Figure 7 Yes Figure 6 A schematic diagram of a semiconductor structure in which an insulating layer material is filled again;

[0048] Figure 8 Yes Figure 7 A schematic diagram of a structure formed after the semiconductor structure in the embodiment of the present invention is subjected to a second grinding;

[0049] Fig. 9 is a flow chart of a method for adjusting gate height in one embodiment of the present invention;

[0050] Fig.10 is a schematic diagram of a structure of depositing a hard mask layer on a semiconductor substrate in one embodiment of the present invention;

[0051] Fig.11 is a schematic diagram of the structure after the hard mask layer is etched back in one embodiment of the present invention;

[0052] Fig.12 It is a schematic diagram of a structure in which an anti-reflection structure layer is formed after back etching in one embodiment of the present invention;

[0053] Fig.13 is a schematic diagram of forming gate structures in a PMOS region and an NMOS region respectively in one embodiment of the present invention;

[0054] Fig.14 is a schematic structural diagram of forming a second stop layer on a gate structure in one embodiment of the present invention;

[0055] Fig.15 is a schematic structural diagram of a dielectric layer filled in a gate structure in one embodiment of the present invention;

[0056] Fig.16is a schematic diagram of a structure in which a sigma trench is formed in a PMOS region in one embodiment of the present invention;

[0057] In the figure,

[0058] 10-groove; 20-first gate;

[0059] 21-silicon dioxide layer; 22-silicon nitride layer;

[0060] 23-insulating material; 30-second grid;

[0061] 100-N well; 110-sigma trench;

[0062] 200-P well; 300-substrate;

[0063] 310- shallow trench isolation; 400- gate structure layer;

[0064] 500-hard mask layer; 510-first stop layer;

[0065] 520-gate structure; 530-second stop layer;

[0066] 540-side wall; 610-first photoresist;

[0067] 620 - second photoresist; 700 - anti-reflective structure layer. DETAILED DESCRIPTION

[0068] In order to make the purpose, advantages and features of the present invention clearer, the method for adjusting the gate height and the semiconductor structure proposed by the present invention are further described in detail in combination with the drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not in precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. It should be understood that the drawings in the specification do not necessarily show the specific structure of the present invention in proportion, and the illustrative features used to illustrate certain principles of the present invention in the drawings in the specification will also adopt a slightly simplified drawing method. The specific design features of the present invention disclosed herein include, for example, specific dimensions, directions, positions and shapes, which will be determined in part by the specific application and use environment. And, in the embodiments described below, sometimes the same figure mark is used in common between different drawings to represent the same part or a part with the same function, and its repeated description is omitted. In this specification, similar numbers and letters are used to represent similar items, so once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.

[0069] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0070] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0071] Ginseng Figure 1 and Figure 2 As shown, in Figure 1 In the semiconductor structure, the N well (ie, Figure 1 The region where the NW in the well is located forms a PMOS transistor. Figure 1 The area where the PW in the circuit is located forms an NMOS transistor. Figure 1 After the semiconductor structure shown in FIG. 1 is patterned, it is dry-etched to form a semiconductor structure as shown in FIG. Figure 2 After the trench 10 is filled, the source and drain of the PMOS transistor are formed. However, during the dry etching process, the etchant only etches the silicon dioxide layer 21 in the area where the PMOS transistor is located, resulting in the loss of the silicon dioxide layer 21 in the area where the PMOS transistor is located, thereby causing the silicon dioxide layer 21 in the area where the PMOS transistor is located to be inconsistent in height with the silicon dioxide layer 21 in the area where the NMOS transistor is located, that is, forming the following Figure 2 In the subsequent process, the height difference d1 mentioned in the figure causes the first gate 20 of the NMOS transistor and the second gate 30 of the PMOS transistor to be inconsistent in height, which affects the performance of the device.

[0072] Ginseng Figures 3 to 8 As shown, in order to solve the above technical problems, the prior art adopts a double grinding process to eliminate the problem of inconsistent heights between the gate of the NMOS transistor and the gate of the PMOS transistor. The specific process of the double grinding process is as follows:

[0073] In completion Figure 2 After the manufacturing process of the source and drain of the PMOS transistor and the NMOS transistor in the semiconductor structure shown in the figure, a sidewall is deposited on the gate of the PMOS transistor and the NMOS transistor. A silicon nitride layer 22 is deposited on the surface of the sidewall and the silicon dioxide layer 21 to form a Figure 3 Next, an insulating material 23 is filled between different gates to form a structure as shown in FIG. Figure 4 The insulating material 23 acts as an insulating layer in the subsequent process. Figure 3 The semiconductor structure shown in FIG. 1 is subjected to a first chemical mechanical polishing and polished to a stop layer to form a semiconductor structure as shown in FIG. Figure 5 In order to increase the rate of the second chemical mechanical polishing and speed up the subsequent process, the semiconductor structure is dry etched to remove part of the insulating material 23. However, in order to reduce the defects of the insulating material 23 and avoid the formation of gaps in the insulating material 23, the semiconductor structure is dry etched again. Figure 6 The semiconductor structure shown is filled with insulating material 23. Finally, the silicon dioxide layer 21 and the silicon nitride layer 22 are removed by a second chemical mechanical polishing process to planarize the PMOS transistor and the NMOS transistor so that the gates of the PMOS transistor and the NMOS transistor have the same height.

[0074] The above double grinding process eliminates the problem of inconsistent heights between the gate of the NMOS transistor and the gate of the PMOS transistor, but the process steps are complicated and the process time is prolonged.

[0075] The core idea of ​​the present invention is to provide a method for adjusting gate height, which can solve the problem of inconsistent heights between the gate of an NMOS transistor and the gate of a PMOS transistor, and can also simplify process steps and shorten process time.

[0076] In order to realize the above idea, the present invention provides a method for adjusting the gate height. Figures 9 to 16 A specific implementation of a method for adjusting gate height disclosed herein includes the following steps S1 to S6.

[0077] Step S1: providing a semiconductor substrate, wherein the semiconductor substrate comprises a PMOS region and an NMOS region.

[0078] Specifically, refer to Fig. 9 and Fig.10As shown, a semiconductor substrate is provided, and the semiconductor substrate includes a substrate 300. An N-well 100 and a P-well 200 are formed by doping in different regions of the substrate 300. That is, an N-type semiconductor is doped in the N-well region of the substrate 300 to form the N-well 100. The N-well 100 serves as a substrate for forming a PMOS transistor. A P-type semiconductor is doped in the P-well region of the substrate 300 to form a P-well 200. The P-well 200 serves as a substrate for forming an NMOS transistor. Therefore, a PMOS transistor is formed in the region where the N-well 100 is located, that is, a PMOS region is formed. An NMOS transistor is formed in the region where the P-well 200 is located, that is, an NMOS region is formed. A shallow trench isolation 310 (STI) is provided between the PMOS transistor and the NMOS transistor to isolate different transistors. The material filled in the STI is a gate oxide compound, such as a silicon dioxide insulating material. The gate oxide compound is not only filled in the STI, but also covers the surface of the substrate, the N-well and the P-well to form an isolation layer.

[0079] The surfaces of the substrate 300, the N-well 100 and the P-well 200 are deposited with a gate structure layer 400 for forming a transistor gate in a subsequent process. The gate structure layer 400 is composed of a gate oxide compound, a high-K dielectric layer, a titanium nitride layer, and an A-Si layer from the substrate upward. A first stop layer 510 for etching and forming a gate is also deposited on the surface of the gate structure layer. The first stop layer 510 is made of silicon nitride material. That is, the first stop layer 510 is deposited on the surface of the A-Si layer.

[0080] Step S2: forming a hard mask layer on the surface of the semiconductor substrate.

[0081] Specifically, refer to Fig. 9 and Fig.10 As shown, a hard mask layer 500 is deposited on the surface of the first stop layer 510 to form a Fig.10 The structure shown in FIG. The material of the first stop layer 510 includes silicon nitride material. The material of the hard mask layer 500 is a silicon oxide compound, and the material of the hard mask layer 500 includes silicon dioxide or silicon oxynitride or a combination thereof.

[0082] Step S3: etching back the hard mask layer 500 in the NMOS region to reduce the thickness of the hard mask layer 500 in the NMOS region.

[0083] Specifically, continue to Fig. 9 , Fig.11 and Fig.16 As shown, etching back the hard mask layer 500 of the NMOS region to reduce the thickness of the hard mask layer 500 of the NMOS region includes:

[0084] First, a first photoresist 610 is formed on the surface of the hard mask layer 500 in the PMOS region. Exemplarily, the first photoresist 610 is deposited on the surface of the hard mask layer 500. After the first photoresist 610 in the NMOS region is exposed and developed, the first photoresist 610 is formed only on the surface of the hard mask layer 500 in the PMOS region. That is, the hard mask layer 500 in the PMOS region is covered with the first photoresist 610, and the hard mask layer 500 in the NMOS region is exposed.

[0085] Next, the hard mask layer 500 of the NMOS region is etched back by dry etching, and the dry etching gas is CF 4 , so as to reduce the thickness of the hard mask layer 500 in the NMOS region, so that the lost height d2 of the hard mask layer 500 in the NMOS region is equal to d1.

[0086] Finally, the first photoresist 610 in the PMOS region is removed.

[0087] For the height of d1, when the process node, device structure and process conditions are determined, engineers can obtain the loss of the hard mask layer 500 based on the height difference of the gate before and after etching the sigma trench 110 in the past, that is, they can directly obtain the height of d2. 4 The etching rate of the gas is known, so by obtaining the d2 height and CF 4 The etching rate of the gas can be used to calculate the dry etching time.

[0088] For example, for a device type with a high-K dielectric layer at a process node of 28 nanometers, the height difference of the gate before and after etching the sigma trench 110 is Therefore, the hard mask layer 500 in the NMOS region is etched without selectivity using CF4 gas for 3 seconds to 4 seconds, thereby reducing the height difference of the gates of different transistors.

[0089] In order to more accurately obtain the height difference of the gate before and after etching of the sigma trench 110 , or in the absence of experimental data, some devices of the same batch of semiconductor devices may be subjected to the following process steps:

[0090] First, a semiconductor structure is provided, wherein the semiconductor structure includes a PMOS region and an NMOS region, wherein both the PMOS region and the NMOS region have a gate. Then, a sigma groove 110 is etched in the PMOS region, and the loss of the gate height of the PMOS region after etching is obtained. That is, by sacrificing some devices, the height of the gate loss under the same process of the devices in the batch is obtained. Furthermore, the time for etching the hard mask layer 500 in the NMOS region using CF4 gas can be calculated. Thus, by determining the etching time, the hard mask layer 500 in the NMOS region can be etched to the target height.

[0091] Step S4: After etching back, a gate structure 520 is formed in the PMOS region and the NMOS region respectively.

[0092] Specifically, refer to Fig. 9 , Figure 12 to Figure 14 As shown, after etching back, forming a gate structure 520 in the PMOS region and the NMOS region respectively includes:

[0093] First, an anti-reflection structure layer 700 and a second photoresist 620 are formed on the surface of the hard mask layer 500. Next, the second photoresist 620 is exposed and developed to pattern the gate structure 520 in the PMOS region and the NMOS region. Finally, the anti-reflection structure layer 700 and the semiconductor substrate are etched to form the gate structure 520 in the PMOS region and the NMOS region, respectively. The anti-reflection structure layer 700 and the photoresist 620 are deposited on the surface of the hard mask layer after the back etching. By patterning the second photoresist 620, a gate structure 520 is formed as shown in FIG. Fig.12 Then, the anti-reflection structure layer 700 is etched to form a Fig.13 The morphology of the gate shown. It should be noted that the anti-reflection structure layer 700 includes a polymer anti-reflection layer (APF), a nitrogen-free anti-reflection layer (NFDARC), a silicon oxide anti-reflection layer, and an organic anti-reflection coating (BARC) in sequence from the substrate upward. And each anti-reflection layer film serves as a hard mask for the next anti-reflection layer, thereby etching the morphology of the gate. By setting different anti-reflection layers, reflection can be effectively reduced, uneven exposure can be prevented, and the accuracy of photolithography patterning can be improved. Since the formation process and etching process of the anti-reflection structure layer 700 are both prior arts, those skilled in the art are already familiar with the specific process and will not be elaborated on in detail here.

[0094] It should be noted that the first photoresist 610 can be a positive photoresist or a negative photoresist. Similarly, the second photoresist 620 can be a positive photoresist or a negative photoresist. The adhesive properties of the first photoresist 610 and the second photoresist 620 can be the same or different. In this embodiment, it is preferred that the first photoresist 610 is a positive photoresist and the second photoresist 620 is a negative photoresist.

[0095] Step S5: Filling the dielectric layer 550, wherein the dielectric layer 550 covers the gate structure 520 of the NMOS region.

[0096] Specifically, refer to Fig. 9 , Figures 14 to 16 As shown, before filling the dielectric layer 550, the method further includes: forming a sidewall 540 on the sidewall of the gate structure 520. Next, a second stop layer 530 is formed, and the second stop layer 530 covers the top of the gate structure 520, the sidewall 540, the N well 100, the P well 200, the STI, and the surface of the substrate 300.

[0097] Filling a dielectric layer 550, wherein the dielectric layer 550 covers the gate structure 520 of the NMOS region and includes:

[0098] A dielectric layer 550 is filled between the gate structures 520 . The height of the dielectric layer 550 is higher than that of the gate structure 520 , so as to completely cover the gate structure 520 .

[0099] Forming a first photoresist 610 on the surface of the dielectric layer;

[0100] Exposing and developing the first photoresist 610 to expose the dielectric layer 550 in the PMOS region;

[0101] The dielectric layer 550 in the PMOS region is removed by etching, and the remaining dielectric layer 550 covers the gate structure 520 in the NMOS region. The material of the dielectric layer 550 is preferably an organic anti-reflective coating (BARC).

[0102] Step S6: patterning trenches, etching trenches in the PMOS region, when the trenches are etched in the PMOS region, the thickness of the hard mask layer lost in the PMOS region is substantially equal to the thickness of the hard mask layer lost in the NMOS region when the trenches are etched back.

[0103] Specifically, refer to Fig. 9 , Figures 14 to 16 As shown, finally, the PMOS region is patterned and dry etching is performed to form a trench in the PMOS region, that is, a Fig.16The structure shown. The dry etching gas can be one of HBr, Cl2, NF3 or any combination thereof. The groove is a sigma groove 110. In the following process, the source and drain of the PMOS transistor are formed by filling the sigma groove 110 with materials. The materials filled in the sigma groove are germanium silicon and silicon nickel metal compounds from the substrate upward. Since the hard mask layer 500 is back-etched in step S3, the thickness of the hard mask layer 500 in the NMOS region is reduced. Therefore, after the sigma groove 110 is etched, the thickness of the hard mask layer 500 in the PMOS region is substantially equal to that of the hard mask layer 500 in the NMOS region. After removing the hard mask layer 500 and the first stop layer 510 in the subsequent process, the height of the gate of the PMOS region is substantially equal to that of the gate of the NMOS region, thereby improving the performance of the device. Although an additional mask is added before etching back the hard mask layer 500, after using this method, in the subsequent process, there is no need to use the double grinding process again for the gate of the PMOS area and the gate of the NMOS area, which simplifies the process steps and shortens the process time.

[0104] To realize the above idea, this embodiment also discloses a semiconductor structure, which is prepared by the method for adjusting the gate height as described above.

[0105] The semiconductor structure provided in this embodiment and the method for adjusting the gate height provided in this embodiment belong to the same inventive concept. Therefore, the semiconductor structure provided in this embodiment has at least all the advantages of the method for adjusting the gate height provided in this embodiment. The height of the gate of the PMOS transistor is substantially equal to that of the gate of the NMOS transistor, which can improve the performance of the device.

[0106] In summary, the above embodiments provide detailed descriptions of the method for adjusting the gate height and different configurations of the semiconductor structure. Of course, the above description is only a description of the preferred embodiments of the present invention, and is not any limitation to the scope of the present invention. The present invention includes but is not limited to the configurations listed in the above embodiments. Those skilled in the art can draw inferences based on the contents of the above embodiments. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure are within the scope of protection of the claims.

Claims

1. A method for adjusting gate height, characterized in that: include: Providing a semiconductor substrate, the semiconductor substrate comprising a PMOS region and an NMOS region; forming a hard mask layer on a surface of the semiconductor substrate; Etching back the hard mask layer of the NMOS region to reduce the thickness of the hard mask layer of the NMOS region; After etching back, forming gate structures in the PMOS region and the NMOS region respectively; Filling a dielectric layer, wherein the dielectric layer covers the gate structure of the NMOS region; A groove is patterned and a groove is etched in the PMOS region. When the groove is etched in the PMOS region, the thickness of the hard mask layer lost in the PMOS region is substantially equal to the thickness of the hard mask layer lost in the NMOS region.

2. The method for adjusting gate height according to claim 1, characterized in that: Before providing a semiconductor substrate, the method for adjusting the gate height further includes: Obtaining the height lost by the gate structure in the PMOS region when etching the trench; The step of etching back the hard mask layer of the NMOS region to reduce the thickness of the hard mask layer of the NMOS region includes: Based on the height loss of the gate structure in the PMOS region, the hard mask layer in the NMOS region is etched back so that the reduced thickness of the hard mask layer in the NMOS region is substantially equal to the height loss of the gate structure in the PMOS region.

3. The method for adjusting gate height according to claim 1, characterized in that: The semiconductor substrate includes a substrate and a gate structure layer formed on the substrate; The gate structure layers are gate oxide compound, high-K dielectric layer, titanium nitride layer and A-Si layer in order from the substrate upward.

4. The method for adjusting gate height according to claim 1, characterized in that: The step of etching back the hard mask layer of the NMOS region to reduce the thickness of the hard mask layer of the NMOS region includes: forming a photoresist on the surface of the hard mask layer in the PMOS region; The hard mask layer of the NMOS region is etched back by dry etching, wherein the dry etching gas is CF4; The photoresist in the PMOS region is removed.

5. The method for adjusting gate height according to any one of claims 1 to 4, characterized in that: The material of the hard mask layer includes silicon dioxide or silicon oxynitride or a combination thereof.

6. The method for adjusting gate height according to claim 4, characterized in that: After etching back, forming gate structures in the PMOS region and the NMOS region respectively includes: forming an anti-reflective structure layer and a photoresist on the surface of the hard mask layer; Exposing and developing the photoresist to pattern the gate structures of the PMOS region and the NMOS region; The anti-reflection structure layer and the semiconductor substrate are etched to form gate structures in the PMOS region and the NMOS region respectively.

7. The method for adjusting gate height according to claim 1, characterized in that: The filling dielectric layer, wherein the dielectric layer covers the gate structure of the NMOS region, comprises: Filling a dielectric layer between the gate structures, wherein the height of the dielectric layer is higher than the height of the gate structure; forming a photoresist on the surface of the dielectric layer; Exposing and developing the photoresist to expose the dielectric layer in the PMOS region; The dielectric layer in the PMOS region is removed by etching, and the remaining dielectric layer covers the gate structure in the NMOS region.

8. The method for adjusting gate height according to claim 1, characterized in that: After patterning the grooves and etching the grooves in the PMOS region, the method for adjusting the gate height further includes: The trench is a sigma trench, which is filled to form a source and a drain in the PMOS region. The materials filled in the sigma trench are germanium silicon and silicon nickel metal compound in order from the substrate upward.

9. The method for adjusting gate height according to claim 1, characterized in that: Shallow trench isolation is provided between adjacent PMOS regions and NMOS regions.

10. A semiconductor structure, characterized in that: include: The method for adjusting the gate height is adopted as described in any one of claims 1 to 9.

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