Tear safety feature for printed circuit board

Abstract

Disclosed is a circuit substrate structure for protecting an area from being damaged. The structure includes a circuit substrate, wherein at least one of a top breakage-proof envelope and a bottom breakage-proof envelope covers components in a protected area of the circuit substrate. The top breakage-resistant encapsulation and the bottom breakage-resistant encapsulation are adhesively bonded to a surface of the circuit substrate, and a tear start point is added to a side of a periphery of the circuit substrate bordering a protection region including the at least one breakage-resistant encapsulation, the tear start point is positioned and configured to enable propagation of layering of the at least one inner layer of the circuit substrate and severing of the safety circuit when a removal force is applied to at least one of the top and bottom breakage-proof envelopes, and the tear start point is positioned and configured to enable propagation of layering of the at least one inner layer of the circuit substrate and severing of the safety circuit when a removal force is applied to at least one of the top and bottom breakage-proof envelopes.

Description

Technical Field

[0001] The present invention relates to the safety of hardware circuit board components, and more particularly to creating tear initiation sites for designated delaminations in response to component encapsulation tampering. Background Art

[0002] A printed circuit board (PCB) includes circuits and components that provide functionality and memory, and in some instances, proprietary technology. A PCB provides circuit connections between components including semiconductor chips that are connected to a substrate that is in turn connected to the PCB, or the chip is directly connected to the surface of the PCB. PCB components also include, but are not limited to, capacitors, resistors, fuses, and connectors. A PCB may be generally referred to as a circuitized substrate or a printed circuit substrate. Summary of the invention

[0003] According to one embodiment of the present invention, there is provided a structure of a circuit substrate for protecting an area from being damaged and a security area from being accessed. The structure includes a circuit substrate, the circuit substrate includes at least one of a top anti-destruction encapsulation and a bottom anti-destruction encapsulation, and at least one of the top anti-destruction encapsulation and the bottom anti-destruction encapsulation provides a safety cover for a protected component in a protected area of ​​the circuit substrate. The structure includes a connection that combines the top anti-destruction encapsulation and / or the bottom anti-destruction encapsulation to the circuit substrate, and the structure includes a tear initiation site added to a side of the circuit substrate that borders a protection area including at least one of the top destructive encapsulation and the bottom destructive encapsulation, wherein the tear initiation site is positioned and configured to enable the delamination of at least one inner layer of the circuit substrate to propagate and cut off a security circuit when a removal force is applied to at least one of the top anti-destruction encapsulation and / or the bottom anti-destruction encapsulation.

[0004] According to another embodiment of the present invention, a method for forming a tear initiation site that disables a protected area of ​​a printed circuit board (PCB) is provided. The method receives a printed circuit board that includes one or more inner layers containing a security circuit, the security circuit being located in an area associated with a protected component, the protected component receiving an anti-tampering encapsulation adhesively attached to the component and the PCB surface, such that severing one or more security trace circuits initiates disabling data and functions of the protected component. The method determines an area associated with the protected component that receives the anti-tampering encapsulation, and the method generates a tear initiation site along a side of the PCB that is aligned with the area associated with the protected component.

[0005] According to another embodiment of the present invention, a method for generating a disabled tear of a printed circuit board due to a vandalism attempt on a protected area of ​​the printed circuit board is provided. The method receives an inner layer of a printed circuit board (PCB), wherein at least one layer of the PCB is reduced in size along a dimension including a side of the protected area of ​​the PCB, and one or a combination of the top anti-tampering encapsulation and the bottom anti-tampering encapsulation are attached to the protected area. The method combines the inner layer, wherein the at least one inner layer reduced in size is positioned to form an insertion step along the dimension of the side of the protected area of ​​the PCB, wherein the combination of a regular sized first inner layer is combined with a reduced adhesion force to at least one layer of the PCB reduced in size along the dimension of the side of the PCB. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is an exemplary side view showing a cross section of a printed circuit substrate including tear initiation sites and delamination according to an embodiment of the present invention.

[0007] Figure 2 is an exemplary side view showing a cross section of a printed circuit substrate including an improved bond of an inner layer according to an embodiment of the present invention.

[0008] Figure 3A is an illustrative side view of a cross-section of a printed circuit substrate including adhesive-filled trenches adjacent to internal circuit traces in accordance with an embodiment of the present invention.

[0009] Figure 3B is an exemplary side view showing a cross section of a printed circuit substrate including a laser drilled trench adjacent to an internal circuit trace in accordance with an embodiment of the present invention.

[0010] Figure 4A is an exemplary side view of an embodiment according to the present invention, showing cross-sections of three alternative forms including a stepped insert structure on one side of a printed circuit substrate.

[0011] Figure 4B is an exemplary top view of a printed circuit substrate.

[0012] Figure 5 is a flow chart depicting the operational steps of an anti-tampering process 500 according to an embodiment of the present invention. DETAILED DESCRIPTION

[0013] Embodiments of the present invention recognize that components attached to printed circuit boards are often targets of unauthorized access, sabotage, and attacks to obtain data, design, or functional information associated with the target components. Typically, the target components include sabotage packages as a security protection, however, malicious actors continually seek methods and techniques to overcome the packages and access the target components. In some cases, malicious actors attempt to determine cryptographic keys, steal secret designs, reverse engineer functions, access data, or gain network access behind firewalls. In other cases, the goal is to disable or destroy the system.

[0014] The disclosed structures and techniques include the use of a security wrapper comprised of a tearable material and bonded to a component or "mother device" that includes a component and an anti-tampering covering of the component. The disclosed structures and techniques utilize edge slits on the security wrapper to facilitate tearing, and rely on tearing of the security wrapper to sever local conductors, which can provide detection of tampering but leave the component and substrate intact for malicious access. Additional disclosures include grooves or grooves as surface features for encapsulation attached to a circuit board. Embodiments of the present invention provide structures, techniques, and methods for detecting a tampered component encapsulation to initiate data removal or data scrambling and create destructive delamination of the internal circuitry of a printed circuit board, thereby preventing functional access to data and / or components or using the component to perform network access to other components or features of a network. One aspect of the present invention includes enabling specified tearing and / or delamination of one or more printed circuit board layers including security trace circuits in response to a removal force applied to the tampered wrapper. Tearing or delamination of the inner layers of the PCB results in a destructive action that disables the function of the target component and at least a portion of the PCB.

[0015] A printed circuit board (PCB) as referred to herein includes a substrate having electronic circuits on a surface and / or in an inner layer, wherein the inner layers are joined by a lamination process. As referred to herein, a PCB may include a printed circuit board, a printed circuit card, or a flexible printed circuit. A destruction package covers one or more components attached to a PCB by bonding to the components and / or the substrate to which the components are attached. The destruction package may be made of a metallic material, a plastic material, or a ridged coating material. Dielectric materials are used to create the inner layers of a PCB and to bond these layers together. Plated vias connecting one layer to another adjacent layer and plated through holes connecting two or more layers of a PCB form electrical connections between the layers.

[0016] Reference is now made to the accompanying drawings. Descriptions of various embodiments of the present invention have been given for illustrative purposes, but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope of the described embodiments. The terms used herein are selected to best explain the principles of the embodiments, practical applications, or technical improvements existing in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

[0017] Figure 1 An exemplary side view of a cross section of a printed circuit substrate including a tear initiation site and delamination according to an embodiment of the present invention is shown. It should be noted that as used herein, the term "tear initiation site" includes features that extend parallel to the inner layer of the PCB along the entire perimeter of the protected area in some embodiments, thereby forming a completely secure perimeter and providing 360-degree protection to prevent damage to the closed assembly of the PCB. The tear initiation site provides a weakened portion of the bond between the layers of the PCB, corresponding to at least a portion of the perimeter of the protected area. Therefore, the terms "tear point", "stress notch" and "tear initiation site" are not limited to a single point location, but include physical changes in the PCB that enable tearing and delamination to propagate along one or more edges of the protected area. Embodiments recognize that parallel stress notches, grooves or tear initiation sites can be produced by rotating blades, routers, lasers, and using inner layers of different sizes and / or bonding strengths to form a separation edge or inserted step on the side of the circuit substrate. In other embodiments, the tear initiation site may include a stress notch formed perpendicular to one side of the PCB.

[0018] Figure 1 The embodiment includes a PCB 102, a top anti-tampering encapsulation 104 sometimes referred to as a "top can", a bottom anti-tampering encapsulation 106 sometimes referred to as a "bottom can", an adhesive 108, parallel tear notches 110, a delamination tear 112, a security circuit 114 (sometimes referred to as a security trace), and a destructive removal force 116 shown by an upward arrow. The embodiments recognize that not all examples of anti-tampering encapsulation include top and bottom anti-tampering encapsulations, but for clarity and completeness, Figure 1 It is shown that both may be present in some embodiments. PCB 102 includes multiple internal circuit layers and may include components connected to the surface of PCB 102. By bonding top anti-tamper encapsulation 104 and / or bottom anti-tamper encapsulation 106 to the corresponding surface of PCB 102 via adhesive 108, components connected to the surface of PCB 102 (e.g., by soldering) may be protected. Figure 1PCB 102 is illustrated in cross-section as including multiple internal circuit layers. A tampering attempt to remove the tamper-resistant encapsulation results in a delamination tear 112 of at least one inner layer of PCB 102 that aligns with the positioning of the instances of parallel tear notches 110.

[0019] In some embodiments, the formation of the parallel tear notches 110 (i.e., tear initiation sites) includes, but is not limited to, mechanically, chemically, or optically removing material from a side of the PCB 102 that is aligned with a protected component attached to the surface of the PCB 102. For example, the parallel tear notches 110 are formed by mechanically, chemically, or optically removing material along a side of the PCB 102. The adhesive 108 bonds the top anti-tampering encapsulation 104 and the bottom anti-tampering encapsulation 106 to the surface of the PCB 102. In some embodiments, the adhesive 108 also bonds the top anti-tampering encapsulation 104 and the bottom anti-tampering encapsulation 106 to a protected component (not shown). Figure 1 The illustration includes a delamination tear 112 occurring at a layer joint aligned with one example of a parallel tear score 110, and displacement and / or severance of a security circuit 114 is also caused by the delamination tear 112. A destructive removal force 116, represented by a large arrow, represents a destructive effort to remove the top anti-tampering encapsulation 104, which generates sufficient force to cause the delamination tear 112. In some embodiments, severing the security circuit 114 triggers actions, which can include deleting or disrupting data included in the protected component, disabling the PCB 102 from layer delamination, or other protective actions.

[0020] Figure 2 is an exemplary side view of a cross section of a printed circuit substrate showing improved bonding including inner layers according to an embodiment of the present invention. Figure 2 Three different structural options are shown that may be incorporated into a PCB, either alone or in combination, to provide tear initiation sites within the PCB for vandalism prevention. Figure 2 Included are PCB 202 , top anti-tamper encapsulation 204 , bottom anti-tamper encapsulation 206 , adhesive 208 , alternative dielectric material 211 , internal circuit 214 , safety circuits 215 and 216 , partially conditioned dielectric material 218 , and edge plating 220 .

[0021] The top anti-tamper encapsulation 204 and the bottom anti-tamper encapsulation 206 form a protective cover for one or more components of the PCB 202, similar to the Figure 1As depicted, adhesive 208 provides a bond between the top and bottom anti-tamper encapsulations 204, 206 and the respective surfaces of PCB 202. In an embodiment of the present invention, alternative dielectric material 211 forms a weaker layer-to-layer bond, providing a selective separation failure point of PCB 202 as a result of a destructive removal force of at least one of the top anti-tamper encapsulation 204 and the bottom anti-tamper encapsulation 206. Layer separation due to delamination of alternative dielectric material 211 caused by the removal destructive force results in severance of safety circuit 215, as depicted in cross-section. Safety circuit 216 includes through-holes and plated vias to other layers of PCB 202, which become severed by delamination of alternative dielectric material 211 due to the removal destructive force applied to the top anti-tamper encapsulation 204 and / or the bottom anti-tamper encapsulation 206. The weaker bond of the replacement dielectric material 211 establishes a designated separation point within a protected area of ​​the PCB that includes a safety circuit that initiates a responsive action when severed or disconnected, such as clearing memory, randomly setting circuit bits, and / or disabling the function of the protected component.

[0022] The partially conditioned dielectric material 218 includes surface characteristics that reduce the bond strength of portions of the dielectric material between layers of the PCB 202. The partially conditioned dielectric material 218 may include the same material as other dielectric materials in the layers of the PCB 202, however, the partially conditioned dielectric material 218 has been subjected to a surface treatment operation that intentionally reduces bonding with the other layers at a designated outer portion of the dielectric material during the lamination process, the designated outer portion corresponding to the peripheral area of ​​the protected component of the PCB 202. The "partially conditioned" characteristic of the partially conditioned dielectric material 218 results in a specific separation area that is intended to correspond to a safety circuit that is destroyed or severed in response to a removal force applied to the tamper-resistant encapsulation (e.g., the top tamper-resistant encapsulation 204 and / or the bottom tamper-resistant encapsulation 206) of the PCB 202. The partially conditioned dielectric material 218 promotes tearing of the PCB 202 in pre-designated areas, but avoids tearing in other areas inside the PCB 202.

[0023] In an alternative embodiment, a selective micro-etching operation performed on the outer perimeter of the protected area of ​​the PCB 202 reduces the thickness of the edge plating layer 220, thereby providing a weaker point for starting to tear and separate the PCB 202, which is aligned with the safety circuit. The edge plating layer 220 provides electromagnetic compatibility (EMC) shielding protection for PCB signals, avoiding intolerable electromagnetic interference (EMI) effects, or excessive radiation of signals generated by circuits in the anti-destructive package. The embodiment identifies the edge plating layer 220 as having a thickness that can inhibit the expected layer separation for damage protection. The embodiment includes weakening the effect of the edge plating layer 220 in the area specified to tear or separate due to the destructive force. In one embodiment, a combination of alternative dielectric materials 211 and parallel tear notches 110 can be applied to weaken the effect of the edge plating layer 220 and enable tearing and delamination between specified layers around the PCB 202. In another embodiment, the etching operation applied to the peripheral area corresponding to the specified delamination layer causes the plating layer thickness to be reduced. In yet another embodiment, the etching operation completely removes the edge plating layer 220 from the peripheral area corresponding to the designated delamination or tear layer. Including stitch vias in the area without the edge plating layer 220 provides an EMC seal instead of the edge plating layer 220.

[0024] Figure 3A An exemplary side view is provided showing a cross-section of a printed circuit substrate including an adhesive-filled trench adjacent to an internal circuit trace in accordance with an embodiment of the present invention. Figure 3AThe present invention comprises a PCB 302, a top anti-tampering encapsulation 304, an adhesive 308, an adhesive-filled groove 313, and a safety circuit 314. In some embodiments, a surface portion of the PCB 302 aligned with the attachment area of ​​the top anti-tampering encapsulation 304 receives a groove structure ("groove") extending from the surface into the inner layer of the PCB. The top anti-tampering encapsulation 304 provides physical coverage of the protected components (not shown) of the PCB 302. The adhesive 308 bonds the top anti-tampering encapsulation 304 to the surface of the PCB 302. Embodiments include removing dielectric material between internal circuit traces, which forms a groove along at least a portion of the protected area, in which the adhesive 308 bonds the top anti-tampering encapsulation 304 and the PCB 302. The adhesive-filled groove 313 is produced by the adhesive 308 that fills the groove structure that can extend to one or more inner layers of the PCB 302. The location and size of the adhesive-filled groove 313 enable access to the safety circuit 314 of the inner layer of the PCB 302. The safety circuit 314 is broken or severed due to the removal force applied to the top anti-tampering envelop 304 bonded to the PCB 302 and the adhesive-filled groove 313 by the adhesive 308. The removal force causes tearing between the layers of the PCB 302 associated with the adhesive-filled groove 313 and the severing of the safety circuit 314, thereby initiating a predetermined action to protect the components covered by the top anti-tampering envelop 304 of the PCB 302.

[0025] Figure 3B is an illustrative side view of a cross-section of a printed circuit substrate including laser drilled trenches located adjacent to internal circuit traces in accordance with an embodiment of the present invention. Figure 3B The invention includes a PCB 302, a laser 305, a safety circuit 314, and a surface groove 315. In an embodiment of the present invention, the laser 305 generates the groove 315, and the laser is configured as a laser drilling device for removing organic materials from dielectric materials used in manufacturing multi-layer printed circuit boards. The laser 305 includes parameters of power level, beam diameter, and duration to generate a surface groove of a specified width, depth, and length of a protected area of ​​the PCB 302, and the surface groove corresponds to the top anti-destruction encapsulation 304 ( Figure 3A ) of the adhesive bonding area. Figure 3B Describes the adhesive 308 ( Figure 3A )The surface trench 315 before filling. Figure 3B The removal of sufficient dielectric material is shown to bring trench 315 into close proximity with safety circuit 314 and, in some embodiments, allow adhesive 308 to be bonded to the sides of safety circuit 314 rather than to a surface layer. Figure 3AThe additional bonding surface area provides an additional amount of tearing and delamination of the PCB 302 and severing of the safety circuit 314 by increasing the force removal level of the top anti-tampering encapsulation 304).

[0026] Figure 4A is an exemplary side view of an embodiment of the present invention, showing a cross-section including a step structure formed on one side of a printed circuit substrate. The embodiment forms a step-like structure on one side of a PCB by using inner layers cut into different sizes. The resulting step structure produces a tear initiation site caused by a stress concentration area, in which delamination tearing occurs preferentially due to the force of attempting to remove the anti-destruction encapsulation covering the protected component. In an embodiment of the present invention, the engagement of different sized inner layers of the PCB with regular sized layers of the PCB forms a step structure along the side of the PCB. For example, a first inner layer whose size along one side of the PCB is shorter than the size of the surface layer and the layer below the first inner layer can be combined with the surface layer and the lower layer (e.g., laminated) to form a step-like structure that introduces a stress concentration area for separation of the layers of the PCB.

[0027] Figure 4A Three optional versions of the stepped insert structure are depicted, and each option may be used in a single instance, multiple instances, or combinations in any order. Figure 4A It includes alternating step structures 404 , strategically placed step structures 406 , and multi-layered step structures 408 . Figure 4A Also included are regularly sized inner layers 409 and smaller sized inner layers 411. In an embodiment, the smaller sized inner layers 411 have shorter dimensions at the periphery of the protected area of ​​the PCB. The alternating step structure 404 forms an area of ​​stress concentration due to the stepped structure formed by the alternating sized layers. In one embodiment, the strategically placed step structure 406 includes forming a step structure at predetermined strategically placed layers, such as a specific layer including a security circuit, to detect tearing and delamination of the PCB due to removal forces applied to the anti-tampering encapsulation. The multi-layer step structure 408 illustrates the formation of a step structure that includes multiple inner layers of different sizes (i.e., shorter lengths relative to the side area of ​​the PCB), which are combined between multiple layers having larger dimensions in the dimensions of the side area of ​​the PCB. It should be noted that Figure 4A Three differently formed step-like structures on one side of a PCB are shown as a convenient example, and embodiments may include only one or any combination of the step structures when applying a tear initiation site structure to the perimeter of a protected area of ​​a PCB.

[0028] Figure 4B is an exemplary top view illustration of a printed circuit substrate having a top anti-tamper encapsulation covering a protected area in accordance with an embodiment of the present invention. Figure 4B Includes PCB 420, top anti-destruction encapsulation 422 and edge plating layer modification area 424. Top anti-destruction encapsulation 422 covers the protected components (not shown) of PCB 420. The dark edge depicting the edge plating modification area 424 borders the outer edge of the top anti-destruction encapsulation 422 on three sides, and includes step structure stress points parallel to the inner layer along the three side edges of PCB 420. Embodiments include performing operations on the edge plating modification area 424 to reduce or eliminate edge plating from the outer area of ​​the step structure. In some embodiments, etching operations or other processing methods perform the removal of all edge plating. In other embodiments, the reduction of the edge plating layer thickness weakens the connection between the layers included in the step structure, further enabling tearing and delamination due to the removal force applied to the top anti-destruction encapsulation 422. In some embodiments, a viscous adhesive can be used in the combination of the step structure layer to prevent the adhesive from providing a stronger lamination strength to the inner layer and offset the benefits of the step structure.

[0029] Figure 5 5 is a flow chart depicting the operational steps of an anti-tampering protection process 500 according to an embodiment of the present invention. The anti-tampering protection process 500 receives a printed circuit board (PCB) (also referred to as a printed circuit substrate) including at least one inner layer having a security circuit associated with a protected area of ​​the PCB (step 502). An embodiment includes receiving a PCB that has been processed through an operation that has joined the inner layers and surface layers that form the PCB. The received PCB includes at least one area designated as a protection area in which components will be surface mounted and covered by an anti-tampering encapsulation to protect the components from access and attack. The security circuit is positioned within at least one inner layer of the PCB including an outer edge corresponding to the protected area, and when severed, initiates an action to protect the data and functionality of the protected component, such as clearing or disrupting data stored in the protected component, and / or disabling the functionality and response of the component due to access or attack.

[0030] An embodiment determines the location of a protected area of ​​the PCB (step 504). An embodiment examines the received PCB to accurately determine the protected area of ​​the PCB, and in some embodiments, there may be more than one protected area. An embodiment identifies an outer edge associated with the location of the protected area and obtains information about a specific layer designated for achieving tearing and delamination. The specific layer information includes the distance from the surface of the PCB to the inner layer designated for tearing and delamination and bonded to the safety circuit to accurately locate the tear start site along the edge of the PCB associated with the protected area. For example, an embodiment determines the size of the protected area and the outer edge adjacent to the protected area, and further determines the location of the inner layer designated for tearing and bonding to the safety circuit at a determined distance from the top surface of the PCB.

[0031] The embodiment forms a tear initiation site along one or more sides of the PCB, which is aligned with the protected area and the inner layer associated with the safety circuit (step 506). The embodiment physically generates the tear initiation site along the side of the PCB and parallel to the inner layer of the PCB. In some embodiments, the generation and positioning of the tear initiation site is aligned with the specified inner layer bonded to the safety circuit. The tear initiation site may include, for example, physically removing material along the side of the PCB adjacent to the protected area by mechanical, chemical, optical or other material removal processes. The embodiment includes a tear initiation site formed by using different dielectric materials in the specified inner layer, which includes a lower bonding strength that can tear and delaminate at the specified layer. The embodiment may also include surface finishing of the periphery of the protected area of ​​the specified inner layer, so that the surface finishing performs a process that reduces the bonding strength of the inner layer to other layers of the PCB and enables tearing and delamination at the specified layer. The embodiment may include using inner layers of different sizes to form a step structure along the outer edge of the protected area of ​​the PCB. The step-like structure generates a stress concentration area, which is conducive to tearing or delamination at the step, and can also be achieved by etching an edge plating layer corresponding to the step structure along the outer edge of the PCB. Embodiments may include performing operations to weaken a portion of the edge plating or selectively remove all edge plating aligned with the step structure, and include stitching vias within inner layers to provide electromagnetic compatibility (EMC) functionality for the PCB in the area of ​​the step structure.

[0032] In response to detecting the severance of at least one security circuit due to an inner layer tear caused by vandalism, an embodiment performs an action to protect access to data in the component and disable the functionality of the PCB (step 508). An embodiment recognizes that after the tear initiation site is created in the PCB, additional PCB processing results in a surface mounted component and an anti-tamper encapsulation that covers the component to be protected in an adhesive manner. The components of the PCB can be protected to prevent access to keys or other data that may be included or stored in the component. An embodiment recognizes that the component can be protected from attacks to monitor the functionality of the component to obtain information that is assumed to be secure. An embodiment also recognizes that access to functional components can enable network access that would otherwise be unavailable.

[0033] Embodiments detect severing of a security circuit due to a removal force applied to a tamper-resistant encapsulation covering a protected component adhesively bonded to a surface of a PCB. The removal force produces delamination at a tear initiation site associated with the protected area and causes initiation of a predetermined action that protects access to data and disables functionality of the PCB to prevent access to other components, other PCBs, or network access that overcomes a protective firewall.

[0034] It should be noted that in some embodiments, the disconnection or severance of the safety circuit may additionally trigger an alarm or notify appropriate responders. Embodiments may include a combination of tear initiation locations, different dielectric materials, edge plating reduction or removal, different sized inner layers, and applying a surface finishing process to the perimeter of the protected area on the inner layer.

Claims

1. A structure of a circuit (hardware) substrate for protecting an area from being damaged, the structure comprising: a circuit substrate including at least one of a top tamper-resistant encapsulation and a bottom tamper-resistant encapsulation, wherein at least one of the top tamper-resistant encapsulation and the bottom tamper-resistant encapsulation provides a secure cover for a protected area of ​​the circuit substrate; a connection bonding at least one of the top anti-tamper encapsulation and the bottom anti-tamper encapsulation to the circuit substrate; as well as A tear initiation site, the tear initiation site being included as a feature extending along at least a portion of a perimeter of a protected area of ​​the circuit substrate including at least one of the top tamper-resistant encapsulation and the bottom tamper-resistant encapsulation, wherein the tear initiation site is positioned and configured to enable propagation of delamination of at least one inner layer of the circuit substrate and severing a safety circuit when a removal force is applied to at least one of the top tamper-resistant encapsulation and the bottom tamper-resistant encapsulation.

2. The structure according to claim 1, wherein: The tear initiation site includes forming a notch on one side of the substrate corresponding to the top anti-tampering encapsulation and the bottom anti-tampering encapsulation, and the notch of the tear initiation site is parallel to the at least one inner layer of the circuit substrate.

3. The structure according to claim 1, wherein: The tear initiation site includes forming a notch on one side of the substrate corresponding to the top anti-tampering encapsulation and the bottom anti-tampering encapsulation, wherein the notch of the tear initiation site is perpendicular to the at least one inner layer of the circuit substrate.

4. The structure according to claim 1, wherein: One or a combination of vias and through holes serves as a safety circuit between layers of the circuit substrate corresponding to the tear initiation site.

5. The structure according to claim 1, wherein: A dielectric material providing a weaker layer-to-layer bond is used for one or more inner layers, enabling delamination from a removal force applied to the at least one of the top tamper-resistant encapsulation and the bottom tamper-resistant encapsulation.

6. The structure according to claim 1, wherein: The tear initiation site includes creating a groove into which an adhesive is applied to increase the bonding strength of a layer connecting the top anti-tampering encapsulation or the bottom anti-tampering encapsulation to the electronic circuit substrate, wherein the groove extends from a surface of the electronic circuit substrate adjacent to an inner layer security circuit that is designated to delaminate immediately after physical damage.

7. The structure according to claim 1, wherein: The tear initiation site includes a change in dielectric material having a reduced bonding strength with other layers of the circuit substrate.

8. The structure according to claim 1, wherein: The tear initiation location includes reducing the bonding strength of the at least one inner layer of the circuit substrate by applying a surface treatment to the perimeter of the protected area of ​​the circuit substrate.

9. The structure according to claim 1, wherein: Edge plating is removed and stitching vias are used along the edge area to provide electromagnetic compatibility (EMC) shielding.

10. The structure according to claim 1, wherein: A trench is created by removing organic material and allows adhesive to bond to one side of the security traces on the plurality of inner layers of the circuit substrate.

11. The structure according to claim 1, wherein: The tear initiation site is produced by at least one physical action, the physical action being selected from the group consisting of a stress notch produced by a blade, the stress notch produced by a router, a groove produced by a laser, the groove produced by a router, and an inner layer of different sizes forming alternating serrated steps on at least one side of the circuit substrate.

12. The structure according to claim 1, wherein: Cutting the security trace circuit initiates at least one of an action from the group consisting of deleting data from components within at least one of the top tamper-resistant enclosure and the bottom tamper-resistant enclosure and disabling the circuit substrate.

13. A method for producing a disabled tear of a printed circuit board (PCB), the method comprising: receiving a printed circuit board including one or more internal layers containing security circuits located in an area associated with a protected component, the protected component receiving a vandal-resistant encapsulation adhesively attached to a surface of the PCB, wherein severing one or more of the security trace circuits initiates disabling of data and functionality of the protected component; determining an area associated with a protected component that receives the tamper-resistant encapsulation; as well as A tear initiation site is created along one side of the PCB, the tear initiation site being aligned with an area associated with the protected component.

14. The method according to claim 13, wherein: The tear initiation site is parallel to the one or more inner layers containing the safety circuit, the safety circuit being positioned in an area associated with the protected component.

15. The method according to claim 13, wherein: The tear initiation site includes a groove formed by removing dielectric material from the surface of the PCB to an inner layer of the PCB, wherein the groove is adjacent to a safety circuit and includes adhesive from a bond between the protected component and the PCB.

16. The method according to claim 13, wherein: The tear initiation site includes reducing the bond strength between one or more inner layers of the PCB by one or a combination selected from the group consisting of alternating dielectric materials and surface conditioning operations in the perimeter of the area associated with the protected component.

17. The method according to claim 13, wherein: The safety circuit includes vias and through holes connecting the layer with reduced bonding strength to another inner layer of the PCB.

18. A method for producing a disabling tear of a printed circuit board due to a tampering attempt at a protected area of ​​the printed circuit board, the method comprising: Receiving an inner layer of a printed circuit board (PCB), wherein at least one layer of the PCB decreases in size along a side that includes a protected area of ​​the PCB to which a top anti-tamper encapsulation or a bottom anti-tamper encapsulation is attached; and Combining the inner layers, wherein the at least one inner layer reduced in size is positioned to form an insertion step along a dimension of a side of the protected area of ​​the PCB, wherein the combination of the regularly sized first inner layer is bonded to the at least one layer of the PCB reduced in size along a dimension of the side of the PCB with reduced adhesion.

19. The method according to claim 18, wherein: The bonding strength of the at least one inner layer that is reduced in size is reduced by using an alternative dielectric material for the at least one inner layer.

20. The method according to claim 18, wherein: The bond strength of the at least one inner layer reduced in size is reduced by using a surface modification operation in the periphery of the protected area of ​​the at least one inner layer.

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