Low-power and high-precision temperature sensor circuit

Abstract

The present invention relates to a low-power and high-precision temperature sensor circuit. By designing a new temperature sensor circuit, a negative temperature coefficient current is generated by an I-VBE generation circuit, and a positive temperature coefficient current is generated by an I-DVBE generation circuit. A current-mode Sigma-Delta ADC quantizes the temperature-related current amounts generated by the I-VBE generation circuit and the I-DVBE generation circuit into a digital bit stream. A digital decimation filter filters the digital bit stream to obtain temperature data DOUT and outputs it. This new temperature sensor circuit is of a current-input Sigma-Delta structure and does not require a high-precision reference voltage independent of temperature to participate in the conversion, eliminating the influence of the accuracy of the reference voltage, realizing the design of a low-power and high-precision temperature sensor, and basically meeting the requirements of low-power and high-precision temperature measurement.

Description

Technical Field

[0001] The present invention belongs to the technical field of sensor circuit design and relates to a low-power high-precision temperature sensor circuit. Background Art

[0002] With the rapid development of the Internet of Things technology, temperature measurement plays a crucial role in many fields. Whether it is industrial production monitoring, thermal management in the aerospace field, medical health monitoring, or temperature monitoring of items in logistics, etc., there are strict requirements for the measurement accuracy and power consumption of temperature sensors. In this context, the research and development of high-precision temperature sensors are particularly important. Traditional temperature sensors usually adopt a voltage-type Sigma-Delta ADC structure. The voltage-type Sigma-Delta ADC requires a very precise reference voltage generation circuit to generate a reference voltage independent of temperature, and the temperature characteristics of the reference voltage will directly affect the accuracy of the entire sensor. Temperature sensors using a SAR ADC (Successive Approximation Register Analog-to-Digital Converter) structure also require a precise reference voltage generation circuit to generate a reference voltage for conversion, and in addition, they consume more power and area. Therefore, how to achieve the design of a low-power high-precision temperature sensor to meet the requirements of low-power high-precision temperature measurement has become one of the technical problems to be solved currently. Summary of the Invention

[0003] Aiming at the problems existing in the above traditional technologies, the present invention proposes a low-power high-precision temperature sensor circuit, which can achieve the design of a low-power high-precision temperature sensor and meet the requirements of low-power high-precision temperature measurement.

[0004] To achieve the above object, the embodiments of the present invention adopt the following technical solutions:

[0005] A low-power high-precision temperature sensor circuit is provided, including an IVBE generation circuit, an IDVBE generation circuit, a current-type Sigma-Delta ADC, a digital decimation filter, and a control logic unit. The current-type Sigma-Delta ADC is respectively connected to the IVBE generation circuit, the IDVBE generation circuit, the digital decimation filter, and the control logic unit, and the control logic unit is also connected to the digital decimation filter;

[0006] The IVBE generation circuit is used to generate a negative temperature coefficient current, the IDVBE generation circuit is used to generate a positive temperature coefficient current, the current-mode Sigma-Delta ADC is used to quantize the negative temperature coefficient current and the positive temperature coefficient current into digital bitstreams respectively, the digital decimation filter is used to filter the digital bitstreams to obtain temperature data and output it, and the control logic unit is used to control the working state of the current-mode Sigma-Delta ADC by using a switching strategy, so that the duty cycle of the output of the current-mode Sigma-Delta ADC changes linearly with temperature, and synchronously control the digital decimation filter to accurately filter and output the digital bitstreams.

[0007] One of the above technical solutions has the following advantages and beneficial effects:

[0008] The above low-power and high-precision temperature sensor circuit designs a new temperature sensor circuit by using circuit modules such as the IVBE generation circuit, the IDVBE generation circuit, the current-mode Sigma-Delta ADC, the digital decimation filter, and the control logic unit. The IVBE generation circuit generates a negative temperature coefficient current, the IDVBE generation circuit generates a positive temperature coefficient current, the current-mode Sigma-Delta ADC quantizes the temperature-related current generated by the IVBE generation circuit and the IDVBE generation circuit into a digital bitstream, and the digital decimation filter filters the digital bitstream processed by the current-mode Sigma-Delta ADC to obtain temperature data DOUT and output it. This new temperature sensor circuit is a current-input Sigma-Delta structure, does not require a high-precision reference voltage independent of temperature to participate in the conversion, eliminates the influence of the accuracy of the reference voltage, realizes the design of a low-power and high-precision temperature sensor, and basically meets the requirements of low-power and high-precision temperature measurement. Brief Description of the Drawings

[0009] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or in the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0010] Figure 1 It is a schematic diagram of the module circuit structure of the low-power and high-precision temperature sensor circuit in an embodiment;

[0011] Figure 2 It is a schematic diagram of the core circuit structure of the current-mode Sigma-Delta ADC in an embodiment;

[0012] Figure 3Schematic diagram of the circuit structure of the control logic unit in an embodiment;

[0013] Figure 4 Schematic diagram of the switching strategy of the current-mode Sigma-Delta ADC in an embodiment;

[0014] Figure 5 Schematic diagram of the simulation waveform of the low-power high-precision temperature sensor circuit in an embodiment;

[0015] Figure 6 Schematic diagram of the circuit structure of the IDVBE generation circuit in an embodiment;

[0016] Figure 7 Schematic diagram of the two-stage offset auto-zero operational amplifier structure in an embodiment;

[0017] Figure 8 Schematic diagram of the circuit structure of the IVBE generation circuit in an embodiment;

[0018] Figure 9 Schematic diagram of the measurement error of the low-power high-precision temperature sensor circuit in an embodiment. Detailed implementation manners

[0019] In order to make the objectives, technical solutions and advantages of the present invention clearer and more understandable, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which the present invention belongs. The terms used in the description of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0020] It should be noted that referring to "embodiment" herein means that a specific feature, structure or characteristic described in connection with the embodiment may be included in at least one embodiment of the present invention. Displaying this phrase at various positions in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art can understand that the embodiments described herein can be combined with other embodiments. The term "and / or" used in the description and claims of the present invention refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0021] The following will describe the embodiments of the present invention in detail with reference to the accompanying drawings in the embodiments of the present invention.

[0022] In one embodiment, as Figure 1As shown in the figure, a low-power and high-precision temperature sensor circuit is provided, which includes an IVBE generation circuit, an IDVBE generation circuit, a current-mode Sigma-Delta ADC, a digital decimation filter, and a control logic unit. The current-mode Sigma-Delta ADC is respectively connected to the IVBE generation circuit, the IDVBE generation circuit, the digital decimation filter, and the control logic unit, and the control logic unit is also connected to the digital decimation filter. The IVBE generation circuit is used to generate a negative temperature coefficient current. The IDVBE generation circuit is used to generate a positive temperature coefficient current. The current-mode Sigma-Delta ADC is used to quantize the negative temperature coefficient current and the positive temperature coefficient current into digital bitstreams respectively. The digital decimation filter is used to filter the digital bitstream to obtain temperature data and output it. The control logic unit is used to control the working state of the current-mode Sigma-Delta ADC by using a switching strategy, so that the duty cycle of the output of the current-mode Sigma-Delta ADC changes linearly with temperature, and synchronously controls the digital decimation filter to accurately filter and output the digital bitstream.

[0023] It can be understood that this embodiment adopts a unique temperature-sensitive current generation circuit (including an IVBE generation circuit and an IDVBE generation circuit) combined with a current-mode Sigma-Delta ADC circuit, and realizes the relationship that the duty cycle of the ADC output changes linearly with temperature through a novel switching strategy; at the same time, the IVBE generation circuit and the IDVBE generation circuit can use chopping technology and automatic zeroing technology to meet the requirements of high-precision temperature measurement, and its overall block diagram is as Figure 1 shown. Among them, IVBE is a current generation circuit proportional to VBE (the base-emitter voltage of a Bipolar Junction Transistor). VBE is an important parameter of a bipolar junction transistor, and it has a negative correlation with temperature. Within a certain temperature range, as the temperature increases, VBE will decrease. The function of the IVBE generation circuit is to generate a current proportional to the voltage VBE, and this current will also change with temperature, and the change trend is the same as that of VBE. And IDVBE is a current generation circuit proportional to ΔVBE (the difference between the base-emitter voltages of a bipolar junction transistor under two different current densities). ΔVBE has a positive temperature coefficient, that is, as the temperature increases, ΔVBE will increase. The purpose of the IDVBE generation circuit is to generate a current proportional to ΔVBE, and this current will also increase as the temperature increases. The temperature sensor circuit of this embodiment is a current-input Sigma-Delta structure, which is different from the traditional voltage-type input and does not require a high-precision and temperature-independent reference voltage to participate in the conversion, so the influence of the reference voltage accuracy is eliminated.

[0024] Specifically, the low-power high-precision temperature sensor circuit consists of an IVBE generation circuit, an IDVBE generation circuit, a current-mode Sigma-Delta ADC, a digital decimation filter, and a control logic unit. Among them, the IVBE generation circuit is used to generate a negative temperature coefficient current, the IDVBE generation circuit is used to generate a positive temperature coefficient current, the current-mode Sigma-Delta ADC is used to quantize the temperature-related current generated by the IVBE generation circuit and the IDVBE generation circuit into a digital bit stream, and the digital decimation filter is used to filter the digital bit stream processed by the current-mode Sigma-Delta ADC to obtain 12-bit (bit) temperature data DOUT and output it. The control logic unit is used to control the working state of the current-mode Sigma-Delta ADC through a unique switching strategy, so that its output duty cycle changes linearly with temperature, and at the same time synchronously controls the digital decimation filter to ensure that the digital decimation filter accurately filters and outputs the digital bit stream processed by the current-mode Sigma-Delta ADC.

[0025] For the above low-power high-precision temperature sensor circuit, by adopting circuit modules such as an IVBE generation circuit, an IDVBE generation circuit, a current-mode Sigma-Delta ADC, a digital decimation filter, and a control logic unit to design a new temperature sensor circuit, the IVBE generation circuit generates a negative temperature coefficient current, the IDVBE generation circuit generates a positive temperature coefficient current, the current-mode Sigma-Delta ADC quantizes the temperature-related current generated by the IVBE generation circuit and the IDVBE generation circuit into a digital bit stream, and the digital decimation filter filters the digital bit stream processed by the current-mode Sigma-Delta ADC to obtain temperature data DOUT and output it. This new temperature sensor circuit is a current-input Sigma-Delta structure, does not require a high-precision reference voltage independent of temperature to participate in the conversion, eliminates the influence of the accuracy of the reference voltage, realizes the design of a low-power high-precision temperature sensor, and basically meets the requirements of low-power high-precision temperature measurement.

[0026] In one embodiment, as Figure 2 shown, the current-mode Sigma-Delta ADC may include switches S1, S2, S3, S4, S5, S6, S7, integrator IG, comparator CP1, D flip-flop D1, inverter INV1, first current source I PTAT and NMOS transistor NM1. The input terminal of the first current source I PTAT is used to connect to a power supply (such as VDD), and the first current source I PTATThe output terminal of [device] is connected to the drain of NMOS transistor NM1. The source of NMOS transistor NM1 is grounded. The gate of NMOS transistor NM1 is connected to the input terminals of switch S1 and switch S5 respectively. The input terminal of switch S2 is connected to the output terminal of the IVBE generation circuit. The output terminals of switch S1 and switch S2 are connected together and connected to the input terminal of switch S3. The input terminal of switch S4 is connected to the output terminal of the IDVBE generation circuit. The output terminals of switch S4 and switch S5 are connected together and connected to the input terminal of switch S6. The output terminals of switch S3 and switch S6 are connected together and connected to the inverting input terminal of integrator IG. The non-inverting input terminal of integrator IG is used to connect to the DC bias voltage V1. Switch S7 is connected in parallel with integrator IG.

[0027] The output terminal of integrator IG is connected to the non-inverting input terminal of comparator CP1. The inverting input terminal of comparator CP1 is used to connect to the DC bias voltage V1. The output terminal of comparator CP1 is connected to the D terminal of D flip-flop D1. The clock terminal of D flip-flop D1 is used to connect to the clock signal CKS. The Q terminal of D flip-flop D1 is connected to the input terminal of inverter INV1. The output terminal of inverter INV1 is connected to the input terminal of the digital decimation filter. The control terminals of switch S1, switch S3, switch S5 and switch S6 are respectively connected to the control logic unit. The control terminals of switch S2 and switch S4 are respectively used to connect to the enable signal EN. The control terminal of switch S7 is used to connect to the enable signal ENB.

[0028] It can be understood that as Figure 2 shown, integrator IG is mainly composed of an operational amplifier, resistor R1 and capacitor C1. The enable signal EN is usually a high-level active signal. When the enable signal EN is at a high level, switch S2 and switch S4 are enabled and closed. When the enable signal EN is at a low level, switch S2 and switch S4 are open. The enable signal ENB is a low-level active signal, that is, when the enable signal ENB is at a low level, switch S7 is enabled and closed. When the enable signal ENB is at a high level, switch S7 is in the open state. In Figure 2 the shown current-mode Sigma-Delta ADC core circuit, the DC bias voltage V1 provides DC bias for integrator IG and comparator CP1, and does not affect the accuracy of the temperature sensor. Among them, the current IVBE connected to the input terminal of switch S2 is a negative temperature coefficient current, and the current IDVBE connected to the input terminal of switch S4 is a positive temperature coefficient current. VIR is a virtual node. Introducing this virtual node can prevent the current source from entering the linear region when switch S3 is turned off, ensuring that the first current source I PTAT is always in the on state. In this way, the error caused by the setup time of the first current source I PTAT can be reduced and the interference caused by charge sharing can be eliminated. Among them, comparator CP1 can be implemented by using the existing Schmitt Trigger in the art to realize its function.

[0029] In one embodiment, as Figure 3 shown, the control logic unit may include an inverter INV2, an AND gate AND1, an AND gate AND2, an OR gate OR1, and an OR gate OR2. The input terminal of the inverter INV2 is used to receive the clock signal CKS. The output terminal of the inverter INV2 is respectively connected to one input terminal of the AND gate AND1 and one input terminal of the AND gate AND2. The other input terminal of the AND gate AND1 is connected to the output terminal of the inverter INV1. The other input terminal of the AND gate AND2 is connected to the Q terminal of the D flip-flop. The output terminal of the AND gate AND1 is connected to one input terminal of the OR gate OR1. The other input terminal of the OR gate OR1 is respectively connected to one input terminal of the OR gate OR2 and the input terminal of the inverter INV2. The other input terminal of the OR gate OR2 is connected to the output terminal of the AND gate AND2. The output terminal of the OR gate OR1 is connected to the control terminal of the switch S3 and simultaneously connected to the control terminal of the switch S1 through an inverter. The output terminal of the OR gate OR2 is connected to the control terminal of the switch S6 and simultaneously connected to the control terminal of the switch S5 through an inverter.

[0030] It can be understood that CKSB is the clock signal after the clock signal CKS passes through the inverter INV2, and its signal level is opposite to that of the clock signal CKS. DS represents the digital code stream output by the D flip-flop D1, and DSB represents the digital code stream after DS passes through the inverter INV1. represents the control signal output by the OR gate OR1, represents the control signal output by the OR gate OR2.

[0031] In one embodiment, when the current-mode Sigma-Delta ADC starts to work, the enable signal EN will be pulled high. The switching strategy includes a conversion 1 stage, a conversion 2 stage, a conversion 3 stage, and a conversion 4 stage. In the conversion 1 stage, the switch S3 is closed, the switch S1 is opened, the switch S2 is closed, the IVBE generation circuit charges the node where the inverting input terminal of the integrator IG is located, the switch S6 is closed, the switch S5 is opened, the switch S4 is closed, and the IDVBE generation circuit discharges the node where the inverting input terminal of the integrator IG is located.

[0032] In the conversion 2 stage, the switch S3 is opened, the switch S1 is closed, the switch S2 is closed, the IVBE generation circuit charges the VIR virtual node, the switch S6 is closed, the switch S5 is opened, the switch S4 is closed, and the IDVBE generation circuit discharges the node where the inverting input terminal of the integrator IG is located.

[0033] In the conversion 3 stage, the switch S3 is closed, the switch S1 is opened, the switch S2 is closed, the IVBE generation circuit charges the node where the inverting input terminal of the integrator IG is located, the switch S6 is closed, the switch S5 is opened, the switch S4 is closed, and the IDVBE generation circuit discharges the node where the inverting input terminal of the integrator IG is located.

[0034] In the fourth conversion stage, switch S3 is closed, switch S1 is open, switch S2 is closed, the IVBE generation circuit charges the node where the inverting input terminal of integrator IG is located, switch S6 is open, switch S5 is closed, switch S4 is closed, and the IDVBE generation circuit discharges the VIR virtual node.

[0035] It can be understood that the specific working mode of the above current-mode Sigma-Delta ADC can be described as follows: When the current-mode Sigma-Delta ADC starts to work, the enable signal EN is pulled high, and the switch strategy starts to work. The functions implemented by its logic are:

[0036] ;

[0037] Specifically, as Figure 4 shown, the working state of the current-mode Sigma-Delta ADC is divided into four stages. In the CONVERSION 1 stage, control switch S3 is closed, the control signal after passing through the inverter controls switch S1 to open, and the current IVBE charges the IN node, control switch S6 is closed, the control signal after passing through the inverter controls switch S5 to open, and the current IDVBE discharges the IN node. In the CONVERSION 2 stage, control switch S3 is open, control switch S1 is closed, and the current IVBE charges the VIR virtual node, control switch S6 is closed, control switch S5 is open, and the current IDVBE discharges the IN node. In the CONVERSION 3 stage, control switch S3 is closed, control switch S1 is open, and the current IVBE charges the IN node, control switch S6 is closed, control switch S5 is open, and the current IDVBE discharges the IN node. In the CONVERSION 4 stage, control switch S3 is closed, control switch S1 is open, and the current IVBE charges the IN node, control switch S6 is open, control switch S5 is closed, and the current IDVBE discharges the VIR virtual node. Through the above unique switch strategy, the relationship between the duty cycle and the temperature changing linearly is efficiently realized.

[0038] Assume that the total number of data in the output digital bitstream (or bitstream) DS is M, where the number of 0s is N. Due to the working characteristics of the current-mode Sigma-Delta ADC, when the current-mode Sigma-Delta ADC operates stably, the average input current should tend to 0. Then we can get:

[0039] N×IDVBE + 0.5×(M - N)×IDVBE = 0.5×N×IVBE + (M - N)×IVBE (1)

[0040] From formula (1), the duty cycle of the output bitstream of the current-mode Sigma-Delta ADC can be obtained u :

[0041] (2)

[0042] The current simulation waveform of the current-mode Sigma-Delta ADC is as follows Figure 5 As shown, when the current IDVBE and the current IVBE are equal, the temperature value is 42.5°C, which is the middle value of the temperature measurement range of -40°C to 125°C. This value can be adjusted by controlling the slopes of IDVBE and IVBE. At this time, the average duty cycle of the output bitstream of the current-mode Sigma-Delta ADC is 50%. Its temperature utilization rate is 75%. The output duty cycle of the current-mode Sigma-Delta ADC u varies linearly with temperature. Therefore, the duty cycle u can well reflect the temperature value. The reference current IREF of the current-mode Sigma-Delta ADC is obtained by adding IDVBE and IVBE, and no additional reference voltage is required compared with the traditional technology.

[0043] Therefore, according to the state of the clock signal CKS and the quantization output results (i.e., the digital bitstream DS and the digital bitstream DSB), the above current-mode Sigma-Delta ADC determines whether the positive temperature coefficient current and the negative temperature coefficient current are connected to the current state of the integrator IG. When the clock signal CKS is at a high level, the positive temperature coefficient current is extracted from the integrator IG and the negative temperature coefficient current is injected into the integrator IG. When the clock signal CKS is at a low level, if the quantization output is at a low level at this time, the negative temperature coefficient current is injected into the integrator IG, otherwise the positive temperature coefficient current is extracted from the integrator IG, so that within the detection temperature range of -40°C to 125°C, the digital range output by the temperature sensor circuit is well expanded, as Figure 5 shown, reaching 75% of the full scale, thus improving the overall absolute accuracy.

[0044] In one embodiment, as Figure 6As shown, the IDVBE generation circuit includes resistor R2, resistor R3, resistor R4, resistor R5, transistor Q1, transistor Q2, chopper CR1, NMOS transistor MN1, and two ping-pong operational amplifier structures with offset automatic zeroing. One end of resistor R2 is used to connect to the power supply, and the other end of resistor R2 is respectively connected to one end of two resistors R3. The other ends of the two resistors R3 are each connected to the emitter of transistor Q1 and the emitter of transistor Q2 through a resistor R4. The base of transistor Q1 is connected to the base of transistor Q2 through two resistors R5. The collectors of transistor Q1 and transistor Q2 are both grounded, and a lead is drawn between the two resistors R5 and grounded.

[0045] The non-inverting input terminals of the two ping-pong operational amplifier structures are both connected through chopper CR1 to the lead drawn between a series of resistor R3 and resistor R4. The inverting input terminals of the two ping-pong operational amplifier structures are both connected through chopper CR1 to the lead drawn between another series of resistor R3 and resistor R4. The output terminals of the two ping-pong operational amplifier structures are both connected to the gate of NMOS transistor MN1. The drain of NMOS transistor MN1 is connected to the input terminal of switch S4, and the source of NMOS transistor MN1 is connected to the base of transistor Q2. The two ping-pong operational amplifier structures have the same structure.

[0046] It can be understood that the IDVBE generation circuit is composed of two ping-pong operational amplifier structures with offset automatic zeroing, transistors, choppers, and resistors, etc. Its working process is as follows: When the control voltage is at a high level, the operational amplifier A1 in the ping-pong operational amplifier structure is in the offset voltage automatic zeroing state, while the operational amplifier A2 in the other ping-pong operational amplifier structure is in the signal amplification state. When the control voltage is at a low level, the operational amplifier A2 is in the offset voltage automatic zeroing state, while the operational amplifier A1 is in the signal amplification state. Among them, represents the inversion of the control voltage , and is the control voltage of chopper CR1. The peripheral circuit part of the ping-pong operational amplifier structure is as shown in Figure 6 , and usually can include a switch (whose control terminal is controlled by the control voltage ) connected in series between the two input terminals of operational amplifier A1, a switch (whose control terminal is controlled by the control voltage ) connected before the inverting input terminal of operational amplifier A1, a switch (whose control terminal is controlled by the control voltage ) connected in series between the output terminal and the feedback input terminal of operational amplifier A1, and a switch (whose control terminal is controlled by the control voltage for control), and a capacitor Caz1 connected in series to the feedback input terminal of the operational amplifier A1, etc.; the peripheral circuit parts of other ping-pong operational amplifier structures can be understood similarly with reference to the corresponding attached drawings.

[0047] When the resistance value of the resistor R4 is much larger than that of the resistor R3, the output current of the IDVBE generation circuit can be approximately expressed as:

[0048] (3)

[0049] Wherein, k is the Boltzmann constant, t is the temperature, q is the electric charge amount, R4 is the resistance value of the resistor R4, and N0 is the ratio of the number of parallel-connected transistors Q1 and Q2.

[0050] In one embodiment, as Figure 7 shown, the ping-pong operational amplifier structure may include NMOS transistors MN2 to MN15, PMOS transistors MP1 to MP6, and two capacitors Caz1. The gate of the PMOS transistor MP1 serves as the non-inverting input terminal, and the gate of the PMOS transistor MP2 serves as the inverting input terminal. The sources of the PMOS transistors MP1 and MP2 are connected together and connected to the drain of the PMOS transistor MP3. The gates of the PMOS transistors MP3 and MP4 are both used to access the control voltage V bp , and the sources of the PMOS transistors MP3 and MP4 are both used to connect to the power supply, and the drain of the PMOS transistor MP4 serves as the output terminal.

[0051] The drain of the PMOS transistor MP1 is respectively connected to the drains of the NMOS transistors MN2, MN6, MN8, MN12, and the source of the PMOS transistor MP5. The drain of the PMOS transistor MP2 is respectively connected to the drains of the NMOS transistors MN3, MN7, MN9, MN13, and the source of the PMOS transistor MP6. The source of the NMOS transistor MN12 is respectively connected to the drains of the NMOS transistors MN14 and MN13. The source of the NMOS transistor MN14 is connected to the gate of the NMOS transistor MN15. The drain of the NMOS transistor MN15 is connected to the drain of the PMOS transistor MP4. The source of the NMOS transistor MN15 is grounded. The gate of the NMOS transistor MN12 is used to access the control voltage and the gate of the NMOS transistor MN13 is used to access the reverse voltage of the control voltage , and the gate of the NMOS transistor MN14 is used to access the control voltage .

[0052] The gate of NMOS transistor MN2 is used to connect to a control voltage of reverse voltage. The gate of NMOS transistor MN3 is used to connect to a control voltage , the sources of NMOS transistors MN2 and MN3 are connected and connected to the gate of NMOS transistor MN4. The gates of NMOS transistors MN4 and MN5 are connected. The sources of NMOS transistors MN4 and MN5 are both grounded. The drain of NMOS transistor MN4 is connected to the drain of PMOS transistor MP5. The drain of NMOS transistor MN5 is connected to the drain of PMOS transistor MP6. The gates of PMOS transistor MP5, PMOS transistor MP6, NMOS transistor MN6 and NMOS transistor MN7 are all used to connect to a control voltage V bn .

[0053] The gates of NMOS transistors MN8 and MN9 are both used to connect to a control voltage of reverse voltage. The source of NMOS transistor MN8 is respectively connected to the gate of NMOS transistor MN10 and one end of a capacitor Caz1. The source of NMOS transistor MN9 is respectively connected to the gate of NMOS transistor MN11 and the other end of another capacitor Caz1. The other ends of the two capacitors Caz1 are both grounded. The sources of NMOS transistors MN10 and MN11 are both grounded. The drain of NMOS transistor MN10 is connected to the source of NMOS transistor MN6. The drain of NMOS transistor MN11 is connected to the source of NMOS transistor MN7.

[0054] It can be understood that the control voltage V bp and the control voltage V bn can be provided by an external power supply and are used to control the operation of the corresponding MOS transistors. In this embodiment, each ping-pong operational amplifier structure is composed of two-stage amplification structures, and a chopper circuit is added to the operational amplifier to further reduce the offset voltage of the operational amplifier, thereby reducing the influence of the offset voltage on temperature measurement. Among them, the control voltage controls the chopper circuit, and the control voltage controls the automatic zero adjustment function of the operational amplifier, and the offset voltage is stored on the capacitor Caz1.

[0055] In one embodiment, as Figure 8 shown, the IVBE generation circuit includes a second current source I BIAS , transistor Q3, chopper CR2, PMOS transistors MP7 to MP12, switches S8 to S11, capacitor Ch1, capacitor Ch2, resistor R6, and two ping-pong operational amplifiers with offset automatic zero adjustment ( A3 and A 4) Structure. The second current source I BIAS has an input terminal for connecting to a power supply. The output terminal of the second current source I BIAS is connected to the emitter of transistor Q3. The collector and base of transistor Q3 are both grounded. The non-inverting input terminals of two ping-pong operational amplifier structures are both connected to the output terminal of the second current source through chopper CR2 I BIAS . The inverting input terminals of the two ping-pong operational amplifier structures are both connected to one end of resistor R6 through chopper CR2. The other end of resistor R6 is grounded. The control terminal of chopper CR2 is used to connect to a control voltage .

[0056] The drains of PMOS transistor MP7 and PMOS transistor MP8 are both connected to one end of resistor R6. The gate of PMOS transistor MP7 is used to connect to a control voltage , and the gate of PMOS transistor MP8 is used to connect to the reverse voltage of the control voltage. The source of PMOS transistor MP7 is respectively connected to the drain of PMOS transistor MP11 and the input terminal of switch S11. The source of PMOS transistor MP8 is respectively connected to the drain of PMOS transistor MP12 and the input terminal of switch S10. The output terminals of switch S10 and switch S11 are connected together as the output terminal of the IVBE generation circuit.

[0057] The gates of PMOS transistor MP11 and PMOS transistor MP12 are both used to connect to a control voltage V bp , the source of PMOS transistor MP11 is connected to the drain of PMOS transistor MP9, the source of PMOS transistor MP12 is connected to the drain of PMOS transistor MP10. The sources of PMOS transistor MP9 and PMOS transistor MP10 are both used to connect to a power supply. The gate of PMOS transistor MP9 is respectively connected to the output terminal of switch S9 and one end of capacitor Ch2. The gate of PMOS transistor MP10 is respectively connected to the output terminal of switch S8 and one end of capacitor Ch1. The other ends of capacitor Ch1 and capacitor Ch2 are both grounded.

[0058] The input terminals of switch S8 are respectively connected to the output terminals of the two ping-pong operational amplifier structures. The input terminals of switch S9 are respectively connected to the output terminals of the two ping-pong operational amplifier structures. The control terminals of switch S8 and switch S11 are both used to connect to a control voltage , and the control terminals of switch S9 and switch S10 are both used to connect to the reverse voltage of the control voltage.

[0059] It can be understood that two ping-pong operational amplifier structures can also be adopted in the IVBE generation circuit. These two ping-pong operational amplifier structures are the same as those used in the IDVBE generation circuit. When the two ping-pong operational amplifier structures are actually working, while one operational amplifier structure amplifies the signal, the other operational amplifier structure performs zero adjustment of the offset voltage, and so on in a cycle. This working method enables the circuit to continuously perform automatic offset zero adjustment while processing continuous input signals, ensuring the continuity of signal processing.

[0060] Specifically, PMOS transistors MP9 to MP12 form a current mirror circuit, and the mismatch between the current mirrors is averaged out by the chopper controlled by the control voltage The output current of the IVBE generation circuit is expressed as:

[0061] (4)

[0062] Among them, VBE in formula (4) is the base-emitter voltage of transistor Q3, and R6 is the resistance value of resistor R6.

[0063] The above low-power and high-precision temperature sensor circuit exhibits good temperature measurement effects in the temperature range of -40°C to 125°C. After two-point calibration (calibration is performed at -20°C and 100°C respectively), its temperature measurement error is within ±1°C, as Figure 9 shown, where σ is the standard deviation.

[0064] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as the combinations of these technical features do not conflict, they should all be considered to be within the scope described in this specification.

[0065] The above embodiments only represent several implementation manners of the present invention, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the protection scope of the invention. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several deformations and improvements can still be made, which all belong to the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the appended claims.

Claims

1. A low-power and high-precision temperature sensor circuit, characterized in that, It includes an IVBE generation circuit, an IDVBE generation circuit, a current-mode Sigma-Delta ADC, a digital decimation filter, and a control logic unit. The digital decimation filter and the control logic unit are connected, and the control logic unit is also connected to the digital decimation filter; The IVBE generation circuit is used to generate a negative temperature coefficient current, the IDVBE generation circuit is used to generate a positive temperature coefficient current, the current-mode Sigma-Delta ADC is used to quantize the negative temperature coefficient current and the positive temperature coefficient current into digital bitstreams respectively, the digital decimation filter is used to filter the digital bitstreams to obtain temperature data and output it, and the control logic unit is used to control the working state of the current-mode Sigma-Delta ADC using a switching strategy, so that the duty cycle of the output of the current-mode Sigma-Delta ADC changes linearly with temperature, and synchronously control the digital decimation filter to accurately filter and output the digital bitstreams; The current-mode Sigma-Delta ADC includes a switch S1, a switch S2, a switch S3, a switch S4, a switch S5, a switch S6, a switch S7, an integrator, a comparator, a D flip-flop, an inverter INV1, a first current source, and an NMOS transistor NM1. The input terminal of the first current source is used to connect to a power supply, the output terminal of the first current source is connected to the drain of the NMOS transistor NM1, the source of the NMOS transistor NM1 is grounded, and the gate of the NMOS transistor NM1 is connected to the input terminals of the switch S1 and the switch S5 respectively; The input terminal of the switch S2 is connected to the output terminal of the IVBE generation circuit, the output terminals of the switch S1 and the switch S2 are connected and connected to the input terminal of the switch S3, the input terminal of the switch S4 is connected to the output terminal of the IDVBE generation circuit, the output terminals of the switch S4 and the switch S5 are connected and connected to the input terminal of the switch S6, the output terminals of the switch S3 and the switch S6 are connected and connected to the inverting input terminal of the integrator, the non-inverting input terminal of the integrator is used to connect to a DC bias voltage, and the switch S7 is connected in parallel with the integrator; the output terminal of the integrator is connected to the non-inverting input terminal of the comparator, the inverting input terminal of the comparator is used to connect to a DC bias voltage, the output terminal of the comparator is connected to the D terminal of the D flip-flop, the clock terminal of the D flip-flop is used to connect to a clock signal, the Q terminal of the D flip-flop is connected to the input terminal of the inverter INV1, and the output terminal of the inverter INV1 is connected to the input terminal of the digital decimation filter; the control terminals of the switch S1, the switch S3, the switch S5, and the switch S6 are respectively connected to the control logic unit, the control terminals of the switch S2 and the switch S4 are respectively used to connect to an enable signal EN, and the control terminal of the switch S7 is used to connect to an enable signal ENB; When the enable signal EN is pulled high, the switching strategy includes: In the conversion 1 stage, the switch S3 is closed, the switch S1 is open, the switch S2 is closed, the IVBE generation circuit charges the node where the inverting input terminal of the integrator is located, the switch S6 is closed, the switch S5 is open, the switch S4 is closed, and the IDVBE generation circuit discharges the node where the inverting input terminal of the integrator is located; For the second conversion stage, switch S3 is turned on, switch S1 is turned off, switch S2 is turned off, the IVBE generation circuit charges the VIR virtual node, switch S6 is turned off, switch S5 is turned on, switch S4 is turned off, and the IDVBE generation circuit discharges the node where the inverting input terminal of the integrator is located; For the third conversion stage, switch S3 is turned off, switch S1 is turned on, switch S2 is turned off, the IVBE generation circuit charges the node where the inverting input terminal of the integrator is located, switch S6 is turned off, switch S5 is turned on, switch S4 is turned off, and the IDVBE generation circuit discharges the node where the inverting input terminal of the integrator is located; For the fourth conversion stage, switch S3 is turned off, switch S1 is turned on, switch S2 is turned off, the IVBE generation circuit charges the node where the inverting input terminal of the integrator is located, switch S6 is turned on, switch S5 is turned off, switch S4 is turned off, and the IDVBE generation circuit discharges the VIR virtual node.

2. The low-power high-precision temperature sensor circuit according to claim 1, characterized in that The control logic unit includes an inverter INV2, an AND gate AND1, an AND gate AND2, an OR gate OR1, and an OR gate OR2. The input terminal of the inverter INV2 is used to connect to the clock signal. The output terminal of the inverter INV2 is respectively connected to one input terminal of the AND gate AND1 and one input terminal of the AND gate AND2. The other input terminal of the AND gate AND1 is connected to the output terminal of the inverter INV1. The other input terminal of the AND gate AND2 is connected to the Q terminal of the D flip-flop; The output terminal of the AND gate AND1 is connected to one input terminal of the OR gate OR1. The other input terminal of the OR gate OR1 is respectively connected to one input terminal of the OR gate OR2 and the input terminal of the inverter INV2. The other input terminal of the OR gate OR2 is connected to the output terminal of the AND gate AND2; The output terminal of the OR gate OR1 is connected to the control terminal of the switch S3 and is connected to the control terminal of the switch S1 through an inverter. The output terminal of the OR gate OR2 is connected to the control terminal of the switch S6 and is connected to the control terminal of the switch S5 through an inverter.

3. The low-power high-precision temperature sensor circuit according to claim 1 or 2, characterized in that, The IDVBE generation circuit includes a resistor R2, a resistor R3, a resistor R4, a resistor R5, a triode Q1, a triode Q2, a chopper CR1, an NMOS transistor MN1, and two ping-pong operational amplifier structures with offset auto-zeroing; One end of the resistor R2 is used to connect to the power supply. The other end of the resistor R2 is respectively connected to one end of the two resistors R3. The other ends of the two resistors R3 are each connected to the emitter of the triode Q1 and the emitter of the triode Q2 through a resistor R4. The base of the triode Q1 is connected to the base of the triode Q2 through two resistors R5. The collectors of the triode Q1 and the triode Q2 are both grounded. A lead is drawn between the two resistors R5 and grounded; The non-inverting input terminals of the two ping-pong operational amplifier structures are both connected through the chopper CR1 to the lead wire between a series of the resistor R3 and the resistor R4. The inverting input terminals of the two ping-pong operational amplifier structures are both connected through the chopper CR1 to the lead wire between another series of the resistor R3 and the resistor R4. The output terminals of the two ping-pong operational amplifier structures are both connected to the gate of the NMOS transistor MN1. The drain of the NMOS transistor MN1 is connected to the input terminal of the switch S4. The source of the NMOS transistor MN1 is connected to the base of the triode Q2. The two ping-pong operational amplifier structures have the same structure.

4. The low-power high-precision temperature sensor circuit according to claim 3, characterized in that, The ping-pong operational amplifier structure includes NMOS transistors MN2 to MN15, PMOS transistors MP1 to MP6, and two capacitors Caz1. The gate of the PMOS transistor MP1 serves as the non-inverting input terminal, and the gate of the PMOS transistor MP2 serves as the inverting input terminal. The sources of the PMOS transistor MP1 and the PMOS transistor MP2 are connected together and connected to the drain of the PMOS transistor MP3. The gates of the PMOS transistor MP3 and the PMOS transistor MP4 are both used to access a control voltage V bp , the sources of the PMOS transistor MP3 and the PMOS transistor MP4 are both used to connect to a power supply, and the drain of the PMOS transistor MP4 serves as the output terminal; The drain of the PMOS transistor MP1 is respectively connected to the drains of the NMOS transistors MN2, MN6, MN8, MN12 and the source of the PMOS transistor MP5. The drain of the PMOS transistor MP2 is respectively connected to the drains of the NMOS transistors MN3, MN7, MN9, MN13 and the source of the PMOS transistor MP6. The source of the NMOS transistor MN12 is respectively connected to the drain of the NMOS transistor MN14 and the source of the NMOS transistor MN13. The source of the NMOS transistor MN14 is connected to the gate of the NMOS transistor MN15. The drain of the NMOS transistor MN15 is connected to the drain of the PMOS transistor MP4. The source of the NMOS transistor MN15 is grounded. The gate of the NMOS transistor MN12 is used to access a control voltage , and the gate of the NMOS transistor MN13 is used to access a control voltage of the reverse voltage. The gate of the NMOS transistor MN14 is used to access a control voltage ; The gate of the NMOS transistor MN2 is used to connect to a control voltage reverse voltage, and the gate of the NMOS transistor MN3 is used to connect to a control voltage , the sources of the NMOS transistor MN2 and the NMOS transistor MN3 are connected and connected to the gate of the NMOS transistor MN4, the gates of the NMOS transistor MN4 and the NMOS transistor MN5 are connected, the sources of the NMOS transistor MN4 and the NMOS transistor MN5 are both grounded, the drain of the NMOS transistor MN4 is connected to the drain of the PMOS transistor MP5, the drain of the NMOS transistor MN5 is connected to the drain of the PMOS transistor MP6, and the gates of the PMOS transistor MP5, the PMOS transistor MP6, the NMOS transistor MN6 and the NMOS transistor MN7 are all used to connect to a control voltage V bn ; The gates of the NMOS transistor MN8 and the NMOS transistor MN9 are both used to access a control voltage The reverse voltage of, the source of the NMOS transistor MN8 is respectively connected to the gate of the NMOS transistor MN10 and one end of the capacitor Caz1, the source of the NMOS transistor MN9 is respectively connected to the gate of the NMOS transistor MN11 and the other end of the capacitor Caz1, the other ends of the two capacitors Caz1 are both grounded, the sources of the NMOS transistor MN10 and the NMOS transistor MN11 are both grounded, the drain of the NMOS transistor MN10 is connected to the source of the NMOS transistor MN6, and the drain of the NMOS transistor MN11 is connected to the source of the NMOS transistor MN7.

5. The low-power high-precision temperature sensor circuit according to claim 4, wherein The IVBE generation circuit includes a second current source, a triode Q3, a chopper CR2, PMOS transistors MP7 to MP12, switches S8 to S11, a capacitor Ch1, a capacitor Ch2, a resistor R6, and two ping-pong operational amplifier structures with offset automatic zero adjustment. The input terminal of the second current source is used to connect to a power supply. The output terminal of the second current source is connected to the emitter of the triode Q3. The collector and base of the triode Q3 are both grounded. The non-inverting input terminals of two ping-pong operational amplifier structures are both connected to the output terminal of the second current source through the chopper CR2. The inverting input terminals of the two ping-pong operational amplifier structures are both connected to one end of the resistor R6 through the chopper CR2. The other end of the resistor R6 is grounded. The control terminal of the chopper CR2 is used to access a control voltage ; The drains of the PMOS transistor MP7 and the PMOS transistor MP8 are both connected to one end of the resistor R6, and the gate of the PMOS transistor MP7 is used to access a control voltage , and the gate of the PMOS transistor MP8 is used to access a control voltage of the reverse voltage. The source of the PMOS transistor MP7 is respectively connected to the drain of the PMOS transistor MP11 and the input end of the switch S11. The source of the PMOS transistor MP8 is respectively connected to the drain of the PMOS transistor MP12 and the input end of the switch S10. The output ends of the switch S10 and the switch S11 are connected to each other as the output end of the IVBE generation circuit; The gates of the PMOS transistor MP11 and the PMOS transistor MP12 are both used to access the control voltage V bp , the source of the PMOS transistor MP11 is connected to the drain of the PMOS transistor MP9, the source of the PMOS transistor MP12 is connected to the drain of the PMOS transistor MP10, the sources of the PMOS transistor MP9 and the PMOS transistor MP10 are both used to connect to the power supply, the gate of the PMOS transistor MP9 is respectively connected to the output terminal of the switch S9 and one end of the capacitor Ch2, the gate of the PMOS transistor MP10 is respectively connected to the output terminal of the switch S8 and one end of the capacitor Ch1, and the other ends of the capacitor Ch1 and the capacitor Ch2 are both grounded; The input ends of the switch S8 are respectively connected to the output ends of two ping-pong operational amplifier structures, the input ends of the switch S9 are respectively connected to the output ends of two ping-pong operational amplifier structures, and the control ends of the switch S8 and the switch S11 are both used for accessing a control voltage , and the control ends of the switch S9 and the switch S10 are both used for accessing a control voltage of the reverse voltage.

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