Microinstruction analysis method and device, equipment and storage medium

Abstract

The invention provides a microinstruction analysis method and device, equipment and a storage medium. The method comprises the steps of obtaining a currently executed target microinstruction; converting the target microinstruction into a binary system; according to the query function, segmenting a binary target microinstruction to obtain a plurality of sub microinstructions; and according to the query function, sequentially analyzing the plurality of sub micro-instructions to obtain the meaning of the target micro-instruction, and displaying the target micro-instruction and the meaning of the target micro-instruction.

Description

Technical Field

[0001] The present invention relates to the technical field of flash memory controllers, and in particular to a microinstruction parsing method, device, equipment and storage medium. Background Art

[0002] With the development of NAND storage technology, the capacity and reading speed of NAND memory are constantly improving, and the corresponding control is becoming more and more complex. The control of NAND memory involves multiple instructions and complex timing, and the interconnection between NAND storage particles and computers, servers and other devices needs to be realized through SSD (Solid State Drive) flash memory controller. Although NAND memory is based on a common interface protocol, there are large differences in control timing between NAND memory from different manufacturers and different models.

[0003] Using hardware to control different types of NAND memories is not conducive to the universal adaptability of the chip. Therefore, the NAND control module in most NAND control chips adopts a software-configurable method. This method not only improves adaptability, but also meets the timing and functional requirements of different NAND memories. However, since the NAND control module requires high performance, it cannot rely entirely on CPU control. In order to achieve diverse timing requirements and functions, the NAND control module is usually completed through microinstructions.

[0004] When designing SSD control chips, debugging of NAND modules is an important step. During the debugging process, it is usually necessary to debug and optimize according to the executed microinstructions. The interpretation of the relevant meanings of microinstructions is particularly important in debugging. Since microinstructions have many bits and complex meanings in reality, debugging through manual analysis is not only inefficient but also prone to errors.

[0005] Therefore, in view of the shortcomings of the prior art solutions, the present invention provides a microinstruction parsing method to assist debugging to improve efficiency and accuracy. Summary of the invention

[0006] Based on this, it is necessary to provide a microinstruction parsing method, device, equipment and storage medium to address the above technical problems.

[0007] On the one hand, a microinstruction parsing method is provided, the method comprising: obtaining a currently executed target microinstruction; converting the target microinstruction into binary; segmenting the binary target microinstruction according to a query function to obtain a plurality of sub-microinstructions; parsing the plurality of sub-microinstructions in turn according to the query function to obtain the meaning of the target microinstruction, and displaying the target microinstruction and the meaning of the target microinstruction.

[0008] Optionally, before obtaining the currently executed target microinstruction, the method also includes: receiving a test excitation signal sent by a user; determining the microinstructions corresponding to the test excitation signal based on the test excitation signal, and executing the microinstructions in sequence, wherein the test excitation signal corresponds to at least one microinstruction.

[0009] Optionally, determining the microinstructions corresponding to the test excitation signal based on the test excitation signal and executing the microinstructions in sequence includes: sequentially acquiring the microinstructions corresponding to the test excitation signal from a first memory, wherein all microinstructions are stored in the first memory; sequentially storing the acquired microinstructions corresponding to the test excitation signal into a second memory; and sequentially outputting the executed microinstructions from the second memory.

[0010] Optionally, obtaining the currently executed target microinstruction includes: obtaining the target microinstruction output from the second memory; and storing the target microinstruction and the current time in a target file.

[0011] Optionally, the method further includes: acquiring a standard microinstruction parsing document, converting the standard microinstruction parsing document into a target document in a preset format; and encapsulating the target document into a query function.

[0012] Optionally, obtaining a standard microinstruction parsing document includes: obtaining a preset microinstruction parsing document, wherein the microinstruction parsing document includes a bit field index, a field name, a conditional bit index, conditional data and a bit description; determining whether the format of the microinstruction parsing document conforms to a preset template; if so, filling the microinstruction parsing document with a standard microinstruction parsing document.

[0013] Optionally, according to the query function, the multiple sub-microinstructions are parsed in sequence to obtain the meaning of the target microinstruction, including: according to the first bit field index in the query function, obtaining the first sub-microinstruction corresponding to the first bit field index in the binary target microinstruction; traversing the query function to determine the number of first bit descriptions corresponding to the first sub-microinstruction; when the query function includes a first bit description, determining the first bit description corresponding to the first sub-microinstruction, and obtaining the second sub-microinstruction corresponding to the second bit field index in the binary target microinstruction; when the query function includes multiple first bit descriptions, determining the conditional bit index associated with the first sub-microinstruction in the query function; obtaining the conditional sub-microinstruction corresponding to the conditional bit index in the binary target microinstruction, matching the conditional sub-microinstruction with the conditional data in the query function, determining the first bit description corresponding to the first sub-microinstruction, and obtaining the second sub-microinstruction corresponding to the second bit field index in the binary target microinstruction; determining the meaning of the target microinstruction according to each sub-microinstruction corresponding to the binary target microinstruction and the bit descriptions corresponding to each sub-microinstruction.

[0014] On the other hand, a microinstruction parsing device is provided, which includes: an acquisition module for acquiring a currently executed target microinstruction; a conversion module for converting the target microinstruction into binary; a segmentation module for segmenting the binary target microinstruction according to a query function to obtain a plurality of sub-microinstructions; and a parsing module for parsing the plurality of sub-microinstructions in turn according to the query function to obtain the meaning of the target microinstruction and display the target microinstruction and the meaning of the target microinstruction.

[0015] On the other hand, a computer device is provided, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the following steps when executing the computer program: obtaining a target microinstruction currently being executed; converting the target microinstruction into binary; segmenting the binary target microinstruction according to a query function to obtain a plurality of sub-microinstructions; parsing the plurality of sub-microinstructions in turn according to the query function to obtain a meaning of the target microinstruction, and displaying the target microinstruction and the meaning of the target microinstruction.

[0016] On the other hand, a computer-readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, the following steps are implemented: obtaining the target microinstruction currently being executed; converting the target microinstruction into binary; according to a query function, segmenting the binary target microinstruction to obtain a plurality of sub-microinstructions; according to the query function, parsing the plurality of sub-microinstructions in turn to obtain the meaning of the target microinstruction, and displaying the target microinstruction and the meaning of the target microinstruction.

[0017] The above-mentioned microinstruction parsing method, device, equipment and storage medium, the method includes: obtaining the currently executed target microinstruction; converting the target microinstruction into binary; according to the query function, dividing the binary target microinstruction to obtain multiple sub-microinstructions; according to the query function, parsing the multiple sub-microinstructions in turn to obtain the meaning of the target microinstruction, and displaying the target microinstruction and the meaning of the target microinstruction; in this way, by automatically capturing and parsing microinstructions, the time and workload of users manually analyzing microinstructions are significantly reduced, thereby improving design efficiency; the automated analysis method reduces human intervention, reduces the possibility of human errors, and ensures the accuracy and consistency of microinstruction analysis. At the same time, through a graphical user interface, the parsed microinstructions and timing diagrams are intuitively displayed to the user, facilitating user understanding and debugging. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 An application environment diagram of a microinstruction parsing method in one embodiment;

[0019] Figure 2 A schematic diagram of a flow chart of a microinstruction parsing method in one embodiment;

[0020] Figure 3 A schematic diagram of a parsing process of a microinstruction parsing method in one embodiment;

[0021] Figure 4 A schematic diagram of a debugging structure of a microinstruction parsing method in one embodiment;

[0022] Figure 5 A schematic diagram of the overall structure of a microinstruction parsing method in one embodiment;

[0023] Figure 6 is a structural block diagram of a microinstruction parsing device in one embodiment;

[0024] Figure 7 FIG. 4 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0025] In order to make the purpose, technical solutions and advantages of this application clearer, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0026] It should be understood that in the description of the present application, unless the context clearly requires otherwise, words such as "include", "comprises", and the like throughout the specification should be interpreted as including rather than being exclusive or exhaustive; that is, as including but not limited to.

[0027] It should also be understood that the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In addition, in the description of this application, unless otherwise specified, "plurality" means two or more.

[0028] It should be noted that the terms "S1", "S2", etc. are only used for the purpose of describing the steps, and do not specifically refer to the order or sequence, nor are they used to limit the present application. They are only for the convenience of describing the method of the present application, and cannot be understood as indicating the order of the steps. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in this field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection required by the present application.

[0029] The microinstruction parsing method provided in this application can be applied to Figure 1 In the application environment shown, the terminal 102 communicates with the server 104 through a network. The terminal 102 may be, but is not limited to, various personal computers, laptops, smart phones, tablet computers, and portable wearable devices, and the server 104 may be implemented as an independent server or a server cluster consisting of multiple servers.

[0030] In one embodiment, Figure 2 As shown, a microinstruction parsing method is provided, comprising the following steps:

[0031] S201: Get the target microinstruction currently being executed.

[0032] Here, microinstructions are several tiny instructions that can be processed by the architecture processing unit obtained by decomposing instructions.

[0033] Specifically, the currently executed target microinstruction is captured and displayed to the user.

[0034] S202: Convert the target microinstruction into binary.

[0035] Exemplarily, assuming that the target microinstruction is “0xe400120000”, the target microinstruction is converted into binary to obtain “00000000000000000100001110000010001001111010000000”.

[0036] S203: According to the query function, the binary target microinstruction is segmented to obtain a plurality of sub-microinstructions.

[0037] Here, the query function includes a reference to the segmentation of microinstructions based on bits.

[0038] Specifically, the binary target microinstruction is segmented according to the bit positions to obtain sub-microinstructions of different bit positions, for example, 0-15 are the first sub-microinstruction, and 16-18 are the second sub-microinstruction.

[0039] S204: According to the query function, the plurality of sub-microinstructions are parsed in sequence to obtain the meaning of the target microinstruction, and the target microinstruction and the meaning of the target microinstruction are displayed.

[0040] Here, the query function includes all the meanings of the sub-microinstructions. By searching the sub-microinstruction meaning corresponding to each sub-microinstruction in the query function, the meaning of the target microinstruction is obtained, and the meaning of the target microinstruction is displayed to the user.

[0041] It should be noted that the automatic microinstruction analysis method based on the automated process not only solves the problem of difficult microinstruction analysis in the design and debugging of the NAND Flash control module, but also significantly improves the design efficiency, accuracy and intuitiveness, providing strong support for the design of SSD main control chips. At the same time, through the graphical user interface, the parsed microinstructions and timing diagrams are intuitively displayed to users, which is convenient for users to understand and debug.

[0042] In some specific implementations, before obtaining the currently executed target microinstruction, the method further includes:

[0043] Receive a test stimulus signal sent by a user;

[0044] According to the test excitation signal, a microinstruction corresponding to the test excitation signal is determined, and the microinstructions are executed in sequence, wherein the test excitation signal corresponds to at least one microinstruction.

[0045] Here, test stimulus signals are used to evaluate system performance, response characteristics, and stability.

[0046] Specifically, according to the test excitation signal, the microinstruction address included in the test excitation signal is determined, the microinstruction is determined according to the microinstruction address, and each microinstruction is executed in sequence.

[0047] In some specific implementations, determining the microinstructions corresponding to the test excitation signal according to the test excitation signal, and sequentially executing the microinstructions includes:

[0048] Sequentially acquiring microinstructions corresponding to the test excitation signal from a first memory, wherein the first memory stores all microinstructions;

[0049] storing the acquired microinstructions corresponding to the test excitation signals into a second memory in sequence;

[0050] The executed microinstructions are output sequentially from the second memory.

[0051] Here, the first memory is used to store all microinstructions, and the second memory is used to store microinstructions to be executed, and the microinstructions stored in the second memory will be executed in sequence. The first memory and the second memory can be SRAM or other memories.

[0052] Specifically, the microinstructions are captured from the first memory, stored in the second memory, and then the microinstructions in the second memory are output in sequence according to the storage order.

[0053] In one embodiment, after the microinstructions are captured from the first memory, the microinstructions are parsed to determine whether the microinstructions are jump microinstructions. If so, the microinstructions are jumped to the corresponding microinstruction address to read new microinstructions, and the new microinstructions are stored in the second memory.

[0054] In some specific implementations, obtaining the currently executed target microinstruction includes:

[0055] Obtaining a target microinstruction output from the second memory;

[0056] The target microinstructions and the current time are stored in the target file.

[0057] Here, multiple target microinstructions and read times are stored in the target file to generate a read log.

[0058] Specifically, each microinstruction output from the second memory is read, each microinstruction and the reading time are recorded, and a reading log is generated. The reading log may be as follows:

[0059] 136807304ps"0000010000040",\

[0060] 136808416ps"0000010000190",\

[0061] 136809528ps"000e400080000",\

[0062] 136810640ps"000f400010000",\

[0063] 136811752ps"000b4005900ff",\

[0064] 136812864ps"000f4005900ff",\

[0065] 136813976ps"000e403ff0000",\

[0066] ===========

[0067] 136821760ps"0000110000199",\

[0068] 157527200ps"0000010000040",\

[0069] 157528312ps"0000010000190",\

[0070] 157529424ps"000e400080000",\

[0071] 157530536ps"000f400010000",\

[0072] ===========

[0073] The left side of each line of log is the read time, and the right side is the microinstruction. For example, in the first line of log, 136807304ps is the read time, and "0000010000040" is the microinstruction.

[0074] In one embodiment, the currently executed microinstruction may also be obtained from the first memory.

[0075] In one embodiment, after a specific condition is triggered, such as a user requesting execution after ten seconds, the target microinstruction will be stored in DRAM. Since the data will disappear after the DRAM loses power, the firmware can store the microinstruction in NAND as needed.

[0076] In this way, microinstructions for debugging are automatically captured and stored, and the captured microinstructions are saved in a file for subsequent reading.

[0077] In some embodiments, the method further comprises:

[0078] Obtaining a standard microinstruction parsing document, and converting the standard microinstruction parsing document into a target document in a preset format;

[0079] The target document is encapsulated as a query function.

[0080] Here, the full meaning of the microinstructions is stored in the standard microinstruction parsing document.

[0081] Among them, the standard microinstruction parsing document can be in a first format, such as Excel, etc., and the target document can be in a second format, such as DataFrame, etc.

[0082] Specifically, to convert a document into a DataFrame, you can define a class, implement the initialization method in the class to create a DataFrame, and provide methods such as obtaining specific cell values, row data, and column data to encapsulate the two-dimensional DataFrame into a query function.

[0083] In this way, the meaning indicated by the corresponding bits of the microinstructions can be easily queried. Encapsulation makes the operation of DataFrame more modular and easy to reuse, making it easier to call and process in other functions.

[0084] In some specific implementations, obtaining a standard microinstruction parsing document includes:

[0085] Obtaining a preset microinstruction parsing document, wherein the microinstruction parsing document includes a bit field index, a field name, a conditional bit index, conditional data, and a bit description;

[0086] Determining whether the format of the microinstruction parsed document conforms to a preset template;

[0087] If it is in compliance, the microinstruction parsing document is filled as a standard microinstruction parsing document.

[0088] Here, the preset microinstruction parsing document includes but is not limited to the name, operation code, function description, execution steps, etc. of each microinstruction. The preset microinstruction parsing document may include all data or part of the data.

[0089] Among them, since the meaning of the sub-microinstructions of certain bits is determined by other bits, it is necessary to set the conditional bit index.

[0090] Specifically, judging whether the format of the microinstruction parsed document conforms to the preset template may include verifying whether the document contains all required columns, checking whether any required data is missing, confirming whether the data type is correct, etc. If required information is missing or the format is wrong, an error reminder is returned to the user. If the detection passes, it is judged whether there is data missing in the microinstruction parsed document. If so, the missing content in the microinstruction parsed document is automatically filled in.

[0091] Specifically, the preset microinstruction parsing document may include Bit Field Index, Field Name, Condition bit index, Condition data, and Bit Description. Exemplarily, the preset microinstruction parsing document may be as shown in Table 1:

[0092]

[0093]

[0094] Table 1

[0095] Among them, 15:0 represents the sub-microinstruction of the 0th to 15th bits of the microinstruction, and the corresponding field name is DATA. The meaning of the sub-microinstruction of the 0th to 15th bits is related to the sub-microinstruction of the 27th and 28th bits. The value of the sub-microinstruction of the 27th and 28th bits is obtained. When the value of the sub-microinstruction of the 27th and 28th bits is 00, the bit description of the sub-microinstruction of the 0th to 15th bits is Data is to be placed on DQ bus. (Data is placed on the DQ bus). When the value of the sub-microinstruction of the 27th and 28th bits is 01, the bit description of the sub-microinstruction of the 0th to 15th bits is Data is a pointer to another sequence memory entry (Data is a pointer to another sequence memory entry).

[0096] The standard microinstruction parsing document can be shown in Table 2:

[0097]

[0098] Table 2

[0099] When it is detected that the table in Table 1 meets the preset template requirements, Table 2 is filled, and the corresponding bit field index and field name are filled in with reference to other rows according to the conditional bit index, conditional data and bit description.

[0100] In this way, through automatic filling, a complete standard microinstruction parsing document is obtained, making the microinstruction parsing process faster and more correct.

[0101] In some specific implementations, the step of sequentially parsing the plurality of sub-microinstructions according to the query function to obtain the meaning of the target microinstruction includes:

[0102] According to the first bit field index in the query function, obtaining a first sub-microinstruction corresponding to the first bit field index in the binary target microinstruction;

[0103] Traversing the query function to determine the number of first bit descriptions corresponding to the first sub-microinstruction;

[0104] When the query function includes a first bit description, determining the first bit description corresponding to the first sub-microinstruction, and obtaining a second sub-microinstruction corresponding to a second bit field index in the binary target microinstruction;

[0105] When the query function includes a plurality of first bit descriptions, determining a conditional bit index associated with the first sub-microinstruction in the query function;

[0106] Obtain a conditional sub-microinstruction corresponding to the conditional bit index in the binary target microinstruction, match the conditional sub-microinstruction with the conditional data in the query function, determine a first bit description corresponding to the first sub-microinstruction, and obtain a second sub-microinstruction corresponding to a second bit field index in the binary target microinstruction;

[0107] The meaning of the target microinstruction is determined according to each sub-microinstruction corresponding to the binary target microinstruction and the bit description corresponding to each sub-microinstruction.

[0108] Here, the first bit field index, the second bit field index, etc. are obtained by the user performing bit segmentation on the binary microinstructions.

[0109] In one embodiment, in order to facilitate viewing and analysis, the microinstructions are segmented by the Last signal, which is generated according to the corresponding bits in the microinstructions.

[0110] Specifically, the meaning of the target microinstructions can be as follows:

[0111]

[0112] In this way, the execution process of each microinstruction can be recorded and tracked, making it easier for designers to quickly locate the root cause of the problem during debugging; with detailed microinstruction execution logs and reports, designers can troubleshoot and optimize more effectively.

[0113] In some embodiments, the method further comprises:

[0114] Obtaining the execution result of the target microinstruction;

[0115] The execution result is compared with the meaning of the displayed target microinstruction to determine whether the meaning of the displayed target instruction is correct.

[0116] In this way, the parsing result of the target microinstruction is verified by the actual execution result of the target microinstruction.

[0117] In one embodiment, Figure 3 Schematic diagram of the analysis process in the embodiment of the present application, such as Figure 3 As shown, the parsing process in the present application includes: obtaining an instruction set Excel document, extracting the document, specifically including: analyzing the document and extracting the document; converting the document format, specifically including: instruction information storage and instruction information interface, inputting instruction translation (i.e., microinstruction parsing); receiving test stimulus, obtaining microinstructions through the DUT module, monitoring with the Monitor module, inputting microinstructions into instruction translation, and obtaining instruction (i.e., microinstruction) information output through the instruction translation module.

[0118] Specifically, the instruction set Excel document is used to describe the instruction set of the NAND control module. This document is a unified reference standard for design analysis in the system, including chip (module) designers, verifiers, etc. This document is a standard for instruction translation (i.e. microinstruction parsing) and instruction (i.e. microinstruction) generation.

[0119] Specifically, document extraction includes document analysis and document extraction. Document analysis includes: using Python to write a program to read and analyze Excel documents. The program uses pandas and openpyxl libraries to read Excel documents. The program first checks the compliance of the Excel document, verifies whether the document contains all required columns, checks whether there is any missing data, and confirms whether the data type is correct. If the document complies with the specified format, subsequent operations are performed; if relevant information is missing or the format is wrong, Error is returned to remind the user. The process of extracting documents includes: if the document format is compliant, the content in the document is filled.

[0120] Specifically, format conversion includes instruction information storage and instruction information interface. Format conversion mainly includes: the process of storing Excel into DataFrame. Storing data in DF form is more convenient for subsequent use. The instruction information interface mainly includes: encapsulated query function. Encapsulating the two-dimensional DataFrame into a query function is achieved by defining a class. The class includes methods to conveniently access and operate the data in the DataFrame. By implementing the initialization method in the class to create a DataFrame and providing methods such as obtaining specific cell values, row data, and column data, the meaning indicated by the corresponding bit of the instruction can be easily queried.

[0121] Specifically, the main function of the verification platform is to send test stimuli to the DUT. The DUT is the designed NAND control module (microinstruction and instruction control part), which includes SRAM1 for storing microinstructions and instructions (for storing all microinstructions) and SRAM2 for executing instructions (for storing microinstructions to be executed). The Monitor is responsible for capturing the microinstructions of SRAM1 and SRAM2 in the DUT and storing the captured microinstructions in a file.

[0122] Specifically, the instruction translation module translates the microinstruction information captured by the Monitor through the instruction information interface to obtain data that facilitates chip designers to intuitively analyze problems.

[0123] In one embodiment, Figure 4 Schematic diagram of the debugging structure in the embodiment of the present application, such as Figure 4 As shown, the debugging structure in the present application includes: other modules, a microinstruction control module and a microinstruction debugging module, and the microinstruction control module specifically includes: an instruction controller, SRAM1, SRAM2 and a microinstruction decoding module.

[0124] Specifically, other modules include a NAND flash controller and an external interconnection structure, which is used to implement control of the NAND flash control module.

[0125] Specifically, SRAM1 is mainly used to store all microinstructions, and needs to be controlled by firmware through other modules to store all microinstructions in SRAM1.

[0126] Specifically, SRAM2 is used to store microinstructions to be executed. The microinstructions stored in the SRAM will be executed sequentially, and will be specifically interpreted by the microinstruction and instruction decoding module according to the specific meaning of the microinstructions.

[0127] Specifically, the instruction controller is mainly used to control the specific execution process of microinstructions. It is responsible for fetching microinstructions from SRAM1 and storing the fetched microinstructions in SRAM2. During the instruction fetching process, it is also necessary to complete the parsing of the fetched microinstructions. For example, if the microinstruction is a jump microinstruction, it is necessary to read the new microinstruction from the corresponding address and then store it in SRAM2.

[0128] Specifically, the instruction debugging module is responsible for storing the microinstructions accessed by SRAM1 or SRAM2 in a specific time according to the relevant signals of the instruction controller, and the firmware can read the stored microinstructions as needed. After triggering specific conditions, the instruction debugging module will store the microinstructions in DRAM. Since the data will disappear after the DRAM power is off, the firmware can store it in NAND as needed. During the debugging process, the instruction log (i.e., microinstruction log) stored in NAND or DRAM can be analyzed to facilitate designers to analyze and find problems.

[0129] In one embodiment, Figure 5 Schematic diagram of the overall structure of the embodiment of the present application, such as Figure 5 As shown, the overall structure in this application includes: a verification platform, an on-chip debugging log, and an instruction analysis module.

[0130] Specifically, the log captured by the verification simulation platform or the log generated by the on-chip debugging module is sent to the instruction analysis module to form a visual instruction analysis result.

[0131] It should be understood that although Figure 1-5 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 1-5 At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.

[0132] In one embodiment, Figure 6As shown, a microinstruction parsing device is provided, and the device includes: an acquisition module 601, used to obtain the target microinstruction currently being executed; a conversion module 602, used to convert the target microinstruction into binary; a segmentation module 603, used to segment the binary target microinstruction according to a query function to obtain a plurality of sub-microinstructions; a parsing module 604, used to parse the plurality of sub-microinstructions in turn according to the query function to obtain the meaning of the target microinstruction, and display the target microinstruction and the meaning of the target microinstruction.

[0133] As a preferred implementation, in an embodiment of the present application, the device also includes: an excitation module, which is specifically used to: receive a test excitation signal sent by a user; determine the microinstructions corresponding to the test excitation signal based on the test excitation signal, and execute the microinstructions in sequence, wherein the test excitation signal corresponds to at least one microinstruction.

[0134] As a preferred implementation mode, in the embodiment of the present application, the excitation module is also specifically used to: sequentially obtain the microinstructions corresponding to the test excitation signal from the first memory, wherein the first memory stores all the microinstructions; sequentially store the obtained microinstructions corresponding to the test excitation signal into the second memory; and sequentially output the executed microinstructions from the second memory.

[0135] As a preferred implementation, in the embodiment of the present application, the acquisition module 601 is specifically used to: acquire the target microinstructions output from the second memory; and store the target microinstructions and the current time in a target file.

[0136] As a preferred implementation, in an embodiment of the present application, the device also includes: an encapsulation module, which is specifically used to: obtain a standard microinstruction parsing document, convert the standard microinstruction parsing document into a target document in a preset format; and encapsulate the target document into a query function.

[0137] As a preferred implementation mode, in an embodiment of the present application, the encapsulation module is specifically used for: obtaining a standard microinstruction parsing document, including: obtaining a preset microinstruction parsing document, wherein the microinstruction parsing document includes a bit field index, a field name, a conditional bit index, conditional data and a bit description; determining whether the format of the microinstruction parsing document conforms to a preset template; if so, filling the microinstruction parsing document with a standard microinstruction parsing document.

[0138] As a preferred implementation, in an embodiment of the present application, the parsing module 604 is specifically used to: obtain the first sub-microinstruction corresponding to the first bit field index in the binary target microinstruction according to the first bit field index in the query function; traverse the query function to determine the number of first bit descriptions corresponding to the first sub-microinstruction; when the query function includes a first bit description, determine the first bit description corresponding to the first sub-microinstruction, and obtain the second sub-microinstruction corresponding to the second bit field index in the binary target microinstruction; when the query function includes multiple first bit descriptions, determine the conditional bit index associated with the first sub-microinstruction in the query function; obtain the conditional sub-microinstruction corresponding to the conditional bit index in the binary target microinstruction, match the conditional sub-microinstruction with the conditional data in the query function, determine the first bit description corresponding to the first sub-microinstruction, and obtain the second sub-microinstruction corresponding to the second bit field index in the binary target microinstruction; determine the meaning of the target microinstruction according to each sub-microinstruction corresponding to the binary target microinstruction and the bit description corresponding to each sub-microinstruction.

[0139] The specific definition of the microinstruction parsing device can be found in the above-mentioned definition of the microinstruction parsing method, which will not be repeated here. Each module in the above-mentioned microinstruction parsing device can be implemented in whole or in part by software, hardware and a combination thereof. Each of the above-mentioned modules can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory in the computer device in the form of software, so that the processor can call and execute the operations corresponding to each of the above modules.

[0140] In one embodiment, a computer device is provided. The computer device may be a terminal, and its internal structure diagram may be as follows: Figure 7 As shown. The computer device includes a processor, a memory, a network interface, a display screen and an input device connected through a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, a microinstruction parsing method is implemented. The display screen of the computer device can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer device can be a touch layer covered on the display screen, or a key, trackball or touchpad set on the computer device housing, or an external keyboard, touchpad or mouse, etc.

[0141] Those skilled in the art will understand that Figure 7 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0142] In one embodiment, a computer device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the following steps are implemented: S1: obtaining the currently executed target microinstruction; S2: converting the target microinstruction into binary; S3: dividing the binary target microinstruction according to a query function to obtain a plurality of sub-microinstructions; S4: parsing the plurality of sub-microinstructions in turn according to the query function to obtain the meaning of the target microinstruction, and displaying the target microinstruction and the meaning of the target microinstruction.

[0143] In one embodiment, when the processor executes the computer program, the following steps are also implemented: receiving a test excitation signal sent by a user; determining the microinstructions corresponding to the test excitation signal based on the test excitation signal, and executing the microinstructions in sequence, wherein the test excitation signal corresponds to at least one microinstruction.

[0144] In one embodiment, when the processor executes the computer program, the following steps are also implemented: sequentially obtaining microinstructions corresponding to the test excitation signal from a first memory, wherein the first memory stores all microinstructions; sequentially storing the obtained microinstructions corresponding to the test excitation signal into a second memory; and sequentially outputting the executed microinstructions from the second memory.

[0145] In one embodiment, when the processor executes the computer program, the following steps are also implemented: obtaining the target microinstructions output from the second memory; and storing the target microinstructions and the current time in a target file.

[0146] In one embodiment, when the processor executes the computer program, the following steps are also implemented: obtaining a standard microinstruction parsing document, converting the standard microinstruction parsing document into a target document in a preset format; and encapsulating the target document into a query function.

[0147] In one embodiment, when the processor executes the computer program, the following steps are also implemented: obtaining a preset microinstruction parsing document, wherein the microinstruction parsing document includes a bit field index, a field name, a conditional bit index, conditional data, and a bit description; determining whether the format of the microinstruction parsing document conforms to a preset template; if so, filling the microinstruction parsing document with a standard microinstruction parsing document.

[0148] In one embodiment, when the processor executes the computer program, the following steps are also implemented: according to the first bit field index in the query function, the first sub-microinstruction corresponding to the first bit field index in the binary target microinstruction is obtained; the query function is traversed to determine the number of first bit descriptions corresponding to the first sub-microinstruction; when the query function includes a first bit description, the first bit description corresponding to the first sub-microinstruction is determined, and the second sub-microinstruction corresponding to the second bit field index in the binary target microinstruction is obtained; when the query function includes multiple first bit descriptions, the conditional bit index associated with the first sub-microinstruction in the query function is determined; the conditional sub-microinstruction corresponding to the conditional bit index in the binary target microinstruction is obtained, the conditional sub-microinstruction is matched with the conditional data in the query function, the first bit description corresponding to the first sub-microinstruction is determined, and the second sub-microinstruction corresponding to the second bit field index in the binary target microinstruction is obtained; the meaning of the target microinstruction is determined according to each sub-microinstruction corresponding to the binary target microinstruction and the bit description corresponding to each sub-microinstruction.

[0149] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the following steps are implemented: S1: obtaining the currently executed target microinstruction; S2: converting the target microinstruction into binary; S3: according to a query function, dividing the binary target microinstruction to obtain a plurality of sub-microinstructions; S4: according to the query function, parsing the plurality of sub-microinstructions in turn to obtain the meaning of the target microinstruction, and displaying the target microinstruction and the meaning of the target microinstruction.

[0150] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: receiving a test excitation signal sent by a user; determining the microinstructions corresponding to the test excitation signal based on the test excitation signal, and executing the microinstructions in sequence, wherein the test excitation signal corresponds to at least one microinstruction.

[0151] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: sequentially obtaining microinstructions corresponding to the test excitation signal from a first memory, wherein all microinstructions are stored in the first memory; sequentially storing the obtained microinstructions corresponding to the test excitation signal into a second memory; and sequentially outputting the executed microinstructions from the second memory.

[0152] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: obtaining the target microinstructions output from the second memory; and storing the target microinstructions and the current time in a target file.

[0153] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: obtaining a standard microinstruction parsing document, converting the standard microinstruction parsing document into a target document in a preset format; and encapsulating the target document into a query function.

[0154] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: obtaining a preset microinstruction parsing document, wherein the microinstruction parsing document includes a bit field index, a field name, a conditional bit index, conditional data, and a bit description; determining whether the format of the microinstruction parsing document conforms to a preset template; if so, filling the microinstruction parsing document with a standard microinstruction parsing document.

[0155] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: according to the first bit field index in the query function, the first sub-microinstruction corresponding to the first bit field index in the binary target microinstruction is obtained; the query function is traversed to determine the number of first bit descriptions corresponding to the first sub-microinstruction; when the query function includes a first bit description, the first bit description corresponding to the first sub-microinstruction is determined, and the second sub-microinstruction corresponding to the second bit field index in the binary target microinstruction is obtained; when the query function includes multiple first bit descriptions, the conditional bit index associated with the first sub-microinstruction in the query function is determined; the conditional sub-microinstruction corresponding to the conditional bit index in the binary target microinstruction is obtained, the conditional sub-microinstruction is matched with the conditional data in the query function, the first bit description corresponding to the first sub-microinstruction is determined, and the second sub-microinstruction corresponding to the second bit field index in the binary target microinstruction is obtained; the meaning of the target microinstruction is determined according to each sub-microinstruction corresponding to the binary target microinstruction and the bit description corresponding to each sub-microinstruction.

[0156] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

[0157] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0158] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A microinstruction parsing method, characterized in that: The method comprises: Get the currently executed target microinstruction; Converting the target microinstructions into binary; According to the query function, the binary target microinstruction is segmented to obtain a plurality of sub-microinstructions; According to the query function, the multiple sub-microinstructions are parsed in sequence to obtain the meaning of the target microinstruction, and the target microinstruction and the meaning of the target microinstruction are displayed.

2. The microinstruction parsing method according to claim 1, characterized in that: Before obtaining the currently executed target microinstruction, the method further includes: Receive a test stimulus signal sent by a user; According to the test excitation signal, a microinstruction corresponding to the test excitation signal is determined, and the microinstructions are executed in sequence, wherein the test excitation signal corresponds to at least one microinstruction.

3. The microinstruction parsing method according to claim 2, characterized in that: The step of determining the microinstructions corresponding to the test excitation signal according to the test excitation signal, and executing the microinstructions in sequence, comprises: Sequentially acquiring microinstructions corresponding to the test excitation signal from a first memory, wherein the first memory stores all microinstructions; storing the acquired microinstructions corresponding to the test excitation signals into a second memory in sequence; The executed microinstructions are output sequentially from the second memory.

4. The microinstruction parsing method according to claim 3, characterized in that: The step of obtaining the currently executed target microinstruction includes: Obtaining a target microinstruction output from the second memory; The target microinstructions and the current time are stored in the target file.

5. The microinstruction parsing method according to claim 1, characterized in that: The method further comprises: Obtaining a standard microinstruction parsing document, and converting the standard microinstruction parsing document into a target document in a preset format; The target document is encapsulated as a query function.

6. The microinstruction parsing method according to claim 5, characterized in that: The step of obtaining a standard microinstruction parsing document includes: Obtaining a preset microinstruction parsing document, wherein the microinstruction parsing document includes a bit field index, a field name, a conditional bit index, conditional data, and a bit description; Determining whether the format of the microinstruction parsed document conforms to a preset template; If it is in compliance, the microinstruction parsing document is filled as a standard microinstruction parsing document.

7. The microinstruction parsing method according to claim 1, characterized in that: The step of sequentially parsing the plurality of sub-microinstructions according to the query function to obtain the meaning of the target microinstruction includes: According to the first bit field index in the query function, obtaining a first sub-microinstruction corresponding to the first bit field index in the binary target microinstruction; Traversing the query function to determine the number of first bit descriptions corresponding to the first sub-microinstruction; When the query function includes a first bit description, determining the first bit description corresponding to the first sub-microinstruction, and obtaining a second sub-microinstruction corresponding to a second bit field index in the binary target microinstruction; When the query function includes a plurality of first bit descriptions, determining a conditional bit index associated with the first sub-microinstruction in the query function; Obtain a conditional sub-microinstruction corresponding to the conditional bit index in the binary target microinstruction, match the conditional sub-microinstruction with the conditional data in the query function, determine a first bit description corresponding to the first sub-microinstruction, and obtain a second sub-microinstruction corresponding to a second bit field index in the binary target microinstruction; The meaning of the target microinstruction is determined according to each sub-microinstruction corresponding to the binary target microinstruction and the bit description corresponding to each sub-microinstruction.

8. A microinstruction parsing device, characterized in that: The device comprises: An acquisition module is used to acquire the target microinstruction currently being executed; A conversion module, used for converting the target microinstruction into binary; A segmentation module, used for segmenting the binary target microinstruction according to the query function to obtain a plurality of sub-microinstructions; The parsing module is used to parse the multiple sub-microinstructions in sequence according to the query function, obtain the meaning of the target microinstruction, and display the target microinstruction and the meaning of the target microinstruction.

9. A computer device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

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