An encoding and decoding method and related apparatus for non-volatile memory.

Abstract

This application provides an encoding and decoding method and related apparatus for non-volatile memory. The encoding method uses the least common multiple of the primitive polynomial of the primitive elements of a finite field and its inverse polynomial as the generator polynomial. The decoding method includes: reading the received sequence and calculating its initial syndrome; if the initial syndrome is not 0, an error exists; adjusting the value of each bit data to obtain two flipped syndromes: a first flipped syndrome and a second flipped syndrome; if both the first and second flipped syndromes are 0, or the product of the first and second flipped syndromes is 1, then it is determined that the bit will be flipped. This application can decode bit by bit in parallel according to the flipped syndrome. Compared with the BCH code error correction scheme, the generator polynomial is different, avoiding high-order power operations of finite field elements during decoding, reducing decoding complexity and decoding delay, and meeting the requirements of fast decoding.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and in particular to an encoding and decoding method and related apparatus for non-volatile memory. Background Technology

[0002] With the development of semiconductor-related technologies, the types of semiconductor devices are also rapidly evolving, including low-cost, high-density non-volatile memories. To improve the storage density of non-volatile memories, multi-level storage technology can be employed. While multi-level storage technology can increase storage density and reduce costs, it reduces the distance between adjacent memory cells, leading to a decrease in the reliability of non-volatile memories. At 45nm technology, the bit error rate of non-volatile memories exceeds 10^65. -6 However, in practical applications, non-volatile memory needs to meet a bit error rate of less than 10. -12 To reduce the bit error rate, error-correcting codes can be introduced during the encoding and decoding processes of non-volatile memory to improve its reliability.

[0003] Error-correcting codes add redundant bits to the original information sequence, enabling the receiver to detect or correct errors that occur during transmission. Cyclic error-correcting codes (BCH codes) are an important class of codes with excellent algebraic structures and efficient encoding algorithms, which can improve the reliability of non-volatile memories. However, the decoding process using BCH codes is relatively complex and time-consuming, failing to meet the requirements for fast decoding. Summary of the Invention

[0004] In view of this, the purpose of this application is to provide an encoding method and a decoding method for non-volatile memory, as well as related apparatus, which can reduce decoding complexity, reduce decoding time, and meet the needs of fast decoding.

[0005] To achieve the above objectives, this application provides the following technical solution:

[0006] This application provides a decoding method for non-volatile memory, characterized by comprising:

[0007] The received sequence is read from a non-volatile memory to obtain the initial syndrome of the received sequence, which includes n binary bits of data; the non-volatile memory stores coded codewords, and during data storage or reading, the coded codewords and erroneous data are superimposed to form the received sequence; the information bits are encoded using a generator polynomial to obtain the coded codewords, which are composed of the primitive polynomials of the primitive elements of the finite field and their inverse polynomials;

[0008] Determine whether the value of the initial syndrome is 0. If the value of the initial syndrome is not 0, then there is an error in the received sequence.

[0009] Adjust the value of the i-th bit data respectively, 0≤i≤n-1; obtain two flipped synods of the received sequence after adjusting the value of the i-th bit data, determine whether the value of the flipped synods is 0, if the value of the flipped synods is 0, then determine to flip the i-th bit data to obtain the flipped bit;

[0010] If the values ​​of the flipped syntactic expressions are not all 0, determine whether the product of the two flipped syntactic expressions is 1. If the product of the two flipped syntactic expressions is 1, then determine to flip the i-th bit data to obtain the flipped bit.

[0011] The received sequence is decoded based on the flipped bits.

[0012] Optionally, the method further includes:

[0013] Simultaneously, the steps of adjusting the value of the i-th bit data are performed, and the results of adjusting the values ​​of different bits data, whether the flipped syndrome is 0, and whether the product of the two flipped syndromes is 1 are obtained.

[0014] Optionally, the two flipping accompaniments include a first flipping accompaniment and a second flipping accompaniment;

[0015] If the values ​​of the flipped syndromes are not all 0, determine whether the product of the two flipped syndromes is 1. If the product of the two flipped syndromes is 1, then determine to flip the i-th bit of data, which includes:

[0016] If the values ​​of the first flipped syntactic and the second flipped syntactic are not both 0, determine whether the product of the first flipped syntactic and the second flipped syntactic is 1. If the product of the first flipped syntactic and the second flipped syntactic is 1, then determine to flip the i-th bit data.

[0017] Optionally, the initial adjoint is based on the coefficients of the polynomial corresponding to the received sequence over the finite field GF(2). m The length of the received sequence is n = 2, obtained by XORing the elements in the sequence. m -1.

[0018] Optionally, the generating polynomial is the least common multiple of the primitive polynomial and the inverse polynomial, and the primitive polynomial is the finite field GF(2). m The minimal polynomial of the primitive elements in the equation, wherein the inverse polynomial is the inverse polynomial of the minimal polynomial.

[0019] This application provides an encoding method for non-volatile memory, including:

[0020] Obtain information bits;

[0021] The length of the check bit and the finite field GF(2) are configured according to the length of the information bits and the error correction number threshold. m The primitive polynomials and inverse polynomials of the primitive elements in the equation, wherein the length of the check bit is 2m;

[0022] The information bits are encoded using a generator polynomial to obtain an encoded codeword, which is then stored in a non-volatile memory. The generator polynomial is composed of the primitive polynomial and the inverse polynomial.

[0023] Optionally, the generating polynomial is the least common multiple of the primitive polynomial and the inverse polynomial, and the primitive polynomial is the finite field GF(2). m The minimal polynomial of the primitive elements in the equation, wherein the inverse polynomial is the inverse polynomial of the minimal polynomial.

[0024] Optionally, m is an odd number greater than or equal to 5.

[0025] This application provides a decoding device for non-volatile memory, comprising:

[0026] A read unit is used to read a received sequence from a non-volatile memory and obtain the initial syndrome of the received sequence, wherein the received sequence includes n binary bits of data; the non-volatile memory stores encoded codewords, and during data storage or reading, the encoded codewords and erroneous data are superimposed to form the received sequence; the encoded codewords are obtained by encoding the information bits using a generator polynomial, wherein the generator polynomial is composed of the primitive polynomial of the primitive element of the finite field and its inverse polynomial;

[0027] The first determining unit is used to determine whether the value of the initial syndrome is 0; if the value of the initial syndrome is not 0, then there is an error in the received sequence.

[0028] The second determining unit is used to adjust the value of the i-th bit data respectively, 0≤i≤n-1; obtain two flipped synods of the received sequence after adjusting the value of the i-th bit data, determine whether the value of the flipped synods is 0, and if the value of the flipped synods is 0, then determine to flip the i-th bit data to obtain the flipped bit.

[0029] The third determining unit is used to determine whether the product of the two flipped companions is 1 if the values ​​of the flipped companions are not all 0; if the product of the two flipped companions is 1, then determine to flip the i-th bit data to obtain the flipped bit.

[0030] A decoding unit is used to decode the received sequence based on the flipped bits.

[0031] This application provides an encoding device for non-volatile memory, comprising:

[0032] Acquisition unit, used to acquire information bits;

[0033] Configuration unit, configured to configure the length of the check bit and the finite field GF(2) according to the length of the information bit and the error correction number threshold. m The primitive polynomials and inverse polynomials of the primitive elements in the equation, wherein the length of the check bit is 2m;

[0034] The encoding unit is used to encode the information bits using a generator polynomial to obtain an encoded codeword, and to store the encoded codeword in a non-volatile memory; the generator polynomial is composed of the primitive polynomial and the inverse polynomial.

[0035] This application provides a decoding method for non-volatile memory, comprising: reading a received sequence from the non-volatile memory; obtaining an initial synod of the received sequence, wherein the received sequence includes n binary bits of data; determining whether the value of the initial synod is 0; if the value of the initial synod is not 0, then the received sequence contains an error. In other words, the method uses the initial synod to determine whether the received sequence read from the non-volatile memory contains an error. When it is determined that the received sequence contains an error, a decoding and error correction process begins. The value of the i-th bit of data is adjusted, 0 ≤ i ≤ n-1, and two flipped synods of the received sequence after adjusting the value of the i-th bit of data are obtained. The method determines whether the values ​​of the flipped synods are both 0. If the values ​​of the flipped synods are both 0, then the i-th bit of data is flipped to obtain a flipped bit. If the values ​​of the flipped synods are not both 0, the method determines whether the product of the two flipped synods is 1. If the product of the two flipped synods is 1, then the i-th bit of data is flipped to obtain a flipped bit. In other words, by adjusting the value of the bit data at each position in the received sequence, the value of the flipped syndrome after adjustment is used to determine whether an error occurred during the reading of the bit data at that position. If an error occurs, the received sequence is decoded based on the flipped bit. Furthermore, the encoded codeword is obtained by encoding the information bits using a generator polynomial. The generator polynomial consists of primitive polynomials of finite field primitives and their inverses. The encoded codeword is stored in non-volatile memory. During data storage or retrieval, the encoded codeword and the erroneous data are superimposed to form the received sequence.

[0036] Therefore, this application can perform bit-by-bit decoding based on the flipped syntactic, avoiding the complex calculations required for decoding using BCH codes, greatly reducing the decoding difficulty, improving decoding efficiency, and reducing decoding time. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 A flowchart illustrating an encoding method for non-volatile memory provided in an embodiment of this application is shown.

[0039] Figure 2 A circuit structure diagram of a system coding method provided in an embodiment of this application is shown;

[0040] Figure 3 A flowchart illustrating a decoding method for a non-volatile memory provided in an embodiment of this application is shown.

[0041] Figure 4 This illustration shows a schematic diagram of the decision process of a decoding method provided in an embodiment of this application;

[0042] Figure 5 This illustration shows a schematic diagram of codeword error probability provided in an embodiment of this application;

[0043] Figure 6 This illustration shows a data format diagram of (26,16) code provided in an embodiment of this application;

[0044] Figure 7 This illustration shows a schematic diagram of the structure of an encoding device for a non-volatile memory according to an embodiment of this application;

[0045] Figure 8 A schematic diagram of the structure of a decoding device for a non-volatile memory provided in an embodiment of this application is shown. Detailed Implementation

[0046] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the specific embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0047] Many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0048] With the development of semiconductor-related technologies, the types of semiconductor devices are also rapidly evolving, including low-cost, high-density non-volatile memories. To improve the storage density of non-volatile memories, multi-level storage technology can be employed. While multi-level storage technology can increase storage density and reduce costs, it reduces the distance between adjacent memory cells, leading to a decrease in the reliability of non-volatile memories. At 45nm technology, the bit error rate of non-volatile memories exceeds 10^65. -6 However, in practical applications, non-volatile memory needs to meet a bit error rate of less than 10. -12 To reduce the bit error rate, error-correcting codes can be introduced during the encoding and decoding processes of non-volatile memory to improve its reliability.

[0049] Error-correcting codes add redundant bits to the original information sequence, enabling the receiver to detect or correct errors that occur during transmission. Cyclic error-correcting codes (BCH codes) are an important class of codes with excellent algebraic structures and efficient encoding algorithms. Binary BCH codes that correct two errors are a subclass of BCH codes. They meet the reliability requirements of non-volatile memories and can achieve high code rates with short to medium code lengths, thus finding widespread application in high data rate scenarios such as storage.

[0050] BCH codes can be used to improve the reliability of non-volatile memories. Although encoding with BCH codes is relatively simple, the decoding process is quite complex. Decoding requires calculating high powers of each element in a finite field, resulting in high decoding complexity and long decoding time, which cannot meet the requirements for fast decoding.

[0051] Based on this, this application provides a decoding method for non-volatile memory, comprising: reading a received sequence from the non-volatile memory; obtaining an initial synod of the received sequence, wherein the received sequence includes n binary bits of data; determining whether the value of the initial synod is 0; if the value of the initial synod is not 0, then the received sequence contains an error. That is, the method uses the initial synod to determine whether the received sequence read from the non-volatile memory contains an error. When it is determined that the read received sequence contains an error, a decoding and error correction process begins, adjusting the value of the i-th bit of data (0≤i≤n-1), obtaining two flipped synods of the received sequence after adjusting the value of the i-th bit of data, and determining whether the values ​​of the flipped synods are both 0. If the values ​​of the flipped synods are both 0, then it is determined that the i-th bit of data will be flipped to obtain a flipped bit. If the values ​​of the flipped synods are not both 0, it is determined whether the product of the two flipped synods is 1. If the product of the two flipped synods is 1, then it is determined that the i-th bit of data will be flipped to obtain a flipped bit. In other words, by adjusting the value of the bit data at each position in the received sequence, the value of the flipped syndrome after adjustment is used to determine whether an error occurred during the reading of the bit data at that position. If an error occurs, the received sequence is decoded based on the flipped bit. Furthermore, the encoded codeword is obtained by encoding the information bits using a generator polynomial. The generator polynomial consists of primitive polynomials of finite field primitives and inverse polynomials. The encoded codeword is stored in non-volatile memory. During data storage or reading, the encoded codeword and the erroneous data are superimposed to form the received sequence. Therefore, this application can perform bit-by-bit decoding based on the flipped syndrome, avoiding the complex calculations required for decoding using BCH codes, greatly reducing decoding difficulty, improving decoding efficiency, and reducing decoding time.

[0052] To better understand the technical solution and effects of this application, the specific embodiments will be described in detail below with reference to the accompanying drawings.

[0053] refer to Figure 1 The diagram shows a flowchart of an encoding method for a non-volatile memory provided in an embodiment of this application. To reduce decoding complexity and decoding time, an error-correcting code encoding scheme needs to be constructed to achieve the same error-correcting capability as the BCH code that corrects two errors, while avoiding high-order calculations of finite field elements during BCH decoding, thus reducing decoding complexity.

[0054] As an example, non-volatile memory can be NOR flash memory.

[0055] The encoding method for non-volatile memory provided in this application includes the following steps:

[0056] S101, Obtain information bits.

[0057] In the embodiments of this application, information bits can also be referred to as information digits. An information digit can include multiple binary bit data. Information digits can be expressed using polynomials. Information digits can be encoded, and the encoded codewords can be stored in non-volatile memory.

[0058] As an example, the information bits can be z = (z0, z1, ..., z k-1 The corresponding polynomial is z(x) = z0 + z1x + ... + z k-1 x k-1 .

[0059] S102, Configure the length of the check bits and the finite field GF(2) according to the length of the information bits and the error correction number threshold. m The primitive polynomials and inverse polynomials of primitive elements in ).

[0060] In the embodiments of this application, the length of the check bit can be pre-configured so that the information bits can be encoded using a generator polynomial later. Specifically, the length of the check bit can be configured according to the length of the information bits and the error correction number threshold. The error correction number threshold refers to the error correction capability of the error correction code provided in the embodiments of this application. For example, the error correction capability of an error correction code that corrects 2 errors is 2.

[0061] The appropriate finite field GF(2) can be determined based on the information bit length and the error correction threshold. m By using this method, we can determine that the length of the check bit is t×m, where t is the error correction threshold.

[0062] As an example, if the error correction number threshold is 2, then the length of the check bit can be determined to be 2m.

[0063] In the embodiments of this application, a generator polynomial can be used to encode the information bits. Specifically, the value of m can be determined based on the length of the information bits and the error-correcting capability of the error-correcting code, thereby obtaining the finite field GF(2). m The primitive polynomials and their inverses within the primitive elements of a given set can form a generator polynomial. In other words, the length of the information bits and the error-correcting capability of the error-correcting code are related to the generator polynomial used to encode the information bits.

[0064] In the embodiments of this application, information bits can be encoded using a generator polynomial to obtain encoded codewords. Both check bits and encoded codewords can be represented using polynomials.

[0065] As an example, the check digit can be s = (s0, s1, ... s 2m-1 The corresponding polynomial is s(x) = s0 + s1x + ... + s 2m-1 x 2m-1The encoded codeword can be c = (c0, c1, ..., c...). n-1 The corresponding polynomial is the codeword polynomial, which can be c(x) = c0 + c1x + ... + c n-1 x n-1 .

[0066] As an example, the codeword length after encoding using a generator polynomial is n=2. m -1, the information bit length is k = n - 2m, and the parity bit length is 2m. Here, m is an odd number greater than or equal to 5. As the value of m increases, the encoded codeword has a higher code rate. For example, when m = 9, the encoded codeword length is 511, and the code rate is 0.9648. The error-correcting code provided in this application embodiment has the same error-correcting capability and code rate as the BCH code that corrects two errors, and is also suitable for high data rate applications.

[0067] In the embodiments of this application, the generating polynomial is the least common multiple of the primitive polynomial and the inverse polynomial, wherein the primitive polynomial is the finite field GF(2 m The minimal polynomial of the primitive elements in is the inverse polynomial of the minimal polynomial; that is, the generating polynomial is composed of the primitive polynomial and its inverse polynomial. Assume α is a finite field GF(2). m If the primitive element is α, then the generating polynomial g(x) is α, α -1 The least common multiple of the smallest polynomials with roots can be expressed as g(x) = LCM{g1(x), g -1 (x)}, where g1(x) is the minimal polynomial of element α, i.e., the primitive polynomial, g -1 (x) is element α -1 The minimal polynomial of g, i.e. -1 (x) is a reverse polynomial, and LCM is the least common multiple of several polynomials.

[0068] S103, the information bits are encoded using a generator polynomial to obtain the encoded codeword, and the encoded codeword is stored in non-volatile memory.

[0069] In the embodiments of this application, after obtaining the generator polynomial, the information bits can be encoded using the generator polynomial to obtain the encoded codeword, and then the encoded codeword can be stored in non-volatile memory.

[0070] As an example, the polynomial for obtaining the encoded codeword can be expressed using the following formula: c(x) = s(x) + x 2m z(x) = s0 + s1x + ... + s 2m-1 x 2m-1 +z0x 2m +…+z k-1 xn-1 That is, [s,z] = c.

[0071] The specific encoding method using generator polynomials can be selected based on the actual situation. Encoding methods can include non-systematic encoding or systematic encoding. For non-systematic encoding, the codeword can be obtained through c(x) = z(x)g(x). For systematic encoding, there are two methods: one is through s(x) = x n-k The parity bit is obtained by converting z(x) to g(x), and the rightmost bit is set as the high-order bit. Then the codeword c(x) is obtained. Another method is to use h(x) = x n -1 / g(x) yields the check polynomial, and then the codeword polynomial c(x) = x n-k ·z(x), let the right side be the high bit, and then pass through Obtain the encoded codeword c(x), refer to Figure 2 As shown.

[0072] As can be seen from the above description, the encoding method for non-volatile memory provided in this application only requires encoding using a generator polynomial, which is simple. Furthermore, the generator polynomial avoids using the minimal polynomial with high-order elements, so there is no need to calculate the high-order power operation of the finite field elements during subsequent decoding, thus helping to reduce the complexity of decoding.

[0073] In the embodiments of this application, addition and multiplication are mod2 addition and mod2 multiplication, respectively.

[0074] refer to Figure 3 The diagram shown is a flowchart of a decoding method for non-volatile memory provided in an embodiment of this application. The method includes the following steps:

[0075] S201, Read the received sequence from the non-volatile memory and obtain the initial syndrome of the received sequence.

[0076] In the embodiments of this application, after storing the encoded codeword in non-volatile memory, the received sequence can be read from the non-volatile memory to determine whether there are any errors in the received sequence. If an error is found, decoding and error correction are performed. That is, during data storage or retrieval, the encoded codeword and the erroneous data are superimposed to form the received sequence. Specifically, the received sequence includes n binary bits of data, that is, the length of the received sequence is n=2. m -1.

[0077] The encoding method for non-volatile memory is described in an embodiment. The encoded codeword is obtained by encoding the information bits using a generator polynomial, where the generator polynomial is the finite field GF(2). mThe primitive polynomials of the primitive elements and their inverse polynomials constitute the generator polynomial. The generator polynomial is the least common multiple of the primitive and inverse polynomials, and the primitive polynomial is the finite field GF(2). m The minimal polynomial of the primitive elements in ) is the inverse polynomial of the minimal polynomial.

[0078] In the embodiments of this application, the non-volatile memory stores encoded codewords, and the encoded codewords combined with error data form the received sequence. Assuming r(x) is the received sequence polynomial corresponding to the received sequence read from the non-volatile memory, c(x) is the codeword polynomial corresponding to the encoded codeword stored in the non-volatile memory after encoding, and e(x) is the error polynomial, then r(x) = c(x) + e(x).

[0079] In the embodiments of this application, the presence of erroneous data in the received sequence can be determined by utilizing the syntactic expression of the received sequence.

[0080] Finite field GF(2) m Each element α in ) i Both can be represented as an m-dimensional vector, and the adjoint can be expressed using the element α. i The summation of vectors is also an m-dimensional vector, for example, the adjoint equation S1=r0+r1α. 1 +…+r n-1 α (n-1) Its vector representation is when r i When α = 1 (0 ≤ i ≤ n-1), the corresponding α i The vectors are added together. Correspondingly, the adjoint equation S... -i It is to use the element α in the finite field -i The corresponding vectors are added together. That is, the initial adjoint is based on the coefficients of the polynomial corresponding to the received sequence over the finite field GF(2). m The elements in the array are obtained by performing an XOR operation.

[0081] Based on the received sequence polynomial r(x) read from the non-volatile memory, the corresponding syndrome S1 = r(α) can be obtained. -1 =r(α) -1 ). Because r(α)=c(α)+e(α)=z(α)·g(α)+e(α),α,α -1 It is a root of g(x), that is, g(α) = g(α). -1 Since ) = 0, then S1 = r(α) = e(α). Similarly, we can obtain S -1 =r(α) -1 )=e(α -1 In other words, the presence of errors in the received sequence can be determined directly using the syndrome of the received sequence, thus achieving relatively simple error data identification.

[0082] Since the decoding method provided in this application has an error correction capability of t=2, it is only necessary to consider the case where there are at most 2 erroneous data:

[0083] (1) When there are no errors in the received sequence, i.e., e(x) = 0, then r(x) = c(x) and S1 = S -1 =0.

[0084] (2) When an error occurs in the received sequence, i.e., e(x) = x i (0≤i≤n-1), at this time S1=α i ,S -1 =α -i That is, S1·S -1 =1.

[0085] (3) When two errors occur in the received sequence, i.e., e(x) = x i +x j (0≤i≠j≤n-1), at this time we have S1=α i +α j ,S -1 =α -i +α -j S1·S -1 =α i-j +α j-i ≠1.

[0086] Therefore, when e(x) = 0, S1 = S -1 =0. When e(x) = x i When (0≤i≤n-1), S1·S -1 =1. When e(x) = x i +x j When (0≤i≠j≤n-1), S1·S -1 =α i-j +α j-i ≠1, S1≠S -1 ≠0. In other words, the value of the syndrome varies depending on the number of erroneous data points. This allows us to directly determine the presence of erroneous data based on the value of the syndrome and to perform error correction decoding based on the syndrome.

[0087] S202, determine whether the value of the initial syndrome is 0. If the value of the initial syndrome is not 0, then there is an error in the received sequence.

[0088] In the embodiments of this application, the syndrome of the received sequence can determine whether there is erroneous data. Therefore, the initial syndrome of the received sequence can be calculated by looking up a table, and whether there is an error in the received sequence can be confirmed based on whether the value of the initial syndrome is 0.

[0089] If the initial syndrome value is not 0, then there is an error in the received sequence, and the decoding and error correction process begins. If the initial syndrome value is 0, i.e., S1 = S... -1 If the value is 0, it is assumed that there are no errors in the received sequence, and decoding is terminated.

[0090] S203, adjust the value of the i-th bit data respectively, obtain two flipped syndromes of the received sequence after adjusting the value of the i-th bit data, determine whether the value of the flipped syndromes is 0, if the value of the flipped syndromes is 0, then determine to flip the i-th bit data to obtain the flipped bit, 0≤i≤n-1.

[0091] In the embodiments of this application, if it is determined that there is erroneous data in the received sequence based on the initial syndrome value not being 0, the value of the i-th bit data (0≤i≤n-1) can be adjusted to obtain two flipped syndromes of the received sequence after adjusting the value of the i-th bit data. It is then determined whether the values ​​of the flipped syndromes are both 0. If the values ​​of the flipped syndromes are both 0, it is determined that the i-th bit data is flipped to obtain the flipped bit. If the values ​​of the flipped syndromes are not both 0, it is determined that there is erroneous data in the received sequence after adjusting the value of the i-th bit data. Flipping the i-th bit data means adjusting the value of the binary bit data to the opposite value. For example, if the value of the i-th bit data is 0, flipping the value of the i-th bit data will adjust the value of the i-th bit data to 1.

[0092] In other words, when it is determined that there is erroneous data in the received sequence, the received sequence can be decoded step by step. By adjusting the value of one bit of data at a time, the flipped syndrome after adjusting the value of that bit of data can be obtained until the values ​​of all bits of data are adjusted. If there is only one erroneous data in the received sequence, the position of the erroneous data can be obtained by flipping the value of the syndrome.

[0093] Specifically, when a single erroneous data point appears in the received sequence, bit-by-bit decoding begins. Assuming the value of the i-th bit is adjusted, the adjusted error polynomial is e'(x) = e(x) + x. i The adjusted flipping formula is S 1,i =e'(α),S -1,i =e'(α) -1 If the i-th bit data is not the erroneous data, then e'(x) = x. i +x j Let j represent the position of the erroneous data in the received sequence, 0≤i≠j≤n-1, then we have S 1,i ·S -1,i ≠1. If the i-th bit of data is the erroneous data, then e'(x) = x i +x i =0, then S 1,i =S -1,i =0.

[0094] In practical applications, after adjusting the bit data at each position of the received sequence and obtaining the flipped syndrome, if the value of the flipped syndrome is 0, then set e. i =1, determining to flip the i-th bit data to obtain the flipped bit, so that subsequent operations can be directly based on e. i The flipped bits obtained by 1 are used for error correction decoding of the received sequence.

[0095] Since the received sequence includes multiple binary bits of data, the value of the i-th bit is adjusted by flipping the value of the i-th bit from 1 to 0, or from 0 to 1.

[0096] S204, if the values ​​of the flipped syntactic expressions are not all 0, determine whether the product of the two flipped syntactic expressions is 1. If the product of the two flipped syntactic expressions is 1, then determine to flip the i-th bit data to obtain the flipped bit.

[0097] In the embodiments of this application, when it is determined that there is erroneous data in the received sequence based on the initial syndrome, the value of one bit of data is adjusted each time, and the reverse syndrome after adjusting the value of that bit of data is obtained, until the values ​​of all bits of data are adjusted. If there are two erroneous data in the received sequence, even if one of the erroneous data is adjusted to correct data, the values ​​of the reverse syndromes are still not all 0. At this time, the product of the two reverse syndromes can be used to determine whether the number of erroneous data in the received sequence has decreased after adjusting the value of one bit of data, for example, from two to one, thereby determining whether the i-th bit of data should be reversed. Wherein, as long as any one of the reverse syndromes is not 0, it is considered that the values ​​of the reverse syndromes are still not all 0.

[0098] In other words, if the values ​​of the flipped synastry are not all 0, determine whether the product of the two flipped synastry is 1. If the product of the two flipped synastry is 1, then determine to flip the i-th bit data to obtain the flipped bit.

[0099] In embodiments of this application, the flipped synergy includes a first flipped synergy and a second flipped synergy. Therefore, if the values ​​of the flipped synergy are not all 0, determining whether the product of the two flipped synergies is 1 can be done by determining whether the product of the first flipped synergy and the second flipped synergy is 1. If the product of the first flipped synergy and the second flipped synergy is 1, then it is determined that the i-th bit data is flipped to obtain the flipped bit. The first flipped synergy and the second flipped synergy can each be S... 1.i =S1+α i ,S -1,i =S -1 +α -i, 0≤i≤n-1.

[0100] Specifically, when a two-bit error occurs in the received sequence, bit-by-bit decoding begins. If the i-th bit is not one of the erroneous bits, then e'(x) = x. i +x j +x l 0≤i≠j≠l≤n-1, assuming (l,j) represents the position of two erroneous data points in the received sequence, then S 1,i ·S -1,i ≠1. If the i-th bit is one of the erroneous bits, then e'(x) = x. i +x j +x i =x j Then S 1,i ·S -1,i =1.

[0101] In practical applications, after adjusting the bit data at each position of the received sequence and obtaining the flipped syndrome, if the value of the flipped syndrome is not 0, it means that there is erroneous data in the received sequence after adjusting the value of the i-th bit data. Then, it is determined whether the product of the first and second flipped syndromes is 1 to flip the bit data, thus obtaining the flipped bit. If S 1,i ·S -1,i =1, 0≤i≤n-1, then set e i =1 indicates that the i-th bit of data will be flipped to obtain the flipped bit; otherwise, set e. i =0, so we can directly use e later. i The flipped bits obtained by 1 are used for error correction decoding of the received sequence.

[0102] S205, decode the received sequence based on the flipped bits.

[0103] In the embodiments of this application, when reading the received sequence r(x) from the non-volatile memory, the initial syndrome S1,S is obtained. -1 If S1 = S -1 If the value is 0, no decoding is performed; otherwise, all bits of data in the range [0, n-1] are flipped and decoded to obtain the flipped syndrome S. 1,i ,S -1,i If S 1,i =S -1,i =0, then set e i =1, otherwise determine S 1,i ·S -1,i =1, if S 1,i ·S -1,i =1, then set e i =1, otherwise set e i=0, thus obtaining erroneous data and erroneous polynomials. Finally, the codewords after error correction of the received sequence are obtained. Decoded output. (Reference) Figure 5 As shown, by employing the encoding and decoding methods of this application embodiment, the error probability when reading data from the received sequence is greatly reduced.

[0104] In the embodiments of this application, since the value of each bit data is independently flipped, the decoding can be implemented in parallel. That is, the steps of adjusting the value of the i-th bit data can be performed simultaneously, while obtaining the results of whether the flipped syndromes are all 0 and whether the product of the two flipped syndromes is 1. For example, the steps of adjusting the value of the 0-th bit data, adjusting the value of the 1-th bit data, adjusting the value of the 2-th bit data, and so on, can be performed in parallel, which can greatly improve the decoding efficiency and reduce the decoding time.

[0105] Therefore, it can be seen that the embodiments of this application adopt g(x)=LCM{g1(x),g -1 (x)} is the generating polynomial, according to the adjoint S1=r(α),S -1 =r(α) -1 By using the relationship between the two fields to perform bit-by-bit decoding, it ensures effective correction of two errors, achieving the same error-correcting capability as BCH codes that correct two errors. This avoids the power operations required for finite field elements in BCH code decoding, reducing decoding complexity. Furthermore, because decoding can be implemented in parallel, it significantly improves decoding efficiency and reduces decoding time.

[0106] refer to Figure 4 The diagram shown illustrates the decoding steps. The decoding steps are as follows:

[0107] S301: Read the received sequence r(x) from the non-volatile memory.

[0108] S302: Obtain the initial syndrome S1,S of r(x). -1 .

[0109] S303: Determine if an error is found in the read-out received sequence by checking if the initial syndrome is 0. If the initial syndrome is 0, there is no error, and the decoding process exits; otherwise, an error has occurred, and the process proceeds to S304.

[0110] S304: via S 1,i ,S -1,i We determine if the i-th bit is incorrect by checking if all bits are 0. If S 1,i ,S -1,i If all bits are 0, and 0 ≤ i ≤ n-1, it indicates that the i-th bit is faulty, so set e. i =1, go to S306, otherwise go to S305.

[0111] S305: via S 1,i ·S -1,i We determine if the i-th bit is incorrect by checking if it is 1. If S 1,i ·S -1,i =1, 0≤i≤n-1, set e i =1, otherwise set e i =0.

[0112] S306: Obtaining an incorrect polynomial And typing Decode output.

[0113] As an example, the encoding and decoding methods provided in the embodiments of this application are further illustrated using the (31,21) code.

[0114] In the (31,21) code, 31 represents the length of the encoded codeword, n = 31 = 2. 5 -1 and 21 represent the length of the information bits, and 10 represents the length of the check bits, satisfying m ≥ 5 and being an odd number. Assume α is a finite field GF(2... 5 The primitive element of ) has a primitive polynomial of g1(x) = x 5 +x 2 +1, the vector representation is [1 0 0 1 0 1]. By reversing the vector, we can obtain the inverse polynomial, that is, the inverse polynomial vector representation is [1 0 1 0 0 1]. Then the inverse polynomial is g. -1 (x)=x 5 +x 3 +1, through g(x) = LCM{g1(x),g -1 From (x)}, we can obtain the generator polynomial of the (31,21) code as g(x)=x 10 +x 8 +x 7 +x 5 +x 3 +x 2 +1, the vector representation is [10 1 1 0 1 0 1 1 0 1].

[0115] The (31,21) code is encoded using a parity-check polynomial. First, the parity-check polynomial h(x) = x is obtained. 31 -1 / g(x), then according to Figure 2 The encoding is performed in the following manner: initially, sw1 is turned on and sw2 is turned off, filling the 21-bit information bit z into the shift register and outputting it simultaneously. Then, sw1 is turned off and sw2 is turned on, and the shift is repeated 10 times, obtaining one parity bit s each time. i Then output the encoded codeword c(x).

[0116] The decoding employs a bit-by-bit decoding method, flipping one bit of data at a time, and performing the flipping in parallel. Assuming r(x) is the received sequence polynomial and e(x) is the error polynomial, the initial syndrome S1 and S2 of r(x) are obtained using a lookup table. -1 First, based on x i mod g1(x)(0≤i≤n) yields the finite field GF(2 5 The vector representations of the elements in the equation are stored in a table. When obtaining the initial colligative equation, the corresponding element vectors are XORed, and S1 = r(α) = r0·α 0 +r1·α 1 +r2·α 2 +…+r 30 ·α 30 S -1 =r(α) -1 )=r0·α 0 +r1·α 30 +r2·α 29 +…+r 30 ·α 1 , r0,…,r 30 The coefficients of the r(x) receiver sequence polynomial, α 0 ,α 1 ,…,α 30 It is a finite field GF(2) 5 A vector of elements in r, when r i When α = 1 (0 ≤ i ≤ n-1), the product of α will be 1. i The vectors are added together.

[0117] Then, based on the values ​​of the initial and reversed adjoints, it is determined whether there is erroneous data, and if so, the number and location of the erroneous data.

[0118] (1) When there is no erroneous data, the initial syndrome S1 = S -1 =0, such as Figure 3 As shown in S303, exit decoding.

[0119] (2) When an erroneous data point occurs, assume the erroneous position is the 2nd position, i.e., e(x) = x. 2 In S303, S1 = α 2 ≠0, perform bit-by-bit decoding and error correction process. When the second bit of data is flipped, the syntactic equation S is flipped. 1,2 =α 2 +α 2 =0,S -1,2 =α -2 +α -2 =0 satisfies condition S in S304 1,2 =S -1,2=0, so e2=1. When flipping other bits of data, the syndrome S is flipped. 1,2 =α 2 +α i ,S -1,2 =α -2 +α -i It does not satisfy S304 1,i =S -1,i =0, and does not satisfy S in S305 1,i ·S -1,i =1, (0≤i≤n-1,i≠2) so e i =0. An incorrect polynomial is obtained. Encoding codeword

[0120] (3) When two erroneous data points occur, assume the error positions are in the 5th and 6th positions, i.e., e(x) = x 5 +x 6 In S303, S1 ≠ 0. During the bit-by-bit decoding and error correction process, regardless of which bit is flipped, the flipped syntactic S in S304 is not satisfied. 1,i =S -1,i =0 (0≤i≤31), when the 5th and 6th bits of data are flipped, S 1,5 =α 5 +α 6 +α 5 =α 6 ,S -1,5 =α -5 +α -6 +α -5 =α -6 Satisfying S305 1,5 ·S -1,5 =1, so e5 = 1, S 1,6 =α 5 +α 6 +α 6 =α 5 ,S -1,6 =α -5 +α -6 +α -6 =α -5 Satisfying S305 1,6 ·S -1,6 =1, e6=1. When other bits of data are flipped, S 1,j =α 5 +α 6 +α j ,S -1,j =α -5 +α -6 +α -j It does not satisfy S3041,j =S -1,j =0, and does not satisfy S in S305 1,j ·S -1,j =1, (0≤j≤n-1,j≠5,6) so e j =0. An incorrect polynomial is obtained. Encoding codeword

[0121] From the above, we obtain the encoded codewords. By retaining z'(x), we obtain the information bits.

[0122] (26,16) code is a shortened code, derived from (31,21) code. The rightmost bit is designated as the high-order bit. Zeros are added to the high-order bits until the length reaches 21. Encoding is performed using the (31,21) code encoding method. When obtaining the codeword, the added zeros in the high-order bits are removed to obtain the corresponding shortened codeword. The shortening process is described in [reference needed]. Figure 6 As shown:

[0123] S401 represents the information bits. S402 represents the sequence after adding zeros to the high-order bits of the information bits. S403 represents the codeword obtained by encoding the sequence after adding zeros. S404 represents the codeword after removing the high-order bits and adding zeros.

[0124] The decoding process is the same as that of (31,21) code. The 26-bit received sequence read from the non-volatile memory is decoded bit by bit, and the high bits do not need to be filled with zeros.

[0125] This application provides a decoding method for non-volatile memory, comprising: reading a received sequence from the non-volatile memory; obtaining an initial synod of the received sequence, wherein the received sequence includes n binary bits of data; determining whether the value of the initial synod is 0; if the value of the initial synod is not 0, then the received sequence contains an error. In other words, the method uses the initial synod to determine whether the received sequence read from the non-volatile memory contains an error, which is simple and intuitive. When it is determined that the received sequence contains an error, the decoding and error correction process begins. The value of the i-th bit of data is adjusted, and two flipped synods of the received sequence after adjusting the value of the i-th bit of data are obtained. The values ​​of the flipped synods are determined to be 0. If the values ​​of the flipped synods are both 0, then the i-th bit of data is flipped to obtain a flipped bit; 0 ≤ i ≤ n-1. If the values ​​of the flipped synods are not both 0, the product of the two flipped synods is determined to be 1. If the product of the two flipped synods is 1, then the i-th bit of data is flipped to obtain a flipped bit; 0 ≤ i ≤ n-1. In other words, by adjusting the value of the bit data at each position in the received sequence, the value of the flipped syndrome after adjustment is used to determine whether an error occurred during the reading of the bit data at that position. If an error occurs, the received sequence is decoded based on the flipped bit. Furthermore, the encoded codeword is obtained by encoding the information bits using a generator polynomial. The generator polynomial consists of primitive polynomials of finite field primitives and inverse polynomials. The encoded codeword is stored in non-volatile memory. During data storage or reading, the encoded codeword and the erroneous data are superimposed to form the received sequence. Therefore, this application can perform bit-by-bit decoding based on the flipped syndrome, avoiding the complex calculations required for decoding using BCH codes, greatly reducing decoding difficulty, improving decoding efficiency, and reducing decoding time.

[0126] Based on the encoding method for non-volatile memory provided in the above embodiments, this application also provides an encoding apparatus for non-volatile memory, referencing... Figure 7 The diagram shown is a structural schematic of an encoding device for non-volatile memory provided in an embodiment of this application. The encoding device 100 for non-volatile memory provided in this embodiment includes:

[0127] Acquisition unit 110 is used to acquire information bits;

[0128] Configuration unit 120 is configured to configure the length of the check bit and the finite field GF(2) according to the length of the information bit and the error correction number threshold. m The primitive polynomials and inverse polynomials of the primitive elements in the equation, wherein the length of the check bit is 2m;

[0129] The encoding unit 130 is used to encode the information bits using a generator polynomial to obtain an encoded codeword, and to store the encoded codeword in a non-volatile memory; the generator polynomial is composed of the primitive polynomial and the inverse polynomial.

[0130] Optionally, the generating polynomial is the least common multiple of the primitive polynomial and the inverse polynomial, and the primitive polynomial is the finite field GF(2). m The minimal polynomial of the primitive elements in the equation, wherein the inverse polynomial is the inverse polynomial of the minimal polynomial.

[0131] Optionally, m is an odd number greater than or equal to 5.

[0132] Based on the decoding method for non-volatile memory provided in the above embodiments, this application also provides a decoding apparatus for non-volatile memory, referencing... Figure 8 The diagram shown is a structural schematic of a decoding device for a non-volatile memory provided in an embodiment of this application. The decoding device 200 for a non-volatile memory provided in this embodiment includes:

[0133] The reading unit 210 is used to read the received sequence from the non-volatile memory and obtain the initial syndrome of the received sequence, wherein the received sequence includes n binary bits of data; the non-volatile memory stores encoded codewords, and during data storage or reading, the encoded codewords and erroneous data are superimposed to form the received sequence; the information bits are encoded using a generator polynomial to obtain the encoded codewords, wherein the generator polynomial is composed of the primitive polynomial of the primitive element of the finite field and its inverse polynomial;

[0134] The first determining unit 220 is used to determine whether the value of the initial syndrome is 0. If the value of the initial syndrome is not 0, then there is an error in the received sequence.

[0135] The second determining unit 230 is used to adjust the value of the i-th bit data respectively, obtain two flipped syndromes of the received sequence after adjusting the value of the i-th bit data, determine whether the value of the flipped syndromes is 0, and if the value of the flipped syndromes is 0, then determine to flip the i-th bit data to obtain the flipped bit; 0≤i≤n-1;

[0136] The third determining unit 240 is used to determine whether the product of the two flipped companions is 1 if the values ​​of the flipped companions are not all 0; if the product of the two flipped companions is 1, then determine to flip the i-th bit data to obtain the flipped bit.

[0137] Decoding unit 250 is used to decode the received sequence according to the flipped bits.

[0138] Optionally, the apparatus further includes a parallel execution unit, the parallel execution unit being configured to:

[0139] The steps of adjusting the value of the i-th bit data are performed in parallel and simultaneously, and the results of adjusting the values ​​of different bits data, whether the flipped syndrome is 0, and whether the product of the two flipped syndromes is 1 are obtained.

[0140] Optionally, the two flipping accompaniments include a first flipping accompaniment and a second flipping accompaniment;

[0141] The third determining unit 240 is used for:

[0142] If the values ​​of the first flipped syntactic and the second flipped syntactic are not both 0, determine whether the product of the first flipped syntactic and the second flipped syntactic is 1. If the product of the first flipped syntactic and the second flipped syntactic is 1, then determine to flip the i-th bit data to obtain the flipped bit.

[0143] Optionally, the initial adjoint is based on the coefficients of the polynomial corresponding to the received sequence over the finite field GF(2). m The length of the received sequence is n = 2, obtained by XORing the elements in the sequence. m -1.

[0144] Optionally, the generating polynomial is the least common multiple of the primitive polynomial and the inverse polynomial, and the primitive polynomial is the finite field GF(2). m The minimal polynomial of the primitive elements in the equation, wherein the inverse polynomial is the inverse polynomial of the minimal polynomial.

[0145] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the apparatus embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0146] The above description is merely a preferred embodiment of this application. Although this application has disclosed preferred embodiments above, it is not intended to limit this application. Any person skilled in the art can make many possible variations and modifications to the technical solutions of this application using the methods and techniques disclosed above, or modify them into equivalent embodiments with equivalent changes, without departing from the scope of the technical solutions of this application. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of this application without departing from the content of the technical solutions of this application shall still fall within the protection scope of the technical solutions of this application.

Claims

1. A decoding method for non-volatile memory, characterized in that, include: Read the received sequence from non-volatile memory to obtain the initial syndrome of the received sequence, the received sequence comprising n binary bits of data; The non-volatile memory stores coded codewords. During data storage or retrieval, the coded codewords and erroneous data are superimposed to form a received sequence. The information bits are encoded using a generator polynomial to obtain the coded codewords. The generator polynomial consists of the primitive polynomial of the primitive element of the finite field and its inverse polynomial. Determine whether the value of the initial syndrome is 0. If the value of the initial syndrome is not 0, then there is an error in the received sequence. Adjust the value of the i-th bit data respectively, 0≤i≤n-1; obtain two flipped syndromes of the received sequence after adjusting the value of the i-th bit data, and determine whether the value of the flipped syndromes is 0. If the value of the flipped syndromes is 0, then determine to flip the i-th bit data to obtain the flipped bit. If the values ​​of the flipped syntactic expressions are not all 0, determine whether the product of the two flipped syntactic expressions is 1. If the product of the two flipped syntactic expressions is 1, then determine to flip the i-th bit data to obtain the flipped bit. The received sequence is decoded based on the flipped bits.

2. The method according to claim 1, characterized in that, The method further includes: The steps of adjusting the value of the i-th bit data are performed in parallel; at the same time, the results of adjusting the values ​​of different bits data, whether the flipped syndrome is 0, and whether the product of the two flipped syndromes is 1 are obtained.

3. The method according to claim 1, characterized in that, The two aforementioned flipping accompaniment schemes include a first flipping accompaniment scheme and a second flipping accompaniment scheme; If the values ​​of the flipped syndromes are not all 0, determine whether the product of the two flipped syndromes is 1. If the product of the two flipped syndromes is 1, then determine to flip the i-th bit of data. If the values ​​of the first flipped syntactic and the second flipped syntactic are not both 0, determine whether the product of the first flipped syntactic and the second flipped syntactic is 1. If the product of the first flipped syntactic and the second flipped syntactic is 1, then determine to flip the i-th bit of data.

4. The method according to claim 1, characterized in that, The initial syndrome is based on the coefficients of the polynomial corresponding to the received sequence over the finite field GF(2). m The elements in the sequence are XORed to obtain the length of the received sequence, which is n=2. m -1.

5. The method according to claim 1, characterized in that, The generating polynomial is the least common multiple of the primitive polynomial and the inverse polynomial, and the primitive polynomial is the finite field GF(2). m The minimal polynomial of the primitive elements in the equation, wherein the inverse polynomial is the inverse polynomial of the minimal polynomial.

6. An encoding method for non-volatile memory, characterized in that, include: Obtain information bits; The length of the check bit and the finite field GF(2) are configured according to the length of the information bits and the error correction number threshold. m The primitive polynomials and inverse polynomials of the primitive elements in the equation, wherein the length of the check bit is 2m; The information bits are encoded using a generator polynomial to obtain an encoded codeword, and the encoded codeword is stored in a non-volatile memory. The generating polynomial is composed of the primitive polynomial and the inverse polynomial; The generating polynomial is the least common multiple of the primitive polynomial and the inverse polynomial, and the primitive polynomial is the finite field GF(2). m The minimal polynomial of the primitive elements in the equation, wherein the inverse polynomial is the inverse polynomial of the minimal polynomial.

7. The method according to claim 6, characterized in that, m is an odd number greater than or equal to 5.

8. A decoding device for a non-volatile memory, characterized in that, include: A read unit is used to read a received sequence from a non-volatile memory and obtain the initial syndrome of the received sequence, wherein the received sequence includes n binary bits of data; the non-volatile memory stores encoded codewords, and during data storage or reading, the encoded codewords and erroneous data are superimposed to form the received sequence; the encoded codewords are obtained by encoding the information bits using a generator polynomial, wherein the generator polynomial is composed of the primitive polynomial of the primitive element of the finite field and its inverse polynomial; The first determining unit is used to determine whether the value of the initial syndrome is 0; if the value of the initial syndrome is not 0, then there is an error in the received sequence. The second determining unit is used to adjust the value of the i-th bit data respectively, obtain two flipped syndromes of the received sequence after adjusting the value of the i-th bit data, determine whether the value of the flipped syndromes is 0, and if the value of the flipped syndromes is 0, then determine to flip the i-th bit data to obtain the flipped bit, 0≤i≤n-1. The third determining unit is used to determine whether the product of the two flipped companions is 1 if the values ​​of the flipped companions are not all 0. If the product of the two flipped companions is 1, then it is determined to flip the i-th bit data to obtain the flipped bit, 0≤i≤n-1. A decoding unit is used to decode the received sequence based on the flipped bits.

9. An encoding device for a non-volatile memory, characterized in that, include: Acquisition unit, used to acquire information bits; Configuration unit, configured to configure the length of the check bit and the finite field GF(2) according to the length of the information bit and the error correction number threshold. m The primitive polynomials and inverse polynomials of the primitive elements in the equation, wherein the length of the check bit is 2m; The encoding unit is used to encode the information bits using a generator polynomial to obtain an encoded codeword, and to store the encoded codeword in a non-volatile memory. The generating polynomial is composed of the primitive polynomial and the inverse polynomial; the generating polynomial is the least common multiple of the primitive polynomial and the inverse polynomial, and the primitive polynomial is the finite field GF(2). m The minimal polynomial of the primitive elements in the equation, wherein the inverse polynomial is the inverse polynomial of the minimal polynomial.

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