NVMe equipment controller debugging method and device, equipment, medium and product

Abstract

The invention discloses an NVMe equipment controller debugging method and device, equipment, a medium and a product, relates to the technical field of storage, is applied to a target NVMe equipment controller, and comprises the steps that a controller memory buffer area is started in the initialization process, and attribute parameters of the controller memory buffer area are set, so that when a target host enumerates the target NVMe equipment controller through a bus, the controller memory buffer area is started; mapping a controller memory buffer area to a memory space of the target host to obtain a virtual mapping address in the memory space; obtaining a target operation command issued by the target host by accessing the virtual mapping address, and analyzing the target operation command to obtain analyzed data; the target operation command is a command used for executing JTAG debugging operation on the NVMe equipment controller; and converting the analyzed data into a JTAG signal by using the TAP state machine, and accessing processor resources in the local system on chip based on the JTAG signal to complete JTAG debugging operation.

Description

Technical Field

[0001] The present invention relates to the field of storage technology, and in particular to an NVMe device controller debugging method, device, equipment, medium and product. Background Art

[0002] With the development of embedded systems and storage technology, the demand for debugging is increasing. The traditional JTAG (Joint Test Action Group) debugging interface faces challenges in high-speed memories and complex systems.

[0003] The schematic diagram of SoC (System on Chip) debugging of traditional NVMe (Non Volatile Memory Express) devices is as follows: Figure 1 As shown in the figure, JTAG-DP (JTAG DebugPort) is an interface in the ARM CoreSight debugging architecture, providing a 5-pin standard JTAG interface for connecting an external debugger to the SoC. JTAG-DP allows the debugger to control and monitor the internal state of the target device by sending specific JTAG instruction sequences. AHB-AP (Advanced High-performance Bus Access Port) is an interface used in the CoreSight architecture to access devices mounted on the AHB system bus. It allows the debugger to access the CPU memory and registers inside the SoC through memory mapping. The debugger connects to the SoC through JTAG-DP, and then converts the debug request to the AHB-AP through the control of the DAP (Debug Access Port). The AHB-AP then converts these accesses into AHB bus accesses to access the internal resources of the processor (such as the CPU) to achieve the purpose of testing and debugging.

[0004] However, the JTAG interface in the traditional JTAG debugging method requires at least 4 pins, which occupies more I / O (Input / Output) resources and board space. In addition, JTAG debugging has certain limitations in terms of stability and data transmission speed, resulting in low debugging efficiency.

[0005] In summary, how to more efficiently implement the JTAG debugging function of the NVMe device controller to improve debugging efficiency is a problem that needs to be solved. Summary of the invention

[0006] In view of this, the purpose of the present invention is to provide an NVMe device controller debugging method, apparatus, device, medium and product, which can more efficiently implement the JTAG debugging function of the NVMe device controller to improve the debugging efficiency. The specific scheme is as follows:

[0007] In a first aspect, the present application discloses an NVMe device controller debugging method, which is applied to a target NVMe device controller, comprising:

[0008] During the initialization process, the controller memory buffer is enabled and the attribute parameters of the controller memory buffer are set, so that when the target host enumerates the target NVMe device controller through the bus, the controller memory buffer is mapped to the memory space of the target host based on the attribute parameters to obtain the virtual mapping address of the controller memory buffer in the memory space; Obtain a target operation command issued by the target host by accessing the virtual mapping address, and parse the target operation command to obtain parsed data; wherein the target operation command is a command for performing a JTAG debugging operation on the target NVMe device controller; The TAP state machine is used to convert the parsed data into JTAG signals, so as to access the processor resources in the local on-chip system based on the JTAG signals to complete the JTAG debugging operation.

[0009] Optionally, the target NVMe device controller is locally provided with a controller capability register; Accordingly, the controller memory buffer is enabled during the initialization process, including: Enable the controller memory buffer by setting the target field in the controller capability register, which indicates support for the controller memory buffer feature, to a target value.

[0010] Optionally, the target host may enumerate any NVMe device controller via the bus, including: The target host obtains the target field in the controller capability register of any NVMe device controller through the bus, and determines whether the target field is a target value; If the target field is a target value, the attribute parameters of the controller memory buffer in any NVMe device controller are obtained to map the controller memory buffer to the local memory space based on the attribute parameters.

[0011] Optionally, the target host initialization process includes: Enumerate each NVMe device controller through the bus to obtain attribute parameters of the controller memory buffer in each NVMe device controller; Initialize the NVMe driver interface and configure the target register to enable the controller memory buffer function; the target register is used to control and report the status of the controller memory buffer.

[0012] Optionally, obtain the target operation command issued by the target host by accessing the virtual mapping address, including: Send a debugging request to the NVMe driver interface through the debugging tool in the target host; Get the target operation command issued by the NVMe driver interface; the target operation command is the target operation command obtained after the NVMe driver interface converts the debugging request into a read and write operation on the virtual mapping address.

[0013] Optionally, the target NVMe device controller is locally provided with a first register for configuring size information of the controller memory buffer and a second register for specifying location information of the controller memory buffer in the memory space of the target host; Accordingly, set the attribute parameters of the controller memory buffer, including: The value of the first register is configured based on the first preset value to obtain size information of the controller memory buffer; The value of the second register is configured based on the second preset value to obtain the location information of the controller memory buffer in the memory space of the target host.

[0014] Optionally, the NVMe device controller debugging method of the present application further includes: The current first value of the first register and the current second value of the second register are obtained through the target host, and the corresponding memory size is allocated in the local memory space based on the current first value, and the physical address of the controller memory buffer in the local memory space is determined based on the current second value, so as to obtain the virtual mapping address of the controller memory buffer in the local memory space according to the memory size and the physical address.

[0015] Optionally, the second preset value includes a base address register field and an offset address field; Accordingly, determining the physical address of the controller memory buffer in the local memory space based on the current second value includes: locally determining a corresponding base address register based on the base address register field; The physical address of the controller memory buffer in the local memory space is determined based on the base address register and the target offset address indicated by the offset address field.

[0016] Optionally, the virtual mapping address includes a command register and a data register; Accordingly, the target operation command issued by the target host by accessing the virtual mapping address is obtained, including: The data written by the target host to the command register and the data register are obtained to obtain the target operation command.

[0017] Optionally, the target operation command includes a command type and a data signal; Accordingly, the data written by the target host to the command register and the data register are obtained to obtain the target operation command, including: Obtain the command type written by the target host to the command register; wherein the command type is a read command type or a write command type; Acquire a data signal written by the target host to the data register; wherein the data signal is a signal corresponding to a read command type or a signal corresponding to a write command type.

[0018] Optionally, the parsed data is converted into JTAG signals using a TAP state machine, including: Set the TAP state machine to the preset initial state; Generate a corresponding TMS signal according to the command type in the parsed data; The TMS signal is used to drive the TAP state machine to perform state transition from the initial state, and the data signal in the parsed data is extracted bit by bit to be converted into a JTAG signal.

[0019] Optionally, the states of the TAP state machine include an initial state, an idle state, a state for selecting a data register path, and a state for selecting an instruction register path.

[0020] Optionally, the virtual mapping address also includes a status register; Accordingly, the method of the present application also includes: After checking that the target host writes data to the command register, the status register is set to a busy state; After completing the JTAG debug operation, the status register is set to the idle state.

[0021] Optionally, after completing the JTAG debugging operation, it also includes: Get the debugging results corresponding to the JTAG debugging operation; Write the debugging result to the data register so that the target host can read the debugging result from the data register.

[0022] Optionally, processor resources in the local system-on-chip are accessed based on JTAG signals to complete JTAG debugging operations, including: The JTAG signal is connected to the debug access port through the JTAG debug port, and the JTAG signal is converted into an access request to the local on-chip system through the debug access port and the advanced high-performance bus access port to access processor resources in the local on-chip system.

[0023] Optionally, the JTAG signal is converted into an access request to the local system-on-chip through the debug access port and the advanced high-performance bus access port to access processor resources in the local system-on-chip, including: The JTAG signal is converted into an access request to the advanced high-performance bus access port through the debug access port, and the access request is converted into an access to the advanced high-performance bus through the advanced high-performance bus access port to obtain processor resources in the local on-chip system through the advanced high-performance bus.

[0024] In a second aspect, the present application discloses an NVMe device controller debugging device, which is applied to a target NVMe device controller, comprising: A buffer mapping module is used to enable the controller memory buffer during the initialization process and set the attribute parameters of the controller memory buffer so that when the target host enumerates the target NVMe device controller through the bus, the controller memory buffer is mapped to the memory space of the target host based on the attribute parameters to obtain the virtual mapping address of the controller memory buffer in the memory space; A command acquisition module, used to acquire a target operation command issued by a target host by accessing a virtual mapping address, and parse the target operation command to obtain parsed data; wherein the target operation command is a command for performing a JTAG debugging operation on a target NVMe device controller; The debugging module is used to convert the parsed data into JTAG signals by using the TAP state machine, so as to access the processor resources in the local on-chip system based on the JTAG signals to complete the JTAG debugging operation.

[0025] In a third aspect, the present application discloses an electronic device, comprising: Memory, used to store computer programs; A processor is used to execute a computer program to implement the steps of the aforementioned disclosed NVMe device controller debugging method.

[0026] In a fourth aspect, the present application discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, the steps of the aforementioned disclosed NVMe device controller debugging method are implemented.

[0027] In a fifth aspect, the present application discloses a computer program product, including a computer program / instruction, which, when executed by a processor, implements the steps of the aforementioned disclosed NVMe device controller debugging method.

[0028] It can be seen that the target NVMe device controller in the present application enables the controller memory buffer during the initialization process and sets the attribute parameters of the controller memory buffer, so that when the target host enumerates the target NVMe device controller through the bus, the controller memory buffer is mapped to the memory space of the target host based on the attribute parameters to obtain the virtual mapping address of the controller memory buffer in the memory space; obtain the target operation command issued by the target host by accessing the virtual mapping address, and parse the target operation command to obtain the parsed data; wherein, the target operation command is a command for performing JTAG debugging operations on the target NVMe device controller; use the TAP state machine to convert the parsed data into a JTAG signal to access the processor resources in the local system-on-chip based on the JTAG signal to complete the JTAG debugging operation.

[0029] Beneficial effect: The NVMe device controller in this application enables the local controller memory buffer during the initialization process and sets the attribute parameters of the controller memory buffer, so that when the target host enumerates the target NVMe device controller through the bus, the controller memory buffer is mapped to the memory space of the target host based on the attribute parameters to obtain the virtual mapping address of the controller memory buffer in the memory space, so that the target host can directly access the controller memory buffer like accessing its own memory, bypassing the traditional NVMe command queue, reducing the protocol stack overhead, and significantly reducing latency. Further, the target operation command for performing JTAG debugging operations on the target NVMe device controller issued by the target host by accessing the virtual mapping address is obtained, that is, the target host can directly operate the virtual mapping address through memory mapping, thereby reducing the CPU overhead and data access delay, improving the host performance, and also reducing the host CPU burden and reducing system resource consumption. Then, the target operation command is parsed to obtain the parsed data, and then converted into a JTAG signal through the TAP state machine, so that the processor resources in the local system-on-chip can be accessed based on the JTAG signal to complete the JTAG debugging operation. That is, the present application utilizes the controller memory buffer of the NVMe device controller as a debugging interface and maps the controller memory buffer to the host memory space so that the host can directly access the controller memory buffer, thereby realizing the JTAG debugging function of the NVMe device controller. In this way, the number of hardware pins is reduced, the data transmission efficiency is improved, and the overall debugging efficiency is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0031] Figure 1 A debugging diagram of a traditional NVMe device controller; Figure 2 A flowchart of a NVMe device controller debugging method disclosed in this application; Figure 3 This is a debugging architecture diagram of an NVMe device controller disclosed in this application; Figure 4 A flowchart of a specific NVMe device controller debugging method disclosed in this application; Figure 5 This is a JTAG debugging timing interaction diagram of an NVMe device disclosed in this application; Figure 6 A conversion flow chart of using CMB as a JTAG interface disclosed in this application; Figure 7 This is a schematic diagram of the structure of an NVMe device controller debugging device disclosed in this application; Figure 8 This is a structural diagram of an electronic device disclosed in this application. DETAILED DESCRIPTION

[0032] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0033] The SoC debugging diagram of traditional NVMe devices is as follows Figure 1As shown in the figure, JTAG-DP is an interface in the ARM CoreSight debugging architecture, which provides a 5-pin standard JTAG interface for connecting an external debugger to the SoC. JTAG-DP allows the debugger to control and monitor the internal state of the target device by sending a specific JTAG instruction sequence. The debugger is connected to the SoC through JTAG-DP, and then through the control of the DAP, it converts the debug request into access to the AHB-AP, and the AHB-AP converts these accesses into AHB bus accesses to access the internal resources of the CPU to achieve the purpose of testing and debugging. However, the JTAG interface in the traditional JTAG debugging method requires at least 4 pins, which occupies more I / O (Input / Output) resources and board space. In addition, JTAG debugging has certain limitations in terms of stability and data transmission speed, resulting in low debugging efficiency.

[0034] To this end, the embodiments of the present application disclose an NVMe device controller debugging method, apparatus, equipment, medium and product, which can more efficiently implement the JTAG debugging function of the NVMe device controller to improve debugging efficiency.

[0035] See also Figure 2 As shown, an embodiment of the present application discloses an NVMe device controller debugging method, which is applied to a target NVMe device controller. The method includes:

[0036] Step S11: Enable the controller memory buffer during the initialization process and set the attribute parameters of the controller memory buffer so that when the target host enumerates the target NVMe device controller through the bus, the controller memory buffer is mapped to the memory space of the target host based on the attribute parameters to obtain the virtual mapping address of the controller memory buffer in the memory space.

[0037] In this embodiment, the NVMe device controller enables the local controller memory buffer (CMB) during the initialization process and sets the attribute parameters of the controller memory buffer, so that when the target host enumerates the target NVMe device controller through the bus, the controller memory buffer is mapped to the target host's memory space based on the attribute parameters to obtain the virtual mapping address of the controller memory buffer in the memory space, so that the target host can directly access the controller memory buffer as if it were accessing its own memory, bypassing the traditional NVMe command queue, reducing protocol stack overhead, and significantly reducing latency. Among them, CMB is an important feature in the NVMe protocol, which allows the SSD controller to map the internal general buffer to the host side, so that the host side can directly access it in the form of PCIe memory read / write.

[0038] Furthermore, since each NVMe device controller has a local controller memory buffer, when multiple NVMe device controllers map the local controller memory buffer to the memory space of the target host, the host can debug multiple devices at the same time.

[0039] It should be pointed out that the target NVMe device controller is locally set with a controller capability register; accordingly, enabling the controller memory buffer during the initialization process includes: setting the target field in the controller capability register that indicates support for the controller memory buffer function to the target value to enable the controller memory buffer. It can be understood that the controller capability register includes a target field for indicating whether the controller memory buffer function is supported, namely the CAP.CMBS (Controller Memory Buffer Support) field. If CAP.CMBS=1, it means that the NVMe device controller supports CMB; if CAP.CMBS=0, it means that the NVMe device controller does not support CMB, and subsequent CMB-related operations cannot be performed. Therefore, the target NVMe device controller will set the CAP.CMBS field in the controller capability register to the target value 1 during the power-on initialization phase, that is, enable the controller capability register CAP.CMBS to enable the controller memory buffer.

[0040] In a specific implementation, the process of the target host enumerating any NVMe device controller through the bus includes: the target host obtains the target field in the controller capability register in any NVMe device controller through the bus, and determines whether the target field is a target value; if the target field is a target value, the attribute parameters of the controller memory buffer in any NVMe device controller are obtained to map the controller memory buffer to the local memory space based on the attribute parameters.

[0041] First of all, it should be pointed out that enumeration refers to the process in which the host scans the PCIe (peripheral component interconnect express) bus at startup to discover devices and allocate resources (such as memory addresses and interrupts). The purposes of enumeration include the following methods: (1) Device discovery: The host needs to know which PCIe EP (EndPoint) devices are connected to the bus. Since the PCIe system supports hot plugging, devices may be plugged in or unplugged at any time during system operation. Therefore, the host needs to perform device enumeration regularly or when hardware changes are detected to discover new devices or confirm removed devices; (2) Resource allocation: Allocate necessary system resources to each PCIe EP device, such as memory address space, I / O address space, and interrupt number. Each device in the system needs to have a unique resource allocation to ensure that they can work properly and do not conflict with each other; (3) Device configuration: Read and set PCIe Configuration information of EP devices. Each PCIe device has a configuration space, which contains information such as the device's manufacturer ID, device ID, device type, supported functions, etc. The host reads this information through the enumeration process and configures the device as needed to adapt it to the system environment.

[0042] In this embodiment, the target host needs to obtain the target field CAP.CMBS in the controller capability register in each NVMe device controller through the PCIe bus. If CAP.CMBS is 1, the attribute parameters of the controller memory buffer in the NVMe device controller are obtained to map the controller memory buffer to the local memory space based on the attribute parameters, that is, to allocate the corresponding memory space for the controller memory buffer, so that the controller memory buffer can be mapped. In other words, when the host enumerates the PCIe device, the host reads the PCIe configuration space of the device and finds that the NVMe device controller supports CMB (CAP.CMBS=1), then maps CMB to its own physical address space according to its attribute parameters.

[0043] Among them, the initialization process of the target host includes: enumerating each NVMe device controller through the bus to obtain the attribute parameters of the controller memory buffer in each NVMe device controller; initializing the NVMe driver interface, and configuring the target register to enable the function of the controller memory buffer; wherein the target register is used to control and report the status of the controller memory buffer. That is, in the power-on initialization phase, both the NVMe device controller and the target host need to complete the local initialization process, wherein the NVMe device completes the basic function initialization, enables the NVMe controller register CAP.CMBS, and sets the attribute parameters of the CMB. The target host side needs to enumerate the PCIE ep device, obtain the attribute parameter setting of the CMB, complete the NVMe driver (driver interface) initialization, and also configure the target register to enable the CMB function to ensure that the CMB can be accessed; the target register specifically refers to CMDMSC (Command Memory Space Control and Status Register), which is mainly used to control and report the status of the controller memory buffer. That is, when the system is initialized, the host sets the CMDMSC register to enable the CMB function. By setting the corresponding bit of the register, the NVMe device is informed to allow the host to access the CMB in the form of PCIe memory read / write, providing a basis for subsequent debugging operations.

[0044] Step S12: Obtain the target operation command issued by the target host by accessing the virtual mapping address, and parse the target operation command to obtain the parsed data; wherein the target operation command is a command for performing a JTAG debugging operation on the target NVMe device controller.

[0045] In this embodiment, the target operation command for performing JTAG debugging operation on the target NVMe device controller issued by the target host by accessing the virtual mapping address is obtained, that is, the target host can directly operate the virtual mapping address through memory mapping, thereby reducing the CPU overhead and data access delay, improving the host performance, and also reducing the host CPU burden and reducing system resource consumption. Then, the target operation command is parsed to obtain the parsed data.

[0046] In a specific implementation, obtaining the target operation command issued by the target host by accessing the virtual mapping address includes: sending a debugging request to the NVMe driver interface through the debugging tool in the target host; obtaining the target operation command issued by the NVMe driver interface; the target operation command is the target operation command obtained after the NVMe driver interface converts the debugging request into a read and write operation on the virtual mapping address. For details, see Figure 3As shown in the architecture, the target host sends a debugging request to the NVMe driver interface through the internal user debugging tool. The NVMe driver interface then converts the debugging request into a read and write operation on the CMB virtual mapping address, and then sends the target operation command to the target NVMe device controller. That is, the host user debugging tool accesses the CMB address by calling the Nvme driver interface, and implements the issuance of JTAG commands by reading and writing the CMB to perform specific debugging operations.

[0047] Step S13: using the TAP state machine to convert the parsed data into a JTAG signal, so as to access the processor resources in the local system-on-chip based on the JTAG signal to complete the JTAG debugging operation.

[0048] Specific as Figure 3 As shown, this embodiment is provided with a CMB2JTAG module, which allows the CMB in the NVMe device controller to be used for the JTAG debugging function, and realizes the JTAG protocol conversion by specifying the CMB memory mapping and reading and writing specific addresses, and manages the JTAG debugging operation using the TAP state machine. Therefore, this embodiment can convert the read CMB data into a JTAG signal through the internal TAP state machine, so that the processor resources in the local system-on-chip can be accessed based on the JTAG signal to complete the JTAG debugging operation. That is, this application uses the controller memory buffer of the NVMe device controller as a debugging interface, and maps the controller memory buffer to the host memory space, so that the host can directly access the controller memory buffer, thereby realizing the JTAG debugging function of the NVMe device controller. In this way, the number of hardware pins is reduced, the data transmission efficiency is improved, and the overall debugging efficiency is improved.

[0049] In a specific implementation, processor resources in a local system-on-chip are accessed based on JTAG signals to complete JTAG debugging operations, including: connecting the JTAG signal to a debug access port through a JTAG debug port, and converting the JTAG signal into an access request to the local system-on-chip through the debug access port and an advanced high-performance bus access port to access the processor resources in the local system-on-chip.

[0050] That is, if Figure 3As shown, this embodiment connects the JTAG signal to the debug access port (DAP) through the JTAG-DP (JTAG debug port), and then converts the JTAG signal into an access request to the local system-on-chip through the control of the debug access port (DAP) and the advanced high-performance bus access port (AHB-AP) to access the processor resources in the local system-on-chip, such as CPU resources, to achieve the purpose of testing and debugging. Among them, DAP is a key component in the ARM CoreSight debugging architecture, which allows an external debugger to access the debugging resources inside the SoC (System on Chip). DAP provides an interface that allows the debugger to communicate with the debugging hardware on the SoC through a set of standard pins (such as JTAG) to access and control the internal resources of the SoC. AHB-AP is a component of DAP, which allows the debugger to access devices connected to the AHB bus in a memory-mapped manner.

[0051] Specifically, the JTAG signal is converted into an access request to the local system-on-chip through the debug access port and the advanced high-performance bus access port to access the processor resources in the local system-on-chip, including: converting the JTAG signal into an access request to the advanced high-performance bus access port through the debug access port, and converting the access request into an access to the advanced high-performance bus through the advanced high-performance bus access port to obtain the processor resources in the local system-on-chip through the advanced high-performance bus. That is, Figure 3 As shown, DAP converts JTAG signals into access requests to AHB-AP, and AHB-AP converts these accesses into accesses to the AHB bus, thereby obtaining processor resources in the local on-chip system through the AHB bus.

[0052] It can be seen that the NVMe device controller in this application will enable the local controller memory buffer during the initialization process and set the attribute parameters of the controller memory buffer, so that when the target host enumerates the target NVMe device controller through the bus, the controller memory buffer is mapped to the memory space of the target host based on the attribute parameters to obtain the virtual mapping address of the controller memory buffer in the memory space, so that the target host can directly access the controller memory buffer like accessing its own memory, bypassing the traditional NVMe command queue, reducing the protocol stack overhead, and significantly reducing latency. Further, the target operation command for performing JTAG debugging operations on the target NVMe device controller issued by the target host by accessing the virtual mapping address is obtained, that is, the target host can directly operate the virtual mapping address through memory mapping, thereby reducing the CPU overhead and data access delay, improving the host performance, and also reducing the host CPU burden and reducing system resource consumption. Then, the target operation command is parsed to obtain the parsed data, and then converted into a JTAG signal through the TAP state machine, so that the processor resources in the local system-on-chip can be accessed based on the JTAG signal to complete the JTAG debugging operation. That is, the present application utilizes the controller memory buffer of the NVMe device controller as a debugging interface and maps the controller memory buffer to the host memory space so that the host can directly access the controller memory buffer, thereby realizing the JTAG debugging function of the NVMe device controller. In this way, the number of hardware pins is reduced, the data transmission efficiency is improved, and the overall debugging efficiency is improved.

[0053] See also Figure 4 and Figure 5 As shown, the embodiment of the present application discloses a specific NVMe device controller debugging method. Compared with the previous embodiment, this embodiment further explains and optimizes the technical solution. Specifically, it includes:

[0054] Step S21: Enable the controller memory buffer during the initialization process, and configure the value of the first register based on a first preset value to obtain size information of the controller memory buffer, and configure the value of the second register based on a second preset value to obtain location information of the controller memory buffer in the memory space of the target host.

[0055] In this embodiment, it should be pointed out that the target NVMe device controller is locally configured with two registers for expressing the basic information of the CMB, specifically a first register for configuring the size information of the controller memory buffer and a second register for specifying the location information of the controller memory buffer in the memory space of the target host, and the information of these two registers can be viewed in the host. Therefore, the NVMe device controller sets the attribute parameters of the controller memory buffer during the initialization process, that is, configures the values ​​of the first register and the second register.

[0056] Specifically, the first register is the CMBSZ register, which is used to configure the size information of the CMB, for example, using a size of 1M; the second register is the CMBLOC register, which is used to specify the location information of the CMB in the memory space of the target host. Therefore, the NVMe device controller can configure the value of the first register based on the first preset value to obtain the size information of the controller memory buffer, and configure the value of the second register based on the second preset value to obtain the location information of the controller memory buffer in the memory space of the target host.

[0057] Step S22: When the target host enumerates the target NVMe device controller through the bus, the controller memory buffer is mapped to the memory space of the target host based on the size information and location information to obtain the virtual mapping address of the controller memory buffer in the memory space.

[0058] In this embodiment, when the target host enumerates the target NVMe device controller, the local register information of the target NVMe device controller can be viewed, thereby mapping the controller memory buffer to the memory space of the target host according to the acquired size information and location information.

[0059] Specifically, the above method also includes: obtaining the current first value of the first register and the current second value of the second register through the target host, and allocating the corresponding memory size in the local memory space based on the current first value, and determining the physical address of the controller memory buffer in the local memory space based on the current second value, so as to obtain the virtual mapping address of the controller memory buffer in the local memory space according to the memory size and the physical address. That is, after the target host obtains the current first value of the first register, it can allocate the corresponding memory size in the local memory space according to the current first value for mapping the CMB. In addition, the debugging tool also needs to know the capacity of the CMB to limit the size of the JTAG command and data and avoid writing addresses beyond the range of the CMB. In addition, after the target host obtains the current second value of the second register, it can determine the physical address of the controller memory buffer in the local memory space according to the current second value, so as to finally obtain the virtual mapping address of the CMB in the local memory space according to the memory size and the physical address.

[0060] In a specific implementation, the first preset value for configuring the CMBSZ register includes a Size field, which refers to the length of the available space in the CMB, and the unit is also CMBSZ.SZ; in addition, CMBSZ also includes Size Units (SZU), which represents the size unit of CMB; wherein, the size of CMB is allowed to be configured very large as long as the device has enough space.

[0061] In a specific implementation, the second preset value includes a base address register field and an offset address field; accordingly, determining the physical address of the controller memory buffer in the local memory space based on the current second value includes: determining the corresponding base address register locally based on the base address register field; determining the physical address of the controller memory buffer in the local memory space based on the base address register and the target offset address represented by the offset address field. That is, the second preset value for configuring the CMBLOC register includes two main fields: OFST (Offset, offset address field), which indicates the offset address of the CMB, the unit is CMBSZ.SZ, and requires 4KB alignment; BIR (Base Indicator Register, base address register field) field, which indicates the serial number of the PCI BAR (base address register). Therefore, when determining the physical address of the CMB in the host memory space, first determine the corresponding base address register locally based on the base address register field, and then determine the final physical address of the controller memory buffer in the local memory space based on the base address register and the target offset address represented by the offset address field. That is, the host first finds the corresponding PCIe BAR through BIR, and maps CMB to the host physical address space in combination with OFST. For example, BIR=0 represents BAR0. The host reads the base address of BAR0 and adds OFST to obtain the final physical address of CMB.

[0062] Step S23: Obtain the data written by the target host to the command register and the data register respectively to obtain the target operation command, and parse the target operation command to obtain the parsed data; wherein the target operation command is a command for performing a JTAG debugging operation on the target NVMe device controller.

[0063] It should be pointed out that the virtual mapping address includes the command register CMD_REG and the data register DATA_REG. Therefore, when the target host issues a target operation command by accessing the virtual mapping address, it mainly issues the target operation command by writing data into the command register and the data register respectively.

[0064] In addition, the virtual mapping address also includes a status register; accordingly, the method of the present application also includes: after checking that the target host writes data to the command register, setting the status register to a busy state; after completing the JTAG debugging operation, setting the status register to an idle state. The status register is recorded as STATUS_REG, which is mainly used to reflect the current operation status. Specifically, after checking that the target host writes data to the command register, the status register is set to a busy state, and after completing the JTAG debugging operation, the status register is set to an idle state.

[0065] In a specific implementation, the target operation command includes a command type and a data signal; accordingly, the data written by the target host to the command register and the data register are obtained to obtain the target operation command, including: obtaining the command type written by the target host to the command register; wherein the command type is a read command type or a write command type; obtaining the data signal written by the target host to the data register; wherein the data signal is a signal corresponding to the read command type or a signal corresponding to the write command type. That is, the issued target operation command includes a command type and a data signal, wherein the target host writes the command type to the command register, and the command type can specifically be a read command type or a write command type, and can be represented by different opcodes, for example, 0x01 represents writing IR (Instruction Register), and 0x02 represents reading DR (Data Register). Writing IR refers to writing a specific instruction to the instruction register of the JTAG TAP (Test Access Port) state machine, thereby realizing various debugging and testing functions; reading DR means reading data from the data register of the JTAG TAP state machine, and the data register is used to store data during the test or debugging process, such as the value of the internal register of the chip, the test results of the boundary scan chain, etc. In addition, the data signal written by the target host to the data register specifically includes a signal corresponding to a read command type (TDO signal, Test Data Out) or a signal corresponding to a write command type (TDI signal, Test Data In).

[0066] That is, this embodiment defines three different registers at the virtual mapping address: (1) CMD_REG: stores JTAG commands; (2) DATA_REG: used to transmit data (TDI signal / TDO signal); (3) STATUS_REG: reflects the current operation status.

[0067] The address definition is as follows: #define CMD_ADDR0x20000000; #define DATA_ADDR0x20000004; #define STATUS_ADDR 0x20000008.

[0068] In this way, the host sends JTAG operation commands through CMB, where CMD_REG in CMB stores JTAG commands, DATA_REG is used to transmit data (TDI / TDO), and STATUS_REG reflects the current operation status. Correspondingly, the NVMe device controller reads the CMD_REG address in CMB to parse the JTAG command, performs read and write operations through DATA_REG in CMB, reads the JTAG operation status through STATUS_REG in CMB, and executes the corresponding JTAG debugging operation according to the determined operation type (such as read, write).

[0069] Step S24: Set the TAP state machine to a preset initial state, generate a corresponding TMS signal according to the command type in the parsed data, use the TMS signal to drive the TAP state machine to perform state transition from the initial state, and extract the data signal in the parsed data bit by bit to convert it into a JTAG signal.

[0070] In this embodiment, Figure 6 As shown, when the CMB2JTAG module detects that a JTAG command is written to CMD_REG, the TAP state machine needs to be reset to set the TAP state machine to a preset initial state, specifically to force it into the Test-Logic-Reset state. Further, the corresponding TMS (Test Mode Select) signal is generated according to the command type in the parsed data, and the TMS signal is used to drive the TAP state machine to transition from the initial state, and the data signal in the parsed data is extracted bit by bit to be converted into a JTAG signal. Among them, the TMS signal controls the TAP state machine to switch between 16 states through a combination of high and low levels (1 or 0).

[0071] It should be noted that the states of the TAP state machine include an initial state, an idle state, a state for selecting a data register path, and a state for selecting an instruction register path.

[0072] It is understandable that the CMB2JTAG module uses the TAP state machine to manage the sending, execution and response process of commands to ensure the orderly progress of the debugging process. The 16 states of the TAP state machine are defined as follows: typedef enum { TEST_LOGIC_RESET, RUN_TEST_IDLE, SELECT_DR_SCAN, CAPTURE_DR, SHIFT_DR, EXIT1_DR, PAUSE_DR, EXIT2_DR, UPDATE_DR, SELECT_IR_SCAN, CAPTURE_IR, SHIFT_IR, EXIT1_IR, PAUSE_IR, EXIT2_IR, UPDATE_IR } TAP_State; TAP_State current_state = TEST_LOGIC_RESET。

[0073] Furthermore, the pseudocode for updating the TAP state machine is as follows: void update_tap_state(uint32_t tms) { switch (current_state) { case TEST_LOGIC_RESET: current_state = tms? TEST_LOGIC_RESET : RUN_TEST_IDLE; break; case RUN_TEST_IDLE: current_state = tms? SELECT_DR_SCAN : RUN_TEST_IDLE; break; case SELECT_DR_SCAN: current_state = tms? SELECT_IR_SCAN : CAPTURE_DR; break; case CAPTURE_DR: current_state = tms ? EXIT1_DR : SHIFT_DR; break; case SHIFT_DR: current_state = tms ? EXIT1_DR : SHIFT_DR; break; case EXIT1_DR: current_state = tms ? UPDATE_DR : PAUSE_DR; break; case PAUSE_DR: current_state = tms ? EXIT2_DR : PAUSE_DR; break; case EXIT2_DR: current_state = tms ? UPDATE_DR : SHIFT_DR; break; case UPDATE_DR: current_state = tms ? SELECT_DR_SCAN : RUN_TEST_IDLE; break; case SELECT_IR_SCAN: current_state = tms ? TEST_LOGIC_RESET : CAPTURE_IR; break; case CAPTURE_IR: current_state = tms ? EXIT1_IR : SHIFT_IR; break; case SHIFT_IR: current_state = tms ? EXIT1_IR : SHIFT_IR; break; case EXIT1_IR: current_state = tms ? UPDATE_IR : PAUSE_IR; break; case PAUSE_IR: current_state = tms ? EXIT2_IR : PAUSE_IR; break; case EXIT2_IR: current_state = tms ? UPDATE_IR : SHIFT_IR; break; case UPDATE_IR: current_state = tms ? SELECT_DR_SCAN : RUN_TEST_IDLE; break; } }.

[0074] The pseudo code for reading and writing CMB data register is as follows: void read_write_data(uint32_t *data, int write) { if (write) { *(volatile uint32_t *)DATA_REG = *data; } else { *data = *(volatile uint32_t *)DATA_REG; } }.

[0075] The pseudo code for updating the CMB status register is as follows: int check_status() { return *(volatile uint32_t *)STATUS_REG; }.

[0076] The following takes the host sending a read DR (data register) command through CMB as an example to explain the above process in detail: Step 1: Initialize the TAP state machine The CMB2JTAG module detects that CMD_REG is written to JTAG_READ_DR and resets the TAP state machine: Force the device to enter the Test-Logic-Reset state (by pulling the TMS signal high). Then jump to Run-Test / Idle (TMS=0).

[0077] Step 2: Enter the Data Register (DR) path 1. Select-DR-Scan (TMS=1): Prepare to switch to the DR path.

[0078] 2. Capture-DR (TMS=0): Capture the current value of a register (such as a CPU register content).

[0079] 3. Shift-DR (TMS=0): On the rising edge of TCK, TDI (from DATA_REG) is shifted in bit by bit, while the captured data is shifted out bit by bit from TDO.

[0080] Data exchange: TCK, TDI shifts in 1 bit, TDO shifts out 1 bit per cycle (completed by reading and writing DATA_REG).

[0081] 4. Exit1-DR (TMS=1): End the shift operation.

[0082] 5. Update-DR (TMS=1): Update the shifted data to the register (such as writing to the CPU register).

[0083] Step 3: Return to idle state Jump back to Run-Test / Idle (TMS=0) and wait for the next command.

[0084] Step S25: Based on the JTAG signal, the processor resources in the local system on chip are accessed to complete the JTAG debugging operation, and the debugging result corresponding to the JTAG debugging operation is obtained, and then the debugging result is written into the data register so that the target host can read the debugging result from the data register.

[0085] In this embodiment, after the JTAG debugging operation is completed, the corresponding debugging result is obtained and written into the data register so that the target host can read the debugging result from the data register, and then update the status register, reset the TAP state machine, and wait for the next JTAG command.

[0086] It can be seen that this application implements the JTAG debugging function of the NVMe device through the NVMe CMB. By completing the settings of the NVMe device controller and CMB in the initialization phase, the host is allowed to access the CMB directly through the NVMe driver interface without going through multiple layers of protocol conversion, reducing CPU overhead and data access delay. The user debugging tool can read and write CMB through the Nvme_driver interface, issue JTAG commands, and the NVMe device parses the commands in the CMB and executes JTAG operations. Finally, the access and debugging of the SoC CPU resources are realized through the CMB to JTAG module and DAP, ensuring the accuracy and timeliness of command execution. The advantage of this method is that it utilizes the characteristics of the NVMe CMB that can quickly access the storage controller, effectively realizes the JTAG debugging function of the NVMe storage controller, and performs JTAG debugging by directly accessing the CMB, reducing intermediate steps, improving debugging efficiency and flexibility, and reducing system resource consumption, providing a more efficient and concise solution for the debugging of NVMe storage devices.

[0087] See also Figure 7 As shown, the embodiment of the present application discloses an NVMe device controller debugging device, which is applied to a target NVMe device controller, and the device includes: The buffer mapping module 11 is used to enable the controller memory buffer during the initialization process and set the attribute parameters of the controller memory buffer so that when the target host enumerates the target NVMe device controller through the bus, the controller memory buffer is mapped to the memory space of the target host based on the attribute parameters to obtain the virtual mapping address of the controller memory buffer in the memory space; A command acquisition module 12 is used to acquire a target operation command issued by the target host by accessing the virtual mapping address, and parse the target operation command to obtain parsed data; wherein the target operation command is a command for performing a JTAG debugging operation on the target NVMe device controller; The debugging module 13 is used to convert the parsed data into JTAG signals by using the TAP state machine, so as to access the processor resources in the local system on chip based on the JTAG signals to complete the JTAG debugging operation.

[0088] It can be seen that the NVMe device controller in this application will enable the local controller memory buffer during the initialization process and set the attribute parameters of the controller memory buffer, so that when the target host enumerates the target NVMe device controller through the bus, the controller memory buffer is mapped to the memory space of the target host based on the attribute parameters to obtain the virtual mapping address of the controller memory buffer in the memory space, so that the target host can directly access the controller memory buffer like accessing its own memory, bypassing the traditional NVMe command queue, reducing the protocol stack overhead, and significantly reducing latency. Further, the target operation command for performing JTAG debugging operations on the target NVMe device controller issued by the target host by accessing the virtual mapping address is obtained, that is, the target host can directly operate the virtual mapping address through memory mapping, thereby reducing the CPU overhead and data access delay, improving the host performance, and also reducing the host CPU burden and reducing system resource consumption. Then, the target operation command is parsed to obtain the parsed data, and then converted into a JTAG signal through the TAP state machine, so that the processor resources in the local system-on-chip can be accessed based on the JTAG signal to complete the JTAG debugging operation. That is, the present application utilizes the controller memory buffer of the NVMe device controller as a debugging interface and maps the controller memory buffer to the host memory space so that the host can directly access the controller memory buffer, thereby realizing the JTAG debugging function of the NVMe device controller. In this way, the number of hardware pins is reduced, the data transmission efficiency is improved, and the overall debugging efficiency is improved.

[0089] Since the embodiments of the device part correspond to the above embodiments, please refer to the description of the embodiments of the method part for the embodiments of the device part, and will not be repeated here.

[0090] Figure 8 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. Specifically, it may include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. Among them, the memory 22 is used to store a computer program, and the computer program is loaded and executed by the processor 21 to implement the relevant steps in the NVMe device controller debugging method performed by the electronic device disclosed in any of the aforementioned embodiments.

[0091] In this embodiment, the power supply 23 is used to provide working voltage for each hardware device on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and the external device, and the communication protocol it follows is any communication protocol that can be applied to the technical solution of the present application, and is not specifically limited here; the input and output interface 25 is used to obtain external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs and is not specifically limited here.

[0092] Among them, the processor 21 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 21 can be implemented in at least one hardware form of DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). The processor 21 may also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state, also known as a CPU (Central Processing Unit); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor 21 may be integrated with a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 21 may also include an AI (Artificial Intelligence) processor, which is used to process computing operations related to machine learning.

[0093] In addition, the memory 22, as a carrier for storing resources, can be a read-only memory, a random access memory, a disk or an optical disk, etc. The resources stored thereon include an operating system 221, a computer program 222 and data 223, etc. The storage method can be temporary storage or permanent storage.

[0094] Among them, the operating system 221 is used to manage and control the hardware devices and computer programs 222 on the electronic device 20, so as to realize the operation and processing of the massive data 223 in the memory 22 by the processor 21, which can be Windows, Unix, Linux, etc. In addition to including a computer program that can be used to complete the NVMe device controller debugging method performed by the electronic device 20 disclosed in any of the aforementioned embodiments, the computer program 222 can further include a computer program that can be used to complete other specific tasks. In addition to data transmitted from an external device received by the electronic device, the data 223 can also include data collected by its own input and output interface 25, etc.

[0095] Furthermore, an embodiment of the present application also discloses a computer-readable storage medium, in which a computer program is stored. When the computer program is loaded and executed by a processor, the NVMe device controller debugging method steps disclosed in any of the aforementioned embodiments are implemented.

[0096] An embodiment of the present invention also discloses a computer program product, including a computer program / instruction, which, when executed by a processor, implements the steps of the NVMe device controller debugging method disclosed in any of the aforementioned embodiments.

[0097] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0098] Those skilled in the art may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented with electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in terms of function in the above description. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0099] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a compact disc read-only memory (CD-ROM), or any other form of storage medium known in the art.

[0100] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0101] The above is a detailed introduction to the NVMe device controller debugging method, apparatus, equipment and storage medium provided by the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea; at the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A method for debugging an NVMe device controller, characterized in that: Applicable to target NVMe device controllers, including: During the initialization process, the controller memory buffer is enabled, and the attribute parameters of the controller memory buffer are set, so that when the target host enumerates the target NVMe device controller through the bus, the controller memory buffer is mapped to the memory space of the target host based on the attribute parameters to obtain a virtual mapping address of the controller memory buffer in the memory space; Obtaining a target operation command issued by the target host by accessing the virtual mapping address, and parsing the target operation command to obtain parsed data; wherein the target operation command is a command for performing a JTAG debugging operation on the target NVMe device controller; The parsed data is converted into a JTAG signal by using a TAP state machine, so as to access processor resources in a local system on chip based on the JTAG signal to complete the JTAG debugging operation.

2. The NVMe device controller debugging method according to claim 1, characterized in that: The target NVMe device controller is locally provided with a controller capability register; Accordingly, enabling the controller memory buffer during the initialization process includes: A target field in the controller capability register for indicating support for a controller memory buffer function is set to a target value to enable the controller memory buffer.

3. The NVMe device controller debugging method according to claim 2, wherein: The process of the target host enumerating any NVMe device controller through the bus includes: The target host obtains a target field in a controller capability register in any NVMe device controller through a bus, and determines whether the target field is the target value; If the target field is the target value, the attribute parameters of the controller memory buffer in any NVMe device controller are obtained to map the controller memory buffer to the local memory space based on the attribute parameters.

4. The NVMe device controller debugging method according to claim 3, characterized in that: The initialization process of the target host includes: Enumerate each NVMe device controller through the bus to obtain attribute parameters of a controller memory buffer in each of the NVMe device controllers; Initialize the NVMe driver interface and configure the target register to enable the function of the controller memory buffer; wherein the target register is used to control and report the status of the controller memory buffer.

5. The NVMe device controller debugging method according to claim 4, characterized in that: The obtaining of the target operation command issued by the target host by accessing the virtual mapping address includes: Sending a debugging request to the NVMe driver interface through a debugging tool in the target host; Obtain a target operation command issued by the NVMe driver interface; the target operation command is a target operation command obtained after the NVMe driver interface converts the debugging request into a read and write operation on the virtual mapping address.

6. The NVMe device controller debugging method according to claim 1, characterized in that: The target NVMe device controller is locally provided with a first register for configuring the size information of the controller memory buffer and a second register for specifying the position information of the controller memory buffer in the memory space of the target host; Correspondingly, the setting of the attribute parameters of the controller memory buffer includes: The value of the first register is configured based on a first preset value to obtain size information of the controller memory buffer; The value of the second register is configured based on a second preset value to obtain location information of the controller memory buffer in the memory space of the target host.

7. The NVMe device controller debugging method according to claim 6, characterized in that: Also includes: The current first value of the first register and the current second value of the second register are obtained through the target host, and a corresponding memory size is allocated in the local memory space based on the current first value, and the physical address of the controller memory buffer in the local memory space is determined based on the current second value, so as to obtain the virtual mapping address of the controller memory buffer in the local memory space according to the memory size and the physical address.

8. The NVMe device controller debugging method according to claim 7, characterized in that: The second preset value includes a base address register field and an offset address field; Accordingly, determining the physical address of the controller memory buffer in the local memory space based on the current second value includes: locally determining a corresponding base address register based on the base address register field; The physical address of the controller memory buffer in the local memory space is determined based on the base address register and the target offset address indicated by the offset address field.

9. The NVMe device controller debugging method according to claim 1, characterized in that: The virtual mapping address includes a command register and a data register; Correspondingly, obtaining the target operation command issued by the target host by accessing the virtual mapping address includes: The data written by the target host to the command register and the data register are obtained to obtain a target operation command.

10. The NVMe device controller debugging method according to claim 9, characterized in that: The target operation command includes a command type and a data signal; Correspondingly, the acquiring of the data written by the target host to the command register and the data register respectively to obtain the target operation command includes: Obtaining a command type written by the target host to the command register; wherein the command type is a read command type or a write command type; Acquire a data signal written by the target host to the data register; wherein the data signal is a signal corresponding to the read command type or a signal corresponding to the write command type.

11. The NVMe device controller debugging method according to claim 10, characterized in that: The converting the parsed data into a JTAG signal by using a TAP state machine includes: Set the TAP state machine to the preset initial state; Generate a corresponding TMS signal according to the command type in the parsed data; The TMS signal is used to drive the TAP state machine to perform state transition from the initial state, and the data signal in the parsed data is extracted bit by bit to be converted into a JTAG signal.

12. The NVMe device controller debugging method according to claim 11, characterized in that: The states of the TAP state machine include the initial state, an idle state, a state for selecting a data register path, and a state for selecting an instruction register path.

13. The NVMe device controller debugging method according to claim 9, characterized in that: The virtual mapping address also includes a status register; Accordingly, the method further includes: After detecting that the target host writes data to the command register, setting the status register to a busy state; After the JTAG debugging operation is completed, the status register is set to an idle state.

14. The NVMe device controller debugging method according to claim 9, characterized in that: After completing the JTAG debugging operation, the method further includes: Obtaining a debugging result corresponding to the JTAG debugging operation; The debugging result is written into the data register so that the target host reads the debugging result from the data register.

15. The NVMe device controller debugging method according to any one of claims 1 to 14, characterized in that: The accessing of processor resources in the local system-on-chip based on the JTAG signal to complete the JTAG debugging operation includes: The JTAG signal is connected to a debug access port through a JTAG debug port, and the JTAG signal is converted into an access request to a local system-on-chip through the debug access port and an advanced high-performance bus access port to access processor resources in the local system-on-chip.

16. The NVMe device controller debugging method according to claim 15, characterized in that: The step of converting the JTAG signal into an access request to a local system-on-chip through the debug access port and the advanced high-performance bus access port to access processor resources in the local system-on-chip includes: The JTAG signal is converted into an access request to an advanced high-performance bus access port through the debug access port, and the access request is converted into an access to an advanced high-performance bus through the advanced high-performance bus access port to obtain processor resources in the local on-chip system through the advanced high-performance bus.

17. A NVMe device controller debugging device, characterized in that: Applicable to target NVMe device controllers, including: A buffer mapping module, used to enable a controller memory buffer during initialization and set attribute parameters of the controller memory buffer so that when a target host enumerates the target NVMe device controller through a bus, the controller memory buffer is mapped to the memory space of the target host based on the attribute parameters to obtain a virtual mapping address of the controller memory buffer in the memory space; A command acquisition module, used to acquire a target operation command issued by the target host by accessing the virtual mapping address, and parse the target operation command to obtain parsed data; wherein the target operation command is a command for performing a JTAG debugging operation on the target NVMe device controller; The debugging module is used to convert the parsed data into a JTAG signal by using a TAP state machine, so as to access processor resources in a local system on chip based on the JTAG signal to complete the JTAG debugging operation.

18. An electronic device, characterized in that: include: Memory, used to store computer programs; A processor, configured to execute the computer program to implement the steps of the NVMe device controller debugging method as described in any one of claims 1 to 16.

19. A computer-readable storage medium, characterized in that: Used to store computer programs; wherein, when the computer program is executed by a processor, the steps of the NVMe device controller debugging method as described in any one of claims 1 to 16 are implemented.

20. A computer program product comprising a computer program / instructions, characterized in that When the computer program / instruction is executed by a processor, the steps of the NVMe device controller debugging method described in any one of claims 1 to 16 are implemented.

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