Multilayer ceramic capacitor and method of manufacturing same

Abstract

The invention provides a multilayer ceramic capacitor and a method of manufacturing the same. The multilayer ceramic capacitor may include: a capacitor body including a dielectric layer and an inner electrode layer; and an external electrode disposed on the capacitor body, in which the dielectric layer may include a plurality of dielectric crystal grains and crystal grain boundaries between the dielectric crystal grains adjacent to each other, in which the dielectric crystal grains may include a barium titanate-based principal component including barium (Ba) and titanium (Ti), in which the crystal grain boundaries include silicon (Si), dysprosium (Dy), and terbium (Tb), and in which the dielectric layer may include a plurality of dielectric crystal grains and crystal grain boundaries between the dielectric crystal grains adjacent to each other, in which the dielectric crystal grains may include a barium titanate-based principal component including barium (Ba) and titanium (Ti), in which the crystal grain boundaries include silicon (Si), dysprosium (Dy), and terbium (Tb). The order of the molar contents of silicon (Si), dysprosium (Dy) and terbium (Tb) in the grain boundary is terbium (Tb) lt; dysprosium (Dy) lt; and silicon (Si).

Description

Technical Field

[0001] The present disclosure relates to a multilayer ceramic capacitor and a method of manufacturing the same. Background Art

[0002] As ceramic electronic components using ceramic materials, there are capacitors, inductors, piezoelectric elements, varistors, thermistors, etc. Among ceramic electronic components, multilayer ceramic capacitors (MLCCs) are used in various electronic devices due to advantages such as small size, high capacitance, and easy mounting.

[0003] For example, multilayer ceramic capacitors (MLCCs) are chip capacitors that can be used to be mounted on boards of several electronic products (such as image display devices (e.g., liquid crystal displays (LCDs), plasma display panels (PDPs), etc.), computers, personal portable terminals, smart phones, etc.) for charging or discharging them.

[0004] In particular, as the demand for ultra-small, high-capacity MLCCs for information technology (IT) increases, high reliability is required in an ultra-thin design. Summary of the invention

[0005] The present disclosure provides a multilayer ceramic capacitor having excellent density and thin-layer reliability.

[0006] The present disclosure provides a method for manufacturing a multilayer ceramic capacitor.

[0007] A multilayer ceramic capacitor may include: a capacitor body including a dielectric layer and an inner electrode layer; and an outer electrode disposed on the capacitor body, wherein the dielectric layer may include a plurality of dielectric grains and grain boundaries between dielectric grains adjacent to each other, wherein the plurality of dielectric grains may include a barium titanate-based main component including barium (Ba) and titanium (Ti), wherein the grain boundaries include silicon (Si), dysprosium (Dy), and terbium (Tb), and wherein molar contents of silicon (Si), dysprosium (Dy), and terbium (Tb) included in the grain boundaries are arranged in the order of terbium (Tb) < dysprosium (Dy) < silicon (Si).

[0008] In the grain boundary, a sum of a content of dysprosium (Dy) and a content of terbium (Tb) may be greater than 0.9 parts by mole and less than 2.0 parts by mole based on 100 parts by mole of titanium (Ti).

[0009] In the grain boundary, silicon (Si) may be included in an amount of 1.3 parts by mol to 2.5 parts by mol based on 100 parts by mol of titanium (Ti).

[0010] In the grain boundary, dysprosium (Dy) may be included in an amount of 0.6 parts by mol to 1.6 parts by mol based on 100 parts by mol of titanium (Ti).

[0011] In the grain boundary, terbium (Tb) may be included in an amount of 0.1 to 0.5 parts by mol based on 100 parts by mol of titanium (Ti).

[0012] In the grain boundary, a molar ratio of terbium (Tb) to dysprosium (Dy) may be 0.3 to 0.8.

[0013] In the grain boundary, an atomic ratio of dysprosium (Dy) to silicon (Si) may be greater than 0.4 and less than 1.0.

[0014] In the grain boundary, an atomic ratio of terbium (Tb) to silicon (Si) may be greater than 0.4 and less than 1.0.

[0015] The grain boundaries may further include tin (Sn).

[0016] In the grain boundary, tin (Sn) may be included in an amount of 0.5 parts by mol to 2.5 parts by mol based on 100 parts by mol of titanium (Ti).

[0017] A diameter of a dielectric grain among the plurality of dielectric grains may be 60% to 90% of a sum of a diameter of the dielectric grain and a thickness of the grain boundary.

[0018] A diameter of a dielectric grain in the plurality of dielectric grains may be 80 nm to 120 nm.

[0019] The size D50 of the plurality of dielectric grains may be 300 nm or less.

[0020] The grain boundary may have a thickness of 10 nm to 100 nm.

[0021] The average thickness of the dielectric layer may be 0.3 µm to 0.6 µm.

[0022] In the grain boundaries, silicon (Si) may be included in an amount of 1.3 to 2.5 parts by mole based on 100 parts by mole of titanium (Ti), dysprosium (Dy) may be included in an amount of 0.6 to 1.6 parts by mole based on 100 parts by mole of titanium (Ti), and terbium (Tb) may be included in an amount of 0.1 to 0.5 parts by mole based on 100 parts by mole of titanium (Ti).

[0023] A method for manufacturing a multilayer ceramic capacitor may include: preparing a dielectric slurry by mixing a barium titanate-based main component powder with a subsidiary component powder including a silicon (Si)-containing compound, a dysprosium (Dy)-containing compound, and a terbium (Tb)-containing compound; preparing a dielectric green sheet using the dielectric slurry, and forming a conductive paste layer on a surface of the dielectric green sheet; manufacturing a dielectric green sheet laminate by stacking a plurality of the dielectric green sheets having the conductive paste layer formed thereon; and manufacturing a capacitor including a plurality of dielectric layers and a plurality of internal electrode layers by firing the dielectric green sheet laminate. a capacitor body; and forming an external electrode on a surface of the capacitor body, wherein the dielectric may include a plurality of dielectric grains and grain boundaries between dielectric grains adjacent to each other, wherein the plurality of dielectric grains may include a barium titanate-based main component including barium (Ba) and titanium (Ti), wherein the grain boundaries include silicon (Si), dysprosium (Dy) and terbium (Tb), and wherein molar contents of silicon (Si), dysprosium (Dy) and terbium (Tb) included in the grain boundaries are arranged in the order of terbium (Tb) < dysprosium (Dy) < silicon (Si).

[0024] The barium titanate-based main component powder may be prepared by mixing a titanium (Ti) precursor and a barium (Ba) precursor, wherein, in the sub-component powder, silicon may include the silicon (Si)-containing compound in an amount of 1.3 to 2.5 parts by mole, dysprosium may include the dysprosium (Dy)-containing compound in an amount of 0.6 to 1.6 parts by mole, and terbium (Tb)-containing compound may include the terbium in an amount of 0.1 to 0.5 parts by mole, based on 100 parts by mole of the titanium (Ti) precursor.

[0025] The sub-component powder may further include a tin (Sn)-containing compound.

[0026] The barium titanate-based main component powder is prepared by mixing a titanium (Ti) precursor and a barium (Ba) precursor, and the sub-component powder includes the tin-containing compound in an amount of 0.5 to 2.5 parts by mole of tin based on 100 parts by mole of the titanium (Ti) precursor.

[0027] The multilayer ceramic capacitor according to the embodiment may improve density and thin-layer reliability by reinforcing the reliability of interfaces of dielectric grains and the reliability of interfaces between dielectric layers and internal electrode layers. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 is a perspective view showing a multilayer ceramic capacitor according to an embodiment.

[0029] Figure 2 It is along Figure 1 A cross-sectional view of a multilayer ceramic capacitor taken along line II' in FIG.

[0030] Figure 3 It is along Figure 1 A cross-sectional view of a multilayer ceramic capacitor taken along line II-II' in FIG.

[0031] Figure 4 is a schematic diagram illustrating dielectric grains and grain boundaries within a dielectric layer according to an embodiment.

[0032] Figure 5A is a transmission electron microscope (TEM) image of a portion of the dielectric layer according to Example 1.

[0033] Figure 5B yes Figure 5A Transmission electron microscopy - energy dispersive spectroscopy (TEM-EDS) analysis image of a portion of the dielectric layer.

[0034] Figure 5C yes Figure 5A EDS line analysis graph of the portion indicated by the arrow. DETAILED DESCRIPTION

[0035] Hereinafter, the present disclosure will be described in detail with reference to the accompanying drawings showing embodiments of the present disclosure. The accompanying drawings and descriptions are considered to be illustrative rather than restrictive in nature. Throughout the specification, the same reference numerals represent the same elements. In the accompanying drawings, some components are exaggerated, omitted or schematically shown, and the size of each component does not fully reflect the actual size.

[0036] The drawings are intended only to facilitate understanding of the exemplary embodiments disclosed in this specification, and it should be understood that the technical ideas disclosed herein are not limited to the drawings, and include all modifications, equivalents, or alternatives within the scope of the ideas and technologies of the present disclosure.

[0037] Although the terms "first", "second", etc. are used to explain various components, the components are not limited by such terms. These terms are only used to distinguish one component from another.

[0038] Furthermore, it should be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, the element can be directly on the other element, or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements. Furthermore, when an element is referred to as being "on" or "above" a reference element, the element can be located "above" or "below" the reference element, and the element is not necessarily located "on" or "above" in a direction opposite to gravity.

[0039] Throughout the specification, the terms "include" or "have" are intended to list the presence of stated features, quantities, steps, operations, components, parts, or combinations thereof, but do not exclude the presence or addition of one or more other features, quantities, steps, operations, components, parts, and / or combinations thereof. Therefore, unless explicitly described to the contrary, the word "include" and variations such as "comprises" or "comprising" will be understood to imply the inclusion of the stated elements without excluding any other elements.

[0040] Furthermore, throughout the specification, the phrase “in a plan view” or “on a plane” means observing a target portion from the top, and the phrase “in a cross-sectional view” or “on a cross section” means observing a cross section formed by vertically cutting the target portion from the side.

[0041] Throughout the specification, the term "connected" not only indicates that two or more constituent components are directly connected, but also may indicate that two or more constituent components are indirectly connected through another constituent component. It not only indicates a physical connection, but also may indicate an electrical connection. It may also indicate a situation where constituent components are indicated by different names due to their positions or functions, but are actually integrated.

[0042] In the following, reference will be made to Figures 1 to 3 A multilayer ceramic capacitor according to an embodiment is described.

[0043] Figure 1 is a perspective view showing a multilayer ceramic capacitor according to an embodiment. Figure 2 It is along Figure 1 A cross-sectional view of a multilayer ceramic capacitor taken along line II' in FIG. Figure 3 It is along Figure 1 A cross-sectional view of a multilayer ceramic capacitor taken along line II-II' in FIG.

[0044] Figures 1 to 3 The L-axis direction, W-axis direction, and T-axis direction shown in represent the length direction, width direction, and thickness direction of the capacitor body 110, respectively. Here, the thickness direction (T-axis direction) may be a direction perpendicular to the wide surface (main surface) of the sheet component, and, for example, may be used as the same concept as the stacking direction of the stacked dielectric layer 111. The length direction (L-axis direction) may be a direction extending parallel to the wide surface (main surface) of the sheet component and approximately perpendicular to the thickness direction (T-axis direction). For example, the length direction (L-axis direction) may be a direction in which the first external electrode 131 and the second external electrode 132 are opposite to each other. The width direction (W-axis direction) may be a direction extending parallel to the wide surface (main surface) of the sheet component and approximately perpendicular to the thickness direction (T-axis direction) and the length direction (L-axis direction). The length of the sheet component in the length direction (L-axis direction) may be longer than the length of the sheet component in the width direction (W-axis direction).

[0045] Reference Figures 1 to 3 , the multilayer ceramic capacitor 100 according to the embodiment includes a capacitor body 110 and external electrodes 131 and 132 disposed on the capacitor body 110. The external electrodes 131 and 132 may include a first external electrode 131 and a second external electrode 132 disposed at opposite ends of the capacitor body 110 in the length direction (L-axis direction).

[0046] For example, the capacitor body 110 may have a substantially hexahedral shape.

[0047] For the convenience of describing the embodiments, two surfaces of the capacitor body 110 that are opposite to each other in the thickness direction (T-axis direction) are referred to as the first surface and the second surface, two surfaces of the capacitor body 110 that are connected to the first surface and the second surface and are opposite to each other in the length direction (L-axis direction) are referred to as the third surface and the fourth surface, and two surfaces of the capacitor body 110 that are connected to the first surface and the second surface and connected to the third surface and the fourth surface and are opposite to each other in the width direction (W-axis direction) are referred to as the fifth surface and the sixth surface.

[0048] As an example, the first surface as the lower surface may be a mounting surface. In addition, the first to sixth surfaces may be flat, but the embodiment is not limited thereto. For example, the first to sixth surfaces may be curved surfaces having a convex central portion, and the edge of each surface (boundary between surfaces) may be rounded.

[0049] The shape and size of the capacitor body 110 and the stacked number of the dielectric layers 111 are not limited to those shown in the drawings of the embodiment.

[0050] The capacitor body 110 includes a plurality of dielectric layers 111 and internal electrode layers (or referred to as internal electrodes) 121 and 122. Specifically, the capacitor body 110 includes a plurality of dielectric layers 111 and first internal electrodes 121 and second internal electrodes 122, the first internal electrodes 121 and the second internal electrodes 122 are alternately arranged in the thickness direction (T-axis direction), and the dielectric layer 111 is interposed between the first internal electrodes 121 and the second internal electrodes 122.

[0051] At this time, the adjacent dielectric layers 111 of the capacitor body 110 may be integrated to such an extent that it is difficult to identify a boundary therebetween without using a scanning electron microscope (SEM).

[0052] The capacitor body 110 may have an active region. The active region is a region where the dielectric layer 111 and the internal electrode layers 121 and 122 are alternately arranged and contributes to forming the capacity of the multilayer ceramic capacitor 100. Specifically, the active region may be a region where the first internal electrode 121 and the second internal electrode 122 stacked in the thickness direction (T-axis direction) overlap each other.

[0053] In addition, the capacitor body 110 may further include a cover portion and a side edge portion.

[0054] The covering portion is a thickness direction edge portion and may be located on the upper and lower surfaces of the active region in the thickness direction (T-axis direction) respectively. The covering portion may be a single dielectric layer 111 or two or more dielectric layers 111 stacked on the upper and lower surfaces of the active region respectively.

[0055] The side edge portion may be considered as a side surface covering portion, and may be located on side surfaces (i.e., surfaces corresponding to the fifth surface and the sixth surface) of the active region that are opposite to each other in the width direction (W-axis direction). The side edge portion may be formed by coating the conductive paste for the internal electrode on the surface of the dielectric green sheet only in a partial region of the surface of the dielectric green sheet without coating the conductive paste on both sides of the surface of the dielectric green sheet in the width direction, and then stacking and firing the obtained dielectric green sheets, but is not limited thereto.

[0056] The covering portion and the side margin portion serve to prevent damage to the first and second internal electrodes 121 and 122 due to physical stress and / or chemical stress.

[0057] According to the embodiment, the dielectric layer 111 is referred to Figure 4 to describe.

[0058] Figure 4 is a schematic diagram illustrating dielectric grains and grain boundaries within a dielectric layer according to an embodiment.

[0059] Reference Figure 4 , the dielectric layer 111 according to the embodiment includes a plurality of dielectric grains 10 and grain boundaries 20 between dielectric grains 10 adjacent to each other.

[0060] The dielectric crystal grains 10 include a barium titanate-based main component including barium (Ba) and titanium (Ti).

[0061] The barium titanate-based main component is a dielectric base material, has a high dielectric constant, and contributes to forming the capacitance of the multilayer ceramic capacitor 100 .

[0062] The barium titanate-based main component may include, for example, BaTiO3, Ba(Ti,Zr)O3, Ba(Ti,Sn)O3, (Ba,Ca)TiO3, (Ba,Ca)(Ti,Ca)O3, (Ba,Ca)(Ti,Zr)O3, (Ba,Ca)(Ti,Sn)O3, (Ba,Sr)TiO3, (Ba,Sr)(Ti,Zr)O3, (Ba,Sr)(Ti,Zr)O3, (Ba,Sr)(Ti,Sn)O3 or combinations thereof.

[0063] The grain boundary 20 may include silicon (Si), dysprosium (Dy), and terbium (Tb), and may have a wall shape.

[0064] The component existing in the grain boundary 20 may be a subcomponent dissolved in the barium titanate-based main component as the dielectric matrix material.

[0065] It is generally known that in order to improve reliability, the grain size of the dielectric in the dielectric layer must be small and the number must be large. In addition, reliability characteristics are achieved by controlling the addition amount of additives (i.e., transition metal elements of fixed valence acceptors and variable valence acceptors and rare earth elements serving as donors) and optimizing the composition ratio. However, even if the same additive composition is used, completely different reliability characteristics may be exhibited depending on the dispersion state and arrangement form of the additives in the dielectric material.

[0066] According to the embodiment, since the components of silicon (Si), dysprosium (Dy) and terbium (Tb) exist in the grain boundary 20, not only the interface reliability between the dielectric grains 10 but also the interface reliability between the dielectric layer and the internal electrode layer can be enhanced. The above components are subcomponents solid-dissolved in the barium titanate-based main component as the dielectric matrix material, and the concentration phenomenon of these components to the interface can be induced by controlling the depth of solid solution. Therefore, when the components Si, Dy and Tb exist in the grain boundary 20 located in the interface between the dielectric grains 10, since the interface reliability is enhanced, a multilayer ceramic capacitor with excellent density and high thin layer reliability can be ensured.

[0067] Silicon (Si) can enhance interface resistance by increasing the Schottky barrier of the interface by existing in the grain boundary 20. Dysprosium (Dy) and terbium (Tb) are rare earth elements and can improve high temperature accelerated life and reliability.

[0068] These components may be included in the order of terbium (Tb) < dysprosium (Dy) < silicon (Si) in the grain boundary 20. Including silicon (Si), dysprosium (Dy) and terbium (Tb) in the above order of content in the grain boundary 20 not only enhances the interface reliability between the dielectric grains 10, but also enhances the interface reliability between the dielectric layer and the internal electrode layer, and can improve density and thin layer reliability.

[0069] In more detail, the contents of silicon (Si), dysprosium (Dy), and terbium (Tb) in the grain boundary 20 may represent the molar contents of silicon (Si), dysprosium (Dy), and terbium (Tb) in the grain boundary 20. For example, in the grain boundary 20, the sum of the contents of dysprosium (Dy) and terbium (Tb) may be greater than 0.9 molar parts and less than 2.0 molar parts, for example, 1.0 molar parts to 1.9 molar parts, based on 100 molar parts of titanium (Ti). When the sum of the contents of dysprosium (Dy) and terbium (Tb) in the grain boundary 20 is within the above range, the density and thin layer reliability of the multilayer ceramic capacitor may be improved due to enhanced interface reliability.

[0070] In the grain boundary 20, silicon (Si) may be included in an amount of 1.3 to 2.5 parts by mole, for example, 1.35 to 2.40 parts by mole, for example, 1.35 to 2.25 parts by mole, based on 100 parts by mole of titanium (Ti). When silicon (Si) included in the grain boundary 20 is within the above content range, interface reliability may be enhanced, density control may become easy, a high dielectric constant may be ensured, and thus density and thin layer reliability of the multilayer ceramic capacitor may be improved.

[0071] In the grain boundary 20, dysprosium (Dy) may be included in an amount of 0.6 to 1.6 parts by mole, for example, 0.7 to 1.5 parts by mole, for example, 0.80 to 1.45 parts by mole, based on 100 parts by mole of titanium (Ti). When dysprosium (Dy) is included in the grain boundary 20 within the above content range, it provides an appropriate level of electron emission as a donor, and a phenomenon that excess electrons emitted when it is solid-dissolved in the dielectric matrix material combine with oxygen vacancies to hinder the movement of oxygen defects does not occur, and thus interface reliability can be enhanced, thereby ensuring a multilayer ceramic capacitor with excellent density and thin layer reliability.

[0072] In the grain boundary 20, terbium (Tb) may be included in an amount of 0.1 to 0.5 parts by mole, for example, 0.20 to 0.48 parts by mole, based on 100 parts by mole of titanium (Ti). When terbium (Tb) is included in the grain boundary 20 in this content range, an appropriate level of electron emission can be achieved as a donor, interface reliability can be enhanced, and thus a multilayer ceramic capacitor having excellent density and thin layer reliability can be ensured.

[0073] In the grain boundary 20, the molar ratio of terbium (Tb) to dysprosium (Dy) may be 0.3 to 0.8, for example, 0.31 to 0.60. When the molar ratio of terbium (Tb) to dysprosium (Dy) in the grain boundary 20 is within the above range, interface reliability may be enhanced, and thus a multilayer ceramic capacitor having excellent density and thin layer reliability may be ensured.

[0074] In the grain boundary 20, the atomic ratio of dysprosium (Dy) to silicon (Si) may be greater than 0.4 and less than 1.0. When the atomic ratio of dysprosium (Dy) to silicon (Si) in the grain boundary 20 is within the above range, the density and thin layer reliability of the multilayer ceramic capacitor may be improved due to enhanced interface reliability.

[0075] In the grain boundary 20, the atomic ratio of terbium (Tb) to silicon (Si) may be greater than 0.4 and less than 1.0. When the atomic ratio of terbium (Tb) to silicon (Si) in the grain boundary 20 is within the above range, the density and thin layer reliability of the multilayer ceramic capacitor may be improved due to enhanced interface reliability.

[0076] The grain boundary 20 may further include tin (Sn). Since tin (Sn) exists in the grain boundary 20, low-temperature density and effective capacity may be increased.

[0077] In the grain boundary 20, tin (Sn) may be included in an amount of 0.5 to 2.5 parts by mole, for example, 0.7 to 2.3 parts by mole, based on 100 parts by mole of titanium (Ti). When the tin (Sn) included in the grain boundary 20 is within the above range, the low temperature density and effective capacity of the multilayer ceramic capacitor may be increased, and the reliability may be improved.

[0078] The presence of the grain boundaries 20 and the contents of Si, Dy, Tb, and Sn in the grain boundaries 20 can be confirmed by transmission electron microscopy-energy dispersive spectroscopy (TEM-EDS) analysis.

[0079] In more detail, the multilayer ceramic capacitor 100 is placed in an epoxy resin mixture and cured, the W-axis direction and T-axis direction surfaces (WT surfaces) of the capacitor body 110 are polished to a depth of 1 / 2 of the capacitor body 110 in the L-axis direction, and then the multilayer ceramic capacitor 100 is fixed and maintained in a vacuum atmosphere chamber, and a cross-sectional sample of an effective area where the dielectric layer 111 and the internal electrode layers 121 and 122 overlap can be obtained. Subsequently, the effective area of ​​the cross-sectional sample can be measured by using a transmission electron microscope (TEM). The transmission electron microscope can be measured by using a focused ion beam (Xe-FIB) under conditions of an acceleration voltage of 200kV and a magnification of 225k times, and the cross-sectional sample can be measured so that at least one layer (for example, 1 to 10 layers) of the dielectric layer 111 can be visible. Subsequently, in the transmission electron microscope (TEM) image of the measured cross-sectional sample, it can be confirmed by EDS analysis that the grain boundary 20 exists and has a thickness, and the contents of Si, Dy, Tb, and Sn in the grain boundary 20 can be confirmed. Even if not described in the present disclosure, other methods and / or other tools understood by one of ordinary skill in the art may be used.

[0080] Generally, in order to achieve high reliability characteristics, the insulation resistance characteristics have been controlled by applying various additive elements to the fine matrix material and changing the interface and grain boundary resistance characteristics of the dielectric layer and the inner electrode layer. That is, in order to improve the withstand voltage characteristics and reliability of the dielectric material (when only additive elements (such as, for preventing the oxidation of the inner electrode layer during the firing process, the anti-reduction enhancement elements, the transition metal elements used as fixed valence acceptors for improving the insulation characteristics, the rare earth elements used as donors) are added, the withstand voltage characteristics and reliability of the dielectric material are insufficient), the variable valence acceptors are combined in appropriate contents, and then sintering aids are added to adjust their solid solution characteristics and sintering temperature. Most of these additive elements are doped into the dielectric material and solid-dissolved in the shell region of the BaTiO3 matrix material grains to form a core-shell structure.

[0081] In contrast, the dielectric grains 10 in the dielectric layer 111 according to the embodiment do not have a special boundary portion that distinguishes the core and the shell, and the dielectric layer 111 may include the dielectric grains 10 and the grain boundaries 20. The dielectric grains 10 according to the embodiment may be considered to be a further expanded form of the core region in the core-shell structure of the existing grains. In addition, in the embodiment, the portion corresponding to the shell region of the existing core-shell structure (which affects reliability improvement by dissolving various additive elements) is reduced, which may reduce the reliability within the grain, but due to the grain boundaries 20 including Si, Dy and Tb, the grain boundary reliability (reliability within the grain) may be enhanced.

[0082] In more detail, the diameter d of the dielectric grain 10 according to the embodiment may account for 60% to 90%, for example, 70% to 90% of the sum of the diameter d of the dielectric grain 10 and the thickness t of the grain boundary 20. For example, the diameter d of the dielectric grain may be 80nm to 120nm, for example, 85nm to 115nm. When the diameter d of the dielectric grain 10 is within the above range, the grain boundary reliability and the interface reliability may be high and the withstand voltage characteristics may be excellent.

[0083] The diameter d of the dielectric grains 10 can be determined by TEM analysis.

[0084] When the multilayer ceramic capacitor 100 is placed in an epoxy resin mixture and cured, the W-axis and T-axis surfaces (WT surfaces) of the capacitor body 110 are polished to a depth of 1 / 2 of the capacitor body 110 in the L-axis direction, and then fixed and maintained in a vacuum atmosphere chamber, a cross-sectional sample of an effective area where the dielectric layer 111 and the inner electrode layers 121 and 122 overlap can be observed can be obtained. Subsequently, the effective area of ​​the cross-sectional sample can be measured by using a transmission electron microscope (TEM). The transmission electron microscope can be measured by using a focused ion beam (Xe-FIB) under conditions of an acceleration voltage of 200kV and a magnification of 225k times, and the cross-sectional sample can be measured so that at least one layer (e.g., 1 to 10 layers) of the dielectric layer 111 can be visible. The diameter of the dielectric grain 10 can be obtained by measuring the maximum principal axis of at least one (e.g., 2-20) dielectric grains 10 from the TEM image of the cross-sectional sample and taking the average thereof. Even if not described in the present disclosure, other methods and / or other tools understood by a person of ordinary skill in the art can also be used.

[0085] The size D50 of the dielectric grains 10 may be 300 nm or less, for example, 280 nm or less. When the size D50 of the dielectric grains 10 is within the above range, grain boundary reliability and interface reliability may be high and withstand voltage characteristics may be excellent.

[0086] The size D50 of the dielectric grains 10 may be measured by measuring the long axes of at least 100 dielectric grains in a transmission electron microscope (TEM) image of a cross-sectional sample, creating a cumulative curve of size distribution, and calculating D50. Even if not described in the present disclosure, other methods and / or other tools understood by a person of ordinary skill in the art may be used. D50 may represent the size at the 50% point of the cumulative curve of size distribution.

[0087] The thickness t of the grain boundary 20 may be 10 nm to 100 nm, for example, 20 nm to 90 nm. When the thickness t of the grain boundary 20 is within the above range, the grain boundary reliability and the interface reliability may be high and the withstand voltage characteristics may be excellent.

[0088] The thickness t of the grain boundary 20 may be an average value of thicknesses at at least 10 points of the grain boundary 20 in a transmission electron microscope (TEM) image of a cross-sectional sample. Even if not described in the present disclosure, other methods and / or other tools understood by those skilled in the art may be used.

[0089] The average thickness of the dielectric layer 111 according to the embodiment may be 0.3 μm to 0.6 μm, for example, 0.35 μm to 0.55 μm. When the average thickness of the dielectric layer 111 is within the above range, a highly reliable thin-layer multilayer ceramic capacitor may be ensured.

[0090] The average thickness of the dielectric layer 111 can be measured by placing the multilayer ceramic capacitor 100 in an epoxy resin mixture and then curing it, polishing it, and then ion milling it, and then performing a scanning electron microscope (SEM) analysis. For example, a Verios G4 product from Thermo Fisher Scientific can be used as a scanning electron microscope, the measurement conditions can be 10kV, 0.2nA, the magnification can be 100 times, and the measurement can be performed so that 1 layer or more (for example, 3 layers or more layers, 5 layers or more layers, or 10 layers or more layers) of the dielectric layer 111 are visible. In the scanning electron microscope (SEM) image, the central point of the dielectric layer 111 in the length direction (L axis direction) or the width direction (W axis direction) is taken as a reference point, and the arithmetic average of the thickness of the dielectric layer 111 can be obtained for 10 points of the dielectric layer 111 that are set at a predetermined interval from the reference point. The intervals between the 10 points are adjusted according to the scale of the SEM image, for example, 1µm to 100µm, 1µm to 50µm, or 1µm to 10µm. At this time, all 10 points must be located within the dielectric layer 111, and if all 10 points are not located within the dielectric layer 111, the position of the reference point may be changed, or the intervals between the 10 points may be adjusted. Even if not described in the present disclosure, other methods and / or other tools understood by those of ordinary skill in the art may be used.

[0091] The first inner electrode 121 and the second inner electrode 122 are electrodes having different polarities, which are alternately arranged opposite to each other along the T-axis direction with a dielectric layer interposed between the first inner electrode 121 and the second inner electrode 122, and the first inner electrode 121 and the second inner electrode 122 may have ends exposed through the third surface and the fourth surface of the capacitor body 110, respectively.

[0092] The first and second internal electrodes 121 and 122 may be electrically insulated from each other by a dielectric layer 111 disposed therebetween.

[0093] Ends of the first and second internal electrodes 121 and 122 alternately exposed through the third and fourth surfaces of the capacitor body 110 may be electrically connected to the first and second external electrodes 131 and 132 , respectively.

[0094] The first and second internal electrodes 121 and 122 may include a conductive metal, for example, a metal such as Ni, Cu, Ag, Pd, Au, or an alloy thereof such as an Ag—Pd alloy.

[0095] In addition, the first and second internal electrodes 121 and 122 may include dielectric grains having the same composition as the ceramic material included in the dielectric layer 111 .

[0096] The first and second internal electrodes 121 and 122 may be formed using a conductive paste including a conductive metal. A printing method of the conductive paste may be a screen printing method or a gravure printing method.

[0097] The average thickness of the first internal electrode 121 and the second internal electrode 122 may be 0.1 μm to 2 μm. The average thickness of the first internal electrode 121 and the second internal electrode 122 may be measured by SEM analysis. Here, since the method for measuring the average thickness of the internal electrodes is the same as the method for measuring the average thickness of the dielectric layer 111 described above, a description thereof will be omitted.

[0098] The capacitor body 110 may be formed by firing a laminated body in which a plurality of dielectric layers 111 and a plurality of internal electrode layers 121 and 122 are stacked.

[0099] The first and second external electrodes 131 and 132 are supplied with voltages of different polarities and may be coupled and electrically connected to exposed portions of the first and second internal electrodes 121 and 122 , respectively.

[0100] According to the above configuration, when a predetermined voltage is applied to the first external electrode 131 and the second external electrode 132, charges are accumulated between the first internal electrode 121 and the second internal electrode 122 facing each other. At this time, the capacitance of the multilayer ceramic capacitor 100 is proportional to the overlapping area in which the first internal electrode 121 and the second internal electrode 122 overlap each other along the T-axis direction in the active region.

[0101] The first outer electrode 131 may include a first connecting portion arranged on the third surface of the capacitor body 110 and connected to the first inner electrode 121, and a first band portion arranged at the edge where the third surface of the capacitor body 110 intersects with the first and second surfaces and / or the fifth and sixth surfaces of the capacitor body 110, and the second outer electrode 132 may include a second connecting portion arranged on the fourth surface of the capacitor body 110 and connected to the second inner electrode 122, and a second band portion arranged at the edge where the fourth surface of the capacitor body 110 intersects with the first and second surfaces and / or the fifth and sixth surfaces of the capacitor body 110.

[0102] The first band portion may extend from the first connection portion to a portion of the first surface and a portion of the second surface and / or a portion of the fifth surface and a portion of the sixth surface of the capacitor body 110, and the second band portion may extend from the second connection portion to a portion of the first surface and a portion of the second surface and / or a portion of the fifth surface and a portion of the sixth surface of the capacitor body 110. The first band portion and the second band portion may be used to improve the bonding strength of the first external electrode 131 and the second external electrode 132 to the capacitor body 110, respectively.

[0103] Each of the first and second external electrodes 131 and 132 may include a sintered metal layer contacting the capacitor body 110 , a conductive resin layer disposed to cover the sintered metal layer, and a plated layer disposed to cover the conductive resin layer.

[0104] The sintered metal layer may include conductive metal and glass.

[0105] The conductive metal may include at least one of copper (Cu), nickel (Ni), silver (Ag), palladium (Pd), gold (Au), platinum (Pt), tin (Sn), tungsten (W), titanium (Ti) and lead (Pb). For example, the sintered metal layer including copper (Cu) may mean including copper (Cu) single substance and / or copper (Cu) alloy. When the conductive metal includes copper, a metal other than copper may be included in an amount of 5 mol parts or less relative to 100 mol parts of copper.

[0106] The glass may include a composition of oxides (e.g., one or more selected from the group consisting of silicon oxide, boron oxide, aluminum oxide, transition metal oxides, alkali metal oxides, and alkaline earth metal oxides). The transition metal may be at least one selected from the group consisting of zinc (Zn), titanium (Ti), copper (Cu), vanadium (V), manganese (Mn), iron (Fe), and nickel (Ni), the alkali metal may be at least one selected from the group consisting of lithium (Li), sodium (Na), and potassium (K), and the alkaline earth metal may be at least one selected from the group consisting of magnesium (Mg), calcium (Ca), strontium (Sr), and barium (Ba).

[0107] Alternatively, the conductive resin layer may be formed on the sintered metal layer, for example, may be formed in a shape that completely covers the sintered metal layer. In addition, the first and second external electrodes 131 and 132 may not include the sintered metal layer, and in this case, the conductive resin layer may directly contact the capacitor body 110.

[0108] The conductive resin layer extends to the first and second surfaces and / or the fifth and sixth surfaces of the capacitor body 110, and the length of the region (i.e., the band portion) where the conductive resin layer extends and is provided to the first and second surfaces and / or the fifth and sixth surfaces of the capacitor body 110 may be longer than the length of the region (i.e., the band portion) where the sintered metal layer extends and is provided to the first and second surfaces and / or the fifth and sixth surfaces of the capacitor body 110. That is, the conductive resin layer may be formed on the sintered metal layer, and may be formed in a shape that completely covers the sintered metal layer.

[0109] The conductive resin layer may include resin and conductive metal.

[0110] The resin included in the conductive resin layer may be implemented by a material having adhesiveness and impact absorption and capable of forming a paste when mixed with the conductive metal powder, but is not limited thereto. For example, the resin may include phenolic resin, acrylic resin, silicone resin, epoxy resin, or polyimide resin.

[0111] The conductive metal included in the conductive resin layer serves to be electrically connected to the first and second internal electrodes 121 and 122 or the sintered metal layer.

[0112] The conductive metal included in the conductive resin layer may have a spherical shape, a flake shape, or a combination thereof. That is, the conductive metal may be formed only in a flake form, or only in a spherical form, or in a mixed form of a flake form and a spherical form.

[0113] Here, the spherical shape may also include a shape that is not a perfect spherical shape, for example, a shape in which the length ratio of the major axis to the minor axis (major axis / minor axis) is less than or equal to 1.45. The flake shape refers to a flat and elongated shape, and is not particularly limited, for example, the length ratio of the major axis to the minor axis (major axis / minor axis) may be greater than or equal to 1.95.

[0114] The first and second external electrodes 131 and 132 may further include a plating layer disposed outside the conductive resin layer.

[0115] The plating layer may include a single nickel (Ni), copper (Cu), tin (Sn), palladium (Pd), platinum (Pt), gold (Au), silver (Ag), tungsten (W), titanium (Ti) or lead (Pb) or an alloy thereof. For example, the plating layer may be a nickel (Ni) plating layer or a tin (Sn) plating layer, or may be a form in which a nickel (Ni) plating layer and a tin (Sn) plating layer are stacked in sequence, or may be a form in which a tin (Sn) plating layer, a nickel (Ni) plating layer and a tin (Sn) plating layer are stacked in sequence. In addition, the plating layer may include a plurality of nickel (Ni) plating layers and / or a plurality of tin (Sn) plating layers.

[0116] The plating layer may improve the mountability to a substrate, structural reliability, durability to the outside, heat resistance, and equivalent series resistance (ESR) of the multilayer ceramic capacitor 100 .

[0117] Hereinafter, a method of manufacturing the multilayer ceramic capacitor 100 according to an embodiment will be described.

[0118] The multilayer ceramic capacitor 100 according to the embodiment can be manufactured according to the following steps: preparing a dielectric slurry by mixing a barium titanate-based main component powder with a subsidiary component powder including a silicon (Si)-containing compound, a dysprosium (Dy)-containing compound, and a terbium (Tb)-containing compound; preparing a dielectric green sheet by using the dielectric slurry, and forming a conductive paste layer on the surface of the dielectric green sheet; manufacturing a dielectric green sheet laminate by stacking the dielectric green sheets on which the conductive paste layer is formed; manufacturing a capacitor body including a dielectric layer and an inner electrode layer by firing the dielectric green sheet laminate; and forming an outer electrode on the surface of the capacitor body.

[0119] First, a dielectric slurry is prepared by mixing a barium titanate-based main component powder with sub-component powders including a silicon (Si)-containing compound, a dysprosium (Dy)-containing compound, and a terbium (Tb)-containing compound.

[0120] The barium titanate-based main component powder may be prepared by mixing a titanium (Ti) precursor and a barium (Ba) precursor.

[0121] The titanium (Ti) precursor may be an oxide, a salt, an alkoxide, etc. of titanium, and may include, for example, titanium dioxide, titanium diisopropyl diacetylacetonate (TPA), titanium alkoxide, or a combination thereof.

[0122] The barium (Ba) precursor may include BaO 2 , BaTiO 3 , BaCO 3 , BaO, or a combination thereof.

[0123] The titanium (Ti) precursor and the barium (Ba) precursor may be mixed in a molar ratio of 1:0.5 to 1:1.5.

[0124] Subcomponent powders such as silicon (Si)-containing compounds, dysprosium (Dy)-containing compounds, and terbium (Tb)-containing compounds may be oxides, nitrides, or salt compounds, or may be used in the form of a sol dispersed in an organic solvent.

[0125] The subcomponent powder may include a silicon-containing (Si) compound in an amount of 1.3 to 2.5 parts by mole (e.g., 1.35 to 2.40 parts by mole) of silicon based on 100 parts by mole of titanium (Ti). When the silicon-containing (Si) compound is used within the above content range, interface reliability may be enhanced, thereby improving density and thin layer reliability of a multilayer ceramic capacitor.

[0126] The auxiliary component powder may include a dysprosium (Dy) compound in an amount of 0.6 to 1.6 parts by mole (e.g., 0.7 to 1.5 parts by mole) of dysprosium based on 100 parts by mole of titanium (Ti). When the dysprosium (Dy) compound is used within the above content range, interface reliability may be enhanced, thereby improving density and thin layer reliability of a multilayer ceramic capacitor.

[0127] The auxiliary component powder may include a terbium (Tb) compound in an amount of 0.1 to 0.5 parts by mole (e.g., 0.20 to 0.48 parts by mole) of terbium based on 100 parts by mole of titanium (Ti). When the terbium (Tb) compound is used within the above content range, interface reliability may be enhanced, thereby improving density and thin layer reliability of a multilayer ceramic capacitor.

[0128] The subsidiary component powder may further include a tin (Sn)-containing compound (or referred to as a fourth compound).

[0129] The subcomponent powder may include a tin (Sn) compound in an amount of 0.5 to 2.5 parts by mole (e.g., 0.7 to 2.3 parts by mole) of tin based on 100 parts by mole of titanium (Ti). When the tin (Sn) compound is used within the above content range, interface reliability may be enhanced, thereby improving density and thin layer reliability of the multilayer ceramic capacitor.

[0130] In addition, the dielectric slurry may be prepared by further mixing additives such as a dispersant, a binder, a plasticizer, a lubricant, and an antistatic agent and a solvent.

[0131] For example, the dispersant may include a phosphate dispersant, a polycarboxylic acid dispersant, or a combination thereof. Based on 100 parts by weight of the barium titanate-based main component powder, 0.1 to 5 parts by weight of the dispersant may be mixed, for example, 0.3 to 3 parts by weight of the dispersant may be mixed. When the mixed dispersant is within the above content range, the dielectric slurry exhibits excellent dispersibility and can reduce the amount of impurities included in the manufactured dielectric layer.

[0132] For example, the binder may be an acrylic resin, a polyvinyl butyl resin, a polyvinyl acetal resin, an ethyl cellulose resin, etc. Based on 100 parts by weight of the barium titanate-based main component powder, the binder may be added in an amount of 0.1 parts by weight to 50 parts by weight (e.g., 3 parts by weight to 30 parts by weight). When the mixed binder is within the above content range, the dielectric slurry exhibits excellent dispersibility and the amount of impurities included in the manufactured dielectric layer may be reduced.

[0133] For example, the plasticizer may be: a phthalic acid compound such as dioctyl phthalate, butyl benzyl phthalate, dibutyl phthalate, dihexyl phthalate, di(2-ethylhexyl) phthalate, and di(2-ethylbutyl) phthalate; an adipic acid compound such as dihexyl adipate and di(2-ethylhexyl) adipate; a glycol compound such as ethylene glycol, diethylene glycol, and triethylene glycol; a glycol ester compound such as triethylene glycol dibutyrate, triethylene glycol di(2-ethylbutyrate), and triethylene glycol di(2-ethylhexanoate); etc. The plasticizer may be added in an amount of 0.1 to 20 parts by weight (e.g., 1 to 10 parts by weight) based on 100 parts by weight of the barium titanate-based main component powder. When the plasticizer is mixed within the above content range, the dielectric slurry shows excellent dispersibility, and the amount of impurities included in the manufactured dielectric layer may be reduced.

[0134] The solvent may be an aqueous solvent such as water; an alcohol solvent such as ethanol, methanol, benzyl alcohol and methoxyethanol; a glycol solvent such as ethylene glycol and diethylene glycol; a ketone solvent such as acetone, methyl ethyl ketone, methyl isobutyl ketone and cyclohexanone; an ester solvent such as butyl acetate, ethyl acetate, carbitol acetate and butyl carbitol acetate; an ether solvent such as methyl cellosolve, ethyl cellosolve, butyl ether and tetrahydrofuran; an aromatic solvent such as benzene, toluene and xylene. Considering the solubility or dispersibility of various additives included in the dielectric slurry, the solvent may be, for example, an alcohol solvent or an aromatic solvent. Based on 100 parts by weight of the barium titanate-based main component powder, a solvent in an amount of 50 parts by weight to 1000 parts by weight (e.g., 100 parts by weight to 500 parts by weight) may be mixed. When the mixed solvent is within the above content range, the dielectric slurry components may be fully mixed and the solvent may be easily removed later.

[0135] The barium titanate-based main component powder and the auxiliary component powder can be mixed by using a wet ball mill or a stirring mill. When zirconia balls are used in a wet ball mill, a plurality of zirconia balls having a diameter of 0.1 mm to 10 mm can be used for wet mixing for 8 to 48 hours, for example, 10 to 24 hours.

[0136] The prepared dielectric slurry forms a dielectric layer after firing.

[0137] As a method for forming the prepared dielectric slurry into a sheet, a belt forming method such as a doctor blade method, a calender roll method, etc. can be used. For example, the prepared dielectric slurry can be formed into a molded body using a roller molding coater using a manifold discharge method, and then a dielectric green sheet can be obtained by drying the molded body.

[0138] In order to form a conductive paste layer that becomes an internal electrode layer after firing, the conductive paste can be prepared by mixing a conductive powder made of a conductive metal or its alloy, a binder, and a solvent. In addition, if necessary, barium titanate powder can be mixed together as a co-material (i.e., the same material as the material of the dielectric layer). The co-material can play a role in suppressing sintering of the conductive powder during the firing process. The conductive paste layer is formed by applying the conductive paste to the surface of the dielectric green sheet in a prescribed pattern using various printing methods such as screen printing or transfer methods.

[0139] The conductive powder may include nickel (Ni) or a nickel (Ni) alloy.

[0140] Next, a dielectric green sheet laminate is prepared by stacking a plurality of dielectric green sheets on which internal electrode patterns are formed and then pressing the plurality of dielectric green sheets in a stacking direction. At this time, dielectric green sheets on which internal electrode patterns are not formed may be stacked so that the dielectric green sheets are located on the upper and lower surfaces of the dielectric green sheet laminate in the stacking direction.

[0141] A step of cutting the prepared dielectric green sheet laminate into a predetermined size by dicing or the like may be selectively performed.

[0142] Furthermore, if necessary, the dielectric green sheet stack may be cured and dried to remove the plasticizer and the like, and after curing and drying, the dielectric green sheet stack may be barrel polished using a horizontal centrifugal drum machine and the like. In barrel polishing, the dielectric green sheet stack is placed in a drum container having a medium and a polishing liquid, and a rotational motion or vibration is applied to the drum container, so that unnecessary portions (such as burrs generated during cutting) may be polished. Furthermore, after barrel polishing, the dielectric green sheet stack may be washed with a cleaning solution (such as water) and dried.

[0143] Subsequently, a capacitor body can be prepared after a binder removal treatment and firing of the dielectric green sheet laminate.

[0144] The conditions for adhesive removal may be appropriately adjusted according to the composition of the dielectric layer and / or the composition of the inner electrode layer. For example, the heating rate during the adhesive removal process may be 5° C. / hour to 300° C. / hour, the support body temperature may be 180° C. to 400° C., and the temperature holding time may be 0.5 hour to 24 hours. The treatment atmosphere for adhesive removal may be an air atmosphere or a reducing atmosphere.

[0145] The conditions of the firing process may be appropriately adjusted according to the main component composition of the dielectric layer and / or the main component composition of the inner electrode. For example, the firing may be performed at a temperature of 1100° C. to 1400° C., for example, the firing may be performed at a temperature of 1200° C. to 1350° C. In addition, the firing may be performed for 0.5 hours to 8 hours, for example, 1 hour to 3 hours. In addition, the firing may be performed in a reducing atmosphere (for example, in a humidified mixed gas of nitrogen and hydrogen). When the inner electrode includes nickel (Ni) or a nickel (Ni) alloy, the oxygen partial pressure in the firing atmosphere may be 1.0×10 -14 MPa to 1.0x10 -10 MPa.

[0146] After firing, annealing may be performed as needed. Annealing is a process for reoxidizing the dielectric layer, and annealing may be performed if firing is performed in a reducing atmosphere. The conditions of the annealing process may also be appropriately adjusted according to the composition of the dielectric layer. For example, the annealing temperature may be 950°C to 1150°C, the time may be 0 to 20 hours, and the heating rate may be 50°C / hour to 500°C / hour. The annealing atmosphere may be a humidified nitrogen (N2) atmosphere, and the oxygen partial pressure may be 1.0x10 -9 MPa to 1.0x10 - 5 MPa.

[0147] In the binder removal process, the firing process or the annealing process, for example, a wetting agent may be used to wet the nitrogen gas or the mixed gas. In this case, the wetting agent temperature may be 5° C. to 75° C. The binder removal process, the firing process and the annealing process may be performed sequentially or independently.

[0148] Optionally, the third surface and the fourth surface of the capacitor body 110 may be subjected to surface treatment (such as sandblasting, laser irradiation, barrel polishing, etc.). By performing the surface treatment, the end of the first inner electrode and the end of the second inner electrode may be exposed to the third surface and the fourth surface, respectively, so that the electrical connection between the first outer electrode and the first inner electrode and the electrical connection between the second outer electrode and the second inner electrode may be improved, and the alloy portion may be easily formed.

[0149] Subsequently, external electrodes are formed on the surface of the manufactured capacitor body 110 .

[0150] As an example, a paste for forming a sintered metal layer may be coated on the surface of the manufactured capacitor body and then sintered to form the sintered metal layer.

[0151] The paste for forming the sintered metal layer may include conductive metal and glass. Since the description of the conductive metal and glass is the same as that of the conductive metal and glass described above, repeated description will be omitted. In addition, the paste for forming the sintered metal layer may optionally include a binder, a solvent, a dispersant, a plasticizer, an oxide powder, etc. The binder may be, for example, ethyl cellulose, acrylic acid, butyral, etc., and the solvent may be, for example, an organic solvent (such as, terpineol, butyl carbitol, ethanol, methyl ethyl ketone, acetone, toluene, etc.) or an aqueous solvent.

[0152] Methods of coating the paste for forming the sintered metal layer on the outer surface of the capacitor body 110 may include a dipping method, various printing methods (such as a screen printing method), a coating method using a dispenser, etc., and a spraying method using a sprayer. The paste for forming the sintered metal layer may be applied to at least the third and fourth surfaces of the capacitor body 110, and optionally to portions of the first, second, fifth, and / or sixth surfaces on which the band portions of the first external electrode and the band portions of the second external electrode are to be formed.

[0153] Thereafter, the capacitor body 110 coated with the paste for forming the sintered metal layer is dried and sintered at a temperature of 700° C. to 1000° C. for 0.1 hour to 3 hours to form a sintered metal layer.

[0154] Alternatively, a paste for forming a conductive resin layer is applied on the outer surface of the obtained capacitor body 110 and then cured to form a conductive resin layer.

[0155] The paste for forming the conductive resin layer may include a resin and a conductive metal, and optionally, may also include a non-conductive filler. Since the description of the conductive metal and the resin is the same as that of the conductive metal and the resin described above, repeated descriptions will be omitted. In addition, the paste for forming the conductive resin layer may optionally include a binder, a solvent, a dispersant, a plasticizer, an oxide powder, etc. The binder may be, for example, ethyl cellulose, acrylic acid, butyral, etc., and the solvent may be an organic solvent (such as terpineol, butyl carbitol, ethanol, methyl ethyl ketone, acetone, and toluene) or an aqueous solvent.

[0156] For example, the conductive resin layer may be formed by immersing the capacitor body 110 in a paste for forming the conductive resin layer and then curing it, or by printing the paste for forming the conductive resin layer on the surface of the capacitor body 110 by screen printing or gravure printing, or by applying the paste for forming the conductive resin layer to the surface of the capacitor body 110 and then curing it.

[0157] Next, a plating layer may be formed on the outside of the conductive resin layer.

[0158] For example, the plated layer can be formed by plating, sputtering, or electrolytic plating (electrodeposition).

[0159] The above embodiment will be described in more detail by the following examples. However, the following examples are only for illustrative purposes and do not limit the scope of the appended claims.

[0160] (Manufacture of multilayer ceramic capacitors) Examples 1 to 13, Comparative Examples 1 and 2, and Reference Examples 1 to 6 The dielectric slurry was prepared by mixing a main component powder of barium titanate (BaTiO3) and auxiliary component powders of silicon dioxide (SiO2), dysprosium oxide (Dy2O3), terbium oxide (Tb2O3), and tin oxide (SnO2) in the composition of Table 1 below, wherein the main component powder of barium titanate (BaTiO3) was prepared by mixing BaCO3 powder and TiO2 powder. At this time, each auxiliary component powder was mixed in an amount based on 100 parts by mole of TiO2 powder. At this time, mixing was performed by using zirconium oxide balls (ZrO2 balls) as a dispersion medium, wherein ethanol / toluene and polyvinyl butyral (PVB) resin were added as a wet dispersant and a binder and mechanical grinding was performed.

[0161] A dielectric green sheet was prepared by using a manifold discharge type roll-on coating machine on the produced dielectric slurry.

[0162] The dielectric green sheet laminate is manufactured by printing a conductive paste including nickel (Ni) on the surface of a dielectric green sheet to form a conductive paste layer and stacking and pressing the dielectric green sheets on which the conductive paste layer is formed.

[0163] The dielectric green sheet stack is subjected to a degreasing treatment at 400° C. or lower in a nitrogen atmosphere, and then fired at a firing temperature of 1300° C. or lower and a hydrogen (H 2 ) concentration of 1.0% or lower.

[0164] Subsequently, a multilayer ceramic capacitor is manufactured through an external electrode forming process such as plating or the like.

[0165] (Table 1) The unit is molar parts based on TiO2, that is, based on 100 molar parts of Ti in TiO2.

[0166]

[0167] Evaluation 1: TEM-EDS analysis The multilayer ceramic capacitor manufactured in Example 1 was subjected to transmission electron microscopy-energy dispersive spectroscopy (TEM-EDS) analysis, and the results are shown in FIG. 5A to FIG. 5C and Table 2 below.

[0168] The TEM-EDS analysis was carried out as follows. The multilayer ceramic capacitor fabricated in Example 1 was placed in an epoxy resin mixture and cured. The surfaces of the capacitor body 110 in the W-axis direction and the T-axis direction (WT surfaces) were polished to a depth of 1 / 2 of the capacitor body 110 in the L-axis direction, and then it was fixed and held in a vacuum atmosphere chamber, thereby obtaining a cross-sectional sample of the effective region where the dielectric layer and the internal electrode layers were stacked. The effective region of the cross-sectional sample was measured using TEM. The effective region of the cross-sectional sample was measured using a focused ion beam (Xe-FIB) under the conditions of an acceleration voltage of 200 kV and a magnification of 225 k times, such that at least one layer in the dielectric layer could be visible.

[0169] Through the transmission electron microscope (TEM) image of the measured cross-sectional sample, the dielectric grains and grain boundaries were confirmed (see Figure 5A ), and the contents of Si, Dy, Tb, and Sn present in the grain boundaries were confirmed by EDS analysis of the TEM image (see Figure 5B and Figure 5C ).

[0170] Figure 5A is a TEM image of a part of the dielectric layer according to Example 1. Figure 5B is Figure 5A a TEM-EDS analysis image of a part of the dielectric layer in Figure 5C is Figure 5A an EDS line analysis curve graph of the part indicated by the arrow in

[0171] Through EDS line analysis, in the part indicated in Figure 5B , that is, in the part including dielectric grains and grain boundaries, for the line segment connected by a straight line from the starting point to the ending point, the atomic % of each component was confirmed.

[0172] In Figure 5C , the region from about 25 nm to about 35 nm corresponds to the grain boundary, and the subsequent region of about 120 nm corresponds to the dielectric grains. Referring to Figure 5C , it can be confirmed that in the grain boundaries within the dielectric layer according to the embodiment, the components Tb, Dy, and Si exist in the order of Tb < Dy < Si in terms of content.

[0173] Evaluation 2: Permittivity For the multilayer ceramic capacitors fabricated in Examples 1 to 13, Comparative Examples 1 and 2, and Reference Examples 1 to 6, the dielectric constant (permittivity) was measured under the conditions of 1 kHz and 0.5 V, and the results are shown in Table 2 below.

[0174] Evaluation 3: Reliability For the multilayer ceramic capacitors manufactured in Examples 1 to 13, Comparative Examples 1 and 2, and Reference Examples 1 to 6, the mean time to failure in hours (hr) (i.e., mean time to failure (MTTF)) at which failures occurred was obtained by measuring under the conditions of a temperature of 125°C and a voltage of 9.45 V, and the results are shown in Table 2 below.

[0175] In Table 2 below, ○ indicates that the mean time to failure is 10 hours or longer, △ indicates that the mean time to failure is greater than or equal to 5 hours and less than 10 hours, and X indicates that the mean time to failure is less than 5 hours.

[0176] Evaluation 4: Density For the multilayer ceramic capacitors manufactured in Examples 1 to 14, Comparative Examples 1 and 2, and Reference Examples 1 to 9, the number of pores in the dielectric layer was confirmed by performing scanning electron microscope (SEM) analysis, and the results are shown in Table 2 below.

[0177] The SEM analysis was performed as follows. The multilayer ceramic capacitors manufactured in Examples 1 to 14, Comparative Examples 1 and 2, and Reference Examples 1 to 9 were placed in an epoxy resin mixture and cured, the surfaces in the W-axis direction and T-axis direction (WT surfaces) of the capacitor body were polished to a point that is 1 / 2 of the capacitor body in the L-axis direction, and then it was fixed and held in a vacuum atmosphere chamber to obtain a cross-sectional sample of the effective region where the dielectric layer and the inner electrode layer are stacked. Subsequently, measurement was performed by a scanning electron microscope (SEM) such that a region with a size of approximately 2 µm × 2 µm could be obtained in the effective region of the cross-sectional sample so that at least three layers in the dielectric layer are visible. For example, for the SEM, the Verios G4 product of Thermo Fisher Scientific was used, and the measurement conditions were 10 kV and 0.2 nA.

[0178] In Table 2 below, ○ indicates that the number of pores observed is less than 5, △ indicates that the number of pores observed is greater than or equal to 5 and less than 10, and X indicates that the number of pores observed is greater than or equal to 10.

[0179] (Table 2) The unit is the mole fraction based on 100 mole fractions of titanium (Ti).

[0180]

[0181] From Table 2 above, it can be seen that in the case of Examples 1 to 13 where the components Tb, Dy, and Si are present in the grain boundaries of the dielectric layer in the content order of Tb < Dy < Si, the dielectric constant, reliability, and density are all high compared to Comparative Examples 1 and 2 that do not satisfy this content order.

[0182] While the present disclosure has been described in connection with what are presently considered to be practical embodiments, it should be understood that the present disclosure is not limited to the disclosed embodiments, but on the contrary is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A multilayer ceramic capacitor comprising: a capacitor body including a dielectric layer and an inner electrode layer; as well as An external electrode is disposed on the capacitor body, The dielectric layer includes a plurality of dielectric grains and grain boundaries between adjacent dielectric grains. wherein the plurality of dielectric grains include a barium titanate-based main component including barium and titanium, wherein the grain boundaries include silicon, dysprosium and terbium, and The molar contents of silicon, dysprosium and terbium included in the grain boundaries are arranged in the order of terbium < dysprosium < silicon.

2. The multilayer ceramic capacitor according to claim 1, wherein In the grain boundary, the sum of the content of dysprosium and the content of terbium is greater than 0.9 parts by mole and less than 2.0 parts by mole based on 100 parts by mole of titanium.

3. The multilayer ceramic capacitor according to claim 1, wherein In the grain boundaries, silicon is included in an amount of 1.3 parts by mol to 2.5 parts by mol based on 100 parts by mol of titanium.

4. The multilayer ceramic capacitor according to claim 1, wherein In the grain boundary, dysprosium is included in an amount of 0.6 parts by mol to 1.6 parts by mol based on 100 parts by mol of titanium.

5. The multilayer ceramic capacitor according to claim 1, wherein In the grain boundary, terbium is included in an amount of 0.1 to 0.5 parts by mol based on 100 parts by mol of titanium.

6. The multilayer ceramic capacitor according to claim 1, wherein In the grain boundaries, the molar ratio of terbium to dysprosium is from 0.3 to 0.

8.

7. The multilayer ceramic capacitor according to claim 1, wherein: In the grain boundaries, an atomic ratio of dysprosium to silicon is greater than 0.4 and less than 1.

0.

8. The multilayer ceramic capacitor according to claim 1, wherein In the grain boundaries, an atomic ratio of terbium to silicon is greater than 0.4 and less than 1.

0.

9. The multilayer ceramic capacitor according to claim 1, wherein: The grain boundaries also include tin.

10. The multilayer ceramic capacitor according to claim 9, wherein In the grain boundary, tin is included in an amount of 0.5 parts by mol to 2.5 parts by mol based on 100 parts by mol of titanium.

11. The multilayer ceramic capacitor according to claim 1, wherein A diameter of a dielectric grain among the plurality of dielectric grains is 60% to 90% of a sum of a diameter of the dielectric grain and a thickness of the grain boundary.

12. The multilayer ceramic capacitor according to claim 1, wherein A diameter of a dielectric grain in the plurality of dielectric grains is 80 nm to 120 nm.

13. The multilayer ceramic capacitor according to claim 1, wherein The plurality of dielectric grains have a size D50 of 300 nm or less.

14. The multilayer ceramic capacitor according to claim 1, wherein The thickness of the grain boundary is 10 nm to 100 nm.

15. The multilayer ceramic capacitor according to claim 1, wherein The average thickness of the dielectric layer is 0.3µm to 0.6µm.

16. The multilayer ceramic capacitor according to claim 1, wherein In the grain boundaries, silicon is included in an amount of 1.3 to 2.5 parts by mole based on 100 parts by mole of titanium, dysprosium is included in an amount of 0.6 to 1.6 parts by mole based on 100 parts by mole of titanium, and terbium is included in an amount of 0.1 to 0.5 parts by mole based on 100 parts by mole of titanium.

17. A method for manufacturing a multilayer ceramic capacitor, the method comprising: preparing a dielectric slurry by mixing a barium titanate-based main component powder with a subsidiary component powder including a silicon-containing compound, a dysprosium-containing compound, and a terbium-containing compound; preparing a dielectric green sheet using the dielectric slurry, and forming a conductive paste layer on a surface of the dielectric green sheet; manufacturing a dielectric green sheet laminate by stacking a plurality of the dielectric green sheets on which the conductive paste layers are formed; manufacturing a capacitor body including a plurality of dielectric layers and a plurality of internal electrode layers by firing the dielectric green sheet laminate; and forming external electrodes on a surface of the capacitor body, The dielectric layer includes a plurality of dielectric grains and grain boundaries between adjacent dielectric grains. wherein the plurality of dielectric grains include a barium titanate-based main component including barium and titanium, wherein the grain boundaries include silicon, dysprosium and terbium, and The molar contents of silicon, dysprosium and terbium included in the grain boundaries are arranged in the order of terbium < dysprosium < silicon.

18. The manufacturing method according to claim 17, wherein: The barium titanate-based main component powder is prepared by mixing a titanium precursor and a barium precursor, and Wherein, based on 100 parts by mole of the titanium precursor containing titanium, in the auxiliary component powder: silicon in an amount of 1.3 parts by mole to 2.5 parts by mole, The dysprosium-containing compound includes dysprosium in an amount of 0.6 parts by mole to 1.6 parts by mole, and The terbium-containing compound is comprised of terbium in an amount of 0.1 parts by mole to 0.5 parts by mole.

19. The manufacturing method according to claim 17, wherein: The auxiliary component powder further includes a tin-containing compound.

20. The manufacturing method according to claim 19, wherein: The barium titanate-based main component powder is prepared by mixing a titanium precursor and a barium precursor, and The sub-component powder includes the tin-containing compound in an amount of 0.5 to 2.5 parts by mol of tin based on 100 parts by mol of the titanium precursor including titanium.

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