Packaging body, preparation method and storage system

Abstract

The invention provides a packaging body, a preparation method and a storage system. The packaging body comprises a plastic packaging body, a circuit layer and a first interconnection structure. The plastic package body comprises a first surface and a second surface which are opposite in a first direction; the circuit layer comprises a first circuit layer and a second circuit layer which are respectively arranged on the first surface and the second surface; the first interconnection structure penetrates through the plastic package body in the first direction and is connected with the first circuit layer and the second circuit layer, the first interconnection structure comprises a first end face and a second end face which are opposite in the first direction, and the size of the first end face is the same as that of the second end face.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more specifically, to a package, a method for preparing a package, and a storage system. Background Art

[0002] Chip packaging is an important aspect of modern semiconductor miniaturization. Multiple integrated circuits are packed into a single package to achieve the integration of homogeneous or heterogeneous chips. For example, memory chips and control logic units can be integrated into a single package to reduce the space occupied by the device and improve the performance of the device while achieving lower manufacturing costs. In advanced packaging, various interposer technologies such as silicon-based interposers based on through-silicon vias and glass interposers are increasingly being used. Summary of the invention

[0003] The present application provides a package, a method for preparing the package, and a storage system that can at least partially solve the problems existing in the related art.

[0004] On the one hand, the present application provides a package body, including: a plastic package body, including a first surface and a second surface opposite to each other in a first direction; a circuit layer, including a first circuit layer and a second circuit layer respectively arranged on the first surface and the second surface; a first interconnection structure, penetrating the plastic package body along the first direction and connected to the first circuit layer and the second circuit layer respectively, wherein the first interconnection structure includes a first end face and a second end face opposite to each other in the first direction, and the size of the first end face is the same as the size of the second end face.

[0005] In one embodiment of the present application, an extension length L of the first interconnect structure in the first direction and a dimension D of an end surface of the first interconnect structure satisfy: 20≤L / D≤30.

[0006] In one embodiment of the present application, adjacent first interconnect structures have a spacing Sp in a plane perpendicular to the first direction, wherein 40 μm≤Sp≤120 μm.

[0007] In one embodiment of the present application, the package body also includes a device structure encapsulated in the plastic package body, wherein the device structure includes at least one of a passive device and an active device, the passive device includes at least one of a resistor, a capacitor and an inductor; and the active device includes a memory chip.

[0008] In one embodiment of the present application, the memory chip includes at least one of a non-volatile memory chip and a volatile memory chip, wherein the non-volatile memory chip includes at least one of a three-dimensional NAND memory chip, a three-dimensional NOR memory chip, a ferroelectric memory chip, and a phase change memory chip.

[0009] In one embodiment of the present application, the device structure is directly bonded to the first circuit layer or the second circuit layer; or a connection layer is provided between the device structure and the first circuit layer or the second circuit layer, wherein the connection layer includes a bonding layer.

[0010] In one embodiment of the present application, a fixing structure is provided between the device structure and one of the first circuit layer and the second circuit layer; and a second interconnection structure is provided between the device structure and the other of the first circuit layer and the second circuit layer.

[0011] In one embodiment of the present application, the package body further includes a wire bonding pad, and the wire bonding pad is located in the first circuit layer or the second circuit layer, wherein the first end surface or the second end surface is connected to the wire bonding pad.

[0012] In one embodiment of the present application, the first circuit layer includes a third surface away from the plastic package body, and the second circuit layer includes a fourth surface away from the plastic package body; and the package body also includes an electrical connection structure configured to be connected to an external circuit, wherein the electrical connection structure is arranged on at least one of the third surface and the fourth surface.

[0013] In one embodiment of the present application, the electrical connection structure includes at least one of a solder ball, a metal bump, a bonding structure and a conductive adhesive structure.

[0014] In one embodiment of the present application, the adapter board package further includes a package high-speed interface exposed outside the plastic package to connect to an external circuit.

[0015] In one embodiment of the present application, the first interconnect structure includes a metal line.

[0016] On the other hand, the present application provides a method for preparing a package, comprising: forming a first circuit layer and a wire bonding pad, wherein the wire bonding pad is located on the surface of the first circuit layer and is connected to the first circuit layer; forming a plastic package and a first interconnection structure connected to the wire bonding pad on the first circuit layer, wherein the first interconnection structure extends along a first direction and penetrates the plastic package; and forming a second circuit layer connected to the first interconnection structure on the plastic package, wherein the first interconnection structure includes a first end face and a second end face opposite to each other in the first direction, and the size of the first end face is the same as the size of the second end face.

[0017] In one embodiment of the present application, forming a plastic package body on the first circuit layer and a first interconnect structure connected to the wire bonding pad includes: forming the first interconnect structure having a predetermined extension length on the first circuit layer; forming an initial plastic package body that at least covers the first interconnect structure; and thinning the initial plastic package body to expose the end surface of the first interconnect structure to form the plastic package body, wherein the predetermined extension length of the first interconnect structure is determined based on a predetermined thickness of the package body in the first direction.

[0018] In one embodiment of the present application, forming a first interconnect structure connected to the wire bonding pad on the first circuit layer includes: forming the first interconnect structure by using a vertical wire bonding process.

[0019] In one embodiment of the present application, the first circuit layer includes a third surface away from the plastic package body, and the second circuit layer includes a fourth surface away from the plastic package body, and the method further includes: on at least one of the third surface and the fourth surface, an electrical connection structure connected to an external circuit is provided, wherein the electrical connection structure includes at least one of a solder ball, a metal bump, a bonding structure and a conductive adhesive structure.

[0020] In one embodiment of the present application, a device structure is formed in the plastic package, wherein the device structure includes at least one of a passive device and an active device, the passive device includes at least one of a resistor, a capacitor and an inductor; and the active device includes a memory chip.

[0021] In one embodiment of the present application, the device structure is connected to the first circuit layer or the second circuit layer by direct bonding; or a connecting layer is provided between the device structure and the first circuit layer, or between the device structure and the second circuit layer, wherein the connecting layer includes a bonding layer.

[0022] In one embodiment of the present application, a fixed structure is arranged between the device structure and the first circuit layer, and a second interconnection structure is arranged between the device structure and the second circuit layer; or a fixed structure is arranged between the device structure and the second circuit layer, and a second interconnection structure is arranged between the device structure and the first circuit layer.

[0023] On the other hand, the present application provides a storage system, including: a controller and a memory, wherein the controller is coupled to the memory to control the memory to store data, and at least one of the controller and the storage wire bonder is located in a package as described in any one of the aspects of the present application.

[0024] According to at least one embodiment of the present application, the package, the method for preparing the package, and the storage system provided, the package includes a plastic package, a circuit layer, and a first interconnection structure, wherein the circuit layer includes a first circuit layer and a second circuit layer (upper and lower circuit layers) located on opposite surfaces of the plastic package, and the first interconnection structure can penetrate the plastic package and connect with the upper and lower circuit layers. The two end faces of the first interconnection structure opposite to each other along the extension direction have the same size. In other words, the key size consistency of the interconnection lines connecting the upper and lower circuit layers in the package is high; in addition, the size of the interconnection lines and the spacing between the interconnection lines are improved, so that the space and area of ​​the spacing area of ​​the interconnection lines and their surroundings are reduced, the density and compatibility of the overall circuit layout of the package are improved, the complexity of the packaging process is reduced, and the requirements of thin and short electronic products can be met. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings, in which:

[0026] Figure 1 is a schematic diagram of a cross-sectional structure of a package body according to an embodiment of the present application;

[0027] Figure 2 yes Figure 1 The enlarged schematic diagram of point A in the middle;

[0028] Figure 3 yes Figure 2 A schematic cross-sectional view taken along line BB' at point A shown;

[0029] Figure 4 is a schematic diagram of a cross-sectional structure of a package body according to an embodiment of the present application;

[0030] Figure 5 is a schematic diagram of a cross-sectional structure of a package body according to an embodiment of the present application;

[0031] Figure 6 is a schematic diagram of a cross-sectional structure of a package body according to an embodiment of the present application;

[0032] Figure 7 is a flow chart of a method for preparing a package according to one embodiment of the present application;

[0033] Figure 8-Figure 14 is a schematic cross-sectional structure diagram of a semiconductor packaging structure according to an embodiment of the present application; and

[0034] Fig.15 It is a schematic diagram of the storage system structure according to one embodiment of the present application. DETAILED DESCRIPTION

[0035] In order to better understand the present application, a more detailed description will be made of various aspects of the present application with reference to the accompanying drawings. It should be understood that these detailed descriptions are only descriptions of exemplary embodiments of the present application, and are not intended to limit the scope of the present application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0036] It should be noted that in this specification, the expressions first, second, third, etc. are only used to distinguish one feature from another feature area, and do not represent any limitation on the features, especially do not represent any order of precedence. Therefore, without departing from the teaching of this application, the first surface discussed in this application may also be referred to as the second surface, and vice versa.

[0037] In the drawings, the thickness, size and shape of the components have been slightly adjusted for ease of illustration. The drawings are for illustration only and are not drawn strictly to scale. As used herein, the terms "substantially," "approximately," and similar terms are used as terms of approximation, not as terms of degree, and are intended to account for the inherent deviations in measurements or calculations that would be recognized by one of ordinary skill in the art.

[0038] It should also be understood that expressions such as "include", "including", "have", "contain" and / or "comprising" are open rather than closed expressions in this specification, which indicate the presence of the stated features, elements and / or components, but do not exclude the presence of one or more other features, elements, components and / or combinations thereof. In addition, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features rather than just the individual elements in the list. In addition, when describing embodiments of the present application, "may" is used to mean "one or more embodiments of the present application". And, the term "exemplary" is intended to refer to an example or illustration.

[0039] Unless otherwise specified, all words (including engineering terms and scientific and technological terms) used in this article have the same meaning as those commonly understood by ordinary technicians in the field to which this application belongs. It should also be understood that, unless clearly stated in this application, words defined in common dictionaries should be interpreted as having the same meaning as their meaning in the context of the relevant technology, and should not be interpreted in an idealized or overly formal sense.

[0040] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. In addition, unless explicitly limited or contradictory to the context, the specific steps included in the method described in the present application are not necessarily limited to the order described, but can be performed in any order or in parallel. The present application will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.

[0041] In addition, in the present application, when “connected” or “coupled” is used, it may indicate direct contact or indirect contact between corresponding components, unless otherwise clearly defined or inferred from the context.

[0042] Figure 1 is a schematic cross-sectional structure diagram of a package body 1000 according to an embodiment of the present application. Figure 2 yes Figure 1 A magnified schematic diagram of point A in the middle.

[0043] like Figure 1 and Figure 2 As shown, the package body 1000 provided in the present application may include: a plastic package body 100, a circuit layer 200 and a first interconnection structure 300. The plastic package body 100 includes a first surface 110 and a second surface 120 opposite to each other in a first direction (z direction). The circuit layer 200 includes a first circuit layer 201 and a second circuit layer 202, wherein the first circuit layer 201 is arranged on the first surface 110, and the second circuit layer 202 is arranged on the second surface 120. The first interconnection structure 300 penetrates the plastic package body 100 along the z direction, and is connected to the first circuit layer 201 and the second circuit layer 202 respectively, wherein the first interconnection structure 300 includes a first end face 310 and a second end face 320 opposite to each other in the z direction, and the first end face 310 and the second end face 320 have the same size. In other words, the key dimensions of the interconnection lines connecting the upper and lower circuit layers in the package are highly consistent; in addition, the dimensions of the interconnection lines and the spacing between the interconnection lines have been improved, thereby reducing the space and area of ​​the interconnection lines and the spacing areas around them, improving the density and compatibility of the overall circuit layout of the package, reducing the complexity of the packaging process, and meeting the needs of electronic products to be light, thin and short.

[0044] It can be understood that the first end face 310 and the second end face 320 are cross-sections of the first interconnect structure 300 perpendicular to the z direction, and the same size of the first end face 310 and the second end face 320 can be understood as the first end face 310 and the second end face 320 have the same shape and the same area. It should be noted that those skilled in the art know that The terms "same" and "equal" should be used It is understood to be completely identical and completely equal as well as approximately the same and within the range of process or measurement error. Basically equal.

[0045] Specifically, as electronic products develop towards miniaturization, high performance, and high reliability, the system integration is also increasing. In this case, the way to improve performance by further reducing the feature size of integrated circuits and the line width of interconnects is limited by the physical properties of materials and equipment processes, and the traditional Moore's Law has been difficult to continue to develop. At present, advanced packaging methods include: wafer-level chip scale packaging, fan-out wafer-level packaging, flip chip, stacked packaging, etc. The 2.5D / 3D integration technology with TSV (Through Silicon Via) as the core has been considered an effective way to break Moore's Law.

[0046] Usually, a 2.5D / 3D package includes a silicon adapter plate with TSV, and a conductive column is formed in the TSV hole of the silicon adapter plate to serve as an interconnection column to interconnect the chip and the substrate. Among them, the TSV hole can be formed by, for example, a deep reactive ion etching process; the barrier layer and the seed layer can be made by, for example, a physical vapor deposition process; the conductive column is formed by, for example, an electroplating or sputtering process, and metal materials such as copper, aluminum, nickel, gold, silver, and titanium are used; and the excess metal material is removed and the substrate is thinned by, for example, chemical mechanical polishing. However, the silicon adapter plate formed by the above method has a large size of the interconnection column and a large spacing between the interconnection columns, so that the interconnection column and the spacing area around it occupy a large space and area, affecting the miniaturization of the packaging structure; in addition, the above steps may also cause the metal material such as copper in the TSV hole to diffuse into the substrate, ultimately resulting in a reduction in the performance of the entire package.

[0047] According to the package provided by at least one embodiment of the present application, the package may include a plastic package, a circuit layer and a first interconnection structure, wherein the circuit layer includes a first circuit layer and a second circuit layer (upper and lower circuit layers) located on opposite surfaces of the plastic package, and the first interconnection structure may penetrate the plastic package and be connected to the upper and lower circuit layers. The two end faces of the first interconnection structure opposite to each other along the extension direction have the same size. In other words, the key size consistency of the interconnection lines connecting the upper and lower circuit layers in the package is high; in addition, the size of the interconnection lines and the spacing between the interconnection lines are improved, so that the space and area of ​​the spacing area of ​​the interconnection lines and their surroundings are reduced, the density and compatibility of the overall circuit layout of the package are improved, the complexity of the packaging process is reduced, and the requirements of thin and short electronic products can be met.

[0048] In addition, the first interconnect structure can also be formed by, for example, a vertical wire bonding process, which will be described in detail below in conjunction with the accompanying drawings. The vertical wire bonding process is used to replace the above-mentioned etching, sputtering and electroplating processes to form the first interconnect structure, which can reduce the complexity and preparation cost of the packaging process, while significantly reducing the key dimensions of the first interconnect structure such as the end face dimensions and the spacing between adjacent first interconnect structures, and significantly improving the aspect ratio and consistency of the first interconnect structure.

[0049] Figure 3 yes Figure 2 The schematic cross-sectional view taken along line BB' at point A is shown.

[0050] Alternatively, if Figure 1-Figure 3 As shown, in one embodiment of the present application, the extension length L of the first interconnect structure 300 in the z direction and the dimension D of the end surface of the first interconnect structure 300 satisfy: 20≤L / D (aspect ratio)≤30.

[0051] Optionally, in one embodiment of the present application, adjacent first interconnect structures 300 have a spacing Sp in a plane (xy plane) perpendicular to the z direction, wherein 40 μm≤Sp≤120 μm.

[0052] Optionally, in one embodiment of the present application, the sizes of the end faces of the first interconnect structure 300 at various locations in the z direction are all equal, wherein the end face of the first interconnect structure 300 is a cross section of the first interconnect structure 300 in a plane parallel to the xy plane. In other words, the shapes of the end faces of the first interconnect structure 300 at various locations in the z direction are all the same and the areas are all equal.

[0053] Optionally, the first end surface 310 of the first interconnect structure 300 is flush with the first surface 110 of the plastic package 100 in the z direction relative to the same reference plane, and the second end surface 320 of the first interconnect structure 300 is flush with the second surface 120 of the plastic package 100 in the z direction relative to the same reference plane, so that the first end surface 310 of the first interconnect structure 300 contacts the conductive part of the first circuit layer 201, and the second end surface 320 of the first interconnect structure 300 contacts the conductive part of the second circuit layer 202. It should be noted that, due to process limitations, the error range of "flush with respect to the same reference plane" can be between -10% and 10%. In addition, in this article Figure 1-Figure 3 In the figure, only the number and position of the first interconnection structure in the package are shown by way of example. However, it can be understood that the package and the first interconnection structure shown in the figures and related contents of this article are only shown for the convenience of illustration, and the present application is not limited thereto. In actual applications, multiple packages can be included as needed, and each package and the first interconnection structure therein can be set.

[0054] Figure 4 is a schematic cross-sectional structure diagram of a package body 1000 according to an embodiment of the present application. Figure 5 is a schematic cross-sectional structure diagram of a package body 1000 according to an embodiment of the present application. Figure 6 is a schematic cross-sectional structure diagram of a package body 1000 according to an embodiment of the present application.

[0055] Take the interposer as an example. In advanced packaging, the interposer that only has the interconnection function is increasingly unable to meet the requirements of advanced electronic products. Figure 4-Figure 6 As shown, in one embodiment of the present application, the package body 1000 including the adapter board may include a device structure 400 encapsulated in the plastic package body 100, wherein the device structure 400 may include at least one of a passive device 401 and an active device 402, the passive device 401 may include at least one of a resistor, a capacitor and an inductor; and the active device 402 may include a memory chip.

[0056] Specifically, the adapter board used in advanced packaging will integrate the corresponding passive modules to meet the electrical performance requirements of miniaturized electronic products. This will naturally form a variety of passive module integration methods to achieve the integration of passive modules on the adapter board. Taking the silicon adapter board as an example, as an option, the TSV interconnection structure can be first made in the front-end process, and then the passive module can be made on the surface of the adapter board. The passive module made by this integration method has high Q (Quality factor) and high quality, but the integration cost is high; as another option, the passive module on the adapter board can be made in the back-end process, and then the TSV interconnection structure can be made, and both are made on the same side of the adapter board. The passive module made by this method is difficult to have high Q and high quality, which may lead to reduced reliability of the passive module and difficult preparation process.

[0057] In some embodiments of the present application, the passive device 401 and the active device 402 may be pre-embedded in the plastic package 100. Due to the accuracy of the parameters of the process such as photolithography used for pre-embedded passive devices and active devices, and the strictness of the process for preparing the pre-embedded passive devices and active devices, the passive devices and active devices with high precision and good reliability can be manufactured.

[0058] For example, the passive module may include at least one of a resistor, a capacitor, and an inductor, an array composed of resistors, capacitors, or inductors, and filters, couplers, and power dividers composed of resistors, capacitors, and inductors. The active device may include a memory chip. Optionally, the memory chip may include at least one of a non-volatile memory chip and a volatile memory chip, wherein the non-volatile memory chip may include at least one of a three-dimensional NAND memory chip, a three-dimensional NOR memory chip, a ferroelectric memory chip, and a phase change memory chip.

[0059] Among them, the capacitor can adopt a metal-insulator-metal structure (Metal-Insulator-Metal, MIM). The capacitor includes a first plate, a second plate and a dielectric layer located between the first plate and the second plate. The first plate and the second plate can be formed by, for example, metal electrode deposition, and the dielectric layer can be formed by physical vapor deposition (Physical Vapor Deposition, PVD) or chemical vapor deposition (Chemical Vapor Deposition, CVD) and the like. The material of the dielectric layer may include silicon nitride, silicon dioxide or ceramics. The inductor can be composed of, for example, a metal coil, and the metal coil can be formed by electroplating or metal sputtering. In addition, active devices such as memory chips can be formed by existing processes and pre-buried in the plastic package, which will not be described in detail in this application.

[0060] Combination Figure 1 , Figure 4-Figure 6 In one embodiment of the present application, the plastic package 100 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride or high-k dielectric.

[0061] Optionally, the first circuit layer 201 and the second circuit layer 202 may include but are not limited to a redistribution layer. It should be noted that, for ease of understanding, the structure of the semiconductor device will be described below by taking the first circuit layer and the second circuit layer as redistribution layers as an example. However, the first circuit layer and the second circuit layer being redistribution layers are only exemplary demonstrations and are not used to limit the first circuit layer and the second circuit layer of the present application. In actual applications, the first circuit layer and the second circuit layer can be set according to specific actual needs and process conditions. It can be understood by those skilled in the art that since the content involved in the structure and preparation process of the redistribution layer described below can be fully or partially applicable to the first circuit layer and the second circuit layer formed by other structures, the content related or similar thereto will not be repeated.

[0062] The first circuit layer 201 may include at least one first inorganic dielectric layer 201-2 and at least one first metal wiring layer 201-1 stacked in the z direction, wherein the first inorganic dielectric layer 201-2 and the first metal wiring layer 201-1 are alternately arranged, and the first circuit layer 201 uses inorganic dielectric materials as insulating materials to be configured as a wiring layer based on inorganic materials, which can reduce the line spacing in the first circuit layer 201; similarly, the second circuit layer 202 may include at least one second inorganic dielectric layer 202-2 and at least one second metal wiring layer 202-1 stacked in the z direction, wherein the second inorganic dielectric layer 202-2 and the second metal wiring layer 202-1 are alternately arranged, and the second circuit layer 202 uses inorganic dielectric materials as insulating materials to be configured as a wiring layer based on inorganic materials, which can reduce the line spacing in the second circuit layer 202.

[0063] The material of the first metal wiring layer 201-1 or the second metal wiring layer 202-1 may include one or a combination of two or more of copper, aluminum, nickel, gold, silver, and titanium. The material of the first inorganic dielectric layer 201-2 or the second inorganic dielectric layer 202-2 may include one or a combination of two or more of silicon nitride, silicon oxide, epoxy resin, silica gel, polyimide, and benzocyclobutene. The second metal wiring layer 202-1 may be prepared from the same material as the first metal wiring layer 201-1, or from a different material, which is not limited in the present application. The second inorganic dielectric layer 202-2 may be prepared from the same material as the first inorganic dielectric layer 201-2, or from a different material, which is not limited in the present application. As an option, the first inorganic dielectric layer 201-2 includes a silicon nitride layer, and the second inorganic dielectric layer 202-2 includes a silicon oxide layer.

[0064] As described above, the first interconnect structure 300 may be formed by, for example, a vertical wire bonding process. Optionally, the material of the first interconnect structure 300 may include one or a combination of two or more of copper, aluminum, nickel, gold, silver, and titanium.

[0065] refer to Figure 4-Figure 5 As an option, the device structure 400 and the first circuit layer 201 or the second circuit layer 202 may be directly bonded to each other; as another option, a connection layer 24 may be provided between the device structure 400 and the first circuit layer 201 or the second circuit layer 202, wherein the connection layer 24 may include a bonding layer.

[0066] For example, the second circuit layer 202 has a first main surface and a second main surface that are arranged opposite to each other, wherein the first main surface is connected to the second surface 120 of the plastic package 100. The connecting layer 24 or the device structure 400 is encapsulated in the plastic package 100 and has a surface that is exposed and flush with the second surface 120, and the surface and the second surface 120 of the plastic package 100 are connected to the first main surface of the second circuit layer 202 together, for electrically coupling the device structure 400 to the first main surface of the first circuit layer 201.

[0067] Optionally, refer to Figure 1 and Figure 4 , a hybrid bonding method can be used to achieve electrical connection between the device structure 400 in the plastic package 100 and the first circuit layer 201 or the second circuit layer 202. It should be noted that the thickness and position of the connection layer 24 and the shape of the device structure 400 given in the above embodiment are only exemplary demonstrations and are not used to limit the connection layer in this application. In actual applications, the device structure or the connection layer can be set according to specific actual process conditions.

[0068] Optionally, device structures 400 such as passive devices 401 and active devices 402 can be directly bonded to the second circuit layer 202 and electrically connected to the second metal wiring layer 202-1; in addition, they can also be electrically connected to the first metal wiring layer 201-1 through the first interconnect structure 300.

[0069] Alternatively, device structures 400 such as passive devices 401 and active devices 402 may be directly bonded to the first circuit layer 201 and electrically connected to the first metal wiring layer 201 - 1 ; in addition, electrical connection to the second metal wiring layer 202 - 1 may be achieved through the first interconnect structure 300 .

[0070] Optionally, refer to Figure 1 and Figure 5 , device structures 400 such as passive devices 401 and active devices 402 can be electrically connected to the second metal wiring layer 202-1 through the connection layer 24; and can be electrically connected to the first metal wiring layer 201-1 through the connection layer 24 and the first interconnect structure 300.

[0071] Alternatively, device structures 400 such as passive devices 401 and active devices 402 can be electrically connected to the first metal wiring layer 201 - 1 through the connection layer 24 ; and can be electrically connected to the second metal wiring layer 202 - 1 through the connection layer 24 and the first interconnect structure 300 .

[0072] refer to Figure 1 and Figure 6 As another option, a fixing structure 25 may be provided between the device structure 400 and one of the first circuit layer 201 and the second circuit layer 202 ; and a second interconnection structure 26 may be provided between the device structure 400 and the other of the first circuit layer 201 and the second circuit layer 202 .

[0073] Optionally, the fixing structure 25 is only used to support the device structure 400. The fixing structure 25 may be, for example, a die attach film (DAF), such as Figure 6 As shown, the second circuit layer 202 has a first main surface and a second main surface that are arranged opposite to each other, and one end of the device structure 400 is fixed to the third main surface or the fourth main surface of the second circuit layer 202 through a fixing structure 25. In addition, a second interconnection structure 26 is arranged between the device structure 400 and the first circuit layer 201. Optionally, the second interconnection structure 26 may include a metal pad, a metal bump, or a metal electrode.

[0074] In one embodiment of the present application, a first passivation layer (not shown) can be formed on the first circuit layer 201 by, for example, spin coating, and then the first passivation layer is subjected to processes such as photolithography to expose a portion of the first metal wiring layer 201-1; on the exposed portion of the first metal wiring layer 201-1, for example, a metal bump is formed by, for example, growing to form a second interconnect structure 26.

[0075] Device structures 400 such as passive device 401 and active device 402 can be electrically connected to first metal wiring layer 201 - 1 through second interconnect structure 26 ; and can be electrically connected to second metal wiring layer 202 - 1 through second interconnect structure 26 and first interconnect structure 300 .

[0076] Alternatively, device structures 400 such as passive device 401 and active device 402 may be electrically connected to second metal wiring layer 202 - 1 through second interconnect structure 26 ; and may be electrically connected to first metal wiring layer 201 - 1 through second interconnect structure 26 and first interconnect structure 300 .

[0077] Optionally, the device structure 400 such as the passive device 401 and the active device 402 may be fanned out from one side of the plastic package 100 to improve the integration of the device structure.

[0078] In addition, combined Figure 1 and Figure 2 In one embodiment of the present application, the package body 1000 further includes a wire bonding pad 330, and the wire bonding pad 330 is located in the first circuit layer 201 or the second circuit layer 202, wherein the first end surface 310 or the second end surface 320 of the first interconnect structure 300 is connected to the wire bonding pad 330. One end of the wire bonding pad 330 is electrically connected to the first metal wiring layer 201-1 of the first circuit layer 201 or the second metal wiring layer 202-1 of the second circuit layer 202; the other end of the wire bonding pad 330 is connected to the first end surface 310 or the second end surface 320 of the first interconnect structure 300. The wire bonding pad 330 may include a conductive metal material, and the conductive metal material includes but is not limited to aluminum, copper, gold and the like.

[0079] In addition, the first circuit layer 201 may include a third surface away from the plastic package 100, and the second circuit layer 202 may include a fourth surface (the second main surface of the second circuit layer described above) away from the plastic package 100. The package 1000 also includes an electrical connection structure 500 configured to be connected to an external circuit, wherein the electrical connection structure 500 is disposed on at least one of the third surface and the fourth surface.

[0080] Optionally, the electrical connection structure 500 includes at least one of a solder ball, a metal bump, a bonding structure, and a conductive adhesive structure.

[0081] As an option, a first insulating dielectric layer (not shown) may be provided between the plurality of electrical connection structures 500 in a plane perpendicular to the z direction. For example, the electrical connection structure 500 may include POP (Package on Package) solder balls, and the first insulating dielectric layer may include a liquid plastic packaging material layer such as Under Fill (bottom filling glue layer), NCF (Non-Conductive Film, non-conductive film layer), etc.

[0082] As an option, the package 1000 may also include a package high-speed interface (not shown) exposed outside the plastic package 100 to connect to an external circuit. For example, the package 1000 includes multiple lines, such as a circuit layer 200, a first interconnect structure 300, and an electrical connection structure 500. The device structures 400 located in the plastic package 100 can be connected to each other through the above-mentioned lines; in addition, the device structure 400 can also be connected to an external circuit through the above-mentioned lines and the package high-speed interface. In the present application, the structure and position of the package high-speed interface are not specifically limited. The material, structure, shape, and connection method of the package high-speed interface with other components can be changed to obtain the various results and advantages described in this specification.

[0083] Figure 7 is a flow chart of a method 2000 for preparing a package according to one embodiment of the present application.

[0084] like Figure 7 As shown, the method 2000 for preparing a package may include:

[0085] S1, forming a first circuit layer and a wire bonding pad, wherein the wire bonding pad is located on a surface of the first circuit layer and connected to the first circuit layer.

[0086] S2, forming a plastic package and a first interconnect structure connected to the wire bonding pad on the first circuit layer, wherein the first interconnect structure extends along a first direction and penetrates the plastic package.

[0087] S3, forming a second circuit layer connected to the first interconnect structure on the plastic package, wherein the first interconnect structure includes a first end face and a second end face opposite to each other in a first direction, and the size of the first end face is the same as the size of the second end face.

[0088] The specific processes of each step of the method 2000 for preparing the semiconductor packaging structure are described below by way of example.

[0089] Step S1

[0090] Figure 8 It is a schematic cross-sectional view of a structure formed after forming a temporary attachment layer 12 according to one embodiment of the present application. Fig. 9 It is a cross-sectional schematic diagram of a structure formed after forming the first circuit layer 201 according to one embodiment of the present application.

[0091] like Figure 8 and Fig. 9 As shown, step S1 forms a first circuit layer and a wire bonding pad, wherein the wire bonding pad is located on the surface of the first circuit layer and is connected to the first circuit layer, and may for example include: preparing a carrier board 11; setting a temporary attachment layer 12 on the carrier board 11; and forming a first circuit layer 201 and a wire bonding pad 330 on the temporary attachment layer 12.

[0092] Specifically, in one embodiment of the present application, a carrier board 11 may be prepared, and a temporary attachment layer 12 may be disposed on the carrier board 11. The temporary attachment layer 12 may be a temporary bonding film, so as to be debonded by a method such as laser in a subsequent step.

[0093] As an option, the first circuit layer 201 and the wire bonding pads 330 may be formed on the temporary attachment layer 12 ; as another option, the first circuit layer 201 and the wire bonding pads 330 may be prepared in advance and fixed on the temporary attachment layer 12 .

[0094] In one embodiment of the present application, forming the first circuit layer 201 may include: forming a seed layer (not shown) on the surface of the temporary attachment layer 12 by, for example, vacuum sputtering; forming an initial circuit layer (not shown) on the seed layer by, for example, graphic electroplating; forming an initial first inorganic dielectric layer (not shown) on the initial circuit layer, and performing a hole opening process on the initial first inorganic dielectric layer to expose the pad area of ​​the initial circuit layer to form a first metal wiring layer 201-1 and a first inorganic dielectric layer 201-2 of the first circuit layer 201.

[0095] Optionally, the seed layer may include a titanium metal layer located on the surface of the temporary attachment layer 12 and a copper metal layer located on the titanium metal layer. The titanium metal layer has high adhesion, excellent electrical conductivity and uniform thickness, and the copper metal layer can be stably attached to the surface of the temporary attachment layer 12 through the titanium metal layer. In addition, the first circuit layer 201 may include a first metal wiring layer 201-1 of a single layer, two layers or more than two layers. The material of the seed layer is not limited to a stacked combination of two single metal materials, but can also be a single metal material, or an alloy material, as long as the circuit layer can be stably attached, and the details will not be repeated.

[0096] The first circuit layer 201 includes two surfaces opposite to each other in the z direction, and the first surface is connected to the temporary attachment layer 12. A wire bonding pad 330 may be provided in the first circuit layer 201, wherein the wire bonding pad 330 includes a surface exposed and flush with the second surface, so that a first interconnection structure is subsequently formed on the exposed surface of the wire bonding pad 330.

[0097] Optionally, the wire bonding pad 330 may be made of conductive metal materials, including but not limited to aluminum, copper, gold, etc. The shape of the wire bonding pad 330 includes but is not limited to round, square, etc. The wire bonding pad 330 is connected to the first metal wiring layer 201 - 1 of the first circuit layer 201 .

[0098] Step S2

[0099] Fig.10 It is a schematic cross-sectional view of a structure formed after forming the first interconnect structure 300 according to one embodiment of the present application. Fig.11 It is a cross-sectional schematic diagram of a structure formed after an initial plastic package body 100 ′ is formed according to an embodiment of the present application. Fig.12 It is a cross-sectional schematic diagram of a structure formed after a plastic package body 100 is formed according to an embodiment of the present application.

[0100] like Figure 9-12 As shown, step S2 forms a plastic package and a first interconnect structure connected to the wire bonding pad on the first circuit layer, wherein the first interconnect structure extends along a first direction and penetrates the plastic package, and may for example include: forming a first interconnect structure 300 connected to the wire bonding pad 330; forming an initial plastic package 100'; and forming the plastic package 100.

[0101] Optionally, in one embodiment of the present application, forming a plastic package body on the first circuit layer and a first interconnect structure connected to the wire bonding pad may include: forming a first interconnect structure having a predetermined extension length H (eg, Fig.12 The invention relates to a first interconnect structure 300 (as shown); forming an initial plastic package 100' that at least covers the first interconnect structure 300; and thinning the initial plastic package 100' to expose the end surface of the first interconnect structure 300 to form a plastic package 100, wherein a predetermined extension length H of the first interconnect structure 300 is determined based on a predetermined thickness of the package 100 in the z direction.

[0102] like Figure 9-10 As shown, the first interconnect structure 300 can be formed by, for example, a vertical wire bonding process. Wire bonding, wire cutting and wire pulling are performed on the wire bonding pad 300, so that the metal wire is broken at the tangent, and a vertical conductive line connected to the wire bonding pad 400 is obtained. Optionally, the material of the first interconnect structure 300 may include one or a combination of two or more of copper, aluminum, nickel, gold, silver, and titanium. The first interconnect structure is formed by a vertical wire bonding process. Since the first interconnect structure is a metal wire, the complexity and preparation cost of the packaging process can be reduced while the key dimensions of the first interconnect structure such as the end face dimension and the spacing between adjacent first interconnect structures can be greatly reduced, and the aspect ratio and consistency of the first interconnect structure can be greatly improved.

[0103] In addition, the predetermined extension length H of the first interconnect structure 300 is determined based on the predetermined thickness of the package 100 in the z direction. Since the first interconnect structure is formed by a vertical wire bonding process, the aspect ratio of the metal line has a greater advantage and a higher value than the aspect ratio of the interconnect pillar formed by etching, sputtering and electroplating processes, so the thickness of the package is no longer limited by etching, sputtering and electroplating processes, and has a greater size improvement.

[0104] like Figure 10-11 As shown, after forming the first interconnect structure 300, the initial plastic package 100' can be formed by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof. The molding compound used to form the initial plastic package 100' can include any one of polyimide, silica gel and EMC (Epoxy Molding Compound).

[0105] like Figure 11-Figure 12 As shown, after the initial plastic package 100' is formed, it can be formed by, for example, a dry etching process or a combination of dry and wet etching processes, or by, for example, a chemical mechanical polishing process; in addition, other manufacturing processes, such as a patterning process including photolithography, cleaning, and chemical mechanical polishing, can also be performed to thin the initial plastic package 100' to expose the end surface of the first interconnect structure 300 to form the plastic package 100. The thickness of the plastic package 100 along the z direction is the same as the predetermined extension length H of the first interconnect structure 300.

[0106] In addition, in one embodiment of the present application, the method 2000 for preparing a package body further includes: forming a device structure in the plastic package body, wherein the device structure includes at least one of a passive device and an active device, the passive device includes at least one of a resistor, a capacitor and an inductor; and the active device includes a memory chip.

[0107] As an option, refer to Figure 4 , Figure 5 as well as Fig.11 The device structure 400 can be connected to the first circuit layer 201 or the second circuit layer 202 by direct bonding; or a connection layer 24 is provided between the device structure 400 and the first circuit layer 201, or between the device structure 400 and the second circuit layer 202, wherein the connection layer 24 includes a bonding layer.

[0108] The second circuit layer 202 has a first main surface and a second main surface arranged opposite to each other, wherein the first main surface is connected to the second surface 120 of the plastic package 100. The connection layer 24 or the device structure 400 is encapsulated in the plastic package 100 and has a surface exposed and flush with the second surface 120, which is connected to the first main surface of the second circuit layer 202 together with the second surface 120 of the plastic package 100, for electrically coupling the device structure 400 to the first main surface of the first circuit layer 201.

[0109] Optionally, refer to Figure 1 , Figure 4 and Fig.11 , a hybrid bonding method can be used to achieve electrical connection between the device structure 400 in the plastic package 100 and the first circuit layer 201 or the second circuit layer 202. It should be noted that the thickness and position of the connection layer 24 and the shape of the device structure 400 given in the above embodiment are only exemplary demonstrations and are not used to limit the connection layer in this application. In actual applications, the device structure or the connection layer can be set according to specific actual process conditions.

[0110] Optionally, device structures 400 such as passive devices 401 and active devices 402 can be directly bonded to the second circuit layer 202 and electrically connected to the second metal wiring layer 202-1; in addition, they can also be electrically connected to the first metal wiring layer 201-1 through the first interconnect structure 300.

[0111] Alternatively, device structures 400 such as passive devices 401 and active devices 402 may be directly bonded to the first circuit layer 201 and electrically connected to the first metal wiring layer 201 - 1 ; in addition, electrical connection to the second metal wiring layer 202 - 1 may be achieved through the first interconnect structure 300 .

[0112] Optionally, refer to Figure 1 , Figure 5 and Fig.11 , device structures 400 such as passive devices 401 and active devices 402 can be electrically connected to the second metal wiring layer 202-1 through the connection layer 24; and can be electrically connected to the first metal wiring layer 201-1 through the connection layer 24 and the first interconnect structure 300.

[0113] Alternatively, device structures 400 such as passive devices 401 and active devices 402 can be electrically connected to the first metal wiring layer 201 - 1 through the connection layer 24 ; and can be electrically connected to the second metal wiring layer 202 - 1 through the connection layer 24 and the first interconnect structure 300 .

[0114] As another option, refer to Figure 6 as well as Fig.11, a fixed structure 25 is set between the device structure 400 and the first circuit layer 201, and a second interconnection structure 26 is set between the device structure 400 and the second circuit layer 202; or a fixed structure 25 is set between the device structure 400 and the second circuit layer 202, and a second interconnection structure 26 is set between the device structure 400 and the first circuit layer 201.

[0115] Optionally, refer to Figure 1 , Figure 6 and Fig.11 The fixing structure 25 is only used to support the device structure 400. The fixing structure 25 may be, for example, a die attach film (DAF), such as Figure 6 As shown, the second circuit layer 202 has a first main surface and a second main surface that are arranged opposite to each other, and one end of the device structure 400 is fixed to the third main surface or the fourth main surface of the second circuit layer 202 through a fixing structure 25. In addition, a second interconnection structure 26 is arranged between the device structure 400 and the first circuit layer 201. Optionally, the second interconnection structure 26 may include a metal pad, a metal bump, or a metal electrode.

[0116] In one embodiment of the present application, a first passivation layer (not shown) can be formed on the first circuit layer 201 by, for example, spin coating, and then the first passivation layer is subjected to processes such as photolithography to expose a portion of the first metal wiring layer 201-1; on the exposed portion of the first metal wiring layer 201-1, for example, a metal bump is formed by, for example, growing to form a second interconnect structure 26.

[0117] Device structures 400 such as passive device 401 and active device 402 can be electrically connected to first metal wiring layer 201 - 1 through second interconnect structure 26 ; and can be electrically connected to second metal wiring layer 202 - 1 through second interconnect structure 26 and first interconnect structure 300 .

[0118] Alternatively, device structures 400 such as passive device 401 and active device 402 may be electrically connected to second metal wiring layer 202 - 1 through second interconnect structure 26 ; and may be electrically connected to first metal wiring layer 201 - 1 through second interconnect structure 26 and first interconnect structure 300 .

[0119] Optionally, the device structure 400 such as the passive device 401 and the active device 402 may be fanned out from one side of the plastic package 100 to improve the integration of the device structure.

[0120] Step S3

[0121] Fig.13It is a cross-sectional schematic diagram of a structure formed after forming the second circuit layer 202 according to one embodiment of the present application. Fig.14 is a schematic diagram of a debonding process according to one embodiment of the present application.

[0122] like Figure 12-14 As shown, step S3 forms a second circuit layer connected to the first interconnect structure on the plastic package, wherein the first interconnect structure includes a first end face and a second end face opposite to each other in a first direction, and the size of the first end face is the same as the size of the second end face, which may include, for example: forming a seed layer (not shown) on the surface of the plastic package 100 and the end face of the first interconnect structure 300 by, for example, vacuum sputtering; forming an initial circuit layer (not shown) on the seed layer by, for example, graphic electroplating; forming an initial second inorganic dielectric layer (not shown) on the initial circuit layer, and performing an opening process on the initial second inorganic dielectric layer to expose the pad area of ​​the initial circuit layer to form a second metal wiring layer 202-1 and a second inorganic dielectric layer 202-2 of the second circuit layer 202.

[0123] Optionally, the seed layer may include a titanium metal layer located on the surface of the plastic package 100 and the end face of the first interconnect structure 300 and a copper metal layer located on the titanium metal layer. The titanium metal layer has high adhesion, excellent electrical conductivity and uniform thickness, and the copper metal layer can be stably attached to the surface of the plastic package 100 and the end face of the first interconnect structure 300 through the titanium metal layer. In addition, the second circuit layer 202 may include a second metal wiring layer 202-1 of a single layer, two layers or more than two layers. The material of the seed layer is not limited to a stacked combination of two single metal materials, and can also be a single metal material, or an alloy material, as long as the circuit layer can be stably attached, and the details will not be repeated.

[0124] like Fig.13 As shown, the first circuit layer 201 includes a third surface away from the plastic package 100, and the second circuit layer 202 includes a fourth surface away from the plastic package 100. After forming the second circuit layer 202, the method 2000 for preparing the package body further includes: on at least one of the third surface and the fourth surface, an electrical connection structure 500 connected to an external circuit is provided, wherein the electrical connection structure 500 includes at least one of a solder ball, a metal bump, a bonding structure and a conductive adhesive structure.

[0125] Optionally, a first insulating dielectric layer may be provided between multiple electrical connection structures 500 in the xy plane. For example, the electrical connection structure 500 may include a POP (Package on Package) solder ball, and the first insulating dielectric layer may include a liquid plastic packaging material layer such as Under Fill (bottom filling glue layer), NCF (Non-Conductive Film, non-conductive film layer). The electrical connection structure may be formed by using existing conventional processes and prepared according to actual needs, which will not be elaborated here. It should be noted that in actual applications, the electrical connection structure may be provided according to the requirements of the semiconductor packaging structure, and the present application does not limit the structure, shape, material and preparation process of the electrical connection structure.

[0126] In addition, if Figure 13-Figure 14 As shown, in one embodiment of the present application, the method 2000 for preparing a package body further includes releasing the temporary attachment layer 12. For example, the temporary attachment layer 12 may be a temporary bonding film, and the surface of the carrier 11 away from the temporary attachment layer 12 may be irradiated by laser 13, for example, to perform debonding.

[0127] According to the method for preparing a package and a storage system provided by at least one embodiment of the present application, the package includes a plastic package, a circuit layer and a first interconnection structure, wherein the circuit layer includes a first circuit layer and a second circuit layer (upper and lower circuit layers) located on opposite surfaces of the plastic package, and the first interconnection structure can penetrate the plastic package and be connected to the upper and lower circuit layers respectively. The two end faces of the first interconnection structure opposite to each other along the extension direction have the same size. In other words, the key size consistency of the interconnection lines connecting the upper and lower circuit layers in the package is high; in addition, the size of the interconnection lines and the spacing between the interconnection lines are improved, so that the space and area of ​​the spacing area of ​​the interconnection lines and their surroundings are reduced, the density and compatibility of the overall circuit layout of the package are improved, the complexity of the packaging process is reduced, and the requirements of thin and short electronic products can be met.

[0128] Fig.15 It is a schematic diagram of the storage system structure according to one embodiment of the present application.

[0129] like Fig.15As shown, at least one embodiment of another aspect of the present application also provides a storage system 30000. The storage system 30000 may include a memory 32100 and a controller 32200, the controller 32200 is coupled to the memory 32100 to control the memory 32100 to store data, wherein at least one of the controller 32200 and the memory 32100 is located in the package 1000 described above. It should be noted that the package exemplified above can be used to form various storage systems. In some embodiments, the storage system can be implemented as a storage device such as a universal flash storage (UFS) device, a solid state drive (SSD), a multimedia card in the form of MMC, eMMC, RS-MMC and micro MMC, a secure digital card in the form of SD, mini SD and micro SD, a storage device of the personal computer memory card international association (PCMCIA) card type, a peripheral component interconnect (PCI) type storage device, a high-speed PCI (PCI-E) type storage device, a compact flash (CF) card, a smart media card or a memory stick, etc. The storage system provided in the present application has the same beneficial effects as the semiconductor packaging structure provided in the present application, and thus will not be described in detail here.

[0130] Specifically, the memory system 30000 may include a memory 32100 and a controller 32200. At least one of the controller 32200 and the memory 32100 is located in the package 1000 described above. The controller 32200 may control the memory 32100 through a channel CH, and the memory 32100 may perform an operation based on the control of the controller 32200 in response to a request from the host 31000. The memory 32100 may receive a command CMD and an address ADDR from the controller 32200 through the channel CH and access an area selected from the memory cell array in response to the address. In other words, the memory 32100 may perform an internal operation corresponding to the command on the area selected by the address.

[0131] Optionally, the memory 32100 may be a memory array wafer or a memory including a peripheral circuit. Specifically, the memory 32100 may include at least one of a two-dimensional memory or a three-dimensional memory. As an option, the three-dimensional memory may include at least one of a three-dimensional NAND memory and a three-dimensional NOR memory.

[0132] The above description is only a preferred embodiment of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of protection involved in the present application is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the technical concept. For example, the above features are replaced with the technical features with similar functions disclosed in this application (but not limited to) by each other.

Claims

1. A package, characterized in that: include: The plastic package body comprises a first surface and a second surface opposite to each other in a first direction; The circuit layer includes a first circuit layer and a second circuit layer respectively disposed on the first surface and the second surface, a first interconnection structure, penetrating the plastic package body along the first direction and connected to the first circuit layer and the second circuit layer respectively; The first interconnect structure includes a first end surface and a second end surface that are opposite to each other in the first direction, and the size of the first end surface is the same as the size of the second end surface.

2. The package according to claim 1, wherein: The extension length L of the first interconnection structure in the first direction and the dimension D of the end surface of the first interconnection structure satisfy: 20≤L / D≤30.

3. The package according to claim 1, wherein: Adjacent first interconnect structures have a spacing Sp in a plane perpendicular to the first direction, Among them, 40μm≤Sp≤120μm.

4. The package according to claim 1, wherein: The package body also includes a device structure encapsulated in the plastic package body. Wherein, the device structure includes at least one of a passive device and an active device, the passive device includes at least one of a resistor, a capacitor and an inductor; and the active device includes a memory chip.

5. The package according to claim 4, wherein: The memory chip includes at least one of a nonvolatile memory chip and a volatile memory chip, wherein the nonvolatile memory chip includes at least one of a three-dimensional NAND memory chip, a three-dimensional NOR memory chip, a ferroelectric memory chip, and a phase change memory chip.

6. The package according to claim 5, wherein: The device structure is directly bonded to the first circuit layer or the second circuit layer; or A connection layer is provided between the device structure and the first circuit layer or the second circuit layer, wherein the connection layer comprises a bonding layer.

7. The package according to claim 5, wherein: A fixing structure is disposed between the device structure and one of the first circuit layer and the second circuit layer; and A second interconnect structure is disposed between the device structure and the other of the first circuit layer and the second circuit layer.

8. The package according to claim 1, wherein: The package body further includes a wire bonding pad, and the wire bonding pad is located on the first circuit layer or the second circuit layer. Wherein, the first end surface or the second end surface is connected to the wire bonding pad.

9. The package according to claim 1, wherein: The first circuit layer includes a third surface away from the plastic package body, and the second circuit layer includes a fourth surface away from the plastic package body; and The package body also includes an electrical connection structure configured to be connected to an external circuit, Wherein, the electrical connection structure is disposed on at least one of the third surface and the fourth surface.

10. The package according to claim 9, wherein: The electrical connection structure includes at least one of a solder ball, a metal bump, a bonding structure and a conductive adhesive structure.

11. The package according to claim 1, wherein: The package body also includes a package body high-speed interface exposed outside the plastic package body for connecting with an external circuit.

12. The package according to any one of claims 1 to 11, wherein: The first interconnect structure includes a metal line.

13. A storage system, characterized in that: The storage system comprises a controller and a memory, wherein the controller is coupled to the memory to control the memory to store data, and at least one of the controller and the memory comprises the package according to any one of claims 1-12.

14. A method for preparing a package, characterized in that: include: forming a first circuit layer and a wire bonding pad, wherein the wire bonding pad is located on a surface of the first circuit layer and connected to the first circuit layer; Forming a plastic package and a first interconnect structure connected to the wire bonding pad on the first circuit layer, wherein the first interconnect structure extends along a first direction and penetrates the plastic package; as well as forming a second circuit layer connected to the first interconnect structure on the plastic package body, The first interconnect structure includes a first end surface and a second end surface that are opposite to each other in the first direction, and the size of the first end surface is the same as the size of the second end surface.

15. The method according to claim 14, wherein: A plastic package is formed on the first circuit layer and a first interconnect structure connected to the wire bonding pad includes: forming the first interconnect structure having a predetermined extension length on the first circuit layer; forming an initial plastic package covering at least the first interconnect structure; and thinning the initial plastic package body until the end surface of the first interconnect structure is exposed to form the plastic package body, The predetermined extension length of the first interconnect structure is determined based on a predetermined thickness of the package body in the first direction.

16. The method according to claim 14, wherein: Forming a first interconnect structure connected to the wire bonding pad on the first circuit layer includes: The first interconnect structure is formed by using a vertical wire bonding process.

17. The method according to claim 14, wherein: The first circuit layer includes a third surface away from the plastic package body, and the second circuit layer includes a fourth surface away from the plastic package body, and the method further includes: An electrical connection structure connected to an external circuit is provided on at least one of the third surface and the fourth surface, Wherein, the electrical connection structure includes at least one of a solder ball, a metal bump, a bonding structure and a conductive adhesive structure.

18. The method according to claim 14, wherein: The method further comprises: forming a device structure in the plastic package, Wherein, the device structure includes at least one of a passive device and an active device, the passive device includes at least one of a resistor, a capacitor and an inductor; and the active device includes a memory chip.

19. The method according to claim 18, wherein: The method further comprises: The device structure is connected to the first circuit layer or the second circuit layer by direct bonding; or A connection layer is provided between the device structure and the first circuit layer, or between the device structure and the second circuit layer, wherein the connection layer comprises a bonding layer.

20. The method according to claim 18, wherein: The method further comprises: A fixing structure is provided between the device structure and the first circuit layer, and a second interconnection structure is provided between the device structure and the second circuit layer; or A fixing structure is provided between the device structure and the second circuit layer, and a second interconnection structure is provided between the device structure and the first circuit layer.

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