Fan-out type dual-polarization packaging antenna array integrated with heterogeneous chipset

Abstract

The invention relates to the field of packaged antenna arrays, and particularly discloses a fan-out type dual-polarization packaged antenna array integrated with a heterogeneous chipset. The packaging antenna array comprises three packaging bodies which are arranged from top to bottom, and a dual-polarized antenna array, a feed network and a heterogeneous chipset embedded in the packaging bodies are integrated in the packaging antenna array, so that high-density fan-out integration of the dual-polarized antenna array and the heterogeneous radio frequency front-end chipset is realized; the phased array module has lower transmission loss and higher integration level, not only can effectively reduce the size and cost of the system, but also has the characteristics of simple assembly process, high consistency, easy realization of random expansion of the array scale and the like, and can be applied to a large-scale phased array system as a standard module.

Description

Technical Field

[0001] The invention belongs to the technical field of packaged antenna arrays, and specifically discloses a fan-out dual-polarized packaged antenna array integrating a heterogeneous chipset. Background Art

[0002] There are currently two main ways to implement packaged antenna arrays: one is to directly make the antenna unit on one side of the substrate, and mount the packaged chip on the other side of the substrate. This implementation method has a longer antenna feeder path and greater signal loss. In addition, since the processing accuracy of the substrate is lower than that of the wafer manufacturing process, the consistency of the array unit is poor, making it difficult to obtain excellent performance. Another method is to fan out the wafer, use rewiring technology to lead the signal from the chip and directly connect it to the antenna unit structure around the chip, and then wrap it with packaging material for protection. Although this method can achieve lower path loss, it has low area utilization and is difficult to effectively expand the antenna structure and the number of channels, reducing antenna performance / area efficiency.

[0003] In view of this, the present invention provides an integrated solution of chip-package-antenna array to enhance the integration of packaged antenna array and improve the overall performance. Summary of the invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides a fan-out dual-polarization packaged antenna array integrating a heterogeneous chipset.

[0005] The technical solution adopted by the present invention is: A fan-out dual-polarized packaged antenna array integrated with a heterogeneous chipset, comprising a first package body, a second package body, a third package body and a solder ball array arranged from top to bottom; One side of the first packaging body and the second packaging body abut against each other and are connected by an adhesive material; The other surface of the second packaging body abuts against one surface of the third packaging body and is connected by an adhesive material; A solder ball array is arranged on the other side of the third package body for transmission of radio frequency signals, control signals and power supply.

[0006] Furthermore, the first package body is composed of a first wiring layer and a first dielectric layer; the first wiring layer is located on the upper surface of the first dielectric layer; The first wiring layer is provided with N antenna radiation patches arranged in an array, where N is 2×2 or 4×4.

[0007] Furthermore, the second package body is composed of a second wiring layer and a second dielectric layer; the second wiring layer is located between the second dielectric layer and the first package body; The second wiring layer is provided with a plurality of parasitic radiation patches arranged in an array at intervals; the parasitic radiation patches correspond one-to-one to the antenna radiation patches, and the parasitic radiation patches are respectively located directly below the corresponding antenna radiation patches.

[0008] Further, the third package body is composed of a third wiring layer, a third dielectric layer and a fourth wiring layer; the third dielectric layer is located between the third wiring layer and the fourth wiring layer, wherein the third wiring layer is in contact with the second package body, and the fourth wiring layer is in contact with the solder ball array; The third wiring layer is provided with 2N slot structures used as antenna coupling gaps; The fourth wiring layer is provided with 2N antenna feed lines; The third dielectric layer encapsulates a heterogeneous chipset consisting of a silicon-based CMOS chip, 2N compound chips and several TMV chips.

[0009] Furthermore, the N antenna radiation patches of the first package body, the N parasitic radiation patches of the second package body, and the 2N slot structures and 2N antenna feed lines of the third package body constitute an N-element dual-polarization antenna unit array structure.

[0010] Further, one end of the 2N compound chips is connected to a plurality of corresponding ports of the silicon-based CMOS chip through first connecting wires on the fourth wiring layer, and the length of each first connecting wire is the same; The other ends of the 2N compound chips are connected to the corresponding antenna feeder lines through the second connecting lines on the fourth wiring layer, and the length of each second connecting line is the same; The TMV chip penetrates the third dielectric layer, and the electrical connection between the third wiring layer and the fourth wiring layer is achieved through metallized vias.

[0011] Compared with the prior art, the present invention has the following beneficial effects: (1) It realizes the miniaturization and integrated three-dimensional fan-out integration of array antenna units and heterogeneous chipsets, thereby improving the integration of antenna arrays; (2) It adopts wafer-level packaging technology, which makes the antenna feed line path shorter and the loss lower, thereby improving the overall performance; (3) It has scalability and can achieve expansion of any array size through splicing. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 A schematic cross-sectional structure diagram of a fan-out dual-polarized packaged antenna array integrated with a heterogeneous chipset in an embodiment of the present invention; Figure 2 The diagram is a layered structure diagram of a fan-out dual-polarized packaged antenna array integrated with a heterogeneous chipset in an embodiment of the present invention. DETAILED DESCRIPTION

[0013] In order to further illustrate the advantages of the present invention and the specific technical means adopted, the specific embodiments of the present invention are described in detail in conjunction with the accompanying drawings. It is understood that these embodiments are only used to illustrate the present invention and are not used to limit the scope of the present invention. After reading the present invention, modifications of various equivalent forms of the present invention by those skilled in the art should fall within the scope of protection of the claims of this application.

[0014] The present invention is further described in detail below in conjunction with the accompanying drawings.

[0015] like Figure 1 As shown, an embodiment of the present invention provides a fan-out dual-polarized packaged antenna array integrated with a heterogeneous chipset, comprising a first package body 1, a second package body 2, a third package body 3 and a solder ball array 4 arranged from top to bottom; One side of the first package body 1 and the second package body 2 are in contact with each other and connected by an adhesive material; The other surface of the second packaging body 2 is in contact with one surface of the third packaging body 3 and connected via an adhesive material; A solder ball array 4 is disposed on the other side of the third package body 3 for transmission of radio frequency signals, control signals and power supply.

[0016] Specifically, the first package body 1 is composed of a first wiring layer 11 and a first dielectric layer 12; The first wiring layer 11 is provided with N (N= 2×2 or 4×4) antenna radiation patches 101 arranged in an array; Specifically, the second package body 2 is composed of a second wiring layer 21 and a second dielectric layer 22; The second wiring layer 21 is provided with N parasitic radiation patches 201 arranged in an array, and the N parasitic radiation patches 201 are located directly below the antenna radiation patch 101; Specifically, the third package body 3 is composed of a third wiring layer 31, a third dielectric layer 32 and a fourth wiring layer 33; The third wiring layer 31 is provided with 2N slot structures 301 used as antenna coupling gaps; The fourth wiring layer 33 is provided with 2N antenna feed lines 401; The third dielectric layer 32 encapsulates a heterogeneous chipset consisting of a silicon-based CMOS chip 501 , 2N compound chips 502 and a plurality of molded through-hole TMV chips 503 .

[0017] Specifically, the N antenna radiation patches 101, the N parasitic radiation patches 201, the 2N slot structures 301, and the 2N antenna feed lines 401 constitute an N-element dual-polarized antenna unit array structure. The antenna radiation patches 101 correspond to the parasitic radiation patches 201 one by one, and the parasitic radiation patches 201 are located below the corresponding antenna radiation patches 101; the 2N slot structures 301 are divided into N groups, each group has two slot structures 301, and in this embodiment, the slot structures are "I"-shaped, and the two slot structures 301 in the same group are perpendicular to each other and are located below the corresponding parasitic radiation patches 201; the antenna feed lines 401 are divided into N groups, each group has two antenna feed lines, and the two antenna feed lines 401 in the same group are both located below the corresponding group of slot structures 301.

[0018] Specifically, one end of the 2N compound chips 502 is connected to a plurality of corresponding ports of the silicon-based CMOS chip 501 through the fourth wiring layer 33, and the length of each connection line is the same; The other ends of the 2N compound chips 502 are connected to the corresponding antenna feed lines 401 through the fourth wiring layer 33, and the length of each connection line is the same; The TMV chip 503 penetrates the third dielectric layer 32 and realizes electrical connection between the third wiring layer 31 and the fourth wiring layer 33 through metallized vias.

[0019] Figure 2 The present invention is a specific embodiment of the present invention, more specifically, when N is 2×2, a schematic diagram of the layered structure of a fan-out dual-polarized packaged antenna array integrating a heterogeneous chipset.

[0020] The working principle of signal transmission in this specific embodiment is as follows: the transmission signal is processed by the silicon-based CMOS chip 501 and then transmitted to the compound chip 502, and then output to the antenna feed line 401 after amplification. The antenna feed line 401 transmits energy to the antenna radiation patch 101 and the parasitic radiation patch 201 through the slot structure 301. The antenna radiation patch 101 and the parasitic radiation patch 201 convert the received energy into radio waves that propagate in an unbounded medium (usually free space), and the radio waves radiate into the surrounding space, thereby realizing signal transmission.

[0021] The working principle of signal reception in this specific embodiment is as follows: the antenna radiation patch 101 and the parasitic radiation patch 201 receive radio waves in space and convert them into energy, which is then transmitted to the compound chip 502 through the slotted structure 301 and the antenna feed line 401 in sequence. The multiple compound chips 502 transmit the received signals to the silicon-based CMOS chip 501, and the silicon-based CMOS chip 501 processes the multi-path received signals, thereby realizing signal reception.

Claims

1. A fan-out dual-polarized packaged antenna array integrated with a heterogeneous chipset, characterized in that: It comprises arranging, from top to bottom, a first package body (1), a second package body (2), a third package body (3) and a solder ball array (4); One side of the first packaging body (1) and the second packaging body (2) are in contact with each other and connected via an adhesive material; The other surface of the second packaging body (2) is in contact with one surface of the third packaging body (3) and is connected via an adhesive material; A solder ball array (4) is arranged on the other side of the third packaging body (3) for transmitting radio frequency signals, control signals and power supply.

2. The fan-out dual-polarized packaged antenna array integrated with a heterogeneous chipset according to claim 1, characterized in that: The first package (1) is composed of a first wiring layer (11) and a first dielectric layer (12); the first wiring layer (11) is located on the upper surface of the first dielectric layer (12); The first wiring layer (11) is provided with N antenna radiation patches (101) arranged in an array at intervals, where N is 2×2 or 4×4.

3. The fan-out dual-polarized packaged antenna array integrated with a heterogeneous chipset according to claim 1, characterized in that: The second package (2) is composed of a second wiring layer (21) and a second dielectric layer (22); the second wiring layer (21) is located between the second dielectric layer (22) and the first package (1); The second wiring layer (21) is provided with a plurality of parasitic radiation patches (201) arranged in an array at intervals; the parasitic radiation patches (201) correspond one-to-one to the antenna radiation patches (101), and the parasitic radiation patches (201) are respectively located directly below the corresponding antenna radiation patches (101).

4. The fan-out dual-polarized packaged antenna array integrated with a heterogeneous chipset according to claim 1, characterized in that: The third package body (3) is composed of a third wiring layer (31), a third dielectric layer (32) and a fourth wiring layer (33); the third dielectric layer (32) is located between the third wiring layer (31) and the fourth wiring layer (33), wherein the third wiring layer (31) is in contact with the second package body (2), and the fourth wiring layer (33) is in contact with the solder ball array (4); The third wiring layer (31) is provided with 2N slotted structures (301) used as antenna coupling gaps; The fourth wiring layer (33) is provided with 2N antenna feed lines (401); The third dielectric layer (32) encapsulates a heterogeneous chip group consisting of a silicon-based CMOS chip (501), 2N compound chips (502) and a plurality of TMV chips (503).

5. The fan-out dual-polarized packaged antenna array integrated with a heterogeneous chipset according to claim 1, characterized in that: N antenna radiation patches (101) of the first package (1), N parasitic radiation patches (201) of the second package (2), and 2N slotted structures (301) and 2N antenna feed lines (401) of the third package (3) form an N-element dual-polarization antenna unit array structure.

6. The fan-out dual-polarized packaged antenna array integrated with a heterogeneous chipset according to claim 4, characterized in that: One end of the 2N compound chips (502) is connected to a plurality of corresponding ports of the silicon-based CMOS chip (501) via first connecting wires on the fourth wiring layer (33), and the length of each first connecting wire is the same; The other ends of the 2N compound chips (502) are connected to the corresponding antenna feeder (401) via second connecting lines on the fourth wiring layer (33), and the length of each second connecting line is the same; The TMV chip (503) penetrates the third dielectric layer (32), and realizes electrical connection between the third wiring layer (31) and the fourth wiring layer (33) through metallized vias.

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