A Digital Active EMI Filtering Method and Circuit Based on Square Wave Analysis and Reconstruction

Abstract

This application relates to a digital active EMI filtering method and circuit based on square wave analysis and reconstruction. The method includes: obtaining the waveform data of the common-mode noise source of the Buck circuit; determining the compensation capacitor parameters according to the equivalent model of the compensation circuit, and generating compensation voltage data that is reduced in proportion to the waveform data of the common-mode noise source; through a synchronous control mechanism, synchronously outputting PWM and the compensation voltage data, and injecting them into the ground wire; measuring the delay between the PWM and the DAC output signal, and reconstructing the compensation voltage data for delay compensation. By using the digital active EMI filtering method and circuit based on square wave analysis and reconstruction provided in this application, it is possible to eliminate delay and reduce common-mode EMI noise while achieving non-detection, reducing costs, and decreasing volume.

Description

Technical Field

[0001] This application relates to the technical field of EMI suppression for power electronic converters, and particularly to a digital active EMI filtering method and circuit based on square wave analysis and reconstruction. Background Art

[0002] Currently, power electronic technology has developed rapidly, and power electronic converters are increasingly widely used in fields such as new energy, electric vehicles, and industrial control. With the popularization of wide bandgap semiconductor devices (such as SiC and GaN), it promotes the development of converters towards high switching frequencies and high power densities. However, high switching frequencies are likely to result in higher rates of voltage change (dv / dt) and current change (di / dt), as well as stronger electromagnetic coupling between components, further exacerbating the electromagnetic interference problem (EMI) of power electronic converters.

[0003] In the face of electromagnetic interference of power electronic converters, EMI filters are usually used for suppression. Traditional EMI filters are divided into two types: passive and active. Among them, the passive EMI filter is composed of passive devices such as inductors and capacitors, which can suppress electromagnetic interference, but its volume is large and it is difficult to meet the requirements of high power density. The active EMI filter detects the electromagnetic interference voltage or current generated by the power electronic converter, amplifies it in reverse through an operational amplifier, and then injects it into the system through an injection circuit, thereby effectively reducing the volume. However, it has high bandwidth requirements for active devices, and while the cost is high, it also requires an additional isolated power supply.

[0004] In the prior art, with the rise of digital control technology, digital active EMI filtering technology has been obtained by combining digital control with active EMI filters. As Figure 12 shown, its core principle is the same as that of traditional active EMI filtering technology, but only replaces the active devices with digital controllers, adds an analog-to-digital converter (ADC) in the detection circuit, and adds a digital-to-analog converter (DAC) in the injection circuit, thereby achieving cost reduction and volume reduction. However, in the above digital active EMI filtering technology, the ADC in the detection circuit and the DAC in the injection circuit still require high costs. Moreover, after two analog-to-digital and digital-to-analog conversion processes in the system, there will be a certain delay, which will affect the EMI suppression effect.

[0005] It should be noted that the information disclosed in the above background art section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to those of ordinary skill in the art. Summary of the Invention

[0006] In view of the above problems, the present application provides a digital active EMI filtering method and circuit based on square wave analysis and reconstruction, which can reduce costs and volume while eliminating delays.

[0007] To achieve the object of the present application, the following technical solutions are provided:

[0008] In a first aspect, the present application provides a digital active EMI filtering method based on square wave analysis and reconstruction, including:

[0009] Obtain the waveform data of the common-mode noise source of the measured buck circuit (Buck circuit); wherein, the common-mode noise source waveform data is the time-domain waveform data points of the drain-source voltage of the lower transistor of the Buck circuit bridge arm;

[0010] Determine the compensation capacitor parameters according to the equivalent model of the compensation circuit, and generate compensation voltage data that is proportionally reduced from the common-mode noise source waveform data;

[0011] Through a synchronous control mechanism, synchronously output pulse width modulation (PWM) and the compensation voltage data, and inject them into the ground wire;

[0012] Measure the delay between PWM and DAC, and reconstruct the compensation voltage data for delay compensation.

[0013] In a possible implementation, the step of obtaining the waveform data of the common-mode noise source of the Buck circuit includes:

[0014] Take the drain-source voltage of the lower transistor of the Buck circuit bridge arm as the common-mode noise source;

[0015] Obtain the drain-source voltage of the lower transistor of the Buck circuit through mathematical modeling;

[0016] Equivalent the drain-source voltage of the lower transistor of the Buck circuit to a trapezoidal wave, and establish a first formula to obtain the rise time, fall time, switching period and duty cycle of the time-domain waveform data of the drain-source voltage of the lower transistor of the Buck circuit; the first formula includes: rise stage, flat top stage, fall stage and turn-off stage;

[0017] According to the rise time, fall time, switching period and duty cycle, obtain the time-domain waveform data points of the drain-source voltage of the lower transistor of the Buck circuit.

[0018] In a possible implementation, the first formula is:

[0019] ;

[0020] Wherein, is the drain-source voltage of the lower transistor of the Buck circuit bridge arm, is the input voltage of the Buck circuit, is the voltage rise time, is the voltage fall time, is the duty cycle, is the switching period, is the time.

[0021] In a possible implementation, the step of determining the compensation capacitor parameter according to the equivalent model of the compensation circuit and generating the compensation voltage data which is a scaled-down version of the common-mode noise source waveform data includes:

[0022] Construct the equivalent model of the compensation circuit including the noise source, compensation capacitor, parasitic capacitor and the ground branch of the linear impedance stabilization network (LISN);

[0023] According to the equivalent model of the compensation circuit, use the superposition cancellation principle to obtain the relationship between the equivalent model compensation voltage and the equivalent model noise source voltage, and construct a second formula;

[0024] According to the second formula, increase the equivalent model compensation capacitor, reduce the equivalent model compensation voltage to the output range of the DAC, and obtain the proportionality coefficient and the compensation capacitor parameter;

[0025] Reduce the waveform data of the drain-source voltage of the lower transistor of the Buck circuit bridge arm by the proportionality coefficient to obtain the compensation voltage data, and store it in the digital controller.

[0026] In a possible implementation, the second formula is:

[0027] ;

[0028] where, is the equivalent model compensation voltage, is the noise source voltage, is the parasitic capacitor, is the compensation capacitor, is the proportionality coefficient.

[0029] In a possible implementation, the step of according to the equivalent model of the compensation circuit, using the superposition cancellation principle to obtain the relationship between the equivalent model compensation voltage and the equivalent model noise source voltage, and constructing a second formula includes:

[0030] According to the equivalent model of the compensation circuit, use the superposition cancellation principle to deduce the relationship between the equivalent model compensation voltage and the equivalent model noise source voltage, and obtain a third formula; the third formula is:

[0031] ;

[0032] where, is the equivalent model parasitic capacitance impedance, is the equivalent model LISN ground branch impedance, is the compensation capacitance impedance;

[0033] Simplifying the third formula yields the second formula.

[0034] In a possible implementation, the step of synchronously outputting PWM and the compensation voltage data through the synchronization control mechanism and injecting them into the ground wire includes:

[0035] Storing the compensation voltage data as an array with a length corresponding to the number of sampling points in the switching period to obtain a compensation voltage array;

[0036] Directly outputting the compensation voltage array from the memory to the DAC through direct memory access, with the output frequency being the same as the timer frequency;

[0037] Interrupting the PWM so that at the start of each PWM, the starting point of the compensation voltage array output by the DAC is synchronized with the starting point of the PWM;

[0038] Injecting the compensation voltage into the ground wire through the compensation capacitance by the DAC.

[0039] In a possible implementation, the step of interrupting the PWM so that at the start of each PWM, the starting point of the compensation voltage array output by the DAC is synchronized with the starting point of the PWM includes:

[0040] Setting the interrupt condition to reach the starting point of the PWM period;

[0041] When an interrupt occurs, resetting the output index of the compensation voltage array to 0;

[0042] Outputting the synchronized compensation voltage and the PWM at the starting point.

[0043] In a possible implementation, the step of measuring the delay between the PWM and the DAC and reconstructing the compensation voltage data to compensate for the delay includes:

[0044] Actually testing the time difference between the output of the compensation voltage and the PWM;

[0045] Moving the first n data corresponding to the time difference in the compensation voltage array to the end of the array.

[0046] In a second aspect, the present application further provides a digital active EMI filtering circuit based on square wave analysis and reconstruction for performing the above-mentioned digital active EMI filtering method based on square wave analysis and reconstruction. The circuit includes an injection circuit and a digital control circuit;

[0047] The digital control circuit is connected to the EUT through an injection circuit, and includes a digital controller and a DAC connected to each other. The digital controller is used to drive a switching tube, store compensation voltage data scaled down from the waveform data of the common-mode noise source, reconstruct the compensation voltage data for delay compensation, and control the synchronization of PWM and the output of the DAC. The DAC is used to perform analog output on the compensation voltage data.

[0048] The injection circuit includes a compensation capacitor for injecting the compensation voltage data output synchronously with the PWM into the ground wire.

[0049] The technical solution provided by this application may include the following beneficial effects:

[0050] Through a digital active EMI filtering method and circuit based on square wave analysis and reconstruction provided by this application, two detection capacitors and an ADC in a traditional digital active EMI filter, as well as a resistor and individual injection capacitors in the injection loop, can be omitted, reducing the cost and volume at the same time. Meanwhile, there is no need for a detection link, and the delay is eliminated by reconstructing the data.

[0051] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit this disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] The drawings are used to provide a further understanding of the present invention, and constitute a part of the specification. They are used to explain the present invention together with the embodiments of the present invention, and do not constitute a limitation to the present invention. Obviously, the drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0053] Figure 1 It is a schematic flowchart of a digital active EMI filtering method based on square wave analysis and reconstruction provided by an embodiment of this application.

[0054] Figure 2 It is a schematic flowchart of step S100 of a digital active EMI filtering method based on square wave analysis and reconstruction provided by an embodiment of this application.

[0055] Figure 3 It is a schematic flowchart of step S200 of a digital active EMI filtering method based on square wave analysis and reconstruction provided by an embodiment of this application.

[0056] Figure 4 It is a schematic flowchart of step S300 of a digital active EMI filtering method based on square wave analysis and reconstruction provided by an embodiment of this application.

[0057] Figure 5 It is a schematic flowchart of step S400 of a digital active EMI filtering method based on square wave analysis and reconstruction provided by an embodiment of the present application;

[0058] Figure 6 It is a logical schematic diagram of a digital active EMI filtering method based on square wave analysis and reconstruction provided by an embodiment of the present application;

[0059] Figure 7 It is a schematic diagram of an equivalent model of a compensation circuit of a digital active EMI filtering method based on square wave analysis and reconstruction provided by an embodiment of the present application;

[0060] Figure 8 It is a schematic diagram of PWM interruption logic of a digital active EMI filtering method based on square wave analysis and reconstruction provided by an embodiment of the present application;

[0061] Figure 9 It is a schematic diagram of compensation voltage data reconstruction of a digital active EMI filtering method based on square wave analysis and reconstruction provided by an embodiment of the present application;

[0062] Figure 10 It is a schematic diagram of a simulation spectrum effect of a digital active EMI filtering method based on square wave analysis and reconstruction provided by an embodiment of the present application;

[0063] Figure 11 It is a schematic diagram of the structure of a digital active EMI filtering circuit based on square wave analysis and reconstruction provided by an embodiment of the present application;

[0064] Figure 12 It is a schematic diagram of the circuit structure in the existing digital active EMI filtering technology in the background art of the present application. Detailed implementation manners

[0065] Now, example embodiments will be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be more complete and comprehensive, and will fully convey the concept of the example embodiments to those skilled in the art. The features, structures, or characteristics described may be combined in any suitable manner in one or more embodiments.

[0066] In this example embodiment, a digital active EMI filtering method based on square wave analysis and reconstruction for dynamic interference power management under feedback sparsity and observation loss conditions is first provided. Refer to Figure 1 As shown in, the digital active EMI filtering method based on square wave analysis and reconstruction may include the following steps:

[0067] Step S100: Obtain the waveform data of the common-mode noise source of the Buck circuit; wherein, the common-mode noise source waveform data is the time-domain waveform data points of the drain-source voltage of the lower transistor of the Buck circuit bridge arm.

[0068] Step S200: Determine the compensation capacitor parameters according to the equivalent model of the compensation circuit, and generate compensation voltage data that is reduced in proportion from the common-mode noise source waveform data.

[0069] Step S300: Through the synchronous control mechanism, synchronously output the PWM and the compensation voltage data, and inject them into the ground wire.

[0070] Step S400: Measure the delay between the PWM and the DAC, and reconstruct the compensation voltage data for delay compensation.

[0071] Through the above digital active EMI filtering method based on square wave analysis and reconstruction, it is possible to achieve a good EMI suppression effect with fewer circuit links, lower cost, smaller volume, and smaller delay. Perform simulink simulation on this method, and the simulation spectrum results are as Figure 10 shown. It can be seen that this method can achieve EMI attenuation of 20 - 30 dB in the full frequency band.

[0072] Next, reference will be made to Figures 2 to 6 to explain each step of the above digital active EMI filtering method based on square wave analysis and reconstruction in the exemplary embodiment in more detail.

[0073] In step S100, obtain the waveform data of the common-mode noise source of the Buck circuit; wherein, the common-mode noise source waveform data includes the rise time, fall time, switching period, and duty cycle.

[0074] It should be noted that first, the noise source is located. Through modeling and analysis, it can be known that the common-mode noise source of the Buck circuit is the voltage across the drain and source of the lower transistor , that is, the drain-source voltage of the lower transistor of the Buck circuit bridge arm.

[0075] In a possible implementation manner, step S100 may further include the following sub-steps:

[0076] In step S110, take the drain-source voltage of the lower transistor of the Buck circuit bridge arm as the common-mode noise source.

[0077] In step S120, obtain the drain-source voltage of the lower transistor of the Buck circuit bridge arm through the mathematical modeling method.

[0078] In step S130, the drain-source voltage of the lower transistor in the Buck circuit leg is equivalent to a trapezoidal wave, and a first formula is established to obtain the rise time, fall time, switching period, and duty cycle of the time-domain waveform of the drain-source voltage of the lower transistor in the Buck circuit leg; the first formula includes a rising stage, a flat-top stage, a falling stage, and a turn-off stage.

[0079] In step S140, based on the rise time, fall time, switching period, and duty cycle, the time-domain waveform data points of the drain-source voltage of the lower transistor in the Buck circuit leg are obtained.

[0080] Optionally, the method for obtaining the waveform data of the drain-source voltage of the lower transistor in the Buck circuit leg can also be: simulation method: simulating the circuit in simulation software and storing the waveform data; experimental test method: when the converter is operating in a steady state during an actual experiment, using an oscilloscope to measure the waveform of the lower transistor and storing the data.

[0081] Further, the first formula is:

[0082] ;

[0083] where, is the drain-source voltage of the lower transistor in the Buck circuit leg, is the input voltage of the Buck circuit, is the voltage rise time, is the voltage fall time, is the duty cycle, is the switching period, is the time.

[0084] It should be noted that in the first formula, is the rising stage, indicating that the voltage linearly rises to ; is the flat-top stage, indicating that the voltage maintains ; is the falling stage, indicating that the voltage linearly falls to 0V; is the turn-off stage, indicating that the voltage maintains 0V.

[0085] In step S200, based on the equivalent model of the compensation circuit, the compensation capacitor parameters are determined, and compensation voltage data that is a geometric reduction of the common-mode noise source waveform data is generated.

[0086] It should be noted that the equivalent model of the compensation circuit can be as Figure 7As shown, by abstracting components such as the noise source, compensation capacitor, parasitic capacitor, and LISN's ground branch in the actual circuit into a mathematical model, a simplified framework is provided for theoretical analysis, helping to derive the proportional relationship between the compensation voltage and the noise source, thereby determining the compensation capacitor parameters and verifying the compensation effect, and avoiding complex actual circuit debugging.

[0087] In a possible implementation, the step S200 may further include the following sub-steps:

[0088] In step S210, construct an equivalent model of the compensation circuit that includes the noise source , compensation capacitor , parasitic capacitor , and the LISN's ground branch .

[0089] In step S220, according to the equivalent model of the compensation circuit, use the superposition cancellation principle to obtain the relationship between the compensation voltage of the equivalent model and the noise source voltage of the equivalent model, and construct a second formula.

[0090] In step S230, according to the second formula, increase the compensation capacitor of the equivalent model, reduce the compensation voltage of the equivalent model to the output range of the DAC, and obtain the proportional coefficient and the compensation capacitor parameters.

[0091] In step S240, scale down the waveform data of the drain-source voltage of the lower transistor in the Buck circuit bridge arm according to the proportional coefficient to obtain the compensation voltage data, and store it in the digital controller.

[0092] It should be noted that by scaling down the waveform data of the drain-source voltage of the lower transistor in the Buck circuit bridge arm according to the proportional coefficient to obtain the compensation voltage data, it can be expressed as , and the obtained compensation voltage can be stored in the digital controller in the form of a look-up table.

[0093] Furthermore, the second formula is:

[0094] ;

[0095] Wherein, is the compensation voltage of the equivalent model, is the noise source voltage, is the parasitic capacitor, is the compensation capacitor, is the proportional coefficient.

[0096] It can be understood that by increasing to reduce the amplitude of the compensation voltage and ensure that it is within the output range of the DAC.

[0097] It should be noted that according to the equivalent model of the compensation circuit, the relationship between the compensation voltage of the equivalent model and the voltage of the noise source of the equivalent model is derived by using the superposition cancellation principle, and the third formula is obtained; the third formula is:

[0098] ;

[0099] Among them, is the impedance of the parasitic capacitance of the equivalent model, is the impedance of the LISN-to-ground branch of the equivalent model, is the impedance of the compensation capacitor.

[0100] The second formula is obtained by simplifying the third formula.

[0101] It can be understood that the superposition cancellation principle means that in a circuit, by injecting a compensation voltage with the same amplitude and opposite phase as the noise source voltage, the two cancel each other out after superposition at a specific node (such as the LISN port), thereby eliminating the common-mode noise.

[0102] In step S300, through the synchronous control mechanism, the PWM and the compensation voltage data are synchronously output and injected into the ground wire.

[0103] It should be noted that the PWM and the compensation voltage data are synchronously output.

[0104] In a possible implementation manner, step S300 may include the following sub-steps:

[0105] In step S310, the compensation voltage data is stored as an array, and the length corresponds to the number of sampling points of the switching period, obtaining a compensation voltage array.

[0106] It should be noted that the compensation voltage data can be stored as an array or a data table, and the system can be initialized, including: configuring the digital controller peripherals: initializing basic functions such as the clock and GPIO pins. Configuring the PWM module (which can be an enhanced pulse width modulation ePWM module), setting the switching frequency and duty cycle; initializing the DAC: setting the reference voltage and output range of the DAC, and configuring the triggering method of the DAC. At the same time, when storing the compensation voltage data as an array, the compensation voltage data can be discretized into a digital signal, and the data is stored as an array according to the number of sampling points of the switching period, and the array length is equal to the number of sampling points of the switching period to ensure that a complete compensation voltage waveform is output in each PWM period.

[0107] In step S320, the compensation voltage array is directly output from the memory to the DAC through direct memory access (DMA), and the output frequency is the same as the timer frequency.

[0108] It should be noted that when the DMA function is enabled, the compensation voltage array is directly transferred from the memory to the DAC. The DMA transfer frequency is set to be the same as the timer frequency to ensure the accurate output of each sampling point. The index of the compensation voltage array is strictly aligned with the PWM period to ensure that the first data point is output at the starting point of each switching cycle.

[0109] In step S330, interrupt the PWM so that at the start of each PWM, the starting point of the compensation voltage array output by the DAC is synchronized with the starting point of the PWM.

[0110] It should be noted that interrupting the PWM can be achieved by triggering an interrupt using the PWM rising edge. In the interrupt service routine, reset the array index to 0 and start the timer to ensure synchronization at the starting point of each switching cycle.

[0111] In step S340, inject the compensation voltage into the ground wire through the compensation capacitor via the DAC.

[0112] It can be understood that the compensation capacitor is used to ensure that the amplitude of the compensation voltage is adapted to the DAC output range. The compensation voltage data stored in the digital controller is converted into an analog voltage signal by the DAC. The compensation voltage and the common-mode noise are superimposed between the PE line and the ground, with opposite phases, to achieve noise cancellation.

[0113] Optionally, step S330 may include the following sub-steps:

[0114] In step S331, set the interrupt condition to reach the starting point of the PWM period.

[0115] In step S332, when an interrupt occurs, reset the output index of the compensation voltage array to 0.

[0116] In step S333, output the compensation voltage and the PWM with synchronized starting points.

[0117] It should be noted that as Figure 8 shown, it is the logic diagram of the PWM interrupt. By resetting the sequence number of the output compensation voltage array, starting the timer, and clearing the interrupt flag bit after triggering the interrupt, the starting point of the compensation voltage array is synchronously output with the starting point of the PWM.

[0118] In step S400, measure the delay between the PWM and the DAC, and reconstruct the compensation voltage data for delay compensation.

[0119] It should be noted that the time difference between the PWM signal and the DAC output compensation voltage can be actually measured ; move the first n data in the compensation voltage array to the end of the array to advance the phase of the compensation voltage , align it with the noise source, asFigure 9 As shown. Meanwhile, by monitoring the delay change in real time, the data sequence can be automatically updated through software algorithms to ensure stable compensation effect.

[0120] Furthermore, the step S400 may include the following sub-steps:

[0121] In step S410, the time difference between the actual test output of the compensation voltage and the PWM is measured.

[0122] In step S420, the first n data corresponding to the time difference in the compensation voltage array are moved to the end of the array.

[0123] Furthermore, in this exemplary embodiment, a digital active EMI filtering circuit based on square wave analysis and reconstruction is also provided for performing the above-mentioned digital active EMI filtering method based on square wave analysis and reconstruction. Refer to Figure 11 As shown, the circuit may include a LISN, an injection circuit, and a digital control circuit.

[0124] The LISN is connected to the measured buck circuit and is connected to the digital control circuit through the injection circuit, and is used to provide a stable impedance environment for electromagnetic interference measurement, so that the impedance seen from the power supply end is constant.

[0125] The digital control circuit includes a digital controller and a DAC connected to each other; the digital controller is used to acquire the waveform data of the common-mode noise source, and is used to store the compensation voltage data scaled down from the waveform data of the common-mode noise source, and is used to reconstruct the compensation voltage data for delay compensation, and is used to control the synchronization of the PWM and the output of the DAC; the DAC is used to perform analog output on the compensation voltage data.

[0126] The injection circuit includes a compensation capacitor for injecting the compensation voltage data output synchronously with the PWM into the ground wire.

[0127] It should be noted that the compensation voltage data is calculated in advance and stored in the digital controller. As Figure 11 shown, the LISN includes a power supply , a resistor , an inductor , a capacitor , and a resistor , which provides a stable impedance environment for EMI measurement, ensures that the impedance seen from the power supply end is constant, and guarantees the repeatability and accuracy of EMI measurement. , , constitute a filtering structure. The measured buck circuit, the Buck circuit, includes: a switching transistor and , Parasitic capacitance of the switching transistor , , Node switch , Connecting inductor , Output capacitance , Load , Common-mode capacitance at the output terminal and , Parasitic capacitance and drive ; Control and conduct alternately to achieve the buck function, connect the switching node to the protective ground wire; when the switching transistor conducts or turns off, the voltage at the point changes frequently, and coupled common-mode noise current is injected into the protective ground wire through

[0128] The overall working principle of the circuit is that LISN provides a stable basis for EMI measurement. When the Buck circuit works, common-mode noise is generated. The digital control circuit injects a compensation signal through the DAC and the compensation capacitor, and uses currents with opposite phases to cancel the noise, thereby reducing the EMI radiation of the system and achieving electromagnetic compatibility.

[0129] After considering the specification and practicing the invention disclosed herein, those skilled in the art will readily conceive of other embodiments of the present disclosure. This application is intended to cover any variations, uses, or adaptations of the present disclosure, which follow the general principles of the present disclosure and include known common general knowledge or conventional technical means in the technical field not disclosed in the present disclosure. The specification and examples are only regarded as exemplary, and the true scope and spirit of the present disclosure are pointed out by the appended claims.

[0130] The above embodiments are only used to illustrate the technical solutions of this application and are not restrictive thereof. This application is not limited to the exact structures already described and illustrated in the drawings, and it cannot be determined that the specific implementation of this application is only limited to these descriptions. For those of ordinary skill in the technical field to which this application belongs, without departing from the concept of this application, various changes and deformations made should be regarded as belonging to the protection scope of this application.

Claims

1. A digital active EMI filtering method based on square wave analysis and reconstruction, characterized in that Including: Obtaining the waveform data of the common-mode noise source of the Buck circuit; wherein, the common-mode noise source waveform data is the time-domain waveform data points of the drain-source voltage of the lower transistor of the Buck circuit bridge arm; specifically including: Taking the drain-source voltage of the lower transistor of the Buck circuit bridge arm as the common-mode noise source; Obtaining the drain-source voltage of the lower transistor of the Buck circuit bridge arm through the mathematical modeling method; Equivalent the drain-source voltage of the lower transistor of the Buck circuit bridge arm to a trapezoidal wave, and establish a first formula to obtain the rise time, fall time, switching period and duty cycle of the time-domain waveform of the drain-source voltage of the lower transistor of the Buck circuit bridge arm; the first formula includes: the rising stage, the flat-top stage, the falling stage and the turn-off stage; According to the rise time, fall time, switching period and duty cycle, obtain the time-domain waveform data points of the drain-source voltage of the lower transistor of the Buck circuit bridge arm; Wherein, the first formula is: ； Among them, is the drain-source voltage of the lower transistor in the Buck circuit arm, is the input voltage of the Buck circuit, is the voltage rise time, is the voltage fall time, is the duty cycle, is the switching period, is the time; Determine the compensation capacitor parameters according to the equivalent model of the compensation circuit, and generate compensation voltage data that is reduced in proportion to the common-mode noise source waveform data; Through the synchronous control mechanism, synchronously output the PWM and the compensation voltage data, and inject them into the ground wire; Measure the delay between the PWM and the DAC, and reconstruct the compensation voltage data for delay compensation.

2. The digital active EMI filtering method based on square wave analysis and reconstruction according to claim 1, wherein The step of determining the compensation capacitor parameters according to the equivalent model of the compensation circuit and generating compensation voltage data that is reduced in proportion to the common-mode noise source waveform data includes: Construct the equivalent model of the compensation circuit including the noise source, compensation capacitor, parasitic capacitor and the ground branch of the LISN; According to the equivalent model of the compensation circuit, use the principle of superposition cancellation to obtain the relationship between the equivalent model compensation voltage and the equivalent model noise source voltage, and construct a second formula; According to the second formula, increase the equivalent model compensation capacitor, and reduce the equivalent model compensation voltage to the output range of the DAC to obtain the proportionality coefficient and the compensation capacitor parameters; Reduce the waveform data of the drain-source voltage of the lower transistor of the Buck circuit bridge arm according to the proportionality coefficient to obtain the compensation voltage data, and store it in the digital controller.

3. The digital active EMI filtering method based on square wave analysis and reconstruction according to claim 2, characterized in that, The second formula is: ； Among them, is the equivalent model compensation voltage, is the noise source voltage, is the parasitic capacitance, is the compensation capacitance, is the proportionality coefficient.

4. The digital active EMI filtering method based on square wave analysis and reconstruction according to claim 3, characterized in that, The step of obtaining the relationship between the equivalent model compensation voltage and the equivalent model noise source voltage according to the equivalent model of the compensation circuit by using the principle of superposition cancellation and constructing a second formula includes: According to the equivalent model of the compensation circuit, use the principle of superposition cancellation to deduce the relationship between the equivalent model compensation voltage and the equivalent model noise source voltage to obtain a third formula; the third formula is: ； Among them, is the equivalent model parasitic capacitance impedance, is the equivalent model LISN impedance to the ground branch, is the compensation capacitance impedance; Simplify the third formula to obtain the second formula.

5. The digital active EMI filtering method based on square wave analysis and reconstruction according to claim 1, wherein The step of synchronously outputting the PWM and the compensation voltage data through the synchronous control mechanism and injecting them into the ground wire includes: Store the compensation voltage data as an array, the length corresponding to the number of sampling points of the switching period, to obtain a compensation voltage array; Output the compensation voltage array from the memory directly to the DAC through direct memory access, and the output frequency is the same as the timer frequency; Interrupt the PWM so that at the start of each PWM, the starting point of the compensation voltage array output by the DAC is synchronized with the starting point of the PWM; Inject the compensation voltage into the ground wire through the compensation capacitor by the DAC.

6. The digital active EMI filtering method based on square wave analysis and reconstruction according to claim 5, characterized in that The step of interrupting the PWM to synchronize the starting point of the compensation voltage array output by the DAC with the starting point of each PWM when each PWM starts includes: Setting the interrupt condition to reach the starting point of the PWM period; When an interrupt occurs, resetting the output index of the compensation voltage array to 0; Outputting the compensation voltage and the PWM with synchronized starting points.

7. The digital active EMI filtering method based on square wave analysis and reconstruction according to claim 1, wherein The step of measuring the delay between the PWM and the DAC and reconstructing the compensation voltage data to compensate for the delay includes: Actually testing the time difference between the output of the compensation voltage and the PWM; Moving the first n data corresponding to the time difference in the compensation voltage array to the end of the array.

8. A digital active EMI filtering circuit based on square wave analysis and reconstruction, characterized in that, The circuit is used to execute the digital active EMI filtering method based on square wave analysis and reconstruction according to any one of claims 1 to 7, and the circuit includes an injection circuit and a digital control circuit; The digital control circuit is connected to the EUT through the injection circuit and includes a digital controller and a DAC connected to each other; The digital controller is used to drive the switching tube, store the compensation voltage data scaled down from the common mode noise source waveform data, reconstruct the compensation voltage data for delay compensation, and control the synchronization of the PWM and the DAC output; The DAC is used to perform analog output on the compensation voltage data; The injection circuit includes a compensation capacitor for injecting the compensation voltage data output synchronized with the PWM into the ground wire.

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