Two-wire ternary circuit

Abstract

The invention provides a two-wire ternary circuit. The two-wire ternary circuit is used for carrying out ternary operation and comprises more than one two-wire input end, and each two-wire input end comprises a high-wire input end for inputting a high-wire input signal and a low-wire input end for inputting a low-wire input signal, the high-line input signal and the low-line input signal are respectively one of a high-level signal and a low-level signal; the two-line output end comprises a high-line output end for outputting a high-line output signal and a low-line output end for outputting a low-line output signal, and the high-line output signal and the low-line output signal are respectively one of a high-level signal and a low-level signal; the high line output end and the low line output end are respectively connected with the outputs of the two binary logic gates; or respectively connected with the output of a binary logic gate and one of the high-line input end and the low-line input end; or respectively connected with the low-line input end and the high-line input end.

Description

Technical Field

[0001] The present disclosure relates to a two-wire ternary circuit. Background Art

[0002] In a ternary circuit, ternary operations are performed through three state signals, for example, through 0, 1, 2, etc. In existing ternary circuits, the noise margin is very low (three levels need to be considered), the implementation speed of TFET is low, and it is currently difficult to have a chip implementation method, which is not enough for efficient operations. Moreover, the single-line representation is not parallel, resulting in low circuit symmetry, the need to introduce complement codes, misalignment and other fragmented situations. In addition, in current ternary circuits, it is difficult to implement operations in special states (such as high-impedance states). For example, GPIO ports usually have three forms: high level, low level and high-impedance states. Existing ternary circuits cannot implement high-impedance state operations, and binary circuits cannot implement high-impedance state operations. Summary of the invention

[0003] The present disclosure provides a two-wire ternary circuit.

[0004] According to one aspect of the present disclosure, a two-line ternary circuit is provided, which is used for performing ternary operations, including: a two-line input terminal, the number of the two-line input terminals is more than one, each of the two-line input terminals respectively includes a high-line input terminal for inputting a high-line input signal and a low-line input terminal for inputting a low-line input signal, the high-line input signal and the low-line input signal are respectively one of a high-level signal and a low-level signal; and a two-line output terminal, the number of the two-line output terminals is one and includes a high-line output terminal for outputting a high-line output signal and a low-line output terminal for outputting a low-line output signal, the high-line output signal and the low-line output signal are respectively one of the high-level signal and the low-level signal, the high-line output terminal and the low-line output terminal are respectively connected to the outputs of two binary logic gates; or are respectively connected to the output of a binary logic gate and one of the high-line input terminal and the low-line input terminal; or are respectively connected to the low-line input terminal and the high-line input terminal.

[0005] According to an embodiment of the present disclosure, the two-line ternary circuit further includes: a binary logic gate, the number of the binary logic gates is one or more, and the input of at least a part of the binary logic gates is connected to at least one input terminal of the high line input terminal and the low line input terminal.

[0006] According to a two-wire ternary circuit of one embodiment of the present disclosure, the two-wire ternary circuit is an inverter circuit, the number of the two-wire input terminal and the number of the two-wire output terminal are respectively one, wherein the high-line input terminal and the low-line input terminal of the two-wire input terminal are interlaced and respectively connected to the low-line output terminal and the high-line output terminal of the two-wire output terminal.

[0007] According to a two-line ternary circuit of an embodiment of the present disclosure, the two-line ternary circuit is a NAND gate circuit, the binary logic gate includes a NAND gate, a NOR gate, and a first inverter and a second inverter, the number of the two-line input terminals is two, the high-line input terminal of the first two-line input terminal is connected to one input of the NAND gate, the low-line input terminal of the first two-line input terminal is connected to one input of the NOR gate, the high-line input terminal of the second two-line input terminal is connected to the other input of the NAND gate, the low-line input terminal of the second two-line input terminal is connected to the other input of the NOR gate, the output of the NAND gate and the output of the NOR gate are respectively connected to the input of the first inverter and the input of the second inverter, the outputs of the first inverter and the second inverter are interleaved to output the low-line output signal and the high-line output signal respectively.

[0008] According to a two-line ternary circuit of an embodiment of the present disclosure, the two-line ternary circuit is an AND gate circuit, the binary logic gate includes a NAND gate, a NOR gate, a first inverter and a second inverter, the number of the two-line input terminals is two, the high-line input terminal of the first two-line input terminal is connected to one input of the NAND gate, the low-line input terminal of the first two-line input terminal is connected to one input of the NOR gate, the high-line input terminal of the second two-line input terminal is connected to the other input of the NAND gate, the low-line input terminal of the second two-line input terminal is connected to the other input of the NOR gate, the output of the NAND gate and the output of the NOR gate are respectively connected to the inputs of the first inverter and the second inverter, the outputs of the first inverter and the second inverter are not interleaved, and the high-line output signal and the low-line output signal are respectively output.

[0009] According to a two-line ternary circuit of an embodiment of the present disclosure, the two-line ternary circuit is a NOR gate circuit, the binary logic gate includes a NOR gate, a NAND gate, and a first inverter and a second inverter, the number of the two-line input terminals is two, the high-line input terminal of the first two-line input terminal is connected to one input of the NOR gate, the low-line input terminal of the first two-line input terminal is connected to one input of the NAND gate, the high-line input terminal of the second two-line input terminal is connected to the other input of the NOR gate, the low-line input terminal of the second two-line input terminal is connected to the other input of the NAND gate, the output of the NOR gate and the output of the NAND gate are respectively connected to the inputs of the first inverter and the second inverter, the outputs of the first inverter and the second inverter are interleaved to output the low-line output signal and the high-line output signal respectively.

[0010] According to a two-line ternary circuit of an embodiment of the present disclosure, the two-line ternary circuit is an OR gate circuit, the binary logic gate includes a NOR gate, a NAND gate, and a first inverter and a second inverter, the number of the two-line input terminals is two, the high-line input terminal of the first two-line input terminal is connected to one input of the NOR gate, the low-line input terminal of the first two-line input terminal is connected to one input of the NAND gate, the high-line input terminal of the second two-line input terminal is connected to the other input of the NOR gate, the low-line input terminal of the second two-line input terminal is connected to the other input of the NAND gate, the output of the NOR gate and the output of the NAND gate are connected to the inputs of the first inverter and the second inverter respectively, the outputs of the first inverter and the second inverter are not interleaved, and the high-line output signal and the low-line output signal are output respectively.

[0011] According to a two-line ternary circuit of one embodiment of the present disclosure, the two-line ternary circuit is a self-increasing gate circuit, the binary logic gate includes an NOR gate, the number of the two-line input terminal is one, the high-line input terminal of the two-line input terminal is connected to one input of the NOR gate, the low-line input terminal of the two-line input terminal is connected to the other input of the NOR gate, the NOR gate outputs a high-line output signal, and the low-line output signal is the high-line input signal of the high-line input terminal.

[0012] According to a two-line ternary circuit of one embodiment of the present disclosure, the two-line ternary circuit is a self-decrementing gate circuit, the binary logic gate includes an NOR gate, the number of the two-line input terminal is one, the high-line input terminal of the two-line input terminal is connected to one input of the NOR gate, the low-line input terminal of the two-line input terminal is connected to the other input of the NOR gate, the NOR gate outputs a low-line output signal, and the high-line output signal is the low-line input signal of the low-line input terminal.

[0013] According to a two-line ternary circuit of one embodiment of the present disclosure, the two-line ternary circuit is an inverter circuit, the binary logic gate includes a first inverter and a second inverter, the number of the two-line input terminals is one, the high-line input terminal and the low-line input terminal of the two-line input terminal are respectively connected to the input of the first inverter and the input of the second inverter, the output of the first inverter and the output of the second inverter are interleaved, and the low-line output signal and the high-line output signal are output respectively.

[0014] According to a two-line ternary circuit of an embodiment of the present disclosure, the two-line ternary circuit is a NAND gate circuit, the binary logic gate includes a first NAND gate and a second NAND gate, the number of the two-line input terminals is two, the high-line input terminal of the first two-line input terminal is connected to one input of the first NAND gate, the high-line input terminal of the second two-line input terminal is connected to the other input of the first NAND gate, the low-line input terminal of the first two-line input terminal is connected to one input of the second NAND gate, the low-line input terminal of the second two-line input terminal is connected to the other input of the second NAND gate, the output of the first NAND gate and the output of the second NAND gate are interlaced, and the low-line output signal and the high-line output signal are output respectively.

[0015] According to a two-line ternary circuit of an embodiment of the present disclosure, the two-line ternary circuit is an AND gate circuit, the binary logic gate includes a first NAND gate, a second NAND gate, a first inverter and a second inverter, the number of the two-line input terminals is two, the high-line input terminal of the first two-line input terminal is connected to one input of the first NAND gate, the high-line input terminal of the second two-line input terminal is connected to the other input of the first NAND gate, the low-line input terminal of the first two-line input terminal is connected to one input of the second NAND gate, the low-line input terminal of the second two-line input terminal is connected to the other input of the second NAND gate, the output of the first NAND gate and the output of the second NAND gate are respectively connected to the input of the first inverter and the input of the second inverter, the output of the first inverter and the output of the second inverter are not interleaved, and the high-line output signal and the low-line output signal are respectively output.

[0016] According to a two-line ternary circuit of an embodiment of the present disclosure, the two-line ternary circuit is an NOR gate circuit, the binary logic gate includes a first NOR gate and a second NOR gate, the number of the two-line input terminals is two, the high-line input terminal of the first two-line input terminal is connected to one input of the first NOR gate, the high-line input terminal of the second two-line input terminal is connected to the other input of the first NOR gate, the low-line input terminal of the first two-line input terminal is connected to one input of the second NOR gate, the low-line input terminal of the second two-line input terminal is connected to the other input of the second NOR gate, the output of the first NOR gate and the output of the second NOR gate are interlaced, and the low-line output signal and the high-line output signal are output respectively.

[0017] According to a two-line ternary circuit of an embodiment of the present disclosure, the two-line ternary circuit is an OR gate circuit, the binary logic gate includes a first NOR gate, a second NOR gate, a first inverter and a second inverter, the number of the two-line input terminals is two, the high-line input terminal of the first two-line input terminal is connected to one input of the first NOR gate, the high-line input terminal of the second two-line input terminal is connected to the other input of the first NOR gate, the low-line input terminal of the first two-line input terminal is connected to one input of the second NOR gate, the low-line input terminal of the second two-line input terminal is connected to the other input of the second NOR gate, the output of the first NOR gate and the output of the second NOR gate are respectively connected to the input of the first inverter and the input of the second inverter, the output of the first inverter and the output of the second inverter are not interleaved, and the high-line output signal and the low-line output signal are respectively output.

[0018] According to a two-line ternary circuit of one embodiment of the present disclosure, the two-line ternary circuit is a self-increasing gate circuit, the binary logic gate includes an inverter, a NOR gate and a NAND gate, the number of the two-line input terminal is one, the high-line input terminal of the two-line input terminal is connected to one input of the NOR gate and one input of the NAND gate, the low-line input terminal of the two-line input terminal is connected to the input of the inverter and the other input of the NAND gate, the output of the inverter is connected to the other input of the NOR gate, and the NOR gate and the NAND gate output a high-line output signal and a low-line output signal respectively.

[0019] According to a two-line ternary circuit of one embodiment of the present disclosure, the two-line ternary circuit is a self-decrementing gate circuit, the binary logic gate includes an inverter, a NOR gate and a NAND gate, the number of the two-line input terminals is one, the high-line input terminal of the two-line input terminal is connected to one input of the NOR gate and the input of the inverter, the output of the inverter is connected to one input of the NAND gate, the low-line input terminal of the two-line input terminal is connected to the other input of the NOR gate and the other input of the NAND gate, and the NOR gate and the NAND gate output a high-line output signal and a low-line output signal respectively.

[0020] The two-wire ternary circuit disclosed in the present invention has good symmetry and can introduce special states, and can be used as the first integrated circuit solution to actually realize balanced ternary operations. The logic depth of the transistor is 1 or 2, which does not reduce the circuit speed. It has a high degree of symmetry and no longer requires complement code, etc. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The accompanying drawings illustrate exemplary embodiments of the present disclosure and together with the description serve to explain the principles of the present disclosure. These drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification.

[0022] Figure 1 is a circuit diagram of an inverter according to an embodiment of the present disclosure.

[0023] Figure 2 is a diagram showing an inverter according to an embodiment of the present disclosure.

[0024] Figure 3 is a circuit diagram of a NAND gate according to an embodiment of the present disclosure.

[0025] Figure 4 is a diagram showing a NAND gate according to an embodiment of the present disclosure.

[0026] Figure 5 is a truth table of a NAND gate according to an embodiment of the present disclosure.

[0027] Figure 6 is a circuit diagram of an AND gate according to an embodiment of the present disclosure.

[0028] Figure 7 is a diagram showing an AND gate according to an embodiment of the present disclosure.

[0029] Figure 8 is a truth table of an AND gate according to an embodiment of the present disclosure.

[0030] Fig. 9 is a circuit diagram of a NOR gate according to an embodiment of the present disclosure.

[0031] Fig.10 is a diagram showing a NOR gate according to an embodiment of the present disclosure.

[0032] Fig.11 is a truth table of a NOR gate according to an embodiment of the present disclosure.

[0033] Fig.12 is a circuit diagram of an OR gate according to an embodiment of the present disclosure.

[0034] Fig.13 is a diagram showing an OR gate according to an embodiment of the present disclosure.

[0035] Fig.14 is a truth table of an OR gate according to an embodiment of the present disclosure.

[0036] Fig.15 is a circuit diagram of a self-increasing gate according to an embodiment of the present disclosure.

[0037] Fig.16 is a diagram showing a self-increasing gate according to an embodiment of the present disclosure.

[0038] Fig.17 is a circuit diagram of a self-decrementing gate according to an embodiment of the present disclosure.

[0039] Fig.18 is a diagram showing a self-reducing gate according to an embodiment of the present disclosure.

[0040] Fig.19 is a circuit diagram of a decoder according to an embodiment of the present disclosure.

[0041] Fig. 20 is a diagram showing a decoder according to an embodiment of the present disclosure.

[0042] Fig.21 is a diagram showing a converter according to an embodiment of the present disclosure.

[0043] Fig. 22 is a diagram showing a converter according to an embodiment of the present disclosure.

[0044] Fig.23 is a circuit diagram of a NAND gate with three two-wire input terminals according to an embodiment of the present disclosure.

[0045] Fig.24 is a diagram showing a NAND gate with three two-wire input terminals according to an embodiment of the present disclosure.

[0046] Fig.25 is a circuit diagram of an inverter according to another embodiment of the present disclosure.

[0047] Fig.26 is a diagram showing an inverter according to another embodiment of the present disclosure.

[0048] Fig. 27 is a circuit diagram of a NAND gate according to another embodiment of the present disclosure.

[0049] Fig.28 is a diagram showing a NAND gate according to another embodiment of the present disclosure.

[0050] Fig.29 is a truth table of a NAND gate according to another embodiment of the present disclosure.

[0051] Fig.30 is a circuit diagram of an AND gate according to another embodiment of the present disclosure.

[0052] Fig.31 is a diagram showing an AND gate according to another embodiment of the present disclosure.

[0053] Fig.32 is a truth table of an AND gate according to another embodiment of the present disclosure.

[0054] Fig.33 is a circuit diagram of a NOR gate according to another embodiment of the present disclosure.

[0055] Fig.34 is a diagram showing a NOR gate according to another embodiment of the present disclosure.

[0056] Fig.35 is a truth table of a NOR gate according to another embodiment of the present disclosure.

[0057] Fig.36 is a circuit diagram of an OR gate according to another embodiment of the present disclosure.

[0058] Fig.37 is a diagram showing an OR gate according to another embodiment of the present disclosure.

[0059] Fig.38 is a truth table of an OR gate according to another embodiment of the present disclosure.

[0060] Fig.39 is a circuit diagram of a self-increasing gate according to another embodiment of the present disclosure.

[0061] Fig.40 is a diagram showing a self-increasing gate according to another embodiment of the present disclosure.

[0062] Fig.41 is a circuit diagram of a self-decrementing gate according to another embodiment of the present disclosure.

[0063] Fig.42 is a diagram showing a self-reducing gate according to another embodiment of the present disclosure.

[0064] Fig.43 is a diagram showing a converter according to another embodiment of the present disclosure.

[0065] Fig.44 is a diagram showing a converter according to another embodiment of the present disclosure.

[0066] Fig.45 is a circuit diagram of a NAND gate with three two-wire input terminals according to another embodiment of the present disclosure.

[0067] Fig.46 is a diagram showing a NAND gate with three two-wire input terminals according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0068] The present disclosure is further described in detail below in conjunction with the accompanying drawings and implementations. It is understood that the specific implementations described herein are only used to explain the relevant content, rather than to limit the present disclosure. It should also be noted that, for ease of description, only the parts related to the present disclosure are shown in the accompanying drawings.

[0069] It should be noted that, in the absence of conflict, the embodiments and features of the embodiments in the present disclosure can be combined with each other. The technical solution of the present disclosure will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0070] According to an embodiment of the present disclosure, a two-wire ternary circuit is provided, and the ternary circuit is used for performing ternary operations. In the ternary circuit of the present disclosure, a two-wire input and two-wire output method is adopted, so that high-impedance operations can be realized, and ternary operations can be realized through a two-bit logic gate.

[0071] The two-line ternary circuit disclosed in the present invention may include: a two-line input terminal and a two-line output terminal. The number of the two-line input terminals is more than one, such as one or two, and of course more than three. Each two-line input terminal includes a high-line input terminal for inputting a high-line input signal and a low-line input terminal for inputting a low-line input signal, and the high-line input signal and the low-line input signal are respectively one of a high-level signal and a low-level signal. The number of the two-line output terminals is one and includes a high-line output terminal for outputting a high-line output signal and a low-line output terminal for outputting a low-line output signal, and the high-line output signal and the low-line output signal are respectively one of a high-level signal and a low-level signal, and the high-line output terminal and the low-line output terminal are respectively connected to the outputs of two binary logic gates; or respectively connected to the output of a binary logic gate and one of the high-line input terminal and the low-line input terminal; or respectively connected to the low-line input terminal or the high-line input terminal. In addition, a binary logic gate may also be included. The number of the binary logic gates is one or more, and the inputs of at least a part of the binary logic gates are connected to at least one of the high-line input terminal and the low-line input terminal.

[0072] The following will describe various implementations of ternary circuits based on the design ideas of the present disclosure. It can be seen from the following embodiments that the logic depth of the transistor is 1 or 2, so that the ternary operation speed can be guaranteed, and the representation of special states can be realized.

[0073] According to an embodiment of the present disclosure, a plurality of binary two-wire ternary circuits are provided, wherein the embodiment may include Figures 1 to 24The embodiment shown. In this embodiment, each state of the ternary system is realized in a binary manner, wherein the three states of the ternary system may include a first state +, a second state -, a third state 0, and a special state. The special state may be one of a high impedance state, an error state, and the like. Each binary two-line input signal includes two input signals, such as a high line in the two lines corresponding to a first input signal (high line input signal), and a low line for a second input signal (low line input signal). The two input signals may be one of a first level and a second level, wherein the first level is a high level and the second level is a low level, or the first level is a low level and the second level is a high level. The ternary signal is represented as +, 0, -. When the high-line input signal of the two input signals of the binary two-line input signal is at the first level and the level of the high-line input signal is different from that of the low-line input signal, the ternary signal is +; when the low-line input signal of the two input signals is at the first level and the level of the high-line input signal is different from that of the low-line input signal, the ternary signal is -; when the low-line input signal and the high-line input signal of the two input signals are the same, the ternary signal is 0 (for example, both the low-line input signal and the high-line input signal are 0). For a special state, the low-line input signal and the high-line input signal may be the same, and the ternary signal indicates a special state (for example, both the low-line input signal and the high-line input signal are 1). In the following embodiments, the binary two-line input signals A, B, and C are each input from a two-line input terminal.

[0074] Figure 1 A ternary circuit using a binary two-wire method according to an embodiment of the present disclosure is shown, wherein the ternary circuit is an inverter. The inverter of this embodiment can be implemented without transistors, and only the high line and the low line need to be interlaced. In this way, the logic depth of the transistor of the inverter of this embodiment is 0, and it has a high degree of symmetry. The inverter includes two input terminals, and the two input terminals are respectively connected to the high line input signal AH and the low line input signal AL of the binary two-wire input signal A, and the high line input signal AH and the low line input signal AL can be a high level signal or a low level signal. The binary two-wire output signal O of the inverter includes a high line output signal OH and a low line output signal OL. The high line input signal AH and the low line input signal AL are interlaced to form a low line output signal OL and a high line output signal OH respectively.

[0075] When the ternary signal is +(10), the high line input signal AH is 1 and the low line input signal AL is 0, so that the high line output signal OH is 0 and the low line output signal OL is 1. The inverter can output the ternary signal + as a ternary signal -(01). When the ternary signal is -(01), the high line input signal AH is 0 and the low line input signal AL is 1, so that the high line output signal OH is 1 and the low line output signal OL is 0. The inverter can output the ternary signal - as a ternary signal +(10). When the ternary signal is 0(00), the high line input signal AH is 0 and the low line input signal AL is 0, so that the high line output signal OH is 0 and the low line output signal OL is 0. The inverter can output the ternary signal - as a ternary signal 0(00). Figure 2 Shows Figure 1 The representation of the inverter.

[0076] Figure 3 A ternary circuit using a binary two-wire method according to an embodiment of the present disclosure is shown, wherein the ternary circuit is a NAND gate circuit. The transistor logic depth of the NAND gate circuit of this embodiment is 2 and has symmetry.

[0077] like Figure 3 As shown, the NAND gate circuit includes a binary NAND gate 301, a binary NOR gate 302, a first binary NOT gate 303, and a second binary NOT gate 304. The two input ends of the binary NAND gate 301 are respectively connected to the high line input signal AH of the first binary two-line input signal A and the high line input signal BH of the second binary two-line input signal B. The two input ends of the binary NOR gate 302 are respectively connected to the low line input signal AL of the first binary two-line input signal A and the low line input signal BL of the second binary two-line input signal B. The binary NAND gate 301 and the binary NOR gate 302 each include an output end, the output end of the binary NAND gate 301 is connected to an input end of the first binary NOT gate 303, and the output end of the binary NOR gate 302 is connected to an input end of the second binary NOT gate 304. The first binary NOT gate 303 and the second binary NOT gate 304 each include an input end and an output end. The output signal of the output terminal of the first binary NOT gate 303 is interleaved with the output signal of the output terminal of the second binary NOT gate 304 to form a binary two-line output signal O, wherein the binary two-line output signal O includes a high line output signal OH and a low line output signal OL. Figure 4 Shows Figure 3 Representation of a ternary NAND gate.

[0078] Figure 5 Shows Figure 3 and Figure 4 Truth table of the NAND gate circuit of the illustrated embodiment.

[0079] For the first binary two-line input signal A, when the high line input signal AH is 1 (high level) and the low line input signal AL is 0 (low level), the ternary signal of the first binary two-line input signal A is +; when the high line input signal AH is 0 and the low line input signal AL is 1, the ternary signal of the first binary two-line input signal A is -; when the high line input signal AH is 0 and the low line input signal AL is 0, the ternary signal of the first binary two-line input signal A is 0.

[0080] For the second binary two-line input signal B, when the high line input signal BH is 1 (high level) and the low line input signal BL is 0 (low level), the ternary signal of the second binary two-line input signal B is +; when the high line input signal BH is 0 and the low line input signal BL is 1, the ternary signal of the second binary two-line input signal B is -; when the high line input signal BH is 0 and the low line input signal BL is 0, the ternary signal of the second binary two-line input signal B is 0.

[0081] For the binary two-line output signal O, when the high-line output signal OH is 1 (high level) and the low-line output signal OL is 0 (low level), the ternary signal of the binary two-line output signal O is +; when the high-line output signal OH is 0 and the low-line output signal OL is 1, the ternary signal of the binary two-line output signal O is -; when the high-line output signal OH is 0 and the low-line output signal OL is 0, the ternary signal of the binary two-line output signal O is 0.

[0082] The following description will refer to the above method. Of course, it can also be another case, when AH is 0 and AL is 1, the ternary signal is +; when AH is 1 and AL is 0, the ternary signal is -; when AH is 0 and AL is 0, the ternary signal is 0.

[0083] Reference Figure 4 and Figure 5Detailed description. As an example, take A as + and B as + as an example for explanation. In the ternary calculation process, the ternary signal of the first binary two-line input signal A is + and the ternary signal of the second binary two-line input signal B is +, then the ternary signal of the binary two-line output signal O is -. If the high-line input signal AH is 1 and the low-line input signal AL is 0, the high-line input signal BH is 1 and the low-line input signal BL is 0. The two input ends of the binary NAND gate 301 are respectively connected to the high-line input signal AH and the high-line input signal BH. The output signal of the binary NAND gate 301 is 0, the output signal of the first binary NOT gate 303 is 1, and the low-line output signal OL is 1. The two input ends of the binary NOR gate 302 are respectively connected to the low-line input signal AL and the low-line input signal BL. The output signal of the binary NOR gate 302 is 1, the output signal of the second binary NOT gate 304 is 0, and the high-line output signal OH is 0. In this way, the output signal O is 10, and its ternary signal is +. For other ternary calculations, please refer to the relevant contents of the truth table.

[0084] Figure 6 A ternary circuit using a binary two-wire method according to an embodiment of the present disclosure is shown, wherein the ternary circuit is an AND gate circuit. The AND gate circuit of this embodiment has a transistor logic depth of 2 and is symmetrical.

[0085] like Figure 6 As shown, the AND gate circuit includes a binary NAND gate 601, a binary NOR gate 602, a first binary NOT gate 603, and a second binary NOT gate 604. The two input ends of the binary NAND gate 601 are respectively connected to the high line input signal AH of the first binary two-line input signal A and the high line input signal BH of the second binary two-line input signal B. The two input ends of the binary NOR gate 602 are respectively connected to the low line input signal AL of the first binary two-line input signal A and the low line input signal BL of the second binary two-line input signal B. The binary NAND gate 601 and the binary NOR gate 602 each include an output end, the output end of the binary NAND gate 601 is connected to an input end of the first binary NOT gate 603, and the output end of the binary NOR gate 602 is connected to an input end of the second binary NOT gate 604. The first binary NOT gate 603 and the second binary NOT gate 604 each include an input end and an output end. The output signal of the output terminal of the first binary NOT gate 603 and the output signal of the output terminal of the second binary NOT gate 604 are not interleaved to form a binary two-line output signal O, wherein the binary two-line output signal O includes a high line output signal OH and a low line output signal OL. Figure 7 Shows Figure 6 Representation of the ternary AND gate.

[0086] Figure 8 Shows Figure 6and Figure 7 The truth table of the AND gate circuit of the embodiment shown. For the relationship between ternary numbers, please refer to Figure 5 Related description. Figure 6 and Figure 8 Detailed description. As an example, take A as - and B as 0 for explanation. In the ternary calculation process, the ternary signal of the first binary two-line input signal A is - and the ternary signal of the second binary two-line input signal B is 0, then the ternary signal of the binary two-line output signal O is -. If the high-line input signal AH is 0 and the low-line input signal AL is 1, the high-line input signal BH is 0 and the low-line input signal BL is 0. The two input ends of the binary NAND gate 601 are respectively connected to the high-line input signal AH and the high-line input signal BH. The output signal of the binary NAND gate 601 is 1, the output signal of the first binary NOT gate 603 is 0, then the high-line output signal OH is 0. The two input ends of the binary NOR gate 602 are respectively connected to the low-line input signal AL and the low-line input signal BL. The output signal of the binary NOR gate 602 is 0, the output signal of the second binary NOT gate 604 is 1, then the low-line output signal OH is 1. In this way, the output signal O is 01, and its ternary signal is -. For other ternary calculations, please refer to the relevant contents of the truth table.

[0087] Fig. 9 A ternary circuit using a binary two-wire method according to an embodiment of the present disclosure is shown, wherein the ternary circuit is a NOR gate circuit. The transistor logic depth of the NOR gate circuit of this embodiment is 2 and has symmetry.

[0088] like Fig. 9 As shown, the NOR gate circuit includes a binary NOR gate 901, a binary NAND gate 902, a first binary NOT gate 903, and a second binary NOT gate 904. The two input ends of the binary NOR gate 901 are respectively connected to the high line input signal AH of the first binary two-line input signal A and the high line input signal BH of the second binary two-line input signal B. The two input ends of the binary NAND gate 902 are respectively connected to the low line input signal AL of the first binary two-line input signal A and the low line input signal BL of the second binary two-line input signal B. The binary NOR gate 901 and the binary NAND gate 902 each include an output end, the output end of the binary NOR gate 901 is connected to an input end of the first binary NOT gate 903, and the output end of the binary NAND gate 902 is connected to an input end of the second binary NOT gate 904. The first binary NOT gate 903 and the second binary NOT gate 904 each include an input end and an output end. The output signal of the output terminal of the first binary NOT gate 903 is interleaved with the output signal of the output terminal of the second binary NOT gate 904 to form a binary two-line output signal O, wherein the binary two-line output signal O includes a high line output signal OH and a low line output signal OL. Fig.10 Shows Fig. 9 Representation of a ternary NOR gate.

[0089] Fig.11 Shows Fig. 9 and Fig.10 The truth table of the NOR gate circuit in the embodiment shown. For the relationship between the ternary systems, please refer to Figure 5 Related description. Fig. 9 and Fig.11 Detailed description. As an example, take A as 0 and B as - for example. In the ternary calculation process, the ternary signal of the first binary two-line input signal A is 0 and the ternary signal of the second binary two-line input signal B is -, then the ternary signal of the binary two-line output signal O is 0. If the high-line input signal AH is 0 and the low-line input signal AL is 0, the high-line input signal BH is 0 and the low-line input signal BL is 1. The two input ends of the binary NOR gate 901 are respectively connected to the high-line input signal AH and the high-line input signal BH. The output signal of the binary NOR gate 901 is 1, the output signal of the first binary NOT gate 903 is 0, and the low-line output signal OL is 0. The two input ends of the binary NAND gate 902 are respectively connected to the low-line input signal AL and the low-line input signal BL. The output signal of the binary NAND gate 902 is 1, the output signal of the second binary NOT gate 904 is 0, and the high-line output signal OH is 0. In this way, the output signal O is 00, and its ternary signal is 0. For other ternary calculations, please refer to the relevant contents of the truth table.

[0090] Fig.12 A ternary circuit using a binary two-wire method according to an embodiment of the present disclosure is shown, wherein the ternary circuit is an OR gate circuit. The transistor logic depth of the OR gate circuit of this embodiment is 2 and has symmetry.

[0091] like Fig.12As shown, the OR gate circuit includes a binary NOR gate 1201, a binary NAND gate 1202, a first binary NOT gate 1203, and a second binary NOT gate 1204. The two input ends of the binary NOR gate 1201 are respectively connected to the high line input signal AH of the first binary two-line input signal A and the high line input signal BH of the second binary two-line input signal B. The two input ends of the binary NAND gate 1202 are respectively connected to the low line input signal AL of the first binary two-line input signal A and the low line input signal BL of the second binary two-line input signal B. The binary NOR gate 1201 and the binary NAND gate 1202 each include an output end, the output end of the binary NOR gate 1201 is connected to an input end of the first binary NOT gate 1203, and the output end of the binary NAND gate 1202 is connected to an input end of the second binary NOT gate 1204. The first binary NOT gate 1203 and the second binary NOT gate 1204 each include an input end and an output end. The output signal of the output end of the first binary NOT gate 1203 is interleaved with the output signal of the output end of the second binary NOT gate 1204 to form a binary two-line output signal O, wherein the binary two-line output signal O includes a high line output signal OH and a low line output signal OL. Fig.13 Shows Fig.12 The representation of the ternary OR gate.

[0092] Fig.14 Shows Fig.12 and Fig.13 The truth table of the OR gate circuit in the embodiment shown. For the relationship between the ternary systems, please refer to Figure 5 Related description. Fig.12 and Fig.14 Detailed description. As an example, take A as - and B as - for explanation. In the ternary calculation process, the ternary signal of the first binary two-line input signal A is - and the ternary signal of the second binary two-line input signal B is -, then the ternary signal of the binary two-line output signal O is -. If the high-line input signal AH is 0 and the low-line input signal AL is 1, the high-line input signal BH is 0 and the low-line input signal BL is 1. The two input ends of the binary NOR gate 1201 are respectively connected to the high-line input signal AH and the high-line input signal BH. The output signal of the binary NOR gate 1201 is 1, the output signal of the first binary NOT gate 1203 is 0, and the high-line output signal OH is 0. The two input ends of the binary NAND gate 1202 are respectively connected to the low-line input signal AL and the low-line input signal BL. The output signal of the binary NAND gate 1202 is 0, the output signal of the second binary NOT gate 1204 is 1, and the low-line output signal OL is 1. In this way, the output signal O is 01, and its ternary signal is -. For other ternary calculations, please refer to the relevant contents of the truth table.

[0093] Fig.15A ternary circuit using a binary two-wire method according to an embodiment of the present disclosure is shown, wherein the ternary circuit is a recurring gate circuit, specifically a self-increment gate circuit. The transistor logic depth of the self-increment gate circuit of this embodiment is 1.

[0094] like Fig.15 As shown, the self-increment gate circuit includes a binary NOR gate 1501. The two input ends of the binary NOR gate 1501 are respectively connected to the high line input signal AH and the low line input signal AL of the binary two-line input signal A. According to the self-increment gate circuit of this embodiment, it can cycle between the first state +, the second state 0 and the third state -. The output of the binary NOR gate 1501 is the high line output signal OH, and the high line input signal AH is used as the low line output signal OL. The cycle of the self-increment gate circuit can be, for example, -0+-0... For example, in the third state -, the high line input signal AH is 0 and the low line input signal AL is 1, then the output signal of the binary NOR gate 1501 is 0, that is, the high line output signal OH is 0. The high line input signal AH is the low line output signal OL, that is, the low line output signal OL is 0. In this way, the output of the self-increment gate is 00, that is, it is transformed into the second state 0. In the second state 0, the high line input signal AH is 0 and the low line input signal AL is 0, then the output signal of the binary NOR gate 1501 is 1, that is, the high line output signal OH is 1. The high line input signal AH is the low line output signal OL, that is, the low line output signal OL is 0. In this way, the output of the self-increment gate is 10, which is the first state +. In the first state +, the high line input signal AH is 1 and the low line input signal AL is 0, then the output signal of the binary NOR gate 1501 is 0, that is, the high line output signal OH is 0. The high line input signal AH is the low line output signal OL, that is, the low line output signal OL is 1. In this way, the output of the self-increment gate is 01, which is the third state -. This cycle is repeated. Fig.16 Shows Fig.15 The representation of the self-increasing gate.

[0095] Fig.17 A ternary circuit using a binary two-wire method according to an embodiment of the present disclosure is shown, wherein the ternary circuit is a recurring gate circuit, specifically a self-decreasing gate circuit. The transistor logic depth of the self-decreasing gate circuit of this embodiment is 1. And the self-increment gate circuit is symmetrical with the self-decreasing gate circuit.

[0096] like Fig.17As shown, the self-increment gate circuit includes a binary NOR gate 1701. The two input ends of the binary NOR gate 1701 are respectively connected to the high line input signal AH and the low line input signal AL of the binary two-line input signal A. According to the self-decrement gate circuit of this embodiment, it can cycle between the first state +, the second state 0 and the third state -. The output of the binary NOR gate 1701 is the low line output signal OL, and the low line input signal AL is used as the high line output signal OH. The cycle of the self-decrement gate circuit can be, for example, -+0-+0... For example, in the third state -, the high line input signal AH is 0 and the low line input signal AL is 1, then the output signal of the binary NOR gate 1701 is 0, that is, the low line output signal OL is 0. The low line input signal AL is the high line output signal OH, that is, the high line output signal OL is 1. In this way, the output of the self-increment gate is 10, that is, the first state +. In the first state +, the high line input signal AH is 1 and the low line input signal AL is 0, then the output signal of the binary NOR gate 1701 is 0, that is, the low line output signal OL is 0. The low line input signal AL is the high line output signal OH, that is, the high line output signal OH is 0. In this way, the output of the self-increment gate is 00, which is the second state 0. In the second state 0, the high line input signal AH is 0 and the low line input signal is 0, then the output signal of the binary NOR gate 1701 is 1, that is, the low line output signal OL is 1. The low line input signal AL is the high line output signal OH, that is, the high line output signal OH is 0. In this way, the output of the self-increment gate is 01, which is the third state -. This cycle is repeated. Fig.18 Shows Fig.17 The representation of the self-decrement gate.

[0097] Fig.19 A ternary circuit using a binary two-wire method according to an embodiment of the present disclosure is shown, wherein the ternary circuit is a decoder circuit. The transistor logic depth of the decoder circuit of this embodiment is only 1.

[0098] The decoder circuit is designed so that, in the case of the first ternary state +, the output P is high and the outputs Z and N are low; in the case of the second ternary state 0, the output Z is high and the outputs P and N are low; and in the case of the third ternary state -, the output N is high and the outputs P and Z are low.

[0099] like Fig.19As shown, the decoder circuit includes a binary NOR gate 1901. The high line input signal AH and the low line input signal AL are respectively connected to the two input terminals of the binary NOR gate 1901, and the output terminal of the binary NOR gate 1901 is connected to the output Z. The high line input signal AH is connected to the output P. The low line input signal AL is connected to the output N. As an example, in the case of the first state +, AH is 1 and AL is 0, so that the high line input signal AH, that is, the output P is 1, the output of the binary NOR gate 1901, that is, the output Z is 0, and the low line input signal AL, that is, the output N is 0, so that the output P is 1 and the outputs Z and N are 0, which corresponds to the first state +. The second state and the third state are the same and will not be repeated. Fig. 20 Shows Fig.19 The representation of the decoder.

[0100] Fig.21 and Fig. 22 The converter for converting between two-wire system and single-wire system is shown. The converter circuit of this embodiment reduces the number of pins, is more modular than conventional multi-valued logic circuits, and has better speed and noise tolerance performance. Fig.21 The converter from two-wire to single-wire is shown. Fig. 22 A converter from a single-wire system to a two-wire system is shown. Fig.21 The converter of the embodiment converts the two-wire signal A into a single-wire signal O, for example, converts 00 into 0, converts 10 into +, and converts 01 into -. In addition, when the two-wire signal A is 11, it can also be converted into a special state. Fig. 22 The converter shown converts the single-wire signal O into a two-wire signal A. Fig. 22 The converter can be realized by using an existing analog comparator. Fig. 22 The converter of the embodiment can convert the ternary signal represented by the ternary system into a two-line ternary signal, and the converted two-line ternary signal can be input to Figure 1-20 A high line input terminal and a low line input terminal of an embodiment. Fig.21 The converter of the embodiment can convert the two-wire ternary signal into a ternary signal represented by a ternary system, Fig.21 The input signal A (AH and AL) of the embodiment can be connected to the high line output terminal OH and the low line input terminal OL of each embodiment of the figure respectively.

[0101] In each of the above embodiments, one or two two-wire input terminals (A or B) are included, but more than three two-wire input terminals may also be included. Fig.23 It is shown in Figure 3 The illustrated embodiment corresponds to three two-wire input terminals of the NAND gate. Fig.23 and Figure 3 The difference in the circuit structure of the embodiment is that Fig.23The embodiment includes three two-line input terminals A, B and C. The high-line input signals AH, BH and CH are respectively connected to the three input terminals of the NAND gate 2301, and the low-line input signals AL, BL and CL are respectively connected to the three input terminals of the NOR gate 2302. The output terminal of the NAND gate 2301 is connected to the input terminal of the first inverter 2303, and the output terminal of the NOR gate 2302 is connected to the input terminal of the second inverter 2304. The output terminals of the first inverter 2303 and the second inverter 2304 are interleaved to output the low-line output signal OL and the high-line output signal OH respectively. Fig.24 Shows Fig.23 In addition, for other suitable embodiments of this implementation, more than three two-wire input terminals may be used, which will not be described in detail here.

[0102] According to another embodiment of the present disclosure, a plurality of binary two-wire ternary circuits are provided, wherein the embodiment may include Figures 25 to 46 The embodiment shown. In this embodiment, each state of the ternary system is realized in a binary manner, wherein the three states of the ternary system may include a first state +, a second state -, a third state 0 and a special state. The special state may be one of a high impedance state, an error state, etc. Each binary two-line input signal includes two input signals, such as a high line of the two lines corresponding to a first input signal (high line input signal), and a low line corresponding to a second input signal (low line input signal). The two input signals may be one of a first level and a second level, wherein the first level and the second level are high levels and the second level is a low level. The ternary signal is represented by +, 0, -. In the two input signals of the binary two-line input signal, when the high line input signal is high level (1) and the low line input signal is high level (1), the ternary signal is +; when the high line input signal is low level (0) and the low line input signal is high level (1), the ternary signal is 0; when the high line input signal is low level (0) and the low line input signal is low level (0), the ternary signal is -. In addition, when the high-line input signal is at a high level (1) and the low-line input signal is at a low level (0), the ternary signal is a special state signal.

[0103] Fig.25A ternary circuit using a binary two-wire method according to an embodiment of the present disclosure is shown, wherein the ternary circuit is an inverter. The inverter of this embodiment can be implemented by binary logic gate expansion and the expansion method is symmetrical, consistent with the logic depth of binary, and will not sacrifice the circuit speed. The inverter includes two input terminals, and the two input terminals are respectively connected to the high-line input signal AH and the low-line input signal AL of the binary two-line input signal A, and the high-line input signal AH and the low-line input signal AL can be a high-level signal or a low-level signal. The binary two-line output signal O of the inverter includes a high-line output signal OH and a low-line output signal OL. The high-line input signal AH is connected to the first binary NOT gate 2501, and the low-line input signal AL is connected to the second binary NOT gate 2502. The outputs of the first binary NOT gate 2501 and the second binary NOT gate 2502 are interleaved to form a low-line output signal OL and a high-line output signal OH respectively.

[0104] When the ternary signal is +(11), the high line input signal AH is 1 and the low line input signal AL is 1. The output of the first binary NOT gate 2501 is 0, and the output of the second binary NOT gate 2502 is 0, so that the high line output signal OH is 0 and the low line output signal OL is 0. Through the inverter, the ternary signal + can be output as a ternary signal -(00). When the ternary signal is -(00), the high line input signal AH is 0 and the low line input signal AL is 0. The output of the first binary NOT gate 2501 is 1, and the output of the second binary NOT gate 2502 is 1, so that the high line output signal OH is 1 and the low line output signal OL is 1. Through the inverter, the ternary signal - can be output as a ternary signal +(11). When the ternary signal is 0(01), the high line input signal AH is 0 and the low line input signal AL is 1, so that the high line output signal OH is 0 and the low line output signal OL is 1. The inverter can output the ternary signal 0 as a ternary signal 0 (01). Fig.26 Shows Fig.25 The representation of the inverter.

[0105] Fig. 27 A ternary circuit using a binary two-wire method according to an embodiment of the present disclosure is shown, wherein the ternary circuit is a NAND gate circuit. The NAND gate circuit of this embodiment can be implemented by expanding a binary logic gate and the expansion method is symmetrical, consistent with the logic depth of binary, and does not sacrifice circuit speed.

[0106] like Fig. 27As shown, the NAND gate circuit includes a binary NAND gate 2701 and a binary NAND gate 2702. The two input ends of the binary NAND gate 2701 are respectively connected to the high line input signal AH of the first binary two-line input signal A and the high line input signal BH of the second binary two-line input signal B. The two input ends of the binary NAND gate 2702 are respectively connected to the low line input signal AL of the first binary two-line input signal A and the low line input signal BL of the second binary two-line input signal B. The output signals of the output ends of the binary NAND gate 2701 and the binary NAND gate 2702 are interleaved to form a binary two-line output signal O, wherein the binary two-line output signal O includes a high line output signal OH (the output signal of the binary NAND gate 2702) and a low line output signal OL (the output signal of the binary NAND gate 2701). Fig.28 Shows Fig. 27 Representation of a ternary NAND gate.

[0107] Fig.29 Shows Fig. 27 and Fig.28 Truth table of the NAND gate circuit of the illustrated embodiment.

[0108] For the first binary two-line input signal A, when the high line input signal AH is 1 (high level) and the low line input signal AL is 1, the ternary signal of the first binary two-line input signal A is +; when the high line input signal AH is 0 (low level) and the low line input signal AL is 0, the ternary signal of the first binary two-line input signal A is -; when the high line input signal AH is 0 and the low line input signal AL is 1, the ternary signal of the first binary two-line input signal A is 0; when the high line input signal AH is 1 and the low line input signal AL is 0, the ternary signal of the first binary two-line input signal A represents a special state.

[0109] For the second binary two-line input signal B, when the high line input signal BH is 1 (high level) and the low line input signal BL is 1, the ternary signal of the second binary two-line input signal B is +; when the high line input signal BH is 0 (low level) and the low line input signal BL is 0, the ternary signal of the second binary two-line input signal B is -; when the high line input signal BH is 0 and the low line input signal BL is 1, the ternary signal of the second binary two-line input signal B is 0; when the high line input signal BH is 1 and the low line input signal BL is 0, the ternary signal of the second binary two-line input signal B represents a special state.

[0110] For the binary two-line output signal O, when the high-line output signal OH is 1 (high level) and the low-line output signal OL is 1, the ternary signal of the binary two-line output signal O is +; when the high-line output signal OH is 0 (low level) and the low-line output signal OL is 0, the ternary signal of the binary two-line output signal O is -; when the high-line output signal OH is 0 and the low-line output signal OL is 0, the ternary signal of the binary two-line output signal O is 0; when the high-line output signal OH is 1 and the low-line output signal OL is 0, the ternary signal of the binary two-line output signal O represents a special state.

[0111] Reference Fig. 27 and Fig.29 Detailed description. As an example, take A as + and B as + as an example for explanation. In the ternary calculation process, the ternary signal of the first binary two-line input signal A is + and the ternary signal of the second binary two-line input signal B is +, then the ternary signal of the binary two-line output signal O is -. If the high-line input signal AH is 1 and the low-line input signal AL is 1, the high-line input signal BH is 1 and the low-line input signal BL is 1. The two input ends of the binary NAND gate 2701 are respectively connected to the high-line input signal AH and the high-line input signal BH. The output signal of the binary NAND gate 2701 is 0, and the low-line output signal OL is 0. The two input ends of the binary NAND gate 2702 are respectively connected to the low-line input signal AL and the low-line input signal BL. The output signal of the binary NAND gate 2702 is 0, and the high-line output signal OH is 0. In this way, the output signal O is 00, and its ternary signal is -. For other ternary calculations, refer to the relevant contents of the truth table.

[0112] Fig.30 A ternary circuit using a binary two-wire method according to an embodiment of the present disclosure is shown, wherein the ternary circuit is an AND gate circuit. The AND gate circuit of this embodiment can be implemented by expanding a binary logic gate and the expansion method is symmetrical, consistent with the logic depth of binary, and does not sacrifice circuit speed.

[0113] like Fig.30As shown, the AND gate circuit includes a binary NAND gate 3001, a binary NAND gate 3002, a first binary NOT gate 3003, and a second binary NOT gate 3004. The two input ends of the binary NAND gate 3001 are respectively connected to the high line input signal AH of the first binary two-line input signal A and the high line input signal BH of the second binary two-line input signal B. The two input ends of the binary NAND gate 3002 are respectively connected to the low line input signal AL of the first binary two-line input signal A and the low line input signal BL of the second binary two-line input signal B. The binary NAND gate 3001 and the binary NAND gate 3002 each include an output end, the output end of the binary NAND gate 3001 is connected to an input end of the first binary NOT gate 3003, and the output end of the binary NAND gate 3002 is connected to an input end of the second binary NOT gate 3004. The first binary NOT gate 3003 and the second binary NOT gate 3004 each include an input end and an output end. The output signal of the output end of the first binary NOT gate 3003 and the output signal of the output end of the second binary NOT gate 3004 are not interleaved, forming a binary two-line output signal O, wherein the binary two-line output signal O includes a high-line output signal OH and a low-line output signal OL, the high-line output signal OH is the output signal of the first binary NOT gate 3003, and the low-line output signal OL is the output signal of the second binary NOT gate 3004. Fig.31 Shows Fig.30 Representation of the ternary AND gate.

[0114] Fig.32 Shows Fig.30 and Fig.31 The truth table of the AND gate circuit of the embodiment shown. For the relationship between ternary numbers, please refer to Fig.29 Related description. Fig.30 and Fig.32Detailed description. As an example, take A as - and B as 0 for explanation. In the ternary calculation process, the ternary signal of the first binary two-line input signal A is - and the ternary signal of the second binary two-line input signal B is 0, then the ternary signal of the binary two-line output signal O is -. If the high line input signal AH is 0 and the low line input signal AL is 0, the high line input signal BH is 0 and the low line input signal BL is 1. The two input ends of the binary NAND gate 3001 are respectively connected to the high line input signal AH and the high line input signal BH. The output signal of the binary NAND gate 3001 is 1, and the output signal of the first binary NOT gate 3003 is 0, then the high line output signal OH is 0. The two input ends of the binary NAND gate 3002 are respectively connected to the low line input signal AL and the low line input signal BL. The output signal of the binary NAND gate 3002 is 0, and the output signal of the second binary NOT gate 3004 is 1, then the low line output signal OH is 0, so the output signal O is 00, and its ternary signal is -. Other ternary calculations can refer to the relevant contents of the truth table.

[0115] Fig.33 A ternary circuit using a binary two-wire method according to an embodiment of the present disclosure is shown, wherein the ternary circuit is a NOR gate circuit. The NOR gate circuit of this embodiment can be implemented by expanding a binary logic gate and the expansion method is symmetrical, consistent with the logic depth of binary, and does not sacrifice circuit speed.

[0116] like Fig.33 As shown, the NOR gate circuit includes a binary NOR gate 3301 and a binary NOR gate 3302. The two input ends of the binary NOR gate 3301 are respectively connected to the high line input signal AH of the first binary two-line input signal A and the high line input signal BH of the second binary two-line input signal B. The two input ends of the binary NOR gate 3302 are respectively connected to the low line input signal AL of the first binary two-line input signal A and the low line input signal BL of the second binary two-line input signal B. The output signal of the output end of the first binary NOT gate 3303 is interleaved with the output signal of the output end of the second binary NOT gate 3304 to form a binary two-line output signal O, wherein the binary two-line output signal O includes a high line output signal OH and a low line output signal OL. The high line output signal OH is the output signal of the second binary NOT gate 3304, and the low line output signal OL is the output signal of the first binary NOT gate 3303. Fig.34 Shows Fig.33 Representation of a ternary NOR gate.

[0117] Fig.35 Shows Fig.33 and Fig.34 The truth table of the NOR gate circuit in the embodiment shown. For the relationship between the ternary systems, please refer to Fig. 27Related description. Fig.33 and Fig.35 Detailed description. As an example, take A as 0 and B as - for explanation. In the ternary calculation process, the ternary signal of the first binary two-line input signal A is 0 and the ternary signal of the second binary two-line input signal B is -, then the ternary signal of the binary two-line output signal O is 0. For example, the high-line input signal AH is 0 and the low-line input signal AL is 1, the high-line input signal BH is 0 and the low-line input signal BL is 0. The two input ends of the binary NOR gate 3301 are respectively connected to the high-line input signal AH and the high-line input signal BH. If the output signal of the binary NOR gate 3301 is 1, the low-line output signal OL is 1. The two input ends of the binary NOR gate 3302 are respectively connected to the low-line input signal AL and the low-line input signal BL. If the output signal of the binary NOR gate 3302 is 0, the high-line output signal OH is 0. In this way, the output signal O is 01, and its ternary signal is 0. For other ternary calculations, refer to the relevant contents of the truth table.

[0118] Fig.36 A ternary circuit using a binary two-wire method according to an embodiment of the present disclosure is shown, wherein the ternary circuit is an OR gate circuit. The OR gate circuit of this embodiment can be implemented by expanding a binary logic gate and the expansion method is symmetrical, consistent with the logic depth of binary, and does not sacrifice circuit speed.

[0119] like Fig.36As shown, the OR gate circuit includes a binary NOR gate 3601, a binary NOR gate 3602, a first binary NOT gate 3603, and a second binary NOT gate 3604. The two input ends of the binary NOR gate 3601 are respectively connected to the high line input signal AH of the first binary two-line input signal A and the high line input signal BH of the second binary two-line input signal B. The two input ends of the binary NOR gate 3602 are respectively connected to the low line input signal AL of the first binary two-line input signal A and the low line input signal BL of the second binary two-line input signal B. The binary NOR gate 3601 and the binary NOR gate 3602 each include an output end, the output end of the binary NOR gate 3601 is connected to an input end of the first binary NOT gate 3603, and the output end of the binary NOR gate 3602 is connected to an input end of the second binary NOT gate 3604. The first binary NOT gate 3603 and the second binary NOT gate 3604 each include an input end and an output end. The output signal of the output end of the first binary NOT gate 3603 and the output signal of the output end of the second binary NOT gate 3604 are not interleaved to form a binary two-line output signal O, wherein the binary two-line output signal O includes a high-line output signal OH and a low-line output signal OL, the high-line output signal OH is the output signal of the first binary NOT gate 3603, and the low-line output signal OL is the output signal of the second binary NOT gate 3604. Fig.37 Shows Fig.36 The representation of the ternary OR gate.

[0120] Fig.38 Shows Fig.36 and Fig.37 The truth table of the OR gate circuit in the embodiment shown. For the relationship between the ternary systems, please refer to Fig.29 Related description. Fig.36 and Fig.38Detailed description. As an example, take A as - and B as - for explanation. In the ternary calculation process, the ternary signal of the first binary two-line input signal A is - and the ternary signal of the second binary two-line input signal B is -, then the ternary signal of the binary two-line output signal O is -. If the high-line input signal AH is 0 and the low-line input signal AL is 0, the high-line input signal BH is 0 and the low-line input signal BL is 0. The two input ends of the binary NOR gate 3601 are respectively connected to the high-line input signal AH and the high-line input signal BH. The output signal of the binary NOR gate 3601 is 1, and the output signal of the first binary NOT gate 3603 is 0, then the high-line output signal OH is 0. The two input ends of the binary NOR gate 3602 are respectively connected to the low-line input signal AL and the low-line input signal BL. The output signal of the binary NOR gate 3602 is 1, and the output signal of the second binary NOT gate 3604 is 0, then the low-line output signal OL is 0. In this way, the output signal O is 00, and its ternary signal is -. For other ternary calculations, please refer to the relevant contents of the truth table.

[0121] Fig.39 A ternary circuit using a binary two-wire method according to an embodiment of the present disclosure is shown, wherein the ternary circuit is a recurring gate circuit, specifically a self-increasing gate circuit.

[0122] like Fig.39As shown, the self-increment gate circuit includes a binary NOT gate 3901, a binary NOR gate 3902 and a binary NAND gate 3903. The binary NOT gate 3901 has an input terminal connected to the low line input signal AL of the binary two-line input signal A. The binary NOR gate 3902 has two input terminals, respectively connected to the high line input signal AH of the binary two-line input signal A and the output signal of the binary NOT gate 3901. The binary NAND gate 3903 has two input terminals, respectively connected to the high line input signal AH and the low line input signal AL of the binary two-line input signal A. The output signal of the binary NOR gate 3902 is the high line output signal OH. The output signal of the binary NAND gate 3903 is the low line output signal OL. According to the self-increment gate circuit of this embodiment, it can be cycled between the first state +, the second state 0 and the third state -. The cycle of the self-increment gate circuit can be, for example, -0+-0... For example, in the third state -, the high line input signal AH is 0 and the low line input signal AL is 0. The output signal of the binary NOT gate 3901 is 1, the output signal of the binary NOR gate 3902 is 0, and the output signal of the binary NAND gate 3903 is 1. Thus, the high-line output signal OH is 0, and the low-line output signal OL is 1, and the state is changed to the second state 0 (01). In the second state 0, the high-line input signal AH is 0 and the low-line input signal AL is 1. The output signal of the binary NOT gate 3901 is 0, the output signal of the binary NOR gate 3902 is 1, and the output signal of the binary NAND gate 3903 is 1. Thus, the high-line output signal OH is 1, and the low-line output signal OL is 1, and the state is changed to the first state + (11). In the first state +, the high-line input signal AH is 1 and the low-line input signal AL is 1. The output signal of the binary NOT gate 3901 is 0, the output signal of the binary NOR gate 3902 is 0, and the output signal of the binary NAND gate 3903 is 0. Thus, the high-line output signal OH is 0, and the low-line output signal OL is 0, and the state is changed to the third state - (00). The cycle continues in this way. Fig.40 Shows Fig.39 The representation of the self-increasing gate.

[0123] Fig.41 A ternary circuit using a binary two-wire method according to an embodiment of the present disclosure is shown, wherein the ternary circuit is a recurring gate circuit, specifically a self-decreasing gate circuit.

[0124] like Fig.41As shown, the self-increment gate circuit includes a binary NOT gate 4101, a binary NOR gate 4102 and a binary NAND gate 4103. The binary NOT gate 4101 has an input terminal connected to the high line input signal AH of the binary two-line input signal A. The binary NOR gate 4102 has two input terminals, respectively connected to the high line input signal AH and the low line input signal AL of the binary two-line input signal A. The binary NAND gate 4103 has two input terminals, respectively connected to the output signal of the binary NOT gate 4101 and the low line input signal AL of the binary two-line input signal A. The output signal of the binary NOR gate 4102 is the high line output signal OH. The output signal of the binary NAND gate 4103 is the low line output signal OL. According to the self-increment gate circuit of this embodiment, it can cycle between the first state +, the second state 0 and the third state -. The cycle of the self-decrement gate circuit can be, for example, -+0-+0... For example, in the third state -, the high line input signal AH is 0 and the low line input signal AL is 0, then the output signal of the binary NOR gate 4102 is 1, the output signal of the binary NOT gate 4101 is 1, the output signal of the binary NAND gate 4103 is 1, then the high line output signal OH is 1, and the low line output signal OL is 1. In this way, the output of the self-increment gate is 11, which is the first state +. In the first state +, the high line input signal AH is 1 and the low line input signal AL is 1, then the output signal of the binary NOR gate 4102 is 0, the output signal of the binary NOT gate 4101 is 0, the output signal of the binary NAND gate 4103 is 1, then the high line output signal OH is 0, and the low line output signal OL is 1. In this way, the output of the self-increment gate is 01, which is the second state 0. In the second state 0, the high line input signal AH is 0 and the low line input signal is 1, then the output signal of the binary NOR gate 4102 is 0, the output signal of the binary NOT gate 4101 is 1, and the output signal of the binary NAND gate 4103 is 0, then the high line output signal OH is 0, and the low line output signal OL is 0. In this way, the output of the self-increment gate is 00, which is the third state -. This cycle is repeated. Fig.42 Shows Fig.41 The representation of the self-decrement gate.

[0125] Fig.43 and Fig.44 The figure shows a converter for converting between two-wire system and single-wire system. Fig.43 The converter from two-wire to single-wire is shown. Fig.44 A converter from a single-wire system to a two-wire system is shown. Fig.43 The converter of the embodiment converts the two-wire signal A into a single-wire signal O, for example, converts 11 into +, converts 00 into -, and converts 01 into 0. In addition, when the two-wire signal A is 10, it can also be converted into a special state. Fig.44 The converter shown converts the single-wire signal O into a two-wire signal A. Fig.42 The converter can be realized by using an existing analog comparator. Fig.44 The converter of the embodiment can convert the ternary signal represented by ternary into a two-line ternary signal, and the converted two-line ternary signal can be input to the high line input terminal and the low line input terminal of each embodiment of the above-mentioned another implementation mode. Fig.43 The converter of the embodiment can convert the two-wire ternary signal into a ternary signal represented by a ternary system, Fig.43 The input signal A (AH and AL) of the embodiment can be connected to the high line output terminal OH and the low line input terminal OL of each embodiment of the above-mentioned another implementation manner respectively.

[0126] In each of the above embodiments of another implementation mode, one or two two-wire input terminals (A or B) are included respectively, but more than three two-wire input terminals may also be included. Fig.45 It is shown in Fig.25 The illustrated embodiment corresponds to three two-wire input terminals of the NAND gate. Fig.45 and Fig.25 The difference in the circuit structure of the embodiment is that Fig.45 The embodiment includes three two-line input terminals A, B and C. The high-line input signals AH, BH and CH are respectively connected to the three input terminals of the NAND gate 4501, and the low-line input signals AL, BL and CL are respectively connected to the three input terminals of the NOR gate 4502. The output terminal of the NAND gate 4501 and the output terminal of the NOR gate 4502 are interleaved to output the low-line output signal OL and the high-line output signal OH respectively. Fig.46 Shows Fig.45 In addition, for other suitable embodiments of this implementation, more than three two-wire input terminals may be used, which will not be described in detail here.

[0127] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0128] Those skilled in the art should understand that the above embodiments are only for the purpose of clearly illustrating the present disclosure, and are not intended to limit the scope of the present disclosure. For those skilled in the art, other changes or modifications may be made based on the above disclosure, and these changes or modifications are still within the scope of the present disclosure.

Claims

1. A two-wire ternary circuit, the two-wire ternary circuit is used for performing ternary operations, characterized in that: include: Two-line input terminals, the number of the two-line input terminals is more than one, each of the two-line input terminals comprises a high-line input terminal for inputting a high-line input signal and a low-line input terminal for inputting a low-line input signal, the high-line input signal and the low-line input signal are respectively one of a high-level signal and a low-level signal; as well as Two-line output terminal, the number of the two-line output terminal is one and includes a high-line output terminal that outputs a high-line output signal and a low-line output terminal that outputs a low-line output signal, the high-line output signal and the low-line output signal are respectively one of the high-level signal and the low-level signal, the high-line output terminal and the low-line output terminal are respectively connected to the outputs of two binary logic gates; or respectively connected to the output of a binary logic gate and one of the high-line input terminal and the low-line input terminal; or respectively connected to the low-line input terminal and the high-line input terminal.

2. The two-wire ternary circuit according to claim 1, characterized in that: Also includes: The binary logic gates are one or more in number, and the inputs of at least a part of the binary logic gates are connected to at least one of the high-line input terminal and the low-line input terminal.

3. The two-wire ternary circuit according to claim 1, characterized in that: The two-line ternary circuit is an inverter circuit. The number of the two-line input terminal and the number of the two-line output terminal are respectively one, wherein the high-line input terminal and the low-line input terminal of the two-line input terminal are staggered and respectively connected to the low-line output terminal and the high-line output terminal of the two-line output terminal.

4. The two-wire ternary circuit as claimed in claim 2, characterized in that: The two-line ternary circuit is a NAND gate circuit. The binary logic gate includes a NAND gate, a NOR gate, a first inverter and a second inverter. The number of the two-line input terminals is two. The high-line input terminal of the first two-line input terminal is connected to one input of the NAND gate, the low-line input terminal of the first two-line input terminal is connected to one input of the NOR gate, the high-line input terminal of the second two-line input terminal is connected to the other input of the NAND gate, the low-line input terminal of the second two-line input terminal is connected to the other input of the NOR gate, the output of the NAND gate and the output of the NOR gate are connected to the input of the first inverter and the input of the second inverter respectively, the outputs of the first inverter and the second inverter are interleaved, and the low-line output signal and the high-line output signal are output respectively.

5. The two-wire ternary circuit as claimed in claim 2, characterized in that: The two-line ternary circuit is an AND gate circuit, The binary logic gate includes a NAND gate, a NOR gate, a first inverter and a second inverter. The number of the two-line input terminals is two. The high-line input terminal of the first two-line input terminal is connected to one input of the NAND gate, the low-line input terminal of the first two-line input terminal is connected to one input of the NOR gate, the high-line input terminal of the second two-line input terminal is connected to the other input of the NAND gate, the low-line input terminal of the second two-line input terminal is connected to the other input of the NOR gate, the output of the NAND gate and the output of the NOR gate are connected to the inputs of the first inverter and the second inverter respectively, the outputs of the first inverter and the second inverter are not interleaved, and the high-line output signal and the low-line output signal are output respectively.

6. The two-wire ternary circuit as claimed in claim 2, characterized in that: The two-line ternary circuit is a NOR gate circuit. The binary logic gate includes a NOR gate, a NAND gate, a first inverter and a second inverter. The number of the two-line input terminals is two. The high-line input terminal of the first two-line input terminal is connected to one input of the NOR gate, the low-line input terminal of the first two-line input terminal is connected to one input of the NAND gate, the high-line input terminal of the second two-line input terminal is connected to the other input of the NOR gate, the low-line input terminal of the second two-line input terminal is connected to the other input of the NAND gate, the output of the NOR gate and the output of the NAND gate are connected to the inputs of the first inverter and the second inverter respectively, and the outputs of the first inverter and the second inverter are interleaved to output low-line output signals and high-line output signals respectively.

7. The two-wire ternary circuit according to claim 2, characterized in that: The two-line ternary circuit is an OR gate circuit. The binary logic gate includes a NOR gate, a NAND gate, a first inverter and a second inverter. The number of the two-line input terminals is two. The high-line input terminal of the first two-line input terminal is connected to one input of the NOR gate, the low-line input terminal of the first two-line input terminal is connected to one input of the NAND gate, the high-line input terminal of the second two-line input terminal is connected to the other input of the NOR gate, the low-line input terminal of the second two-line input terminal is connected to the other input of the NAND gate, the output of the NOR gate and the output of the NAND gate are connected to the inputs of the first inverter and the second inverter respectively, the outputs of the first inverter and the second inverter are not interleaved, and the high-line output signal and the low-line output signal are output respectively.

8. The two-wire ternary circuit as claimed in claim 2, characterized in that: The two-line ternary circuit is a self-increasing gate circuit. The binary logic gate comprises an NOR gate, the number of the two-line input terminal is one, the high-line input terminal of the two-line input terminal is connected to one input of the NOR gate, the low-line input terminal of the two-line input terminal is connected to the other input of the NOR gate, the NOR gate outputs a high-line output signal, and the low-line output signal is the high-line input signal of the high-line input terminal.

9. The two-wire ternary circuit according to claim 2, characterized in that: The two-line ternary circuit is a self-decreasing gate circuit. The binary logic gate includes an NOR gate, the number of the two-line input terminal is one, the high-line input terminal of the two-line input terminal is connected to one input of the NOR gate, the low-line input terminal of the two-line input terminal is connected to the other input of the NOR gate, the NOR gate outputs a low-line output signal, and the high-line output signal is the low-line input signal of the low-line input terminal.

10. The two-wire ternary circuit according to claim 2, characterized in that: The two-line ternary circuit is an inverter circuit. The binary logic gate includes a first inverter and a second inverter, the number of the two-line input terminal is one, the high-line input terminal and the low-line input terminal of the two-line input terminal are respectively connected to the input of the first inverter and the input of the second inverter, the output of the first inverter and the output of the second inverter are interleaved, and the low-line output signal and the high-line output signal are output respectively.

11. The two-wire ternary circuit according to claim 2, characterized in that: The two-line ternary circuit is a NAND gate circuit. The binary logic gate includes a first NAND gate and a second NAND gate. The number of the two-line input terminals is two. The high-line input terminal of the first two-line input terminal is connected to one input of the first NAND gate, the high-line input terminal of the second two-line input terminal is connected to the other input of the first NAND gate, the low-line input terminal of the first two-line input terminal is connected to one input of the second NAND gate, and the low-line input terminal of the second two-line input terminal is connected to the other input of the second NAND gate. The output of the first NAND gate and the output of the second NAND gate are interlaced to output a low-line output signal and a high-line output signal respectively.

12. The two-wire ternary circuit according to claim 2, characterized in that: The two-line ternary circuit is an AND gate circuit, The binary logic gate includes a first NAND gate, a second NAND gate, a first inverter and a second inverter. The number of the two-line input terminals is two. The high-line input terminal of the first two-line input terminal is connected to one input of the first NAND gate, the high-line input terminal of the second two-line input terminal is connected to the other input of the first NAND gate, the low-line input terminal of the first two-line input terminal is connected to one input of the second NAND gate, and the low-line input terminal of the second two-line input terminal is connected to the other input of the second NAND gate. The output of the first NAND gate and the output of the second NAND gate are respectively connected to the input of the first inverter and the input of the second inverter. The output of the first inverter and the output of the second inverter are not interleaved, and the high-line output signal and the low-line output signal are output respectively.

13. The two-wire ternary circuit according to claim 2, characterized in that: The two-line ternary circuit is a NOR gate circuit. The binary logic gate includes a first NOR gate and a second NOR gate, the number of the two-line input terminals is two, the high-line input terminal of the first two-line input terminal is connected to one input of the first NOR gate, the high-line input terminal of the second two-line input terminal is connected to the other input of the first NOR gate, the low-line input terminal of the first two-line input terminal is connected to one input of the second NOR gate, the low-line input terminal of the second two-line input terminal is connected to the other input of the second NOR gate, the output of the first NOR gate and the output of the second NOR gate are interlaced, and the low-line output signal and the high-line output signal are output respectively.

14. The two-wire ternary circuit according to claim 2, characterized in that: The two-line ternary circuit is an OR gate circuit. The binary logic gate includes a first NOR gate, a second NOR gate, a first inverter and a second inverter. The number of the two-line input terminals is two. The high-line input terminal of the first two-line input terminal is connected to one input of the first NOR gate, the high-line input terminal of the second two-line input terminal is connected to the other input of the first NOR gate, the low-line input terminal of the first two-line input terminal is connected to one input of the second NOR gate, and the low-line input terminal of the second two-line input terminal is connected to the other input of the second NOR gate. The output of the first NOR gate and the output of the second NOR gate are respectively connected to the input of the first inverter and the input of the second inverter. The output of the first inverter and the output of the second inverter are not interleaved, and the high-line output signal and the low-line output signal are output respectively.

15. The two-wire ternary circuit according to claim 2, characterized in that: The two-line ternary circuit is a self-increasing gate circuit. The binary logic gate includes an inverter, a NOR gate and a NAND gate. The number of the two-line input terminal is one. The high-line input terminal of the two-line input terminal is connected to one input of the NOR gate and one input of the NAND gate. The low-line input terminal of the two-line input terminal is connected to the input of the inverter and the other input of the NAND gate. The output of the inverter is connected to the other input of the NOR gate. The NOR gate and the NAND gate output a high-line output signal and a low-line output signal respectively.

16. The two-wire ternary circuit according to claim 2, characterized in that: The two-line ternary circuit is a self-decreasing gate circuit. The binary logic gate includes an inverter, a NOR gate and a NAND gate. The number of the two-line input terminal is one. The high-line input terminal of the two-line input terminal is connected to one input of the NOR gate and the input of the inverter. The output of the inverter is connected to one input of the NAND gate. The low-line input terminal of the two-line input terminal is connected to the other input of the NOR gate and the other input of the NAND gate. The NOR gate and the NAND gate output a high-line output signal and a low-line output signal respectively.

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