Magnetic isolation coding and decoding circuit

Abstract

The invention relates to the technical field of analog integrated circuits, in particular to a magnetic isolation coding and decoding circuit, which comprises a transmitting end circuit, an isolation transformer and a receiving end circuit, and is characterized in that the transmitting end circuit comprises a logic control circuit, an oscillator, a pulse generation circuit and a driving circuit; the receiving end circuit comprises a pulse filtering circuit, a band-gap reference circuit, a comparator circuit, a phase inverter and a D trigger; according to the invention, by adding amplitude variation, a high pulse signal is further pulled up, a low pulse signal is grounded and pulled down, then a common-mode signal is filtered out, and a refresh pulse is additionally added to help real-time monitoring of the signal, so that the interference resistance and reliability of signal transmission are greatly improved, and a power switch device is effectively protected.

Description

Technical Field

[0001] The present invention relates to the technical field of analog integrated circuits, and in particular to a magnetic isolation encoding and decoding circuit. Background Art

[0002] In the prior art, the modulation methods of magnetically coupled digital isolators include four traditional modulation methods: set-reset modulation, polarity pulse modulation, pulse count modulation, and on-off keying modulation. The principle of set-reset modulation is to modulate the rising edge of the data signal into one pulse signal and the falling edge into another pulse signal. After receiving the rising edge pulse, the decoding circuit sets the output of the digital isolator to high, and resets the input after receiving the falling edge pulse signal. This modulation method has a simple circuit structure, but is easily affected by noise interference, causing errors in the output signal and damage to the power device. Summary of the invention

[0003] Aiming at the problem that the set-reset signal modulation mode in the traditional magnetic coupling digital isolator is susceptible to noise interference, the present invention proposes a magnetic isolation encoding and decoding circuit, including a transmitting end circuit, an isolation transformer and a receiving end circuit, the transmitting end circuit includes a logic control circuit, an oscillator, a pulse generating circuit, and a driving circuit, and the receiving end circuit includes a pulse filtering circuit, a bandgap reference circuit, a comparator circuit, an inverter and a D flip-flop, wherein:

[0004] A logic control circuit, used for providing a clock signal and a switch signal for the driving circuit and an enable signal for the pulse generating circuit according to the oscillator and the input signal;

[0005] A pulse generating circuit, used for generating a pulse signal according to an enable signal provided by the logic control circuit, and inputting the generated pulse signal into the driving circuit;

[0006] A driving circuit, used for providing a driving signal to the isolation transformer;

[0007] The pulse filtering circuit is used to receive the high pulse signal and the low pulse signal coupled from the secondary coil of the isolation transformer, and modulate them into two high pulse signals and low pulse signals presented in negative pulses;

[0008] A bandgap reference circuit is used to provide a common-mode voltage for the secondary coil of the isolation transformer and a bias voltage for the pulse filtering circuit;

[0009] A comparator circuit includes a first comparator and a second comparator, wherein the pulse signal output by the pulse filtering circuit is input into the two comparators with opposite logic, and two non-overlapping pulse signals are generated at the output ends of the two comparators, and the output of the first comparator is used as the input of the CP end of the D flip-flop;

[0010] An inverter, used for processing the pulse signal output by the second comparator, and using the output of the inverter as the input of the RESET terminal of the D flip-flop;

[0011] D flip-flop, outputs a restoration signal or clears the output according to the input signal.

[0012] The present invention adds amplitude changes to further pull up the high pulse signal and pull down the low pulse signal to the ground, then filters out the common mode signal, and additionally adds a refresh pulse to help monitor the signal in real time, which greatly improves the anti-interference and reliability of signal transmission and effectively protects the power switching device. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a structural diagram of the gate magnetic isolation encoding and decoding circuit of the present invention;

[0014] Figure 2 It is the DRIVER circuit principle diagram of the present invention;

[0015] Figure 3 This is a schematic diagram of DRIVER working mode 1 of the present invention;

[0016] Figure 4 This is a schematic diagram of DRIVER working mode 2 of the present invention;

[0017] Figure 5 This is the DRIVER working timing diagram of the present invention;

[0018] Figure 6 It is the schematic diagram of the FLITER circuit of the present invention;

[0019] Figure 7 This is the simulation result of signal restoration completed by the digital isolator of the present invention. DETAILED DESCRIPTION

[0020] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0021] The present invention provides a magnetic isolation coding and decoding circuit, comprising a transmitting end circuit, an isolation transformer and a receiving end circuit, wherein the transmitting end circuit comprises a logic control circuit, an oscillator, a pulse generating circuit and a driving circuit, and the receiving end circuit comprises a pulse filtering circuit, a bandgap reference circuit, a comparator circuit, an inverter and a D flip-flop, wherein:

[0022] A logic control circuit, used for providing a clock signal and a switch signal for the driving circuit and an enable signal for the pulse generating circuit according to the oscillator and the input signal;

[0023] A pulse generating circuit, used for generating a pulse signal according to an enable signal provided by the logic control circuit, and inputting the generated pulse signal into the driving circuit;

[0024] A driving circuit, used for providing a driving signal to the isolation transformer;

[0025] The pulse filtering circuit is used to receive the high pulse signal and the low pulse signal coupled from the secondary coil of the isolation transformer, and modulate them into two high pulse signals and low pulse signals presented in negative pulses;

[0026] A bandgap reference circuit is used to provide a common-mode voltage for the secondary coil of the isolation transformer and a bias voltage for the pulse filtering circuit;

[0027] A comparator circuit includes a first comparator and a second comparator, wherein the pulse signal output by the pulse filtering circuit is input into the two comparators with opposite logic, and two non-overlapping pulse signals are generated at the output ends of the two comparators, and the output of the first comparator is used as the input of the CP end of the D flip-flop;

[0028] An inverter, used for processing the pulse signal output by the second comparator, and using the output of the inverter as the input of the RESET terminal of the D flip-flop;

[0029] D flip-flop, outputs a restoration signal or clears the output according to the input signal.

[0030] like Figure 1 In this embodiment, the following is provided: Figure 1 The illustrated embodiment shows a coding and decoding circuit based on magnetic isolation, which is used for SiCMOSFET isolation driver, and mainly includes a transmitting circuit, an isolation transformer (Isolation Transformer) and a receiving circuit. The transmitting circuit includes a logic control circuit (CONTROL LOGIC), an oscillator (OSC), a pulse generating circuit (PULSEGENERATOR), and a driving circuit (DRIVER); the receiving circuit includes a pulse filtering circuit (FILTER), a bandgap reference circuit (BG2), a comparator circuit, an inverter (INV) and a D flip-flop (DFF), and the comparator circuit includes a first comparator COMP1 and a second comparator COMP1; the isolation transformer includes two transformers, namely a first transformer Transfomer1 and a second transformer Transformer2.

[0031] This embodiment provides a specific implementation of a driving circuit. Figure 2The circuit includes a first transmission gate TG1, a second transmission gate TG2, a third transmission gate TG3, a fourth transmission gate TG4, a first P-type MOS transistor PM1, a second P-type MOS transistor PM2, a first N-type MOS transistor NM1, a second N-type MOS transistor NM2, a first triode Q1, and a second triode Q2, wherein:

[0032] The input of the first transmission gate TG1 is connected to the high pulse signal HPULSE output by the pulse generating circuit, the positive control terminal of the first transmission gate TG1 is connected to the second clock signal CLKN generated by the logic control circuit, the negative control terminal of the first transmission gate TG1 is connected to the first clock signal CLK generated by the logic control circuit, and the output of the first transmission gate TG1 is connected to the output terminal of the third transmission gate TG3, the drain of the first P-type MOS transistor PM1, the drain of the first N-type MOS transistor NM1 and the base of the first transistor Q1;

[0033] The input of the second transmission gate TG2 is connected to the high pulse signal HPULSE output by the pulse generating circuit, the positive control terminal of the second transmission gate TG2 is connected to the first clock signal CLK generated by the logic control circuit, the negative control terminal of the second transmission gate TG2 is connected to the second clock signal CLKN generated by the logic control circuit, and the output terminal of the second transmission gate TG2 is connected to the output terminal of the fourth transmission gate TG4, the drain of the second P-type MOS transistor PM2, the drain of the second N-type MOS transistor NM2, and the base of the second triode Q2;

[0034] The input of the third transmission gate TG3 is connected to the low pulse signal LPULSE output by the pulse generating circuit, the positive control terminal of the third transmission gate TG3 is connected to the first clock signal CLK generated by the logic control circuit, and the negative control terminal of the third transmission gate TG3 is connected to the second clock signal CLKN generated by the logic control circuit;

[0035] The input of the fourth transmission gate TG4 is connected to the low pulse signal LPULSE output by the pulse generating circuit, the positive control terminal of the fourth transmission gate TG4 is connected to the second clock signal CLKN generated by the logic control circuit, and the negative control terminal of the fourth transmission gate TG4 is connected to the first clock signal CLK generated by the logic control circuit;

[0036] The gate of the first P-type MOS transistor PM1 is connected to the first control signal A output by the logic control circuit, and the source is connected to the power supply terminal VCC and the collector of the first transistor Q1;

[0037] The gate of the second P-type MOS transistor PM2 is connected to the third control signal C output by the logic control circuit, and the source is connected to the power supply terminal VCC and the collector of the second transistor Q2;

[0038] The gate of the first N-type MOS transistor NM1 is connected to the second control signal B output by the logic control circuit, and the source is connected to the ground terminal GND;

[0039] The gate of the second N-type MOS transistor NM2 is connected to the fourth control signal D output by the logic control circuit, and the source is connected to the ground terminal GND;

[0040] The emitter of the first transistor Q1 is connected to the first primary input signal IFP of the isolation transformer; the emitter of the second transistor Q2 is connected to the second primary input signal IFM of the isolation transformer;

[0041] The first clock signal CLK and the second clock signal CLKN are two complementary clock signals, and the first control signal A, the second control signal B, the third control signal C, and the fourth control signal D are four signals used to control whether the gates of the first P-type MOS transistor, the first N-type MOS transistor, the second P-type MOS transistor, and the second N-type MOS transistor are turned on, respectively.

[0042] In this embodiment, the driving circuit has two working modes, and the working modes are controlled by the first clock signal CLK and the second clock signal CLKN. Figure 3 In this working mode, the first clock signal CLK and the second clock signal CLKN are used to control the first transmission gate and the fourth transmission gate to open and the second transmission gate and the third transmission gate to close. At this time:

[0043] like Figure 3 (a), when the transistor is in a charging state, that is, the first control signal A and the fourth control signal D are used to control the first P-type MOS transistor and the second N-type MOS transistor to be turned on, and the second control signal B and the third control signal C are used to control the second P-type MOS transistor and the first N-type MOS transistor to be turned off, at this time, the high pulse signal HPULSE generated by the pulse generating circuit flows into the first transistor Q1 through the first transmission gate TG1, and the first P-type MOS transistor PM1 assists in pulling up, so that the high pulse signal HPULSE path obtains a higher pulse amplitude, so the first transformer Transfomer1 self-inducts a high pulse level; the low pulse signal flows into the second transistor Q2 through the fourth transmission gate TG4, and the second N-type MOS transistor NM2 assists in pulling down, so that the low pulse signal path obtains a downward pulse, so the second transformer Transfome2 self-inducts a low pulse level;

[0044] like Figure 3(b) When the transistor is in the discharge state, that is, the first control signal A, the second control signal B, the third control signal C, and the fourth control signal D are used to control the first P-type MOS transistor, the second P-type MOS transistor, the first N-type MOS transistor, and the second N-type MOS transistor to be turned off, the base voltages of the first transistor and the second transistor follow the falling edges of the high and low pulses respectively, the current in the transformer gradually decreases, and a negative pulse is coupled out.

[0045] The second working mode of the driving circuit is as follows Figure 3 In this working mode, the first clock signal CLK and the second clock signal CLKN are used to control the second transmission gate and the third transmission gate to open and the first transmission gate and the fourth transmission gate to close. At this time:

[0046] like Figure 4 (a), when the transistor is in the charging state, that is, the second control signal B and the third control signal C are used to control the first N-type MOS transistor and the second P-type MOS transistor to be turned on respectively, and the first control signal A and the fourth control signal D are used to control the first P-type MOS transistor and the second N-type MOS to be turned off respectively, at this time, the high pulse signal HPULSE generated by the pulse generating circuit flows into the second transistor Q2 through the second transmission gate TG2, and the second P-type MOS transistor PM2 assists in pulling up, so that the high pulse signal HPULSE path obtains a higher pulse amplitude, so the second transformer Transfomer2 self-sensing a high pulse level. The low pulse signal flows into the first driving tube Q1 through the third transmission gate TG3, and the first N-type MOS tube NM1 assists in pulling down, so that the low pulse signal path obtains a downward pulse, so the first transformer Transfomer1 self-sensing a low pulse level;

[0047] like Figure 4 (b) When the transistor is in the discharge state, that is, the first control signal A, the second control signal B, the third control signal C, and the fourth control signal D are used to control the first P-type MOS transistor, the first N-type MOS transistor, the second P-type MOS transistor, and the second N-type MOS to be turned off respectively, the base voltages of the first transistor Q1 and the second transistor Q2 follow the falling edges of the high and low pulses respectively, the current in the transformer gradually decreases, and a negative pulse is coupled out.

[0048] like Figure 5, this embodiment provides the timing relationship of the first clock signal CLK, the second clock signal CLKN, the first control signal A, the second control signal B, the third control signal C, and the fourth control signal D of the driving circuit in two modes, wherein the first mode is when the first clock signal CLK is at a low level and the second clock signal CLKN is at a high level, and the second mode is when the first clock signal CLK is at a high level and the second clock signal CLKN is at a low level; when the first control terminal A outputs a low pulse signal, the first P-type MOS transistor is turned on, when the fourth control terminal outputs a high pulse signal, the second N-type MOS transistor is turned on, when the second control terminal B maintains a low level, the first N-type MOS transistor is turned off, and when the third control terminal C maintains a high level, the second P-type MOS transistor is turned off; similarly, when the first control terminal A maintains a high level, the first P-type MOS transistor is turned off, when the fourth control signal D maintains a low level, the second N-type MOS transistor is turned off, when the second control terminal B outputs a high pulse signal, the first N-type MOS transistor is turned on, and when the third control terminal C outputs a low pulse signal, the second P-type MOS transistor is turned on.

[0049] This embodiment also provides a specific implementation of a pulse filtering circuit, which includes a third N-type MOS transistor NM3, a fourth N-type MOS transistor NM4, a fifth N-type MOS transistor NM5, a sixth N-type MOS transistor NM6, a seventh N-type MOS transistor NM7, an eighth N-type MOS transistor NM8, a ninth N-type MOS transistor NM9, a tenth N-type MOS transistor NM10, an eleventh N-type MOS transistor NM11, a twelfth N-type MOS transistor NM12, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, and a sixth resistor R6, as shown in FIG. Figure 6 ,in:

[0050] The gate of the third N-type MOS transistor NM3, the bias voltage VO1 provided by the bandgap reference circuit, the gate of the fourth N-type MOS transistor NM4, the gate of the fifth N-type MOS transistor NM5, and the gate of the sixth N-type MOS transistor NM6 are connected together;

[0051] The drain of the third N-type MOS transistor, the power supply terminal VCC, the upper end of the first resistor R1, the upper end of the second resistor R2, and the drain of the sixth N-type MOS transistor NM6 are connected together;

[0052] The source of the third N-type MOS tube is connected to the upper end of the third resistor R3;

[0053] The drain of the fourth N-type MOS transistor NM4, the lower end of the first resistor R1, and the drain of the twelfth N-type MOS transistor NM12 are connected together and serve as the second pulse output terminal OUTM of the pulse filtering circuit, and the source of the fourth N-type MOS transistor NM4 is connected to the upper end of the fourth resistor R4;

[0054] The drain of the fifth N-type MOS transistor NM5, the lower end of the second resistor R2, and the drain of the eleventh N-type MOS transistor NM11 are connected together and serve as the first pulse output terminal OUTP of the pulse filtering circuit; the source of the fifth N-type MOS transistor NM5 is connected to the upper end of the fifth resistor R5;

[0055] The source of the sixth N-type MOS transistor NM6 is connected to the upper end of the sixth resistor R6;

[0056] The gate of the seventh N-type MOS transistor NM7 is connected to the drain, the lower end of the third resistor R3, the lower end of the fourth resistor R4, the drain of the tenth N-type MOS transistor NM10, and the first pulse input terminal INP of the receiving end of the isolation transformer are connected together; the source of the seventh N-type MOS transistor NM7, the drain and gate of the ninth N-type MOS transistor NM9, the gate of the tenth N-type MOS transistor NM10, and the gate of the eleventh N-type MOS transistor NM11 are connected together;

[0057] The gate and drain of the eighth N-type MOS transistor NM8, the lower end of the fifth resistor R5, the lower end of the sixth resistor R6, the drain of the thirteenth N-type MOS transistor NM13, and the second pulse input terminal INM of the receiving end of the isolation transformer are connected together;

[0058] The source of the eighth N-type MOS transistor NM8, the drain and gate of the fourteenth N-type MOS transistor NM14, the gate of the thirteenth N-type MOS transistor NM13, and the gate of the twelfth N-type MOS transistor NM12 are connected together;

[0059] The source of the ninth N-type MOS transistor NM9 , the source of the tenth N-type MOS transistor NM10 , the source of the eleventh N-type MOS transistor NM11 , the source of the twelfth N-type MOS transistor NM12 , the source of the thirteenth N-type MOS transistor NM13 , and the source of the fourteenth N-type MOS transistor NM14 are connected to the ground terminal GND.

[0060] Since the circuit has a symmetrical structure, this embodiment is described with reference to the left half of the circuit. The working principle of the circuit is as follows:

[0061] When a positive pulse appears at the first pulse input terminal INP of the receiving end of the isolation transformer, the signal is stepped down by the fifth N-type MOS tube MN5 and the seventh N-type MOS tube MN7 and then passes through the common source amplifier formed by the ninth N-type MOS tube MN9 to obtain an inverted output at the first pulse output terminal OUTP of the pulse filtering circuit. At this time, the first pulse output terminal OUTP is a negative pulse, and the higher the amplitude of the input positive pulse, the smaller the minimum value of the obtained negative pulse output. A small negative pulse will appear immediately after the positive pulse of the first pulse input terminal INP of the receiving end of the isolation transformer. At this time, the first N-type MOS tube MN1 and the second N-type MOS tube MN2 are used as current sources to provide current flowing out of the first pulse input terminal INP. The negative pulse should generate a positive pulse signal after passing through the ninth N-type MOS tube MN9. However, since the first pulse output terminal OUTP is biased at a level close to the power supply voltage, there is no voltage margin to generate the positive pulse, so the negative pulse can be filtered out. Therefore, when a high pulse is input to the first pulse input terminal INP, a negative pulse with a large swing is generated at the first pulse output terminal OUTP. Similarly, a low pulse is input to the second pulse output terminal OUTM of the pulse filtering circuit, and a negative pulse with a small swing is obtained at the second pulse output terminal OUTM.

[0062] After describing the driving circuit and the pulse filtering circuit of the present invention respectively, this embodiment further describes the working principle of a magnetic isolation encoding and decoding circuit of the present invention, including:

[0063] In the transmitting end circuit, the input data signal IN and the refresh clock signal REFCLK generated by the oscillator are input to the logic control circuit together, and are modulated into two signals after being processed by the logic control circuit. One is the data clock signal and the control signal input to the driving circuit, including the first clock signal CLK and the second clock signal CLKN and the first control signal A, the second control signal B, the third control signal C, and the fourth control signal D. The other is the enable signal of the pulse generating circuit input to the pulse generating circuit, including the first enable signal EN, the second enable signal ENP0, the third enable signal ENP1, and the fourth enable signal ENN1; the pulse generating circuit is divided into two channels. Under the action of the control signal, at the rising edge, the falling edge of the data signal and the rising edge of the refresh clock signal, the pulse generating circuit is respectively Generate a high pulse signal HPULSE and a low pulse signal LPULSE, the driving circuit receives the control signal from the logic control circuit and the high and low pulse signals generated by the pulse generating circuit; when the rising edge of the data signal arrives, the first transistor Q1 is driven by a high pulse to transmit the set signal to the primary coil, and the second transistor Q2 is driven by a low pulse at this time; when the falling edge of the data signal arrives, the second transistor Q2 is driven by a high pulse to transmit the reset signal to the primary coil, and the first transistor Q1 is driven by a low pulse at this time; when the rising edge of the clock signal arrives, if the data signal is high, a high pulse is generated on the path for transmitting the set signal, and if the data signal is low, a high pulse is generated on the path for transmitting the reset signal, so that the recognition of the data signal can be refreshed in real time to ensure the accuracy of signal transmission;

[0064] In the receiving end circuit, the bandgap reference circuit provides a common mode voltage VO1 to the secondary coil and a bias voltage VO0 to the pulse filtering circuit; the pulse filtering circuit receives the first pulse input terminal INP and the second pulse input terminal INM coupled from the secondary coil, modulates them into two first pulse output terminals OUTP and second pulse output terminals OUTM presented with negative pulses, and inputs the two signals into the first comparator COMP1 and the second comparator COMP2 respectively with opposite logic, generates two non-overlapping first pulse signals Z and second pulse signals ZN at the output terminals of the first comparator COMP1 and the second comparator COMP2, connects the output terminal of the first comparator COMP1 to the CP terminal of the D flip-flop, and connects the output terminal of the second comparator COMP2 to the RESET terminal of the D flip-flop after inversion, that is, when the first comparator COMP1 has a pulse, the D flip-flop follows the high voltage of the output VCC until the RESET terminal receives the inverted pulse signal of the second comparator COMP2, and then clears the output, and finally obtains the restored data signal at the output terminal OUT of a magnetic isolation encoding and decoding circuit, and the whole process ends.

[0065] like Figure 7This embodiment provides a schematic diagram of the simulation results of the entire process. The input signal IN is modulated into two high and low pulse signals IFM and INP by the transmitting circuit. After being isolated by the isolation transformer, it is demodulated into the set signal Z and reset signal ZN for controlling the D flip-flop in the receiving circuit, and finally the restored signal OUT is obtained, which meets the design expectations.

[0066] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A magnetic isolation encoding and decoding circuit, characterized in that: It includes a transmitting circuit, an isolation transformer and a receiving circuit. The transmitting circuit includes a logic control circuit, an oscillator, a pulse generating circuit, and a driving circuit. The receiving circuit includes a pulse filtering circuit, a bandgap reference circuit, a comparator circuit, an inverter and a D flip-flop, wherein: A logic control circuit, used for providing a clock signal and a switch signal for the driving circuit and an enable signal for the pulse generating circuit according to the oscillator and the input signal; A pulse generating circuit, used for generating a pulse signal according to an enable signal provided by the logic control circuit, and inputting the generated pulse signal into the driving circuit; A driving circuit, used for providing a driving signal to the isolation transformer; The pulse filtering circuit is used to receive the high pulse signal and the low pulse signal coupled from the secondary coil of the isolation transformer, and modulate them into two high pulse signals and low pulse signals presented in negative pulses; A bandgap reference circuit is used to provide a common-mode voltage for the secondary coil of the isolation transformer and a bias voltage for the pulse filtering circuit; A comparator circuit includes a first comparator and a second comparator, wherein the pulse signal output by the pulse filtering circuit is input into the two comparators with opposite logic, and two non-overlapping pulse signals are generated at the output ends of the two comparators, and the output of the first comparator is used as the input of the CP end of the D flip-flop; An inverter, used for processing the pulse signal output by the second comparator, and using the output of the inverter as the input of the RESET terminal of the D flip-flop; D flip-flop, outputs a restoration signal or clears the output according to the input signal.

2. A magnetic isolation encoding and decoding circuit according to claim 1, characterized in that: The driving circuit includes a first transmission gate, a second transmission gate, a third transmission gate, a fourth transmission gate, a first P-type MOS transistor, a second P-type MOS transistor, a first N-type MOS transistor, a second N-type MOS transistor, a first triode, and a second triode, wherein: The high pulse signal HPULSE generated by the pulse generating circuit is used as the input signal of the first transmission gate and the second transmission gate, and the low pulse signal LPULSE generated by the pulse generating circuit is used as the input signal of the third transmission gate and the fourth transmission gate; The first clock signal CLK generated by the logic control circuit is input as the positive control terminal of the second transmission gate and the third transmission gate, and the negative control terminal of the first transmission gate and the fourth transmission gate; A second clock signal CLKN generated by the logic control circuit and complementary to the first pulse signal CLK is input as the positive control terminal of the first transmission gate and the fourth transmission gate, and the negative control terminal of the second transmission gate and the third transmission gate; The logic control circuit generates four switch signals, which are respectively used to control the conduction of the gates of the first P-type MOS transistor, the second P-type MOS transistor, the first N-type MOS transistor, and the second N-type MOS transistor; The source of the first P-type MOS transistor is connected to the power supply terminal and the collector of the first transistor, the drain of the first P-type MOS transistor is connected to the output terminal of the first transmission gate, the output terminal of the second transmission gate, the drain of the first N-type MOS transistor, and the base of the first transistor, and the emitter of the first transistor serves as the first primary input signal IFP of the isolation transformer; The source of the second P-type MOS transistor is connected to the power supply terminal and the collector of the second triode, the drain of the second P-type MOS transistor is connected to the output terminal of the third transmission, the output terminal of the fourth transmission gate, the drain of the second N-type MOS transistor, and the base of the second triode, and the emitter of the second triode serves as the second primary input signal IFM of the isolation transformer; Sources of the first N-type MOS transistor and the second N-type MOS transistor are grounded respectively.

3. A magnetic isolation encoding and decoding circuit according to claim 2, characterized in that: When the first transmission gate and the fourth transmission gate are turned on and the second transmission gate and the third transmission gate are turned off, the driving circuit is in the first working mode. At this time: When the first P-type MOS tube and the second N-type MOS tube are turned on, the second P-type MOS tube and the first N-type MOS tube are turned off, the first triode and the second triode are in a charging state, the coil of the isolation transformer connected to the first triode self-inducts a high pulse level, and the coil connected to the second triode self-inducts a low pulse level; When the gates of the first P-type MOS tube, the second P-type MOS tube, the first N-type MOS tube, and the second N-type MOS tube are all closed, the first triode and the second triode are in a discharge state, the current of the isolation transformer gradually decreases, and a negative pulse is coupled out.

4. A magnetic isolation encoding and decoding circuit according to claim 2, characterized in that: When the second transmission gate and the third transmission gate are turned on and the first transmission gate and the fourth transmission gate are turned off, the driving circuit is in the second working mode. At this time: When the first N-type MOS tube and the second P-type MOS tube are turned on, and the second N-type MOS tube and the first P-type MOS tube are turned off, the first triode and the second triode are in a charging state, and the coil of the isolation transformer connected to the first triode self-inducts a low pulse level, and the coil connected to the second triode self-inducts a high pulse level; When the gates of the first P-type MOS tube, the second P-type MOS tube, the first N-type MOS tube and the second N-type MOS tube are all cut off, the first triode and the second triode are in a discharge state, the current of the isolation transformer gradually decreases, and a negative pulse is coupled out.

5. The magnetic isolation encoding and decoding circuit according to claim 1, characterized in that: The pulse filtering circuit includes a third N-type MOS transistor, a fourth N-type MOS transistor, a fifth N-type MOS transistor, a sixth N-type MOS transistor, a seventh N-type MOS transistor, an eighth N-type MOS transistor, a ninth N-type MOS transistor, a tenth N-type MOS transistor, an eleventh N-type MOS transistor, a twelfth N-type MOS transistor, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, and a sixth resistor, wherein: The gates of the third to sixth N-type MOS transistors are connected to a bias voltage provided by a bandgap reference circuit; The drain of the third N-type MOS tube is connected to one end of the first resistor, one end of the second and third groups, and the drain of the sixth N-type MOS tube; the source of the third N-type MOS tube is connected to one end of the third resistor; the source of the sixth N-type MOS tube is connected to one end of the sixth resistor; The drain of the fourth N-type MOS transistor is connected to the other end of the first resistor and the drain of the twelfth N-type MOS transistor, and serves as the second pulse output terminal OUTM of the pulse filtering circuit; the source of the fourth N-type MOS transistor is connected to one end of the fourth resistor; The drain of the fifth N-type MOS transistor is connected to the other end of the second resistor and the drain of the eleventh N-type MOS transistor, and serves as the first pulse output terminal OUTP of the pulse filtering circuit; the source of the fifth N-type MOS transistor is connected to one end of the fifth resistor; The drain and gate of the seventh N-type MOS tube, the other end of the third resistor, the other end of the fourth resistor, and the drain of the tenth N-type MOS tube are connected to the first pulse input terminal INP of the receiving end of the isolation transformer; the source of the seventh N-type MOS tube is connected to the drain and gate of the ninth N-type MOS tube, the gate of the tenth N-type MOS tube, and the gate of the eleventh N-type MOS tube; The drain and gate of the eighth N-type MOS transistor, the other end of the fifth resistor, the other end of the sixth resistor, and the drain of the thirteenth N-type MOS transistor are connected to the second pulse input terminal INM of the receiving end of the isolation transformer; the source of the eighth N-type MOS transistor is connected to the drain and gate of the fourteenth N-type MOS transistor, the gate of the thirteenth N-type MOS transistor, and the gate of the twelfth N-type MOS transistor; The sources of the ninth to fourteenth MOS tubes are grounded.

6. A magnetic isolation encoding and decoding circuit according to claim 5, characterized in that: When the first pulse input terminal INP of the receiving end of the isolation transformer is a high pulse, the first pulse output terminal OUTP of the pulse filtering circuit generates a negative pulse with a large swing; when the second pulse input terminal INM of the receiving end of the isolation transformer is a low pulse, the second pulse output terminal OUTM of the pulse filtering circuit generates a negative pulse with a small swing.

7. The magnetic isolation encoding and decoding circuit according to claim 1, characterized in that: The high pulse output terminal generated by the pulse filtering circuit serves as the positive input terminal of the first comparator and the negative input terminal of the second comparator, and the low pulse output terminal generated by the pulse filtering circuit serves as the negative input terminal of the first comparator and the positive input terminal of the second comparator.

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