PSI5 Interface Circuit Current Threshold Control Method, Device, Equipment and Storage Medium

Abstract

The present application discloses a method, device, equipment and storage medium for controlling the current threshold of a PSI5 interface circuit, which relates to the field of sensing detection. Gradient current thresholds are set for N current comparators. Each current comparator generates a Manchester signal based on the sampled current value and the corresponding current threshold, and records the corresponding decoding success rate through a register group. After power-on, the target current comparator is determined based on the decoding success rates recorded by the N current comparators; the target current comparator and the current threshold are obtained to output a Manchester encoding signal and calculate the duty cycle; the current threshold of the target current comparator is updated gradientually according to the duty cycle, and the decoding success rates of the N channels are updated. This solution does not directly continuously monitor the Manchester encoding signal, but sets different current thresholds gradientually. First, the current comparators are screened by the decoding success rate, and then the duty cycle is adjusted, which can optimize the chip computing resources to the greatest extent and improve the encoding and decoding accuracy.

Description

Technical Field

[0001] This application relates to the field of sensing detection, and particularly to a method, device, equipment and storage medium for controlling the current threshold of a PSI5 interface circuit. Background Art

[0002] In the automotive industry, the Peripheral Sensor Interface (PSI5) is the most common automotive sensor interface. PSI5 is an open standard and is widely used in airbag systems. Its sensor data is transmitted at a preset baud rate through Manchester code. Manchester coding, also known as split-phase code, synchronous code, and phase coding, is a coding method that uses level transitions to represent 1 or 0.

[0003] In a sensor detection circuit, when an ECU chip collects sensor data encoded in Manchester code, it will inevitably be affected by various external interferences, thus affecting the level signal judgment of the current comparator. In traditional solutions, the ECU chip will inversely control the output to adjust the current threshold of the current comparator to identify the Manchester signal and determine the sensor data content. Specifically, refer to Figure 1 the circuit structure shown. In this solution, the current comparator U2 mainly performs periodic adjustment, focusing on the active adjustment of abnormal conditions of the PSI5 sensor, and the real-time performance and adjustment accuracy are average. In addition, this adjustment mechanism mainly infers and adjusts the current based on the duty cycle, and needs to calculate and analyze the duty cycle in real time, which requires more ECU chip resources. Summary of the Invention

[0004] This application provides a method, device, equipment and storage medium for controlling the current threshold of a PSI5 interface circuit, which improves the decoding accuracy of the Manchester code transmitted by the PSI5 interface and optimizes chip resources.

[0005] On the one hand, this application provides a method for controlling the current threshold of a PSI5 interface circuit. The method is used for a PSI5 interface circuit including N current comparators, and the method includes:

[0006] Set gradient-changing current thresholds for the N current comparators. During operation, each current comparator generates a Manchester signal based on the sampled current value and the corresponding current threshold, and records the corresponding decoding success rate through a register group;

[0007] In the first detection period after power-on, determine the target current comparator based on the decoding success rates recorded by the N current comparators;

[0008] In the second detection period, obtain the Manchester-encoded signal and calculate the duty cycle of the target current comparator and the corresponding current threshold; update the current threshold of the target current comparator according to the duty cycle gradient, and update the decoding success rate recorded by the N-channel current comparators.

[0009] After the second detection period, obtain in real time the decoding success rate recorded by the N-channel current comparators and re-determine the target current comparator, and perform the steps of calculating the duty cycle and updating the current threshold on the target current comparator.

[0010] Specifically, each channel of current comparator is respectively provided with a register group, including a first register and a second register; the first register stores the number of decoding successes, and the second register stores the decoding success rate.

[0011] During the working stage, obtain in real time the decoding results of each channel of current comparator, and record and update the sum of the number of decoding successes in the first register and the decoding success rate data in the second register.

[0012] Specifically, in the first detection period after power-on, determining the target current comparator based on the decoding success rate recorded by the N-channel current comparators includes:

[0013] After the system is powered on, control the N-channel current comparators to generate Manchester signals according to the initial current thresholds set by the gradient. After reaching the target set data frame length, determine the channel with the highest decoding success rate as the target current comparator.

[0014] After the second detection period, obtain in real time the number of decoding successes and the decoding success rate of the N-channel current comparators, continuously update and determine the channel with the highest decoding success rate as the target current comparator, and calculate the duty cycle of the target comparator and update the current threshold by gradient; the gradient update value is determined based on the length of the second detection period.

[0015] Specifically, the decoding results recorded by the N-channel current comparators are determined according to the chip's verification mechanism. When the number of channels with successful decoding is 0, report the decoding error in this round and update the decoding success rate.

[0016] When the number of channels with successful decoding is not 0 and the results are consistent, report the correct result and update the number of decoding successes and the decoding success rate.

[0017] When the number of channels with successful decoding is not 0 and the results are inconsistent, report errors for all and update the decoding success rate.

[0018] Specifically, after obtaining the Manchester signal, monitor the edge signal of the Manchester signal, and start clock counting when the initial edge signal is detected.

[0019] When the timing does not reach the clock threshold specified by the filtering parameter, monitor whether there is an edge signal opposite to the initial edge signal;

[0020] When an edge signal opposite to the initial edge signal is detected within the clock counting period, decrease the clock count value by the step value and continue to detect the edge signal; when an edge signal the same as the initial edge signal is detected within the clock counting period, increment the clock count value by one;

[0021] When the timing reaches the clock threshold specified by the filtering parameter and no edge signal opposite to the initial edge signal is detected within all clock counting periods, use the level value after the initial edge signal as the output level value.

[0022] Specifically, in the first detection period, 1024 frames of Manchester data are received, the decoding success rate of the N-channel register group is updated according to the decoding results of the 1024 frames, and the target current comparator is determined based on the channel with the highest decoding success rate;

[0023] In the second detection period, 250 frames of Manchester data are received, and the decoding success rate of the N-channel register group is continuously updated according to the decoding results of the 250 frames; the duty cycle of the target current comparator is calculated in each data period, and the current threshold is updated according to the difference gradient from the target duty cycle.

[0024] Specifically, after the second detection period, when the decoding success rates of at least two current comparators are the same, select the channel with the smallest difference between the current current threshold and the corresponding initial threshold current to determine the target current comparator.

[0025] On the other hand, the present application provides a current threshold control device for a PSI5 interface circuit. The device is used for a PSI5 interface circuit including N current comparators, and the device includes:

[0026] A setting module for setting gradient-changing current thresholds for the N current comparators. During operation, each current comparator generates a Manchester signal based on the sampled current value and the corresponding current threshold, and records the corresponding decoding success rate through a register group;

[0027] A determination module for determining the target current comparator based on the decoding success rates recorded by the N current comparators in the first detection period when power is on;

[0028] A first update module for, in the second detection period, obtaining the Manchester encoding signal and calculating the duty cycle value output by the target current comparator and the corresponding current threshold; updating the current threshold of the target current comparator according to the duty cycle value gradient, and updating the decoding success rate recorded by the N current comparators;

[0029] A second update module, configured to, after a second detection period, obtain in real time the decoding success rate recorded by N current comparators and re-determine a target current comparator, and perform steps of calculating a duty cycle and updating a current threshold on the target current comparator.

[0030] In another aspect, the present application provides a computer device, which includes a processor and a memory. At least one instruction, at least one program, a code set or an instruction set is stored in the memory, and the at least one instruction, the at least one program, the code set or the instruction set is loaded and executed by the processor to implement the PSI5 interface circuit current threshold control method described in any of the above aspects.

[0031] In another aspect, the present application provides a computer-readable storage medium, in which at least one instruction, at least one program, a code set or an instruction set is stored, and the at least one instruction, the at least one program, the code set or the instruction set is loaded and executed by a processor to implement the PSI5 interface circuit current threshold control method described in any of the above aspects.

[0032] The beneficial effects brought by the technical solutions provided in the embodiments of the present application at least include: Instead of directly and continuously monitoring the Manchester encoding signal, different current thresholds are set in gradients. First, the current comparator with the highest decoding effect is screened by the decoding success rate, and then the duty cycle difference is analyzed to adjust the current threshold. In the subsequent adjustment process, the decoding success rate is always used as the first reference dimension for preliminary screening, and then the duty cycle is used for secondary adjustment. This adjustment mechanism can optimize the CPU computing resources to the greatest extent, and the entire process can ensure that data is output with the highest decoding success rate. Compared with the traditional single-channel threshold adjustment method, the best-decoding channel is always output. Compared with the negative feedback adjustment, the output method based on the decoding success rate has no delay in adjustment actions, and the adjustment process is faster and smoother. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 is a circuit diagram of a simplified vehicle PSI5 sensing detection system circuit;

[0034] Figure 2 is a schematic diagram of Manchester data encoding;

[0035] Figure 3 is a schematic diagram of data input of a simplified five-channel current comparator;

[0036] Figure 4 is a flowchart of the PSI5 interface circuit current threshold control method provided by the embodiment of the present application;

[0037] Figure 5 is a schematic diagram of a Manchester encoding signal output under different current thresholds applied to a current signal;

[0038] Figure 6 is the flowchart of the filtering algorithm for Manchester-encoded signals;

[0039] Figure 7 is the noise filtering comparison graph generated after the low level jumps to the high level;

[0040] Figure 8 is the structural block diagram of the PSI5 interface circuit current threshold control device provided by the embodiment of the present application. Detailed implementation manners

[0041] To make the objectives, technical solutions, and advantages of the present application clearer, the following will further describe the embodiments of the present application in detail with reference to the accompanying drawings.

[0042] As used herein, "a plurality of" means two or more. "And / or" describes the association relationship of associated objects and indicates that three relationships may exist. For example, A and / or B may represent: A exists alone, A and B exist simultaneously, and B exists alone. The character " / " generally represents an "or" relationship between the associated objects before and after.

[0043] Manchester encoding (Manchester), also known as split-phase code, synchronous code, and phase encoding, is a coding method that uses level transitions to represent 1 or 0. Its change rule is very simple, that is, each code element is represented by two level signals with different phases, which is a square wave of one period, but the phases of the 0 code and the 1 code are exactly opposite. It is stipulated that one bit of the low level to high level transition is used as Bit 0, and one bit of the high level to low level transition is used as Bit 1.

[0044] In this solution, it is an algorithm improvement for the vehicle PSI5 sensing detection system circuit, and the vehicle PSI5 sensing detection system circuit can be simplified to Figure 1 the content (which can be other forms of circuit structures). Overall, several sensor devices sensor are mounted on the PSI5 bus. The data of these sensor devices are sent to the current comparator U2 for comparison through a sampling circuit (R5 sampling resistor) and an amplification circuit (operational amplifier U1), etc., and the sampled current I1 is sent into the current comparator U2 for comparison, and Manchester data is generated and sent into the ECU chip for detection. The reference current I among them is the amplified current and is used to determine the amplification coefficient; the current threshold I2 is output from the ECU in the reverse direction to the current comparator, and the Manchester data is exactly generated based on the magnitude relationship between the current threshold I2 and the sampled current I1. See Figure 2 the Manchester data encoding schematic diagram shown. When the sampling signal (the current input to U2) is less than the current threshold, the low level signal is output by U2, and vice versa, the high level signal is output.

[0045] To solve the problems of current threshold adjustment accuracy and ECU resource occupation mentioned in the background art, this application selects to set a current comparator U2 with different current comparison thresholds and corresponding filtering and decoding parts. The current thresholds of each path of current comparators are adaptively adjusted according to the actual situation, and the most suitable path is selected through an algorithm and output as the final target input. Figure 3 It is a schematic diagram of the simplified five-way current comparator data input. The amplifier circuit U1 is multiplexed into the five-way current comparator circuit, and the Manchester data output by it is sent to the ECU chip. The ECU chip performs feedback adjustment on the corresponding current thresholds of the five paths through an internal algorithm.

[0046] Figure 4 It is a flowchart of the current threshold control method for the PSI5 interface circuit provided by the embodiment of this application, including the following steps:

[0047] S1. Set current thresholds with gradient changes for N paths of current comparators. When working, each path of current comparator generates a Manchester signal based on the sampled current value and the corresponding current threshold, and records the corresponding decoding success rate through a register bank;

[0048] In the initial stage of circuit setting, the current thresholds of N paths of current comparators are default set according to gradient changes, that is, there is a certain interval between the current thresholds of the five comparators. For example, the current threshold of the P3 path (the middle path) is set to Ibase, the P2 and P4 paths are set to Ibase ± 5%, and the P1 and P5 paths are set to Ibase ± 10%. Such current thresholds are set in the form of a proportional function, which can cover the conventional current adjustment range.

[0049] Figure 5 It is a schematic diagram of the Manchester encoding signal output under different current thresholds applied to the current signal. In this embodiment, a five-way current comparator is taken as an example. After setting different values of current thresholds in the positive period of the sine wave, the obtained Manchester encoding signals are also different. Especially between the Manchester encoding of the first path and the fifth path, the length and time ratio of the valid data are extremely different, which is also the key to the signal encoding and decoding accuracy.

[0050] The decoding success rate is generated after the chip internally receives the Manchester data and decodes it. This stage mainly relies on a series of verification mechanisms specified in the PSI5 protocol such as CRC verification, and this application will not introduce it too much. The decoding success rate determined after decoding is stored in the register bank, and this register bank can be the internal register bank of the ECU or set separately externally, mainly to record the decoding success rate of N paths of current comparators. As Figure 3 In the figure, five groups of register banks are set to record the decoding success rates of the five groups of current comparators generating Manchester data respectively.

[0051] S2. In the first detection period after power-on, determine the target current comparator based on the decoding success rates recorded by N current comparators;

[0052] During the power-on stage, the system will reset values such as the current thresholds and decoding success rates of the N current comparators. In the first detection period after power-on, the ECU will continuously record and update the decoding success rates of each other according to the Manchester data output by each channel. After continuously recording the duration of the first detection period, one path will be selected from the decoding success rates corresponding to the N current comparators as the target current comparator for subsequent key adjustment targets.

[0053] In this embodiment, the higher the decoding success rate, the more reasonable the setting of the current threshold. Therefore, select the current comparator with the highest decoding success rate as the target current comparator, and further execute the content of S3.

[0054] S3. In the second detection period, obtain the Manchester encoding signal output by the target current comparator and the corresponding current threshold, and calculate the duty cycle; update the current threshold of the target current comparator according to the duty cycle gradient, and update the decoding success rates recorded by the N current comparators;

[0055] After entering the second detection period, the system mainly makes individual fine-tuning of the target current comparator determined in step S2, and no operation is performed on the other N-1 current comparators, but the decoding success rates of the N current comparators are still recorded and updated in real time.

[0056] For the fine-tuning process of the selected target current comparator, this stage uses duty cycle adjustment for operation. As Figure 5 shown in the Manchester encoding signal, within a complete signal period (composed of a high-level signal duration t1 and a low-level signal duration t1), the ratio of the high-level signal duration to the low-level signal duration is the duty cycle. The system usually sets an ideal duty cycle according to the actual situation (for example, this application takes 50% as an example), because when the duty cycle is too large or too small, it will affect the encoding and decoding operation of the system. In this embodiment, in the second detection period, the current comparison threshold with the highest decoding success rate is further adjusted, that is, the square wave duty cycle is further adjusted towards 50%. The principle is: if the duty cycle obtained by the duty cycle calculation logic is greater than 50%, increase the current comparator threshold; if the duty cycle obtained by the duty cycle calculation logic is less than 50%, decrease the current comparator threshold; if the duty cycle is 50%, do not increase or decrease. For example Figure 5 in the 5th path in , the duty cycle of t1 / (t1 + t2) is the closest to 50%, and the target current comparator is selected for this path.

[0057] The significant difference between this application and the traditional solution is that although both directly detect the duty cycle value of the Manchester-encoded signal to inversely adjust the current threshold, the traditional solution performs continuous monitoring and only inversely adjusts based on the negative feedback mechanism when the duty cycle deviates from the target range. This solution requires more ECU resources to continuously monitor the level signal and calculate the duty cycle, and the negative feedback trigger adjustment mechanism has a certain time delay. In contrast, in this embodiment, the level signal value is not continuously monitored. Instead, the target current comparator with the highest decoding success rate is first selected, which is equivalent to preliminarily screening a target comparator that is closest to the target duty cycle. Then, the target current comparator is finely adjusted. Since the data in the first detection period during the system power-on process is usually system test data, it does not affect the actual sensor data reception and judgment, and the entire adjustment cycle is shorter and the adjustment process is smoother. The fine adjustment process can last for one or more complete signal cycles, specifically determined according to the duty cycle difference.

[0058] In the above steps, since there is no need to call additional ECU resources to monitor the level signal and calculate the duty cycle during the first detection period, but directly determine the decoding situation based on the backend decoding verification, and use the decoding success rate to replace the level signal monitoring and duty cycle calculation, thereby saving the computing resources of the ECU.

[0059] It should be noted that the target current comparator determined in step S2 is only temporary. Because circuit and noise fluctuations, or sensor disconnection anomalies, etc. will all affect the amplitude of the sampling signal, there may also be large signal fluctuations at this stage. Although this step monitors and finely adjusts the duty cycle, it only monitors during the fine adjustment stage and does not require continuous monitoring because the fine adjustment process and the process register group after the fine adjustment are always recording the decoding success rate. As mentioned above, the decoding success rate is a direct indicator of system stability and is positively correlated with the duty cycle difference. And the decoding situation can be directly obtained without level signal monitoring and calculation, which is the key to saving ECU resources in this application.

[0060] S4. After the second detection period, obtain in real time the decoding success rates recorded by the N current comparators and re-determine the target current comparator, and perform the steps of calculating the duty cycle and updating the current threshold for the target current comparator.

[0061] This step is a loop operation of the judgment mechanism in S2, that is, the target current comparator is not fixed. Although the duty cycle is calculated and finely adjusted for a temporarily selected current comparator in step S3, after the detection period, if the subsequent decoding success rate changes due to system or line fluctuations, the target current comparator will be re-selected.

[0062] For example, within the first detection cycle after the system is powered on, it is determined through cumulative calculation that the Manchester-encoded signal output by the 4th current comparator has the highest decoding success rate (98%) after subsequent decoding verification. This current comparator is designated as the target current comparator. During the second detection cycle, the level signal of the 4th current comparator is briefly detected and the duty cycle is calculated. After determining the duty cycle threshold, fine-tuning is performed. The fine-tuning process uses the Manchester data output by this path as the sensor data collected for vehicle analysis. Although the sensor data of other paths is not analyzed, the decoding success power of all Manchester-encoded signals is still updated.

[0063] After the second detection cycle, assuming that system fluctuations and error accumulation cause the decoding success rate of the 2nd path to exceed that of the 4th path (the decoding success rate of the 4th path may also fluctuate and decrease), the 2nd current comparator is determined as the target current comparator. In subsequent steps, the level signal and threshold fine-tuning of this path are detected.

[0064] Generally speaking, this solution does not directly and continuously monitor the Manchester-encoded signal. Instead, different current thresholds are set in gradients. First, the current comparator with the highest decoding effect is screened based on the decoding success rate, and then the duty cycle difference is analyzed to adjust the current threshold. In the subsequent adjustment process, the decoding success rate is always used as the first reference dimension for preliminary screening, and then secondary adjustment is performed based on the duty cycle. This adjustment mechanism can optimize the CPU computing resources to the greatest extent, and ensure that data is output with the maximum decoding success rate throughout the process. Compared with the traditional single-path threshold adjustment method, the path with the best decoding ability is always output. Compared with negative feedback adjustment, the method based on the decoding success rate output has no time delay in the adjustment action, and the adjustment process is more rapid and gentle.

[0065] In some embodiments, the ECU chip can set a register group for each current comparator, including a first register and a second register. The first register is used to store the number of decoding successes, and the second register stores the decoding success rate (the ratio of the number of decoding successes to the total number of decodings). Throughout the subsequent working stage, the ECU will obtain the decoding results of each current comparator in real time, record and update the sum of the number of decoding successes in the first register and the decoding success rate data in the second register. The total number of decodings (i.e., the received Manchester data frames) can be stored additionally through a register or the ECU chip.

[0066] Regarding the process of determining the target current comparator, it can be specifically summarized as follows:

[0067] 1. After the system is powered on, control the N current comparators to generate Manchester signals according to the initially set current thresholds in gradients. After reaching the target set data frame length, determine the path with the highest decoding success rate as the target current comparator;

[0068] The first detection cycle process can set a time. For example, in this application, the time for receiving 1024 frames of Manchester data is used as the standard. After obtaining the decoding result of the 1024th frame, the decoding success rate of the N-channel register group is updated, and the path with the highest decoding success rate is determined as the target current comparator.

[0069] The decoding results recorded by the N-channel current comparators are determined according to the chip's verification mechanism.

[0070] 1) If the number of successfully decoded paths = 0, report the decoding error for this round and update the decoding success rate of each path.

[0071] 2) If the number of successfully decoded paths = 1, report the correct result of this path and update the number of successful decoding times of this path and the decoding success rate of each path.

[0072] 3) If the number of successfully decoded paths > 1 and the results are consistent, report the correct result and update the number of successful decoding times and the decoding success rate of each path.

[0073] 4) If the number of successfully decoded paths > 1 and the results are inconsistent, report errors for all and update the decoding success rate of each path. (In this case, at least one of the results is incorrect. To ensure accuracy, errors are reported for all.)

[0074] 2. After the second detection cycle, the number of successful decoding times and the decoding success rate of the N-channel current comparators are obtained in real time. The path with the highest decoding success rate is continuously updated and determined as the target current comparator, and the duty cycle of the target comparator is calculated and the current threshold is updated by gradient.

[0075] The second detection cycle of this application is based on 250 frames of Manchester data. Within these 250 frames, the decoding success rate of the N-channel register group is continuously updated and the threshold is finely adjusted. During fine adjustment, the duty cycle of the target current comparator is calculated within each complete data cycle, and the current threshold is updated by gradient according to the difference from the target duty cycle.

[0076] Considering some special cases, during the second detection cycle process and later, when the decoding success rates of at least two current comparators are the same, the path with the smallest difference between the current threshold and the corresponding initial threshold current can be selected to determine the target current comparator, that is, the path closest to Ibase is selected. This is also for the convenience of subsequent circuit fine adjustment. The closer the current value is to Ibase, the larger its free adjustment range at both ends and the stronger its anti-fluctuation ability.

[0077] To achieve precise control, the present application provides an adjustment mechanism that combines fast adjustment and slow adjustment. The fast adjustment mechanism is only enabled when the device is powered on. In this example, the fast adjustment period is set to 250 frames of data. That is, when powered on, the PSI5 host sends 1024 + 250 frames of data. The first 1024 frames of data are used to obtain the current comparator threshold with the highest decoding success rate, and the latter 250 frames of data are used for fast adjustment. For example, in this example, the adjustment step size is set to 0.02% each time, that is, the target comparator adjusts 0.02% of Ibase at a time. In the formal adjustment stage after the second cycle, because sensor data needs to be transmitted and a group with the highest decoding success rate has been preliminarily screened, a slow adjustment mechanism is adopted until the device is powered off. The slow adjustment step size is set to 0.001% of Ibase each time. It should be noted that the slow adjustment and fast adjustment always act on the current comparison threshold with the highest decoding success rate and will not adjust the current thresholds of other channels. Moreover, the adjusted current threshold will not change when reselecting other comparators subsequently because it may be selected again later, making current adjustment more convenient. It will only return to the initial current threshold after a power-off restart.

[0078] In this solution, it is also necessary to consider the influence of noise interference on encoding and decoding, especially that high-frequency noise fluctuations near will affect encoding, decoding, and duty cycle calculation. Therefore, the present application provides a more precise noise filtering solution. The specific discrimination and filtering process is shown in Figure 6 as follows:

[0079] S1. After obtaining the Manchester signal, monitor the edge signal of the Manchester signal. When the initial edge signal is detected, start clock counting;

[0080] It should be noted that Figure 6 The flowchart of is to judge and count one by one in the order of the clk clock. For the convenience of explaining the working principle, the present application uses the noise filtering comparison diagram generated after the low-to-high level transition in Figure 7 for explanation. Figure 7 The glitch signal in will generate much lower low-level signals, which will cause the system to misidentify a normal signal transition. The traditional solution is to collect the half-bit signal duration and combine the overall data to confirm the actual signal. Although the filtering purpose can also be achieved, the algorithm is too complex. The present application chooses to filter based on the most basic clk signal as the reference. Because noise signals are usually dense and have a short duration, they generally do not reach a certain number (taking 20 in the embodiment as an example) of clk signals. Therefore, the present application uses the clk signal counting threshold as the filtering counting parameter to judge whether it is a noise signal.

[0081] In Figure 7 the initial edge signal is the rising edge signal at the 4th clk moment, and at this time, clock counting starts (starting from 0 and incrementing by 1 successively).

[0082] S2. Detect the signals one by one according to the clock cycle. When the clock count does not reach the threshold specified by the filtering parameter, monitor whether there is an edge signal opposite to the initial edge signal;

[0083] Obviously, within the clk cycle when the initial edge signal is detected, the threshold specified by the filtering parameter is not reached (for example, in this application, 20 clks are used as the standard). Therefore, continue to detect the edge signal opposite to the initial signal in the subsequent clks.

[0084] 1) When no edge signal opposite to the initial edge signal is detected, update the clock count based on the clock signal and continue to detect one by one according to the clock cycle. This step corresponds to the signal at the 5th clk moment. Obviously, there is no falling edge signal. Therefore, after the clock count is incremented by 1, continue to determine whether the filtering threshold is reached and detect the falling edge. When there is no falling edge, continue to detect and time the signal at the 6th clk.

[0085] 2) When an edge signal opposite to the initial edge signal is detected, decrease the clock count value by the step value and continue to detect one by one according to the clock cycle;

[0086] When an edge signal opposite to the initial edge signal is detected at a certain clk moment (corresponding to Figure 7 the falling edge at the 7th clk moment in Figure 7 ), decrease the clock count value by the step value (for example, in this application, the count is decremented by 1). Subsequently, only the edge signal same as the initial edge signal can be detected continuously (that is,

[0087] detect the rising edge signal in

[0088] ). When the next clk remains low, the count is incremented by 1; otherwise, continue to set the count to be decremented by 1. It should be noted that when the low level lasts for multiple clks, the count will be continuously incremented by 1. Figure 7 For example, at the 12th clk moment, the signal returns to high level and stabilizes. Because there are multiple noises between the 7th and 12th clks. Assuming all are rising and falling edge signals, then the cumulative count is 3 at the 12th clk. Subsequently, the high level lasts until the 30th clk when the set filtering threshold is reached. Therefore, from this moment, it is defined as the formal effective output level, that is, high level. So there is a certain delay between the filtered signal output in Figure 7 and the ideal signal. The delay time is Ts, and the maximum value of this time is T 噪声 +T 滤波阈值, in practice, the noise appears for an extremely short time, usually only a few clk durations. If the noise time is longer, it indicates that there are significant problems in the circuit itself. Therefore, the entire delay time is negligible compared to the duty cycle duration and has no impact on encoding and decoding.

[0089] In summary, this filtering method can quickly filter the output by using the method of filtering threshold counting. The clock count value can be increased or decreased according to the actual situation by the step value. As a result, the delay time becomes correspondingly longer or shorter, achieving a reasonable balance between monitoring accuracy and time delay requirements.

[0090] Figure 8 is the structural block diagram of the PSI5 interface circuit current threshold control device provided by the embodiment of the present application. The device is used for a PSI5 interface circuit including N current comparators. The device includes:

[0091] A setting module 810, configured to set gradient-changing current thresholds for the N current comparators. During operation, each current comparator generates a Manchester signal based on the sampled current value and the corresponding current threshold, and records the corresponding decoding success rate through a register group;

[0092] A determining module 820, configured to determine a target current comparator based on the decoding success rates recorded by the N current comparators in the first detection period when powering on;

[0093] A first update module 830, configured to, in the second detection period, obtain the Manchester encoding signal and calculate the duty cycle ratio output by the target current comparator and the corresponding current threshold; update the current threshold of the target current comparator according to the duty cycle ratio gradient, and update the decoding success rates recorded by the N current comparators;

[0094] A second update module 840, configured to, after the second detection period, continuously obtain the decoding success rates recorded by the N current comparators and re-determine the target current comparator, and perform the steps of calculating the duty cycle ratio and updating the current threshold on the target current comparator.

[0095] In some embodiments, the present application further provides a computer device, which may optionally further include: a peripheral device interface and at least one peripheral device. The processor, the memory, and the peripheral device interface may be connected through a bus or signal lines. Each peripheral device may be connected to the peripheral device interface through a bus, signal lines, or a circuit board. Specifically, the peripheral devices include at least one of a radio frequency circuit, a display screen, and a keyboard.

[0096] The peripheral device interface can be used to connect at least one peripheral device related to I / O (Input / Output) to the processor and the memory. In some embodiments, the processor, the memory, and the peripheral device interface are integrated on the same chip or circuit board; in some other embodiments, any one or two of the processor, the memory, and the peripheral device interface can be implemented on separate chips or circuit boards, and this embodiment does not limit this.

[0097] The display screen is used to display the UI (User Interface). The UI may include graphics, text, icons, videos, and any combination thereof. When the display screen is a touch display screen, the display screen also has the ability to collect touch signals on or above the surface of the display screen. The touch signal can be input to the processor for processing as a control signal. At this time, the display screen can also be used to provide virtual buttons and / or a virtual keyboard, also known as soft buttons and / or a soft keyboard. In some embodiments, there can be one display screen, which is set on the front panel of the computer device; in some other embodiments, there can be at least two display screens, which are respectively set on different surfaces of the computer device or are in a folding design; in some other embodiments, the display screen can be a flexible display screen, which is set on the curved surface or the folding surface of the computer device. Even, the display screen can be set to an irregular non-rectangular shape, that is, a special-shaped screen. The display screen can be prepared from materials such as LCD (Liquid Crystal Display) and OLED (Organic Light-Emitting Diode).

[0098] The power supply is used to supply power to each component in the computer device. The power supply can be alternating current, direct current, a disposable battery, or a rechargeable battery. When the power supply includes a rechargeable battery, the rechargeable battery can be a wired rechargeable battery or a wireless rechargeable battery. A wired rechargeable battery is a battery charged through a wired line, and a wireless rechargeable battery is a battery charged through a wireless coil. The rechargeable battery can also be used to support fast charging technology.

[0099] Those skilled in the art can understand that the structure shown in this embodiment does not constitute a limitation on the computer device, and it may include more or fewer components than shown in the figure, or combine some components, or adopt different component arrangements.

[0100] Embodiments of the present application also disclose a computer-readable storage medium. Specifically, the computer-readable storage medium is used to store a computer program, and when the computer program is executed by a processor, the methods in the above method embodiments are implemented. Those skilled in the art can understand that to implement all or part of the processes in the above method embodiments of the present application, it can be completed by instructing relevant hardware through a computer program. The program can be stored in a computer-readable storage medium. When the program is executed, it can include the processes of the above method embodiments. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only memory (ROM), a random access memory (RAM), a flash memory, a hard disk drive (HDD), or a solid-state drive (SSD), etc.; the storage medium can also include a combination of the above types of memories.

[0101] The above describes the preferred embodiments of the present invention; it should be understood that the present invention is not limited to the above specific embodiments, and the devices and structures not described in detail should be understood to be implemented in a common manner in the art; any person skilled in the art can make many possible changes and modifications without departing from the technical solution of the present invention, or modify it into an equivalent embodiment with equivalent changes, which does not affect the essence of the present invention; therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the technical solution of the present invention still fall within the scope of protection of the technical solution of the present invention.

Claims

1. A method for controlling the current threshold of a PSI5 interface circuit, characterized in that The method is used for a PSI5 interface circuit including an N-channel current comparator. The method includes: Setting current thresholds with a gradient change for the N-channel current comparators. During operation, each channel of the current comparator generates a Manchester signal based on the sampled current value and the corresponding current threshold, and records the corresponding decoding success rate through a register bank. In the first detection period after power-on, after the system is powered on, control the N-channel current comparators to generate Manchester signals according to the initially set current thresholds with a gradient. After reaching the target set data frame length, determine the channel with the highest decoding success rate as the target current comparator. In the second detection period, obtain the Manchester encoding signal output by the target current comparator and the corresponding current threshold, and calculate the duty cycle; update the current threshold of the target current comparator according to the duty cycle gradient, and update the decoding success rates recorded by the N-channel current comparators. After the second detection period, continuously obtain the decoding success rates recorded by the N-channel current comparators, continuously update and determine the channel with the highest decoding success rate as the target current comparator, and perform the steps of calculating the duty cycle and updating the current threshold with a gradient for the target current comparator.

2. The method according to claim 1, characterized in that, Each channel of the current comparator is respectively provided with a register bank, including a first register and a second register; the first register stores the number of decoding successes, and the second register stores the decoding success rate. During the working stage, continuously obtain the decoding results of each channel of the current comparator, and record and update the sum of the number of decoding successes in the first register and the decoding success rate data in the second register.

3. The method according to claim 2, wherein In the step of performing the calculation of the duty cycle and updating the current threshold with a gradient for the target current comparator, the step size of updating the current threshold with a gradient is determined based on the length of the second detection period.

4. The method according to any one of claims 1 to 3, characterized in that The decoding results recorded by the N-channel current comparators are determined according to the chip's verification mechanism. When the number of channels with successful decoding is 0, report the decoding error in this round and update the decoding success rate. When the number of channels with successful decoding is not 0 and the results are consistent, report the correct result and update the number of decoding successes and the decoding success rate. When the number of channels with successful decoding is not 0 and the results are inconsistent, report errors for all and update the decoding success rate.

5. The method according to any one of claims 1 to 3, characterized in that, After obtaining the Manchester signal, monitor the edge signal of the Manchester signal. When the initial edge signal is detected, start clock counting. Detect the signal one by one according to the clock cycle. When the clock count does not reach the threshold specified by the filtering parameter, monitor whether there is an edge signal opposite to the initial edge signal. When no edge signal opposite to the initial edge signal is detected, update the clock count based on the clock signal and continue to detect one by one according to the clock cycle; when an edge signal opposite to the initial edge signal is detected, reduce the clock count value by the step value and continue to detect one by one according to the clock cycle. When the clock count does not reach the threshold specified by the filtering parameter, use the level value of the corresponding clock cycle as the output level.

6. The method according to claim 1, characterized in that Receive 1024 frames of Manchester data in the first detection period, update the decoding success rates of the N-channel register banks according to the decoding results of the 1024 frames, and determine the target current comparator based on the channel with the highest decoding success rate. Receive 250 frames of Manchester data during the second detection period, and continue to update the decoding success rate of the N-channel register set according to the decoding results of the 250 frames; Calculate the duty cycle of the target current comparator in each data cycle, and update the current threshold according to the difference gradient from the target duty cycle.

7. The method according to claim 4, characterized in that, After the second detection period, when the decoding success rates of at least two current comparators are the same, select the one with the smallest difference between the current threshold and the corresponding initial threshold current, and determine the target current comparator.

8. A current threshold control device for a PSI5 interface circuit, characterized in that, The device is used for a PSI5 interface circuit including N current comparators, and the device includes: A setting module, configured to set a current threshold with a gradient change for the N current comparators. During operation, each current comparator generates a Manchester signal based on the sampled current value and the corresponding current threshold, and records the corresponding decoding success rate through a register set; A determining module, configured to, in the first detection period after power-on, until the system is powered on, control the N current comparators to generate Manchester signals according to the initially set current threshold with a gradient. After reaching the target set data frame length, determine the one with the highest decoding success rate as the target current comparator; A first update module, configured to, in the second detection period, obtain the Manchester encoding signal and calculate the duty cycle value output by the target current comparator and the corresponding current threshold; update the current threshold of the target current comparator according to the duty cycle value gradient, and update the decoding success rate recorded by the N current comparators; A second update module, configured to, after the second detection period, continuously obtain the decoding success rate recorded by the N current comparators, continuously update and determine the one with the highest decoding success rate as the target current comparator, and perform the steps of calculating the duty cycle and gradient-updating the current threshold on the target current comparator.

9. A computer device, characterized in that, The computer device includes a processor and a memory. At least one instruction, at least one program, a code set or an instruction set is stored in the memory. The at least one instruction, the at least one program, the code set or the instruction set is loaded and executed by the processor to implement the method for controlling the current threshold of the PSI5 interface circuit according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, At least one instruction, at least one program, a code set or an instruction set is stored in the readable storage medium. The at least one instruction, the at least one program, the code set or the instruction set is loaded and executed by the processor to implement the method for controlling the current threshold of the PSI5 interface circuit according to any one of claims 1 to 7.

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