Electronic device

Abstract

The invention provides an electronic device. The electronic device comprises a substrate, an electronic component, a circuit structure and a shielding layer. The electronic component is disposed under the substrate. The circuit structure is disposed under the substrate. The shielding layer is disposed under the substrate and covers the electronic component and is connected to the circuit structure. The circuit structure and the shielding layer are collectively configured to block the electronic component from electromagnetic interference.

Description

Technical Field

[0001] The present disclosure relates generally to an electronic device, and more particularly to an electronic device including an electromagnetic interference (EMI) shielding structure. Background Art

[0002] In order to meet the characteristic impedance requirements and prevent interference to electronic devices that transmit signals with relatively high frequencies (e.g., radio frequency (RF) signals) or input / output signals, electromagnetic interference (EMI) shielding layers are utilized. However, in some cases, the arrangement of EMI shielding layers presents manufacturing challenges. For example, when a metal cover is used to act as an EMI shielding layer, it is difficult to fill the molding material within the metal cover, which forms an undesirable void and thus reduces the performance of the electronic device. Therefore, a new electronic device is needed. Summary of the invention

[0003] In some embodiments, an electronic device includes a substrate, an electronic component, a circuit structure, and a shielding layer. The electronic component is disposed under the substrate. The circuit structure is disposed under the substrate. The shielding layer is disposed under the substrate and covers the electronic component and is connected to the circuit structure. The circuit structure and the shielding layer are collectively configured to block the electronic component from electromagnetic interference.

[0004] In some embodiments, an electronic device includes an electronic component, a circuit structure, an encapsulation layer, and an EMI shielding layer. The circuit structure is adjacent to the electronic component. The circuit structure has a bottom surface configured to provide external connections to the electronic device. The encapsulation layer encapsulates the electronic component. The EMI shielding layer is disposed on a lower surface of the encapsulation layer and at least partially disposed on the bottom surface of the circuit structure.

[0005] In some embodiments, an electronic device includes an electronic component, a circuit structure, an encapsulation layer, and an EMI shielding layer. The circuit structure is adjacent to the electronic component and includes a conductive pad. The encapsulation layer encapsulates the electronic component. The encapsulation layer and the circuit structure jointly define a step. The EMI shielding layer covers the electronic component. A portion of the EMI shielding layer is disposed on the step and connected to the conductive pad. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of some embodiments of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings.It should be noted that the various structures may not be drawn to scale, and that the dimensions of the various structures may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 is a cross-sectional view of an electronic device according to an embodiment of the present disclosure.

[0008] Figure 2 A partial layout of a circuit structure according to an embodiment of the present disclosure is shown.

[0009] Figure 3 The following is an example of an embodiment of the present disclosure. Figure 1 A partial enlarged view of the electronic device shown in FIG.

[0010] Figure 4 The following is an example of an embodiment of the present disclosure. Figure 1 A partial layout of the electronic device shown in FIG.

[0011] Figure 5 is a cross-sectional view of an electronic device according to an embodiment of the present disclosure.

[0012] Fig. 6A is a cross-sectional view of an electronic device according to an embodiment of the present disclosure.

[0013] Figure 6B According to the embodiment of the present disclosure Fig. 6A A perspective view of the electronic device shown in FIG.

[0014] Figure 7 is a cross-sectional view of an electronic device according to an embodiment of the present disclosure.

[0015] Figure 8 is a cross-sectional view of an electronic device according to an embodiment of the present disclosure.

[0016] Fig. 9 A partial layout of a circuit structure according to an embodiment of the present disclosure is shown.

[0017] Fig.10 A partial layout of a circuit structure according to an embodiment of the present disclosure is shown.

[0018] Fig.11 A partial layout of a circuit structure according to an embodiment of the present disclosure is shown.

[0019] Fig.12 A partial layout of a circuit structure according to an embodiment of the present disclosure is shown.

[0020] Fig.13A A partial layout of a circuit structure according to an embodiment of the present disclosure is shown.

[0021] Fig. 13B is a cross-sectional view of an electronic device according to an embodiment of the present disclosure.

[0022] Fig.14 is a cross-sectional view of an electronic device according to an embodiment of the present disclosure.

[0023] Fig.15The following is an example of an embodiment according to the present disclosure. Fig.14 A partial enlarged view of the electronic device shown in FIG.

[0024] Fig.16A and Fig. 16B One or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure are shown.

[0025] Fig.17 One or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure are shown.

[0026] Fig.18 One or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure are shown.

[0027] Fig.19 One or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure are shown.

[0028] Fig. 20 One or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure are shown.

[0029] Fig.21 One or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure are shown.

[0030] Fig. 22 One or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure are shown.

[0031] Fig.23 One or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure are shown.

[0032] Fig.24 One or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure are shown.

[0033] Fig.25 One or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure are shown.

[0034] Fig.26 One or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure are shown. DETAILED DESCRIPTION

[0035] Common reference numbers are used throughout the drawings and detailed description to indicate the same or similar components.Embodiments of the present disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings.

[0036] The following disclosure provides many different embodiments or examples for implementing the different features of the provided themes. Specific examples of components and arrangements are described below to explain certain aspects of the present disclosure. Of course, these components and arrangements are only examples and are not intended to be restrictive. For example, in this specification, the formation of a first feature above or on a second feature may include an embodiment in which the first and second features are formed or arranged in direct contact, and may also include an embodiment in which additional features may be formed or arranged between the first and second features so that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0037] Figure 1 1 is a cross-sectional view of an electronic device 1a according to an embodiment of the present disclosure. In some embodiments, the electronic device 1a may include a substrate 10, an electronic component 22, an electronic component 24, an electronic component 30, an electronic component 32, a circuit structure 40, an encapsulation layer 52, an encapsulation layer 54, an electromagnetic interference (EMI) shielding layer 60, and an EMI shielding layer 70. In some embodiments, the electronic device 1a may be a package structure including six side shielding structures.

[0038] In some embodiments, the substrate 10 (or carrier) may be or include, for example, a printed circuit board, such as a paper-based copper foil laminate, a composite copper foil laminate, or a polymer-impregnated glass fiber-based copper foil laminate. In the present disclosure, the substrate 10 may also be referred to as a substrate. The substrate 10 may have a surface 10s1 (or lower surface), a surface 10s2 (or upper surface) opposite to the surface 10s1, and a surface 10s3 (or side) extending between the surface 10s1 and the surface 10s2. In some embodiments, the substrate 10 may include a conductive pad, a trace, a through hole, a layer, or other interconnects. For example, the substrate 10 may include one or more transmission lines (e.g., a communication cable) and one or more ground lines and / or ground planes. For example, the substrate 10 may include one or more conductive pads (not shown) close to, adjacent to, or embedded in and exposed through the surface 10s1 and / or the surface 10s2 of the substrate 10. The substrate 10 may include a solder resist (not shown) on the surface 10s1 and / or the surface 10s2 to completely expose the conductive pads or expose at least a portion of the conductive pads for electrical connection. The substrate 10 may include a ground trace 10g. The ground trace 10g may be electrically connected to the ground.

[0039] The electronic components 22 and 24 may be disposed on or under the surface 10s1 of the substrate 10. Each of the electronic components 22 and 24 may be electrically connected to the substrate 10. Each of the electronic components 22 and 24 may include a logic die (e.g., an application-specific IC (ASIC), an application processor (AP), a system-on-a-chip (SoC), a central processing unit (CPU), a graphics processing unit (GPU), a microcontroller, etc.), a memory die (e.g., a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, etc.), a power management die (e.g., a power management integrated circuit (PMIC) die), a radio frequency (RF) die, a sensor die, a micro-electro-mechanical-system (MEMS) die, a signal processing die (e.g., a digital signal processing (DSP) die), a front-end die (e.g., an analog front-end (AFE) die), or other active components. In some embodiments, each of electronic components 22 and 24 may include passive devices such as inductors, resistors, and / or capacitors.

[0040] The electronic component 30 may be disposed on or over the surface 10s2 of the substrate 10. The electronic component 30 may be electrically connected to the substrate 10. The electronic component 30 may include a logic die (e.g., an application specific IC, an application processor, a system on a chip, a central processing unit, a graphics processing unit, a microcontroller, etc.), a memory die (e.g., a dynamic random access memory die, a static random access memory die, etc.), a power management die (e.g., a power management integrated circuit die), an RF die, a sensor die, a micro-electromechanical system die, a signal processing die (e.g., a digital signal processing die), a front-end die (e.g., an analog front-end die), or other active components.

[0041] Electronic component 32 may be disposed on or over surface 10s2 of substrate 10. Electronic component 32 may be electrically connected to substrate 10. Electronic component 32 may include a passive device, such as a capacitor, an inductor, or other suitable passive device.

[0042] In some embodiments, the circuit structure 40 (or interposer) may be disposed on or below the surface 10s1 of the substrate 10. In some embodiments, the circuit structure 40 may be disposed at a peripheral region of the substrate 10. In some embodiments, the circuit structure 40 may be configured to receive and / or transmit a non-ground signal (e.g., an input / output (I / O) signal). In some embodiments, the circuit structure 40 may be configured to receive and / or transmit a ground signal to reduce electromagnetic interference (EMI) between components and / or traces. The circuit structure 40 may have a surface 40s1 (or a lower surface), a surface 40s2 (or an upper surface) opposite to the surface 40s1, a surface 40s3 (or an inner side) facing the electronic component 22 (or the electronic component 24), and a surface 40s4 (or an outer side) opposite to the surface 40s3. In some embodiments, the circuit structure 40 may include a substrate 41, a conductive element 42a (or an element), a conductive element 42b (or an element), and dielectric layers 43a and 43b.

[0043] The substrate 41 (or core substrate) may encapsulate the conductive element 42a and the conductive element 42b. The substrate 41 may include or be composed of a plurality of dielectric layers. The substrate 41 may include, for example, polyimide (PI), polyimide-isoindoloquinazolinedione (PIQ), polybenzoic acid, or a plurality of other dielectric layers. polybenzoxazole (PBO), benzocyclobutene (BCB) or other suitable materials.

[0044] In some embodiments, conductive element 42a may be disposed within substrate 41 of circuit structure 40. Conductive element 42a may include a conductive via that at least partially penetrates substrate 41. In some embodiments, conductive element 42a may be disposed between conductive element 42b and electronic component 22 (or electronic component 24). Conductive element 42a may be disposed on opposite sides of electronic component 22 (or electronic component 24) or surround electronic component 22 (or electronic component 24). In some embodiments, conductive element 42a is closer to surface 40s3 than conductive element 42b. In some embodiments, conductive element 42a may be electrically connected to ground or configured to transmit a ground signal, thereby causing EMI interference between conductive element 42b and electronic component 22 (or electronic component 24) to be reduced. Electronic components 22 and 24 may be sensitive to EMI from external devices (e.g., RF devices). Conductive element 42a may block (or shield) electronic components 22 and 24 from external EMI.

[0045] Conductive element 42b may be disposed within substrate 41 of circuit structure 40. Conductive element 42b may include a conductive via that at least partially penetrates substrate 41. In some embodiments, conductive element 42b may be spaced apart from electronic component 22 (or electronic component 24) by conductive element 42a. In some embodiments, conductive element 42 may be configured to transmit a non-ground signal, such as an I / O signal. Conductive element 42b may serve as part of a signal delivery structure. In some embodiments, each of conductive element 42a and conductive element 42b may include a seed layer (not shown) and a conductive material (not shown) formed on the seed layer. The seed layer may include titanium, titanium nitride, or other suitable materials. The conductive material may include copper, silver, aluminum, or other suitable materials.

[0046] Figure 2 4 shows the layout of the circuit structure 40. The substrate 41 may include a plurality of dielectric layers, each of which has an annular profile. In some embodiments, the conductive element 42a may be located in the innermost dielectric layer of the substrate 41. The conductive element 42b may surround the conductive element 42a. The conductive element 42b may be located in the outer dielectric layer of the substrate 41. The conductive element 42a may define a spacing P1. The conductive element 42b may define a spacing P2. In some embodiments, the spacing P2 (or the average distance between the conductive elements 42b) may be greater than the spacing P1 (or the average distance between the conductive elements 42a). Since the spacing P1 is relatively small, EMI (e.g., EMI with a larger frequency) may be more effectively blocked. In some embodiments, the density of the conductive element 42a may be greater than the density of the conductive element 42b. As used herein, the term "density" may refer to the number of elements (e.g., conductive elements) per unit area.

[0047] Return to view Figure 1, dielectric layer 43a is disposed adjacent to surface 40s1 of circuit structure 40. Dielectric layer 43b is disposed adjacent to surface 40s2 of circuit structure 40. Dielectric layer 43a (or 43b) may cover substrate 41 (e.g., the lower surface and upper surface of substrate 41). Dielectric layer 43a (or 43b) may be disposed between encapsulation layer 52 and substrate 41. Dielectric layer 43a (or 43b) may include a solder resist that defines a space exposing terminals 44a and 44b of circuit structure 40. Terminal 44a may be electrically connected to conductive element 42a. Terminal 44a may include a conductive pad or other suitable element. Terminal 44b may be electrically connected to conductive element 42b. Terminal 44b may include a conductive pad or other suitable element. In some embodiments, each of terminals 44a and 44b may include a seed layer (e.g., titanium, titanium nitride, or other suitable material) and a conductive material (e.g., copper or other suitable material). The lower surface and the upper surface of the dielectric layers 43 a and 43 b may be respectively regarded as the surface 40 s 1 and the surface 40 s 2 of the circuit structure 40 .

[0048] The electronic device 1a may include an electrical connector 45 (or electrical contact). The electrical connector 45 may be disposed on or below the surface 40s1 of the circuit structure 40. The electrical connector 45 may be configured to electrically connect the electronic device 1a to an external device (not shown). The electrical connector may include a soldering material (or soldering element), such as an alloy of gold and solder or an alloy of silver and solder.

[0049] The electronic device 1a may include an electrical connector 46 (or electrical contact). The electrical connector 46 may be disposed on or above the surface 40s2 of the circuit structure 40. The electrical connector 46 may be configured to electrically connect the circuit structure 40 and the substrate 10. The electrical connector 46 may include a solder material (or solder element), such as an alloy of gold and solder or an alloy of silver and solder. In some embodiments, the number of electrical connectors 46 may be different from the number of electrical connectors 45. In some embodiments, the number of electrical connectors 46 may be different from the number of electrical connectors 45 in a cross-sectional view. In some embodiments, the number of electrical connectors 46 may be greater than the number of electrical connectors 45. In some embodiments, the number of electrical connectors 46 may be greater than the number of electrical connectors 45 in a cross-sectional view.

[0050] In some embodiments, the encapsulation layer 52 may be disposed on or below the surface 10s1 of the substrate 10. In some embodiments, the encapsulation layer 52 may encapsulate the electronic component 22 and the electronic component 24. In some embodiments, the encapsulation layer 52 may encapsulate the electrical connector 46. The encapsulation layer 52 may cover the surface 40s1 of the circuit structure 40. The encapsulation layer 52 may cover the surface 40s2 of the circuit structure 40. In some embodiments, the encapsulation layer 52 may contact the surface 40s3 of the circuit structure 40. In some embodiments, the encapsulation layer 52 may be spaced apart from the surface 40s4 of the circuit structure 40. The encapsulation layer 52 may include a novolac-based resin, an epoxy resin, a silicone-based resin, or another suitable material. Suitable fillers such as powdered SiO2 may also be included. The encapsulation layer 52 may have a surface 52s1 (or lower surface) and a surface 52s2 (or side surface). In some embodiments, the surface 52s2 of the encapsulation layer 52 may be substantially aligned with the surface 10s3 of the substrate 10. In some embodiments, the surface 52s2 of the encapsulation layer 52 can be substantially aligned with the surface 40s4 of the circuit structure 40. The electrical connector 45 can be exposed by the surface 52s1 of the encapsulation layer 52.

[0051] In some embodiments, encapsulation layer 54 may be disposed on or above surface 10s2 of substrate 10. In some embodiments, encapsulation layer 54 may encapsulate electronic component 30. Encapsulation layer 54 may be spaced apart from encapsulation layer 52 by substrate 10. Encapsulation layer 54 may include a novolac-based resin, an epoxy resin, a silicone-based resin, or another suitable material. Suitable fillers such as powdered SiO2 may also be included. Encapsulation layer 54 may have surface 54s1 (or upper surface) and surface 54s2 (or side). In some embodiments, surface 54s2 of encapsulation layer 54 may be substantially aligned with surface 10s3 of substrate 10.

[0052] In some embodiments, the EMI shielding layer 60 (or grounding layer) may be disposed on or below the surface 52s1 of the encapsulation layer 52. In some embodiments, the EMI shielding layer 60 may be electrically connected to the ground. In some embodiments, the EMI shielding layer 60 may be electrically connected to the ground trace 10g. In some embodiments, the EMI shielding layer 60 may be configured to receive and / or transmit a ground signal. In some embodiments, the EMI shielding layer 60 may cover or vertically overlap the electronic components 22 and the electronic components 24 to prevent EMI from components below the electronic device 1a. In some embodiments, the EMI shielding layer 60 may be electrically connected to the conductive element 42a of the circuit structure 40 via the terminal 44a. In some embodiments, the EMI shielding layer 60 may be electrically isolated from the conductive element 42b of the circuit structure 40.

[0053] Figure 3 Show Figure 1. In some embodiments, the encapsulation layer 52 may define a plurality of recesses, such as recesses 52r1, 52r2, and 52r3. The encapsulation layer 52 may have a surface 52s3 and a surface 52s4 that serve as sides (or lateral surfaces) of the recess 52r1. Figure 3 Surface 52s3 is shown separated from surface 52s4, but it should be noted that recess 52r1 may have a generally circular profile (or an elliptical profile) in a bottom view so that surface 52s3 may be connected to surface 52s4. Recess 52r1 may expose terminal 44a. Recess 52r2 (or recess 52r3) may expose terminal 44b. In some embodiments, electrical connector 45 may be disposed in recess 52r2. In some embodiments, electrical connector 45 may be disposed in recess 52r3. In some embodiments, recess 52r1 may not contain solder elements or solder materials. In some embodiments, the side (not labeled) of dielectric layer 43a of circuit structure 40 and surfaces 52s3 and 52s4 of encapsulation layer 52 may serve as the side of recess 52r1 (or recess 52r2 or 52r3). The side of dielectric layer 43a may be substantially aligned with surface 52s3 (or surface 52s4) of encapsulation layer 52. The encapsulation layer 52 may have a surface 52s5 spaced apart from the surface 52s1 by a recess 52r1. Figure 3 Surface 52s1 is shown separated from surface 52s5 in the cross-sectional view, but it should be noted that surface 52s1 is connected to surface 52s5 in the bottom view.

[0054] In some embodiments, the encapsulation layer 52 and the circuit structure 40 may jointly define a step 40t. The lower surface of the substrate 41 and the surfaces 52s1 and 52s3 of the encapsulation layer 52 define the step 40t. The step 40t may expose a portion of the terminal 44a. The EMI shielding layer 60 may be disposed on the step 40t.

[0055] In some embodiments, the EMI shielding layer 60 may include a portion 61, a portion 62, and a portion 63. The portion 61 may be disposed on or below the surface 52s1 of the encapsulation layer 52. In some embodiments, the portion 61 may be in contact with the encapsulation layer 52.

[0056] In some embodiments, portion 62 (or connecting portion) may be disposed on surface 52s3 of encapsulation layer 52. Portion 62 may connect portions 61 and 63. In some embodiments, portion 62 may be disposed within recess 52r1 of encapsulation layer 52. In some embodiments, portion 62 may contact encapsulation layer 52.

[0057] In some embodiments, portion 63 may be disposed on or below terminal 44a. In some embodiments, portion 63 may be disposed within recess 52r1. In some embodiments, portion 63 may be separated from encapsulation layer 52 by dielectric layer 43a.

[0058] In some embodiments, the surface 52s4 may be exposed by the EMI shielding layer 60 . That is, a portion of the side defining the recess 52r1 is exposed by the EMI shielding layer 60 .

[0059] In some embodiments, the EMI shielding layer 60 may have a non-uniform thickness. Portion 61 may have a thickness T1, which may be defined as the minimum distance between the outer surface of portion 61 of the EMI shielding layer 60 and the encapsulation layer 52. Portion 62 may have a thickness T2, which may be defined as the minimum distance between the outer surface of portion 62 of the EMI shielding layer 60 and the encapsulation layer 52. Portion 63 may have a thickness T3, which may be defined as the minimum distance between the outer surface of portion 63 of the EMI shielding layer 60 and the terminal 44a. In some embodiments, thickness T1 may be greater than thickness T2. In some embodiments, thickness T1 may be greater than thickness T3. In some embodiments, thickness T3 may be equal to or greater than thickness T2. In some embodiments, the ratio of thickness T1 to thickness T2 may be in the range of about 1.1 to about 1.5, such as 1.1, 1.2, 1.3, 1.4, or 1.5.

[0060] In some embodiments, portion 61 may be considered as a generally horizontal portion ES1 of the EMI shielding structure ES. In some embodiments, portion 63, terminal 44a, and conductive element 42a may be collectively considered as a generally vertical portion ES2 of the EMI shielding structure ES. The generally horizontal portion ES1 may be generally orthogonal to the generally vertical portion ES2. In some embodiments, the generally horizontal portion ES1 of the EMI shielding structure ES may be in contact with the encapsulation layer 52. In some embodiments, the generally vertical portion ES2 of the EMI shielding structure ES may be spaced apart from the encapsulation layer 52. The generally vertical portion ES2 may be connected to the generally horizontal portion ES1 by portion 62 of the EMI shielding layer 60. Portion 62 may be tilted relative to the generally horizontal portion ES1. Portion 62 may be tilted relative to the generally vertical portion ES2.

[0061] In some embodiments, a gap 52g may be defined between the lower surface 43as1 of the dielectric layer 43a and the surface 52s1 of the encapsulation layer 52. In some embodiments, the height of the lower surface 43as1 of the dielectric layer 43a may be lower than the height of the lower surface (not labeled) of the portion 63 of the EMI shielding layer 60. In some embodiments, the height of the surface 60s1 (or lower surface) of the EMI shielding layer 60 may be lower than the height of the bottom of the electrical connector 45.

[0062] Figure 4The layout of the encapsulation layer 52 and the EMI shielding layer 60 is shown in a bottom view. It should be noted that some elements are omitted for simplicity. In some embodiments, each of the recesses 52r1, 52r2, and 52r3 may have a circular profile, an elliptical profile, or other suitable profile. In other embodiments, each of the recesses 52r1, 52r2, and 52r3 may have a rectangular profile. The terminal 44a may be exposed by the recess 52r1 and covered by the portion 63. Although Figure 4 Terminal 44a is shown as having a rectangular profile in bottom view, but terminal 44a may have other profiles, such as a circular profile. Portion 63 may be located on an exposed portion of terminal 44a. Portion 62 may extend between portions 61 and 63.

[0063] Figure 5 An enlarged view of the EMI shielding layer 60 is shown. In some embodiments, the composition of the EMI shielding layer 60 may be different from the composition of the conductive element 42a (or 42b). In some embodiments, the EMI shielding layer 60 may include an adhesive metal layer 60p1, one or more intervening metal layers 60p2, and a protective metal layer 60p3. The adhesive metal layer 60p1 may face the encapsulation layer 52. The intervening metal layer 60p2 may be sandwiched by the adhesive metal layer 60p1 and the protective metal layer 60p3. The adhesive metal layer 60p1 may have relatively good adhesion to the encapsulation layer 52 to prevent the EMI shielding layer 60 from peeling off from the encapsulation layer 52. The adhesive metal layer 60p1 may include, for example, stainless steel or other suitable materials. The intervening metal layer 60p2 may have relatively good ductility and shielding capabilities to block electronic components (such as electronic components 22 and 24) from interference signals (such as light or other optical signals) in the surrounding environment. The intervening metal layer 60p2 may include, for example, copper or other suitable materials. The protective metal layer 60p3 may be configured to protect the intervening metal layer 60p2 from oxidation. The protective metal layer 60p3 may include, for example, stainless steel or other suitable materials.

[0064] Return to view Figure 1 , an EMI shielding layer 70 (or grounding layer) may be disposed on or over a surface 54s1 of the encapsulation layer 54. The EMI shielding layer 70 may be configured to prevent EMI in the electronic components 22, 24, and / or 30 due to the exterior of the electronic device 1a. The EMI shielding layer 70 may cover a surface 54s2 of the encapsulation layer 54. The EMI shielding layer 70 may cover a surface 10s3 of the substrate 10. The EMI shielding layer 70 may cover and contact a surface 40s4 of the circuit structure 40. The EMI shielding layer 70 may cover and contact a surface 52s2 of the encapsulation layer 52. In some embodiments, the EMI shielding layer 70 may be electrically connected to a ground. The EMI shielding layer 70 may be electrically connected to the substrate 10. In some embodiments, the EMI shielding layer 70 may be spaced apart from the EMI shielding layer 60.

[0065] like Figure 1 As shown in , electronic device 1a may include a path L1 for transmitting a ground signal. Path L1 may pass through EMI shielding layer 60 and conductive element 42a. Electronic device 1a may include a path L2 for transmitting a non-ground signal (e.g., an I / O signal). Path L1 may traverse electronic components 22 and 24. Path L1 may be connected to ground trace 10g. Path L1 may be connected to EMI shielding layer 70. Path L2 may pass through electrical connector 45 and conductive element 42b. It should be noted that some conductive elements 42b are configured to transmit a ground signal to an external device (e.g., a printed circuit board) that provides a power supply connected to ground.

[0066] In the comparative example, a metal cover is used to act as an EMI shielding layer. The metal cover may include a top plate having an opening and four side walls connected to the top plate. Under some conditions, after the four side walls of the metal cover are attached to the carrier, the molding material is filled into the internal space of the metal cover through the opening of the top plate. Since the size of the opening should be relatively small to ensure the shielding performance, it is difficult to fill the molding material in the metal cover through such a small opening, thereby generating a void formed in the molding material. As a result, the reliability of the electronic device is degraded. In some embodiments of the present disclosure, the metal cover is replaced by the conductive element 42a of the circuit structure 40 and the EMI shielding layer 60. The EMI shielding layer 60 is formed after the formation of the encapsulation layer 52. In addition, the conductive element 42a and the EMI shielding layer 60 are not formed integrally. Therefore, the aforementioned problems of the comparative example are avoided, thereby improving the reliability of the electronic device 1a.

[0067] Fig. 6A 1 is a cross-sectional view of an electronic device 1b according to an embodiment of the present disclosure. The electronic device 1b is similar to the electronic device 1a, with the following differences.

[0068] In some embodiments, EMI shielding layer 60 may extend between recesses 52r1 and 52r2. EMI shielding layer 60 may include portions 64 and 65. Portion 64 may be disposed on surface 52s4. Portion 64 may extend between portions 63 and 65. In the cross-sectional view, portion 64 may be spaced apart from portion 62. Portion 65 may be disposed on a portion of surface 52s5 located between recesses 52r1 and 52r2. In the cross-sectional view, portion 65 may be spaced apart from portion 61. In some embodiments, the thickness (not labeled) of portion 65 may be substantially the same as the thickness of portion 61. In some embodiments, the thickness (not labeled) of portion 64 may be substantially the same as the thickness of portion 62. In this embodiment, EMI shielding layer 60 further includes portion 65. Portion 65 may completely cover the exposed portion of terminal 44a, thereby enhancing EMI shielding performance. The formation of portion 65 will be in Fig.25 and Fig.26 Described in.

[0069] Figure 6B According to the embodiment of the present disclosure Fig. 6A . In some embodiments, portions 62 and 64 may be portions of a generally circular ring (or generally elliptical ring). The aperture of the generally circular ring (or generally elliptical ring) may taper toward terminal 44a. Portions 61 and 65 may be portions of a base plate connected to the generally circular ring (or generally elliptical ring). Portion 63 may have a generally circular profile (or generally elliptical profile) covering terminal 44a.

[0070] Figure 7 1 is a cross-sectional view of an electronic device 1c according to an embodiment of the present disclosure. The electronic device 1c is similar to the electronic device 1a, with the following differences.

[0071] In some embodiments, the electronic device 1c may include a compartment structure 72. In some embodiments, the compartment structure 72 may be disposed between the electronic components 22 and 24. In some embodiments, the compartment structure 72 may penetrate the encapsulation layer 52. In some embodiments, the compartment structure 72 may extend between the surface 10s1 of the substrate 10 and the EMI shielding layer 60. In some embodiments, the compartment structure 72 may be electrically connected to the substrate 10. In some embodiments, the compartment structure 72 may be electrically connected to the ground trace 10g. In some embodiments, the compartment structure 72 may be electrically connected to the EMI shielding layer 60. In some embodiments, the compartment structure 72 may be configured to reduce EMI between the electronic components 22 and 24. In some embodiments, the compartment structure 72 may include a seed layer (e.g., titanium, titanium nitride, or other suitable materials) and a conductive material (e.g., copper or other suitable materials).

[0072] Figure 8 1 is a cross-sectional view of an electronic device 1d according to an embodiment of the present disclosure. The electronic device 1d is similar to the electronic device 1a, with the following differences.

[0073] In some embodiments, the electronic device 1d may include an electronic component 26. The electronic component 26 may be disposed on or below the surface 10s1 of the substrate 10. The electronic component 26 may be electrically connected to the substrate 10. The electronic component 26 may include a logic die (e.g., a dedicated IC, an application processor, a system on a chip, a central processing unit, a graphics processing unit, a microcontroller, etc.), a memory die (e.g., a dynamic random access memory die, a static random access memory die, etc.), a power management die (e.g., a power management integrated circuit die), a radio frequency die, a sensor die, a micro-electromechanical system die, a signal processing die (e.g., a digital signal processing die), a front-end die (e.g., an analog front-end die), or other active components. In some embodiments, the lower surface (not marked) of the electronic component 26 may be exposed by the surface 52s1 of the encapsulation layer 52. In some embodiments, the electronic component 26 may be in contact with the EMI shielding layer 60'. In some embodiments, the adhesive metal layer, the intervening metal layer, and the protective metal layer of the EMI shielding layer 60' may include titanium, copper, and titanium, respectively, or be composed of titanium, copper, and titanium.

[0074] Fig. 9 A partial layout of a circuit structure 40 of an electronic device 1e according to an embodiment of the present disclosure is shown. The electronic device 1e is similar to the electronic device 1a with the following differences.

[0075] In some embodiments, conductive element 42a may be replaced with conductive element 47. In some embodiments, conductive element 47 may be embedded within substrate 41 of circuit structure 40. Conductive element 47 may be configured to receive or transmit a ground signal. In some embodiments, conductive element 47 may include an annular profile. In some embodiments, in a top view, surface 40s3 may be completely separated from surface 40s4 by conductive element 47. In some embodiments, conductive element 47 may define a completely closed loop, thereby resulting in improved EMI shielding performance.

[0076] Fig.10 A partial layout of a circuit structure 40 of an electronic device 1f according to an embodiment of the present disclosure is shown. The electronic device 1f is similar to the electronic device 1a with the following differences.

[0077] In some embodiments, the circuit structure 40 may include a conductive element 42a1 and a conductive element 42a2. In some embodiments, each of the conductive element 42a1 and the conductive element 42a2 may be configured to receive or transmit a ground signal. The conductive element 42a1 may surround the conductive element 42a2. In some embodiments, the conductive element 42a1 and the conductive element 42a2 may have a staggered arrangement. For example, the conductive element 42a1 may be misaligned with the conductive element 42a2 along the horizontal direction and the longitudinal direction. In some embodiments, the conductive element 42a2 is closer to the surface 40s3 than the conductive element 42a1. Through such an arrangement, EMI shielding performance is enhanced.

[0078] Fig.11 FIG. 4 shows a partial layout of a circuit structure 40 of an electronic device 1g according to an embodiment of the present disclosure. The electronic device 1g is similar to the electronic device 1a, with the following differences. It should be noted that for the sake of simplicity, Fig.11 For example, terminal 44a, dielectric layer 43a, substrate 41, and encapsulation layer 52 are omitted, and conductive elements 42a and 42b and electronic components 27 and 28 are shown as dashed lines.

[0079] In some embodiments, the electronic device 1g may include electronic components 27 and 28. The electronic components 27 and 28 may be disposed in a circuit structure (eg, Figure 1 10) and surrounded by circuit structure 40. In some embodiments, conductive elements 42a and conductive elements 42b may be aligned along a first direction (e.g., a horizontal direction) and a second direction (e.g., a longitudinal direction) to form an array arrangement. In some embodiments, EMI shielding layer 60 may overlap electronic components 27 and 28. In some embodiments, EMI shielding layer 60 may overlap conductive element 42a. In some embodiments, EMI shielding layer 60 may not overlap conductive element 42b. In some embodiments, EMI shielding layer 60 may have a rectangular profile, a square profile, or other suitable profile.

[0080] Fig.12 FIG. 1 shows a partial layout of an electronic device 1h according to an embodiment of the present disclosure. The electronic device 1h is similar to the electronic device 1a, with the following differences. It should be noted that for the sake of brevity, Fig.12 For example, terminal 44a, dielectric layer 43a, substrate 41, and encapsulation layer 52 are omitted, and conductive elements 42a and 42b and electronic components 27 and 28 are shown as dashed lines.

[0081] In some embodiments, EMI shielding layer 60 may have a cross-shaped profile. In some embodiments, a portion of conductive element 42b (eg, conductive element 42b1) may be aligned with conductive element 42a along both a first direction (eg, horizontal direction) and a second direction (eg, longitudinal direction).

[0082] Fig.13A A partial layout of a circuit structure 40 of an electronic device 1i according to an embodiment of the present disclosure is shown. The electronic device 1i is similar to the electronic device 1a, with the following differences. It should be noted that some features are omitted in FIG. 13 for the sake of brevity. For example, the terminal 44a, the dielectric layer 43a, the substrate 41, and the encapsulation layer 52 are omitted, and the conductive elements 42a and 42b and the electronic components 27 and 28 are represented as dashed lines.

[0083] In some embodiments, conductive element 42a is not disposed at some sides of surface 40s3. For example, surface 40s3-1 only faces conductive element 42b. Conductive element 42a is not disposed between conductive element 42b and surface 40s3-1. In some embodiments, some sides of surface 40s3 may face both conductive element 42a and conductive element 42b. For example, surface 40s3-2 may face both conductive element 42a and conductive element 42b. In some embodiments, in a bottom view or a top view, EMI shielding layer 60 may not encroach on surface 40s3-1 of circuit structure 40.

[0084] Under some conditions, the conductive element 42b at the left side of the surface 40s3-1 of the circuit structure 40 may be configured to transmit a signal having a smaller frequency. This smaller frequency may have relatively less interference with the signals from the electronic components 27 and 28. In this case, the conductive element 42b at the left side of the surface 40s3-1 of the circuit structure 40 may not be connected to the ground trace (e.g., 10g). As a result, the conductive element 42b at the left side of the surface 40s3-1 may be connected to an electrical connector (e.g., a soldering element), which allows the circuit structure 40 to have more input / output terminals.

[0085] Fig. 13B is a cross-sectional view of an electronic device 1i' according to an embodiment of the present disclosure. The electronic device 1h is similar to the electronic device 1i', with the following differences.

[0086] In some embodiments, a portion of conductive element 42a may be replaced by conductive element 42b. Figure 1 The conductive element 42a on the left side of the conductive element 42b can be replaced by the conductive element 42b. The electrical connector 45 can be connected to the conductive element 42b, and the filling Figure 3In this embodiment, the number of electrical connectors 45 at the left side of the circuit structure 40 may be different from the number of electrical connectors at the right side of the circuit structure 40 .

[0087] Fig.14 is a partial cross-sectional view of an electronic device 1 j according to an embodiment of the present disclosure.

[0088] The electronic device 1j shows a scanning electron microscope (SEM) image. In some embodiments, the electronic device 1j may include a circuit structure 81 , a circuit structure 82 , an encapsulation layer 83 , an encapsulation layer 84 , an EMI shielding layer 85 , an EMI shielding layer 86 , an electrical connector 87 , and an electrical connector 88 .

[0089] The circuit structure 81 may be or include, for example, a printed circuit board, such as a paper-based copper foil laminate, a composite copper foil laminate, or a polymer-impregnated fiberglass-based copper foil laminate. The circuit structure 81 may have a surface 81s1 (or lower surface) and a surface 81s2 (or upper surface) opposite to the surface 81s1. The circuit structure 81 may include one or more transmission lines (e.g., communication cables) and one or more ground lines and / or ground planes. For example, the circuit structure 81 may include one or more conductive pads that are close to, adjacent to, or embedded in the surface 81s1 and / or the surface 81s2 of the circuit structure 81 and exposed by the surface 81s1 and / or the surface 81s2.

[0090] In some embodiments, the circuit structure 82 may be disposed on or below the surface 81s1 of the circuit structure 81. In some embodiments, the circuit structure 82 may be disposed at a peripheral region of the circuit structure 81. In some embodiments, the circuit structure 82 may include a substrate 82d1, a dielectric layer 82d2, a conductive element 82v1, a conductive element 82v2, a terminal 82p1, and a terminal 82p2.

[0091] The substrate 82d1 may encapsulate the conductive element 82v1 and the conductive element 82v2. The substrate 82d1 may include or be composed of a plurality of dielectric layers. The substrate 82d1 may include, for example, polyimide, polyimide-isoindolequinazolinedione, polybenzoic acid, or the like. azole, benzocyclobutene or other suitable materials.

[0092] In some embodiments, the conductive element 82v1 may be disposed within the substrate 82d1 of the circuit structure 82. In some embodiments, the conductive element 82v1 may be electrically connected to ground or configured to transmit a ground signal, thereby resulting in reduced EMI interference between the conductive element 82v2 and electronic components (not shown).

[0093] The conductive element 82v2 may be disposed within the substrate 82d1 of the circuit structure 82. In some embodiments, the conductive element 82v2 may be configured to transmit a non-ground signal, such as an I / O signal.

[0094] In some embodiments, each of the conductive elements 82v1 and 82v2 may include a seed layer (not labeled) and a conductive material (not labeled). The seed layer may include titanium, titanium nitride, or other suitable materials. The conductive material may include copper, silver, aluminum, or other suitable materials. In some embodiments, the conductive elements 82v1 and / or 82v2 may have an X-shaped profile. For example, the conductive elements 82v1 and / or 82v2 have upper and lower portions that taper toward each other. The upper and lower portions may be formed by separate laser drilling steps.

[0095] The dielectric layer 82d2 may cover the substrate 82d1. The dielectric layer 82d2 may include a solder resist that defines a space where the terminal 82p1 and the terminal 82p2 are exposed.

[0096] The terminal 82p1 may be electrically connected to the conductive element 82v1. The terminal 82p2 may be electrically connected to the conductive element 82v2.

[0097] In some embodiments, the encapsulation layer 83 may be disposed on or below the surface 81s1 of the circuit structure 81. The encapsulation layer 83 may cover the upper surface and the lower surface (not labeled) of the circuit structure 82. The encapsulation layer 83 may include a novolac-based resin, an epoxy resin, a silicone-based resin, or another suitable material. A suitable filler, such as powdered SiO2, may also be included. The encapsulation layer 83 may have a surface 83s1 (or lower surface). In some embodiments, the electrical connector 88 may be exposed by the surface 83s1 of the encapsulation layer 83.

[0098] In some embodiments, encapsulation layer 84 may be disposed on or above surface 81s2 of circuit structure 81. Encapsulation layer 84 may be separated from encapsulation layer 83 by circuit structure 81. Encapsulation layer 84 may include a novolac-based resin, an epoxy resin, a silicone-based resin, or another suitable material. Suitable fillers such as powdered SiO2 may also be included.

[0099] In some embodiments, EMI shielding layer 85 may cover encapsulation layer 84. EMI shielding layer 85 may cover sides (not labeled) of circuit structure 81. EMI shielding layer 85 may cover sides (not labeled) of circuit structure 82. EMI shielding layer 85 may cover sides (not labeled) of encapsulation layer 83. EMI shielding layer 85 may cover sides (not labeled) of encapsulation layer 84.

[0100] In some embodiments, the EMI shielding layer 86 may be disposed on or below the surface 81s1 of the circuit structure 81. In some embodiments, the EMI shielding layer 86 may be electrically connected to ground. In some embodiments, the EMI shielding layer 86 may be electrically connected to the conductive element 82v1 of the circuit structure 82 via the terminal 82p1. In some embodiments, the EMI shielding layer 86 may be electrically isolated from the conductive element 82v2 of the circuit structure 82.

[0101] The electrical connector 87 may be electrically connected between the conductive element 82v1 (or the conductive element 82v2) and the circuit structure 81. The electrical connector 88 may be electrically connected to the conductive element 82v2. Each of the electrical connectors 87 and 88 may include a solder material, such as an alloy of gold and solder or an alloy of silver and solder. In some embodiments, the terminal 82p1 may not contain a solder joint. In some embodiments, the conductive structure including the conductive element 82v1 and the terminal 82p1 does not contain a solder joint at a side away from the circuit structure 81.

[0102] See also Fig.15 , Fig.15 Show Fig.14 82p1. In some embodiments, the encapsulation layer 83 may define a recess 83r that exposes the terminal 82p1. The encapsulation layer 83 may have surfaces 83s2 and 83s3 that serve as one side of the recess 83r. In some embodiments, the recess 83r may not contain a solder element or solder material. In some embodiments, the roughness of the surface 83s2 may be greater than the roughness of the surface 83s1. In some embodiments, the roughness of the outer surface (or lower surface) of the portion 86p3 may be less than the roughness of the outer surface (or side) of the portion 86p2 (or 86p4). In some embodiments, the roughness of the outer surface (or lower surface) of the portion 86p1 (or 86p5) may be less than the roughness of the outer surface (or side) of the portion 86p2 (or 86p4).

[0103] In some embodiments, the EMI shielding layer 86 may include portions 86p1, 86p2, 86p3, 86p4, and 86p5. Portion 86p1 may be disposed on or below the surface 83s1 of the encapsulation layer 83. In some embodiments, portion 86p1 may be in contact with the encapsulation layer 83. In some embodiments, portion 86p2 may be disposed on the surface 83s2 of the encapsulation layer 83. In some embodiments, portion 86p2 may be disposed in a recess 83r of the encapsulation layer 83. In some embodiments, portion 86p3 may be in contact with the terminal 82p1. In some embodiments, portion 86p3 may be disposed in the recess 83r. In some embodiments, portion 86p3 may be spaced apart from the encapsulation layer 83. Portion 86p2 may connect portions 86p1 and 86p3. Portion 86p4 may be disposed on the surface 83s3 of the encapsulation layer 83. Portion 86p5 may be disposed on or below the surface 83s1 of the encapsulation layer 83. Portion 86p4 may connect portions 86p3 and 86p5. In some embodiments, the thickness of portion 86p1 may be greater than the thickness of portion 86p2. In some embodiments, the thickness of portion 86p1 may be greater than the thickness of portion 86p3.

[0104] Fig.16A , Fig. 16B , Fig.17 , Fig.18 , Fig.19 , Fig. 20 , Fig.21 , Fig. 22 , Fig.23 and Fig.24 One or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure are shown.

[0105] See also Fig.16A , Fig.16A A top view of a core carrier 40u is shown. The core carrier 40u may include a plurality of circuit structures 40 constituting a repeating unit that will be singulated later. Each of the circuit structures 40 may include an opening 40r. Figures 16B to 24 A cross-sectional view of one of the repeating units at different stages is shown. That is, the circuit structure 40 can be a ring-shaped insert or have other suitable contours. In some embodiments, depending on the number of I / O terminals required and the requirements of EMI shielding, the packaging unit can include multiple inserts spaced apart from each other.

[0106] See also Fig. 16B , conductive elements 42a and conductive elements 42b may be formed in substrate 41. Dielectric layers 43 and 43b may be formed to cover surfaces 40s1 and 40s2 of circuit structure 40. Electrical connector 46 may be formed on or over surface 40s2 of circuit structure 40.

[0107] See also Fig.17, a substrate 10 may be provided. The substrate 10 may be attached to a circuit structure 40 (or a core carrier 40u) via an electrical connector 46. Electronic components 22 and 24 may be attached to a surface 10s1 of the substrate 10.

[0108] See also Fig.18 The encapsulation layer 52 may be formed on or below the surface 10s1 of the substrate 10 . The electronic components 22 and 24 may be encapsulated by the encapsulation layer 52 . The encapsulation layer 52 may cover the surface 40s1 of the circuit structure 40 .

[0109] See also Fig.19 , the electronic component 30 may be attached to the surface 10s2 of the substrate 10. In some embodiments, the electronic component 30 may be attached to the substrate 10 by, for example, flip chip technology or other suitable technology.

[0110] See also Fig. 20 The encapsulation layer 54 may be formed on or above the surface 10s2 of the substrate 10 . The encapsulation layer 54 may encapsulate the electronic component 30 .

[0111] See also Fig.21 , a portion of the dielectric layer 43a and the encapsulation layer 52 may be removed. The conductive elements 42a and the conductive elements 42b may be exposed. In some embodiments, the dielectric layer 43a and the encapsulation layer 52 may be removed by, for example, laser ablation technology or other suitable technology.

[0112] See also Fig. 22 , the EMI shielding layer 60 may be formed to cover a portion of the surface 52s1 of the encapsulation layer 52. The EMI shielding layer 60 may be electrically connected to the conductive element 42a. In some embodiments, a mask (not shown) may be used to define a pattern of the EMI shielding layer 60. In some embodiments, the EMI shielding layer 60 may be formed by, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), or other suitable processes. For example, the EMI shielding layer 60 may be formed by a sputtering technique.

[0113] See also Fig.23 , the electrical connector 45 can be formed on or below the conductive element 42b.

[0114] See also Fig.24 , can be sawed Fig.16A 4 to separate the plurality of circuit structures 40. In some embodiments, the substrate 10, the encapsulation layer 52, and the encapsulation layer 54 may be sawn to define the surface 10s3, the surface 52s2, and the surface 54s2. In addition, the EMI shielding layer 70 may be formed to cover the surface 54s1 and the surface 54s2 of the encapsulation layer 54, the surface 10s3 of the substrate 10, and the surface 52s2 of the encapsulation layer 52. As a result, an electronic device (e.g., Figure 1 The electronic device 1a shown in FIG.

[0115] Fig.25 and Fig.26 One or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure are shown. The initial stage of the process is shown with FIG. 16B to FIG. 21 The stages shown in are the same or similar. Fig.25 Depicted in Fig.21 The stage following the stage depicted in .

[0116] See also Fig.25 , a mask 80 may be provided to cover a portion of the surface 52s1 of the encapsulation layer 52. In addition, the recess 52r2 and the recess 52r3 may be covered by the mask 80. A portion of the surface 52s1 located between the recesses 52r1 and 52r2 may be partially exposed by the mask 80. The recess 52r1 may be exposed by the mask 80.

[0117] See also Fig.26 , EMI shielding layer 60 may be formed. EMI shielding layer 60 may be formed on portions of encapsulation layer 52 that are not covered by mask 80. As a result, portions 64 and 65 may be formed. After forming EMI shielding layer 60, mask 80 may be removed, and a Fig.23 and Fig.24 The manufacturing process shown in the embodiment of the present invention is used to form an electronic device (e.g., Fig. 6A The electronic device 1b shown in FIG.

[0118] In some embodiments, an electronic device includes an electronic component, an insert, and an electromagnetic interference (EMI) shielding layer. The insert is adjacent to the electronic component and includes a first conductive element and a second conductive element. The EMI shielding layer covers the electronic component and is electrically connected to the second conductive element.

[0119] In some embodiments, the second conductive element is disposed on opposite sides of the electronic component.

[0120] In some embodiments, the second conductive element surrounds the electronic component.

[0121] In some embodiments, the first conductive element includes a first conductive via group, the second conductive element includes a second conductive via group, and a density of the first conductive via group is less than a density of the second conductive via group.

[0122] In some embodiments, a plurality of electrical contacts are electrically connected to the first group of conductive vias and are electrically isolated from the second group of conductive vias.

[0123] In some embodiments, an encapsulation layer covers the electronic component and the interposer. The encapsulation layer defines a first recess exposing the second conductive element, and the EMI shielding layer extends into the first recess.

[0124] In some embodiments, the encapsulation layer has a side defining the first recess, and the EMI shielding layer is disposed on two opposing sides of the side of the recess in a cross-sectional view.

[0125] In some embodiments, the encapsulation layer defines a second recess that exposes the first conductive element and accommodates an electrical contact.

[0126] In some embodiments, the encapsulation layer defines a second recess exposing the first conductive element, and the EMI shielding layer covers a portion of the encapsulation layer between the first conductive element and the second conductive element.

[0127] In some embodiments, the EMI shielding layer has a first portion on a bottom surface of the encapsulation layer and a second portion on a side surface of the encapsulation layer, and a thickness of the first portion is greater than a thickness of the second portion.

[0128] In some embodiments, the EMI shielding layer covers a bottom surface of the encapsulation layer between the first conductive element and the second conductive element.

[0129] In some embodiments, the second conductive element is free of solder joints at the side adjacent to the EMI shielding layer.

[0130] In some embodiments, the compartment structure penetrates the encapsulation and is electrically connected to the EMI shielding layer.

[0131] In some embodiments, an encapsulation layer encapsulates the electronic component. The interposer has an inner side facing the electronic component and an outer side opposite to the inner surface, and the outer side is exposed by the encapsulation layer.

[0132] In some embodiments, an electronic device includes an electronic component, an insert, and an electromagnetic interference (EMI) shielding layer. The insert is adjacent to the electronic component and includes a first conductive element and a second conductive element. The EMI shielding layer covers the electronic component and is electrically connected to the second conductive element.

[0133] In some embodiments, the EMI shielding structure includes a connecting portion connecting a vertical portion and a horizontal portion, and the connecting portion is inclined relative to the vertical portion and the horizontal portion.

[0134] In some embodiments, a thickness of the connecting portion is less than a thickness of the horizontal portion.

[0135] In some embodiments, the composition of the horizontal portion is different from the composition of the vertical portion.

[0136] In some embodiments, a signal delivery structure is spaced apart from the electronic component by the vertical portion of the EMI shielding structure.

[0137] In some embodiments, the signal delivery structure includes a conductive via surrounding the vertical portion of the EMI shielding structure.

[0138] In some embodiments, an electronic device includes an electronic component, an insert, and an electromagnetic interference (EMI) shielding layer. The insert is adjacent to the electronic component and includes a first conductive element and a second conductive element. The EMI shielding layer covers the electronic component and is electrically connected to the second conductive element.

[0139] In some embodiments, an encapsulation layer encapsulates the first electronic component and is spaced apart from the second conductive element by a dielectric structure of the interposer.

[0140] In some embodiments, a ground layer is disposed on a lower surface of the encapsulation layer at intervals and is electrically connected to the second conductive element.

[0141] In some embodiments, the ground layer vertically overlaps the second conductive element.

[0142] In some embodiments, the ground layer does not vertically overlap the first conductive element.

[0143] In some embodiments, the second electronic component is disposed adjacent to the first electronic component. A compartment structure is disposed between the first electronic component and the second electronic component. The compartment structure is connected to the ground layer.

[0144] In some embodiments, the encapsulation layer has a first side surface connected to the lower surface and defining a first recess exposing the second conductive element, and the ground layer completely covers the first side surface of the encapsulation layer.

[0145] In some embodiments, the encapsulation layer has a second side connected to the lower surface and defining a second recess exposing the first conductive element, and the ground layer is spaced apart from the second side of the encapsulation layer.

[0146] In some embodiments, a portion of the ground layer extends from the first side toward the second side.

[0147] In some embodiments, the ground layer has a non-uniform thickness.

[0148] Unless otherwise specified, spatial descriptions such as "above", "below", "up", "left", "right", "lower", "top", "bottom", "vertical", "horizontal", "side", "above", "below", "upper", "above", "below", etc. are indicated relative to the orientation shown in the figure. It should be understood that the spatial descriptions used herein are for illustrative purposes only, and that embodiments of the structures described herein may be spatially arranged in any orientation or manner, provided that the advantages of the embodiments of the present disclosure are not deviated by such arrangements.

[0149] As used herein, the terms "approximately," "substantially," "substantially," "about," and "about" are used to describe and explain minor variations. When used in conjunction with an event or circumstance, these terms may refer to instances where the event or circumstance occurred exactly as well as instances where the event or circumstance occurred very approximately. For example, when used in conjunction with a numerical value, these terms may refer to a range of variation of less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if the difference between two values ​​is less than or equal to ±10% of the average of the values, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%, then the two values ​​can be considered to be "substantially" the same or equal.

[0150] Two surfaces may be considered coplanar or substantially coplanar if the displacement between them is no greater than 5 μm, no greater than 2 μm, no greater than 1 μm, or no greater than 0.5 μm.

[0151] As used herein, the singular terms "a," "an," and "the" may include plural referents unless the context clearly dictates otherwise.

[0152] As used herein, the term “distance between A and B” may refer to the length from an edge of A to an edge of B or the length from a center of A to a center of B.

[0153] As used herein, the terms "conductive," "electrically conductive," and "conductivity" refer to the ability to carry an electric current. Conductive materials are materials that present little or no resistance to the flow of electric current. One unit of measurement for conductivity is Siemens per meter (S / m). Typically, a conductive material is one that has a conductivity greater than about 10 4 S / m, for example at least 10 5S / m or at least 10 6 S / m of a material. The conductivity of a material sometimes varies with temperature. Unless otherwise specified, the conductivity of a material is measured at room temperature.

[0154] In addition, amounts, ratios and other numerical values ​​are sometimes presented herein in a range format. It should be understood that such a range format is used for the sake of convenience and brevity, and should be flexibly construed to include not only the values ​​explicitly specified as the limits of the range, but also all individual values ​​or sub-ranges encompassed within the range, as if each value and sub-range were explicitly specified.

[0155] Although the present disclosure has been described and illustrated with reference to the specific embodiments of the present disclosure, these descriptions and illustrations are not restrictive. It should be understood by those skilled in the art that various changes may be made and equivalents may be replaced without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not necessarily be drawn to scale. Due to manufacturing processes and tolerances, there may be differences between the process reproduction in the present disclosure and the actual equipment. There may be other embodiments that are not specifically described in the present disclosure. The description and drawings should be regarded as illustrative rather than restrictive. Modifications may be made to make specific situations, materials, material compositions, methods or processes suitable for the goals, spirit and scope of the present disclosure. All such modifications are deemed to be included within the scope of the appended claims. Although the disclosed method has been described herein with reference to specific operations performed in a specific order, it should be understood that these operations may be combined, subdivided or reordered to form equivalent methods without departing from the teachings of the present disclosure. Therefore, unless specifically indicated herein, the order and grouping of operations are not limitations of the present disclosure.

Claims

1. An electronic device, comprising: substrate; an electronic component disposed below the substrate; A circuit structure disposed under the substrate; and A shielding layer is disposed under the substrate and covers the electronic component and is connected to the circuit structure, wherein the circuit structure and the shielding layer are collectively configured to shield the electronic component from electromagnetic interference. 2 . The electronic device according to claim 1 , wherein the circuit structure comprises a first element and a second element disposed between the first element and the electronic component, and wherein the second element is connected to the shielding layer. 3 . The electronic device according to claim 2 , wherein the first element and the second element are configured to transmit different electrical signals, and the second element is a ground element. 4 . The electronic device of claim 2 , wherein the electronic component has four sides, and the second element is disposed adjacent to at least two sides of the electronic component. The electronic device according to claim 2 , wherein the second element comprises a plurality of conductive vias spaced apart from each other.

6. The electronic device according to claim 1, further comprising: An encapsulation layer encapsulates the electronic component and the circuit structure, wherein the circuit structure comprises a first terminal connected to the shielding layer and exposed by the encapsulation layer. The electronic device of claim 6 , wherein the encapsulation layer defines a first recess exposing the first terminal. The electronic device according to claim 7 , wherein the first recess is recessed from a first lower surface of the encapsulation layer. 9 . The electronic device according to claim 7 , wherein in a cross-sectional view, the shielding layer includes a first portion disposed on a first side surface of the first recess. 10 . The electronic device according to claim 9 , wherein in the cross-sectional view, the shielding layer includes a second portion disposed on a second side surface of the first recess, the second side surface being opposite to the first side surface. 11 . The electronic device of claim 9 , wherein in the cross-sectional view, the shielding layer includes a second portion disposed on a second lower surface of the encapsulation layer and spaced apart from the first portion. 12 . The electronic device of claim 9 , wherein the shielding layer comprises a second portion disposed on the first lower surface of the encapsulation layer, wherein a thickness of the second portion is greater than a thickness of the first portion.

13. The electronic device according to claim 7, further comprising: Electrical connectors, The encapsulation layer defines a second recess exposing a second terminal of the circuit structure, and the electrical connector is at least partially disposed in the second recess and is spaced apart from the shielding layer.

14. The electronic device according to claim 1, further comprising: a plurality of first welding elements disposed on the upper surface of the circuit structure; and A plurality of second welding elements are disposed on the lower surface of the circuit structure, wherein in a cross-sectional view, the number of the plurality of first welding elements is different from the number of the plurality of second welding elements.

15. An electronic device comprising: Electronic components; a circuit structure adjacent to the electronic component, wherein the circuit structure has a bottom surface configured to provide external connections to the electronic device; an encapsulation layer encapsulating the electronic component; and The electromagnetic interference shielding layer is disposed on the lower surface of the encapsulation layer and is at least partially connected to the bottom surface of the circuit structure. 16 . The electronic device of claim 15 , wherein a portion of the electromagnetic interference shielding layer is disposed below the circuit structure, and the circuit structure is spaced apart from the electromagnetic interference shielding layer by the encapsulation layer. 17 . The electronic device according to claim 15 , wherein the circuit structure comprises a dielectric layer, and a height of a lower surface of the EMI shielding layer is higher than a height of a lower surface of the dielectric layer.

18. An electronic device comprising: Electronic components; a circuit structure adjacent to the electronic component and including a conductive pad; an encapsulation layer encapsulating the electronic component, wherein the encapsulation layer and the circuit structure jointly define a step; and A shielding layer covers the electronic component, wherein a portion of the shielding layer is disposed on the step and connected to the conductive pad. 19 . The electronic device of claim 18 , wherein the step exposes a portion of the conductive pad of the circuit structure, and the portion of the shielding layer is conformal to the conductive pad.

20. The electronic device of claim 18, wherein the step exposes a dielectric layer of the circuit structure, and the portion of the shielding layer contacts the dielectric layer.

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