Storage unit capable of realizing reconfigurable in-memory logical operation and control method of storage unit

Abstract

The invention provides a storage unit capable of realizing reconfigurable in-memory logic operation and a control method of the storage unit. The memory cell includes: a first magnetic tunnel junction, a second magnetic tunnel junction, and a third magnetic tunnel junction; the first magnetic tunnel junction comprises a first free layer, a first tunneling layer, a first reference layer and a first pinning layer which are sequentially stacked from bottom to top; the second magnetic tunnel junction comprises a second pinning layer, a second reference layer, a second tunneling layer and a second free layer which are sequentially stacked from bottom to top; and the third magnetic tunnel junction comprises a third reference layer, a third tunneling layer and a third free layer which are sequentially stacked from bottom to top. According to the invention, a new memory cell structure is designed, three discrete magnetic tunnel junctions in the prior art are arranged in a device area through a stacking design, additional transistor design is not needed, reconfigurable in-memory arithmetic logic is realized through adjustment of the input voltage, and the memory cell structure is simple in structure and high in reliability. The area overhead of the calculation circuit in the memory is effectively reduced, and meanwhile, the power consumption is reduced.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor storage technology, and in particular to a storage unit for realizing reconfigurable in-memory logic operation and a control method thereof, a magnetic random access memory, and an electronic device. Background Art

[0002] The von Neumann computing architecture relies on a bus for communication between the processor and memory. When faced with data-intensive applications, it faces the bottleneck of the "storage wall". The Process in Memory architecture can significantly improve data processing efficiency and reduce the required computing resources. It has good application prospects in image processing, edge computing and other fields.

[0003] The existing in-memory computing architecture CRAM electrically connects three magnetic tunnel junctions (MTJs), where two MTJs are used as logic inputs and one MTJ is used as logic output to form a reconfigurable in-memory logic operation unit. Figure 1 As shown, by changing the operating voltage, the AND / OR logic can be reconstructed. This structure can perform in-memory logic operations in parallel at high speed, but it requires the participation of three MTJs, and in terms of circuit design, it requires at least three additional transistors, as well as more complex routing, which brings about a large area overhead. Therefore, how to achieve higher throughput in-memory computing with less area and lower power consumption is an urgent problem to be solved. Summary of the invention

[0004] The purpose of the embodiments of the present disclosure is to provide a storage unit and a control method thereof, a magnetic random access memory, and an electronic device that implement reconfigurable in-memory logic operations, so as to solve the problem of large area overhead of in-memory computing architecture in the prior art.

[0005] The embodiments of the present disclosure adopt the following technical scheme: a storage unit for realizing reconfigurable in-memory logic operation, comprising: a first magnetic tunnel junction, a second magnetic tunnel junction and a third magnetic tunnel junction stacked in sequence from top to bottom; wherein the first magnetic tunnel junction comprises: a first free layer, a first tunneling layer, a first reference layer and a first pinned layer stacked in sequence from bottom to top; the second magnetic tunnel junction comprises: a second pinned layer, a second reference layer, a second tunneling layer and a second free layer stacked in sequence from bottom to top; the third magnetic tunnel junction comprises: a third reference layer, a third tunneling layer and a third free layer stacked in sequence from bottom to top.

[0006] In some embodiments, the thickness of the third tunnel layer is greater than the thickness of the first tunnel layer and the thickness of the second tunnel layer, so that the resistance of the third magnetic tunnel junction high resistance state is greater than the resistance of the first magnetic tunnel junction high resistance state and the resistance of the second magnetic tunnel junction high resistance state.

[0007] In some embodiments, a first electrode layer is also included between the third free layer and the second pinned layer, so that a third write current that drives the third magnetic tunnel junction resistance state flip is smaller than a first write current that drives the first magnetic tunnel junction resistance state flip and a second write current that drives the second magnetic tunnel junction resistance state flip.

[0008] In some embodiments, a second electrode layer is further included between the first free layer and the second free layer.

[0009] The disclosed embodiment also provides a control method for the above-mentioned storage unit, including: initializing the resistance state of each magnetic tunnel junction in the storage unit so that the resistance state of each magnetic tunnel junction is a low resistance state; writing a first voltage to the first input terminal of the storage unit according to a first input value of a logic operation, and grounding the second input terminal, so that the resistance state of the first magnetic tunnel junction represents the first input value, wherein the first input terminal is connected to a first pinned layer, and the second input terminal is connected to a third reference layer; writing a second voltage to the second input terminal according to a second input value of the logic operation, and grounding the first input terminal, so that the resistance state of the second magnetic tunnel junction represents the second input value; writing a third voltage to the second input terminal, and grounding the first input terminal, and collecting the resistance value of the third magnetic tunnel junction as the output result of the logic operation.

[0010] In some embodiments, when the input value of the logic operation is 1, a voltage is written to the input terminal to drive the first magnetic tunnel junction or the second magnetic tunnel junction to flip from a low resistance state to a high resistance state; when the input value of the logic operation is 0, zero voltage is written to the input terminal.

[0011] In some embodiments, the storage unit is used to implement at least a NOR operation and a NAND operation.

[0012] In some embodiments, a voltage value of the third voltage input to the storage unit when implementing an OR operation is greater than a voltage value of the third voltage input to the storage unit when implementing an AND operation.

[0013] The embodiment of the present disclosure also provides a magnetic random access memory, which at least includes: storage units as described above arranged in an array.

[0014] The disclosed embodiment also provides an electronic device, which at least includes the above-mentioned magnetic random access memory.

[0015] The beneficial effects of the embodiments of the present disclosure are: a new storage cell structure is designed, and three discrete magnetic tunnel junctions in the prior art are arranged within a device area through a stacked design, and no additional transistor design is required. Reconfigurable in-memory operation logic is achieved by adjusting the input voltage, which effectively reduces the area overhead of the in-memory computing circuit and achieves a reduction in power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate one or more embodiments of this specification or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this specification. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0017] Figure 1 A working principle diagram of the CRAM architecture in the prior art to realize in-memory logic operations;

[0018] Figure 2 It is a schematic diagram of the structure of a storage unit for implementing reconfigurable in-memory logic operation in the first embodiment of the present disclosure;

[0019] Figure 3 is a flow chart of a control method of a storage unit in a second embodiment of the present disclosure;

[0020] Figure 4 A schematic diagram of the change of magnetization direction of each level when the storage unit performs a NOR operation in the second embodiment of the present disclosure;

[0021] Figure 5 FIG. 1 is a schematic diagram of the change in magnetization direction of each level of the memory cell when performing a NAND operation in the second embodiment of the present disclosure. DETAILED DESCRIPTION

[0022] In order to enable those skilled in the art to better understand the technical solutions in one or more embodiments of this specification, the following will be combined with the drawings in one or more embodiments of this specification to clearly and completely describe the technical solutions in one or more embodiments of this specification. Obviously, the described embodiments are only part of the embodiments of this specification, not all of the embodiments. Based on one or more embodiments of this specification, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of this document.

[0023] The von Neumann computing architecture relies on a bus for communication between the processor and memory. When faced with data-intensive applications, it faces the bottleneck of the "storage wall". The Process in Memory architecture can significantly improve data processing efficiency and reduce the required computing resources. It has good application prospects in image processing, edge computing and other fields.

[0024] The existing in-memory computing architecture CRAM electrically connects three magnetic tunnel junctions (MTJs), where two MTJs are used as logic inputs and one MTJ is used as logic output to form a reconfigurable in-memory logic operation unit. Figure 1 As shown, by changing the operating voltage, the AND / OR logic can be reconstructed. This structure can perform in-memory logic operations in parallel at high speed, but it requires the participation of three MTJs, and in terms of circuit design, it requires at least three additional transistors, as well as more complex routing, which brings about a large area overhead. Therefore, how to achieve higher throughput in-memory computing with less area and lower power consumption is an urgent problem to be solved.

[0025] In order to solve the above problems, the first embodiment of the present disclosure provides a storage unit for implementing reconfigurable in-memory logic operations, and its structural diagram is shown in FIG. Figure 2 As shown, it at least includes a first magnetic tunnel junction 10, a second magnetic tunnel junction 20 and a third magnetic tunnel junction 30 stacked in sequence from top to bottom. In actual implementation, the first magnetic tunnel junction 10 and the second magnetic tunnel junction 20 are used as inputs of logic operations, and the resistance state of the third magnetic tunnel junction 30 is used as the output result of the logic operation.

[0026] Specifically, the first magnetic tunnel junction 10 at least includes a first free layer 11, a first tunnel layer 12, a first reference layer 13 and a first pinned layer 14 stacked in sequence from bottom to top; the second magnetic tunnel junction 20 at least includes a second pinned layer 24, a second reference layer 23, a second tunnel layer 22 and a second free layer 21 stacked in sequence from bottom to top; the third magnetic tunnel junction 30 at least includes a third reference layer 33, a third tunnel layer 32 and a third free layer 31 stacked in sequence from bottom to top, and all magnetic tunnel junctions are stacked in a vertical direction, so that the chip area actually occupied by the three magnetic tunnel junctions is only one device area. At the same time, there is no need to set up a transistor matching each magnetic tunnel junction, and the logic operation control and reconstruction of the storage unit of this embodiment can be achieved only by configuring a single transistor in a conventional magnetic random access memory.

[0027] for Figure 2The specific implementation materials of each level can be based on the setting of the corresponding level materials in the conventional magnetic tunnel junction, such as using magnesium oxide MgO as the tunneling layer material, using cobalt iron boron CoFeB as the free layer and reference layer material, using cobalt / platinum multilayer film [Co / Pt]n as the pinning layer material, or selecting other materials for the corresponding level preparation according to the device performance and process requirements, which is not specifically limited in this embodiment. In addition, Figure 2 The sizes of each level are for reference only and do not represent the sizes of the levels in actual devices or the size relationships between the sizes.

[0028] In this embodiment, when preparing the third tunnel layer 32, the thickness of the third tunnel layer 32 should be set to be greater than the thickness of the first tunnel layer 12 and the thickness of the second tunnel layer 22, so that the resistance value of the high resistance state of the third magnetic tunnel junction 30 is greater than the resistance value of the high resistance state of the first magnetic tunnel junction 10 and the resistance value of the high resistance state of the second magnetic tunnel junction 20. In this way, the resistance state change of the third magnetic tunnel junction 30 as a logic output result can be more easily collected to improve the accuracy of the logic output.

[0029] In some embodiments, a first electrode layer 41 may also be included between the third free layer 31 and the second pinned layer 24, which is used to provide additional spin current for the flipping of the third free layer 31 when a voltage is applied to the storage unit, so that the third write current that drives the resistance state flipping of the third magnetic tunnel junction 30 is smaller than the first write current that drives the resistance state flipping of the first magnetic tunnel junction 10 and the second write current that drives the resistance state flipping of the second magnetic tunnel junction 20, so as to meet the independent control of the first magnetic tunnel junction 10, the second magnetic tunnel junction 20 and the third magnetic tunnel junction 30 when performing logic operations.

[0030] In addition, a second electrode layer 42 may be provided between the first free layer 11 and the second free layer 12 to realize electrical connection between the first magnetic tunnel junction 10 and the second magnetic tunnel junction 20. Both the first electrode layer 41 and the second electrode layer 42 may be realized by using metal tungsten W, and the layer thickness of the two is set according to the electrical requirements of the storage unit, and generally, the thickness thereof should be greater than the thickness of the free layer of each magnetic tunnel junction.

[0031] This embodiment designs a new storage cell structure, which arranges three discrete magnetic tunnel junctions within a device area through a stacked design, and does not require additional transistor design. Reconfigurable in-memory operation logic is achieved by adjusting the input voltage, which effectively reduces the area overhead of the in-memory computing circuit and reduces power consumption.

[0032] The second embodiment of the present disclosure provides a control method for the storage unit provided in the first embodiment, which is mainly used to control the storage unit to implement reconfigurable logic operations. The flow chart is as follows: Figure 3 As shown, it mainly includes the following steps:

[0033] S10, initializing the resistance state of each magnetic tunnel junction in the storage unit so that the resistance state of each magnetic tunnel junction is a low resistance state;

[0034] S20, writing a first voltage to a first input terminal of a storage unit according to a first input value of a logic operation, and grounding a second input terminal, so that a resistance state of a first magnetic tunnel junction represents the first input value;

[0035] S30, writing a second voltage to the second input terminal according to a second input value of the logic operation, and grounding the first input terminal, so that the resistance state of the second magnetic tunnel junction represents the second input value;

[0036] S40, writing a third voltage to the second input terminal, grounding the first input terminal, and collecting the resistance value of the third magnetic tunnel junction as an output result of the logic operation.

[0037] In this embodiment, the first input terminal IN1 is connected to the first pinned layer, and the second input terminal IN2 is connected to the third reference layer. By changing the voltage magnitude and direction to the first input terminal and the second input terminal, the input data writing, logic operation control and operation type reconstruction are realized. When actually writing, if the value to be input for the current logic operation is 1, a voltage (i.e., the first voltage and the second voltage) that can drive the first magnetic tunnel junction or the second magnetic tunnel junction to flip from a low resistance state to a high resistance state is written to the input terminal, so that the first magnetic tunnel junction or the second magnetic tunnel junction presents a high resistance state, which is used to represent the value 1; if the value to be input for the current logic operation is 0, a zero voltage can be written to the input terminal, and at this time, there is no voltage input to the first magnetic tunnel junction or the second magnetic tunnel junction, and its resistance state remains unchanged at a low resistance state, which is used to represent the value 0. It should be noted that when writing the value 1 to the second magnetic tunnel junction, it is necessary to ensure that no matter whether the current resistance state of the first magnetic tunnel junction is a high resistance state or a low resistance state, the application of the second voltage can flip the magnetization direction of the second free layer of the second magnetic tunnel junction, so that the second magnetic tunnel junction presents a high resistance state, while not affecting the resistance state change of the first magnetic tunnel junction.

[0038] The storage unit of this embodiment is used to implement at least NOR operation and NAND operation. Figure 4 and Figure 5 The schematic diagram of the magnetization direction of the free layer of each magnetic tunnel junction is shown, which explains the steps of implementing the NOR operation and the NAND operation of the storage unit. It should be noted that Figure 4 and Figure 5 In the figure, only the magnetization directions of the reference layer and the free layer of each magnetic tunnel junction are shown, and the direction of voltage application is indicated by the dotted arrow.

[0039] Figure 4 The figure shows the change of magnetization direction of each level when the memory cell performs NOR operation. Figure 4(a) shows the change of magnetization direction when both logic inputs are 1. First, all layers are initialized so that the magnetization directions of all free layers are the same as the reference layer, and the resistance state of each magnetic tunnel junction is low resistance. Then, the first voltage V1 is written to IN1, and IN2 is grounded (gnd). At this time, the magnetization direction of the free layer 1 of the first magnetic tunnel junction is reversed, and the first magnetic tunnel junction is in a high resistance state. Then, the second voltage V2 is written to IN2, and IN1 is grounded. At this time, the magnetization direction of the free layer 2 of the second magnetic tunnel junction is reversed, and the second magnetic tunnel junction is also in a high resistance state. Finally, the third voltage V3 is written to IN2. At this time, since the first magnetic tunnel junction and the second magnetic tunnel junction are both in a high resistance state, the current written in the storage unit is not enough to drive the free layer 3 of the third magnetic tunnel junction to flip, and the third magnetic tunnel junction still maintains a low resistance state, and the output result of the corresponding logic operation is 0.

[0040] Figure 4 (b) shows the change in magnetization direction when the first input value of the NOR logic operation is 0 and the second input value is 1. First, the magnetization direction of the free layer is initialized to be consistent with the reference layer, and the resistance state of each magnetic tunnel junction is low resistance. Then, since the first input value is 0, the first voltage V1 inputs zero voltage ( Figure 4 (b) Indicated by the dotted arrow when zero voltage is not applied), the magnetization direction of the free layer 1 is not reversed, and the resistance state of the first magnetic tunnel junction remains in a low resistance state; then the second voltage V2 is written to IN2, and IN1 is grounded. At this time, the magnetization direction of the free layer 2 of the second magnetic tunnel junction is reversed, and the second magnetic tunnel junction presents a high resistance state; finally, the third voltage V3 is written to IN2. At this time, since the first magnetic tunnel junction is in a low resistance state and the second magnetic tunnel junction is in a high resistance state, the current in the device is sufficient to drive the free layer 3 to flip, and the third magnetic tunnel junction becomes a high resistance state, and the output result of the corresponding logic operation is 1.

[0041] Similarly, Figure 4 (c) shows the change in magnetization direction when the first input value of the NOR logic operation is 1 and the second input value is 0. Figure 4 (b) Similarly, during logic operation, the first magnetic tunnel junction is in a high-resistance state, the second magnetic tunnel junction is in a low-resistance state, and the current in the device is sufficient to drive the free layer 3 to flip, and the third magnetic tunnel junction becomes a high-resistance state. The output result of the corresponding logic operation is 1. Figure 4 (d) shows the change in magnetization direction when both logic inputs in the NOR operation are 0. At this time, the first magnetic tunnel junction and the second magnetic tunnel junction are both in a low-resistance state, and the current in the device is large enough to drive the free layer 3 to flip, and the output result of the logic operation is 1.

[0042] It should be noted that when executing NOR logic, the voltage value of the third voltage should be guaranteed to satisfy the requirement that the magnetization direction of the free layer 3 can be driven to flip when at least one of the first magnetic tunnel junction and the second magnetic tunnel junction is in a low resistance state. The specific value is set according to the high resistance value of the first magnetic tunnel junction and the second magnetic tunnel junction and the electrical characteristics of the third magnetic tunnel junction. This embodiment does not limit a specific value. When executing NAND logic, the third voltage can be adjusted to satisfy the requirement that the magnetization direction of the free layer 3 can be driven to flip when both the first magnetic tunnel junction and the second magnetic tunnel junction are in a low resistance state. Therefore, the voltage value of the third voltage when executing NAND operation is less than the voltage value of the third voltage when executing NOR operation. However, no matter which logic operation is performed, the value of the third voltage should at least ensure that the free layer 3 can be driven to flip when both the first magnetic tunnel junction and the second magnetic tunnel junction are in a low resistance state.

[0043] Specifically, Figure 5 The figure shows the change of magnetization direction of each level of the memory cell when performing NAND operation. Figure 5 (a) shows the change of magnetization direction when both logic inputs are 1. First, all layers are initialized so that the magnetization directions of all free layers are the same as the reference layer, and the resistance state of each magnetic tunnel junction is low resistance. Then, the first voltage V1 is written to IN1, and IN2 is grounded. At this time, the magnetization direction of the free layer 1 of the first magnetic tunnel junction is reversed, and the first magnetic tunnel junction is in a high resistance state. Then, the second voltage V2 is written to IN2, and IN1 is grounded. At this time, the magnetization direction of the free layer 2 of the second magnetic tunnel junction is reversed, and the second magnetic tunnel junction is also in a high resistance state. Finally, the third voltage V3 is written to IN2. At this time, since the first magnetic tunnel junction and the second magnetic tunnel junction are both in a high resistance state, the current written in the storage unit is not enough to drive the free layer 3 of the third magnetic tunnel junction to flip, and the third magnetic tunnel junction still maintains a low resistance state, and the output result of the corresponding logic operation is 0.

[0044] Figure 5 (b) shows the change in magnetization direction when the first input value of the NAND logic operation is 0 and the second input value is 1. First, the magnetization direction of the free layer is initialized to be consistent with the reference layer, and the resistance state of each magnetic tunnel junction is low resistance. Then, because the first input value is 0, the first voltage V1 inputs zero voltage, the magnetization direction of the free layer 1 is not reversed, and the resistance state of the first magnetic tunnel junction remains in a low resistance state. Then, the second voltage V2 is written to IN2, and IN1 is grounded. At this time, the magnetization direction of the free layer 2 of the second magnetic tunnel junction is reversed, and the second magnetic tunnel junction presents a high resistance state. Finally, the third voltage V3 is written to IN2. At this time, although the first magnetic tunnel junction is in a low resistance state, the second magnetic tunnel junction is in a high resistance state. The current in the device is not sufficient to drive the free layer 3 to flip, so the third magnetic tunnel junction remains in a low resistance state, and the output result of the corresponding logic operation is 0.

[0045] Similarly, Figure 5 (c) shows the change in magnetization direction when the first input value of the NAND logic operation is 1 and the second input value is 0. Figure 5 (b) Similarly, during the logic operation, the first magnetic tunnel junction is in a high-resistance state, the second magnetic tunnel junction is in a low-resistance state, and the current in the device is also insufficient to drive the free layer 3 to flip. The third magnetic tunnel junction remains in a low-resistance state, and the output result of the corresponding logic operation is 0. Figure 5 (d) shows the change in magnetization direction when both logic inputs in the NAND operation are 0. At this time, the first magnetic tunnel junction and the second magnetic tunnel junction are both in a low-resistance state, and the current in the device is large enough to drive the free layer 3 to flip, and the output result of the logic operation is 1.

[0046] In some embodiments, an inverter may be provided to invert the output result after reading the output result corresponding to the resistance state of the third magnetic tunnel junction, thereby realizing AND logic and OR logic operations. The circuit design for reading the resistance state of the third magnetic tunnel junction is not provided in this embodiment, and it can be implemented in conjunction with conventional read-write transistors of the memory, and will not be described in detail here.

[0047] This embodiment designs a new storage cell structure, which arranges three discrete magnetic tunnel junctions within a device area through a stacked design, and does not require additional transistor design. Reconfigurable in-memory operation logic is achieved by adjusting the input voltage, which effectively reduces the area overhead of the in-memory computing circuit and reduces power consumption.

[0048] Based on the same inventive concept, the third embodiment of the present disclosure provides a magnetic random access memory, which at least includes storage cells arranged in an array as provided in the first embodiment. Combined with the stacking structure of the storage cells, more storage cells can be configured without changing the memory area, thereby achieving higher throughput in-memory logical operations. At the same time, no additional transistor design is required, and power consumption is reduced with the same performance.

[0049] Based on the same inventive concept, a fourth embodiment of the present disclosure provides an electronic device, which at least includes the magnetic random access memory provided by the third embodiment of the present disclosure.

[0050] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A storage unit for implementing reconfigurable in-memory logic operations, characterized in that: include: A first magnetic tunnel junction, a second magnetic tunnel junction and a third magnetic tunnel junction are stacked in sequence from top to bottom; wherein, The first magnetic tunnel junction includes: a first free layer, a first tunnel layer, a first reference layer and a first pinned layer stacked in sequence from bottom to top; The second magnetic tunnel junction includes: a second pinned layer, a second reference layer, a second tunneling layer and a second free layer stacked in sequence from bottom to top; The third magnetic tunnel junction includes: a third reference layer, a third tunnel layer and a third free layer stacked in sequence from bottom to top.

2. The storage unit according to claim 1, characterized in that The thickness of the third tunneling layer is greater than the thickness of the first tunneling layer and the thickness of the second tunneling layer, so that the resistance value of the third magnetic tunnel junction high resistance state is greater than the resistance value of the first magnetic tunnel junction high resistance state and the resistance value of the second magnetic tunnel junction high resistance state.

3. The storage unit according to claim 1, characterized in that A first electrode layer is also included between the third free layer and the second pinned layer, so that a third write current driving the third magnetic tunnel junction resistance state flip is smaller than a first write current driving the first magnetic tunnel junction resistance state flip and a second write current driving the second magnetic tunnel junction resistance state flip.

4. The storage unit according to any one of claims 1 to 3, characterized in that: A second electrode layer is further included between the first free layer and the second free layer.

5. A method for controlling a storage unit according to any one of claims 1 to 4, characterized in that: include: Initializing the resistance state of each magnetic tunnel junction in the storage unit so that the resistance state of each magnetic tunnel junction is a low resistance state; According to a first input value of the logic operation, a first voltage is written to a first input terminal of the storage unit, and a second input terminal is grounded, so that the resistance state of the first magnetic tunnel junction represents the first input value, wherein the first input terminal is connected to a first pinned layer, and the second input terminal is connected to a third reference layer; According to a second input value of the logic operation, a second voltage is written to the second input terminal, and the first input terminal is grounded, so that the resistance state of the second magnetic tunnel junction represents the second input value; A third voltage is written to the second input terminal, the first input terminal is grounded, and the resistance value of the third magnetic tunnel junction is collected as an output result of the logic operation.

6. The control method according to claim 5, characterized in that: When the input value of the logic operation is 1, a voltage is written to the input end to drive the first magnetic tunnel junction or the second magnetic tunnel junction to flip from a low resistance state to a high resistance state; when the input value of the logic operation is 0, zero voltage is written to the input end.

7. The control method according to claim 5, characterized in that: The storage unit is used to implement at least a NOR operation and a NAND operation.

8. The control method according to claim 7, characterized in that: The voltage value of the third voltage input to the storage unit when implementing an OR operation is greater than the voltage value of the third voltage input to the storage unit when implementing an AND operation.

9. A magnetic random access memory, characterized in that: At least: The memory cells according to any one of claims 1 to 4 are arranged in an array.

10. An electronic device, characterized in that: At least includes the magnetic random access memory as described in claim 9.

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