Heterogeneous integrated cascode type power device and preparation method thereof
Through the heterogeneous integrated cascode power device structure, the problem of high on-resistance of SiC MOSFET is solved, lower on-resistance and higher withstand voltage characteristics are achieved, and the device size is shortened.
Patent Information
- Application Number
- CN202411222002.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-02
- Publication Date
- 2025-05-16
AI Technical Summary
The on-resistance in existing planar SiC MOSFET devices is high, which is difficult to effectively reduce.
It adopts a heterogeneous integrated cascode power device structure, including substrate, epitaxial layer, deep P region, JFET region, N+ region, PN region, gate dielectric layer and gate electrode, and is prepared through process steps such as ion implantation and high temperature activation.
It effectively reduces the SiC on-resistance, so that the device has a lower on-resistance than SiC MOSFETs, and has high-voltage resistance that is comparable to SiC, and shortens the size of the device period structure.
Smart Images
Figure CN120018532A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a heterogeneously integrated cascode power device and a preparation method thereof. Background Art
[0002] Silicon carbide (SiC) material is a typical representative of the third generation of wide bandgap semiconductor materials. It has a wide bandgap width of 3.26eV, which is three times higher than that of silicon (Si). Therefore, SiC has a higher breakdown electric field strength. Under the same withstand voltage, the thickness of the withstand voltage layer required by the device is thinner, so the chip volume can be made smaller, which is more suitable for the production of high-power devices.
[0003] At present, the current bottleneck of planar gate SiC vertical structure metal oxide semiconductor field effect transistor (MOSFET) is to reduce its on-resistance, which is mainly composed of drift region resistance, JFET resistance and channel resistance. The drift region resistance is the pressure-bearing layer resistance, which is basically fixed, while the JFET resistance accounts for a relatively small proportion, so the main way to reduce the on-resistance is to reduce the on-channel resistance.
[0004] In 2016, Jin Wei from HKUST proposed using GaN's two-dimensional electron gas as the channel layer and heterogeneously integrating it in SiC MOSFET transistors, which can effectively reduce the on-resistance of SiC. However, it is difficult to grow GaN on SiC and the process is relatively difficult. In 2017, Baoxing Duan proposed a heterogeneously integrated Si / SiC MOSFET structure, which can improve the withstand voltage and reduce the on-resistance compared to Si MOSFET, but there will be a potential barrier when the on-current flows from Si to SiC, and it still has a high on-resistance.
[0005] In view of the current development status of the prior art, the art is currently in urgent need of seeking an effective way to overcome the defect of low on-resistance in existing planar SiCMOSFET devices. The present invention provides a new heterogeneously integrated cascode power device and a preparation method thereof. Summary of the invention
[0006] Based on the above description, the present invention provides a heterogeneously integrated cascode power device and a method for preparing the same to solve the problem of low on-resistance in existing planar SiC MOSFET devices.
[0007] The technical solution of the present invention to solve the above technical problems is as follows:
[0008] In a first aspect, the present invention provides a heterogeneously integrated cascode power device, comprising: a substrate, an epitaxial layer, a first deep P region, a second deep P region, a JFET region, a first N+ region, a second N+ region, a silicon layer, a first PN region, a second PN region, a gate dielectric layer, and a gate;
[0009] The epitaxial layer, the silicon layer, the gate dielectric layer, and the gate are sequentially stacked on the substrate;
[0010] The first deep P region, the second deep P region, the JFET region and the first N+ region are formed on a side of the epitaxial layer away from the substrate, wherein the first deep P region and the second deep P region are arranged at two side regions of the epitaxial layer, the JFET region is located between the first deep P region and the second deep P region, and the first N+ region is formed in a partial region of the JFET region and is arranged close to the silicon layer;
[0011] The first PN region and the second PN region are formed in the left and right side regions of the silicon layer, corresponding to the positions of the first deep P region and the second deep P region respectively; the second N+ region is formed in a partial region of the silicon layer and is arranged close to the gate dielectric layer.
[0012] Based on the above technical solution, the present invention can also be improved as follows.
[0013] Furthermore, the doping concentration of the first deep P region and the second deep P region is 1E16cm -3 ~1E20 cm -3 , the depth is 0.5μm~5μm.
[0014] Furthermore, the doping ion concentration of the JFET region is 5E15 cm -3 ~1E18 cm -3 The ion implantation depth is 0.1 μm to 2 μm deeper than the first deep P region.
[0015] Furthermore, the N+ region is a high-concentration N+ region with a doping ion concentration of 1E18 cm -3 ~1E21cm -3 The ion implantation depth is 0.1μm to 2μm.
[0016] Furthermore, the first PN region and the second PN region have the same PN region structure, and the PN region structure includes an N+ type region and a P type region, and the N+ type region is arranged in the upper region of the P type region and close to the outer side.
[0017] Furthermore, the doping concentration of the N+ region is 1E17 cm -3 ~1E21 cm-3 The doping concentration of the P-type region is 1E16 cm -3 ~1E18 cm -3 .
[0018] Furthermore, the heterogeneously integrated cascode power device further includes a drain;
[0019] The drain is formed at the bottom of the substrate, on the gate dielectric layer and in the silicon layer; the drain on the gate dielectric layer is connected to the first N+ region in ohmic contact; the drain in the silicon layer is connected to the second N+ region in ohmic contact.
[0020] Furthermore, the heterogeneously integrated cascode power device further includes a source;
[0021] The two source electrodes are respectively formed on the two outer sides of the silicon layer and the gate dielectric layer, and the gate is arranged between the source electrode and the drain electrode on either side; the source electrode located on the dielectric layer outside the gate electrode is respectively connected to the N+ type region in the first PN region and the second PN region by ohmic contact; the source electrode located in the silicon layer is respectively connected to the first deep P region and the second deep P region by ohmic contact.
[0022] Further, the substrate and the epitaxial layer are SiC;
[0023] The gate dielectric layer is SiO2, Al2O3 or Hf2O3;
[0024] The first PN region and the second PN region are obtained by P-type doping and N-type doping of Si.
[0025] In a second aspect, the present invention further provides a method for preparing a heterogeneously integrated cascode power device as described in the first aspect, comprising:
[0026] growing an epitaxial layer on a substrate;
[0027] Injecting a first deep P region, a second deep P region, a JFET region and an N+ region into the epitaxial layer by selective ion implantation, activating at high temperature, and protecting the surface with a carbon film;
[0028] Depositing a layer of polysilicon on the surface of the implanted epitaxial layer to obtain a silicon layer;
[0029] Performing N+ type and P type implantation on the silicon layer respectively, and annealing and activating, to obtain a first PN region and a second PN region;
[0030] Fabricate a gate dielectric layer on the surface of the polysilicon, and fabricate a gate on the surface of the gate dielectric layer;
[0031] Holes are dug on both sides of the gate to form a source electrode, metal is deposited at the bottom of the substrate and holes are dug on the gate dielectric layer and in the silicon layer to form a drain electrode, thus obtaining a heterogeneously integrated cascode power device.
[0032] Compared with the prior art, the technical solution of this application has the following beneficial technical effects:
[0033] The heterogeneously integrated cascode power device provided by the present invention is formed with a first deep P region, a second deep P region, a JFET region, a first N+ region, and a second N+ region, wherein the first deep P region and the second deep P region are arranged at two side regions of the epitaxial layer, the JFET region is located between the first deep P region and the second deep P region, the first N+ region is formed in a partial region of the JFET region and is arranged close to the epitaxial layer; the first PN region and the second PN region are formed at two side regions of the silicon layer, corresponding to the positions of the first deep P region and the second deep P region respectively. Compared with the prior art, it has the following beneficial effects:
[0034] (1) The present invention can effectively transfer electrons in Si to SiC, thereby reducing the on-resistance, so that the device can have a lower on-resistance than SiC MOSFET and have high-voltage resistance comparable to SiC.
[0035] (2) The present invention can effectively shorten the size of the device periodic structure. Specifically, from a process perspective, the existing SiC power device has the smallest unit cell size of a half-package structure, and the unit cell size includes three parts: the P+ region, the trench region, and the N+ region. Due to process limitations, the minimum unit cell size can be reduced to 2μm; while the unit cell size of the structure of the present invention includes the P+ region and the JFET region, wherein the JFET region includes the N+ region, and the TSV is connected above the N+ region to form an ohmic contact with the source. The 100nm Si layer thickness can realize the control of the device switch, and the Si TSV etching depth-to-width ratio can be achieved at 10:1, so the TSV width in Si can be 10nm, and the SiC JFET can reach 0.5μm while ensuring a small on-resistance. When the P+ region width is 1μm, a unit cell size of 1.5μm can be achieved, which is the current SiC power device with the smallest unit cell size. BRIEF DESCRIPTION OF THE DRAWINGS
[0036] Figure 1 A schematic diagram of the structure of a heterogeneously integrated cascode power device provided in Embodiment 1 of the present invention;
[0037] Figure 2 A schematic diagram of the preparation process of a heterogeneously integrated cascode power device provided in Example 2 of the present invention;
[0038] Figure 3A schematic structural diagram of a heterogeneously integrated cascode power device provided in Embodiment 3 of the present invention;
[0039] Figure 4 A schematic structural diagram of a heterogeneously integrated cascode power device provided in Embodiment 4 of the present invention;
[0040] In the accompanying drawings, the components represented by the reference numerals are listed as follows:
[0041] 1. Substrate;
[0042] 2. Epitaxial layer;
[0043] 3. The first deep P zone;
[0044] 4. The second deepest P zone;
[0045] 5. JFET region;
[0046] 6. The first N+ region;
[0047] 7. The second N+ area;
[0048] 8. Silicon layer;
[0049] 9. First PN region; 901. N+ type region; 902. P type region;
[0050] 10. Second PN zone;
[0051] 11. Gate dielectric layer;
[0052] 12. Gate;
[0053] 13. Source;
[0054] 14. Drain. DETAILED DESCRIPTION
[0055] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.
[0056] In the prior art, conventional heterogeneous integration applications in SiC MOSFET transistors include:
[0057] Method 1: GaN / SiC heterogeneous integrated HEMT high-voltage device
[0058] The device uses GaN epitaxially grown on SiC JFET to prepare GaN HEMT devices. P-GaN is used as the gate to control the conduction and blocking of the two-dimensional electron gas directly below, and then the two-dimensional electron gas is conducted to the JFET area of the SiC device below through the TSV structure to form a path. The advantage is that this structure can reduce the on-resistance to a certain extent, but its disadvantage is that heterogeneous epitaxial GaN on SiC is difficult and difficult to achieve in terms of process.
[0059] Method 2: Si / SiC heterogeneous integrated planar MOSFET devices
[0060] A layer of Si is epitaxially grown or bonded on SiC, and a MOSFET structure is prepared on the Si layer, in which the P region penetrates into the SiC. At the same time, the high channel mobility of Si and the voltage resistance characteristics of SiC are utilized to form a heterogeneous integrated MOSFET device with lower on-resistance than pure Si and higher voltage resistance than pure SiMOSFET. The disadvantage is that since the bandgap width of Si is lower than that of SiC, there will be a potential barrier when the conducting electrons in the device move from Si to SiC, resulting in a larger on-resistance than that in pure SiC MOSFET and relatively large switching losses.
[0061] The invention provides a novel heterogeneous integrated cascode type power device.
[0062] The following embodiments of the present invention are further described in detail in conjunction with the accompanying drawings and examples. The following examples are used to illustrate the present invention but cannot be used to limit the scope of the present invention.
[0063] Example 1
[0064] like Figure 1 As shown, this embodiment provides a heterogeneously integrated cascode power device, including: a substrate 1, an epitaxial layer 2, a first deep P region 3, a second deep P region 4, a JFET region 5, a first N+ region 6, a second N+ region 7, a silicon layer 8, a first PN region 9, a second PN region 10, a gate dielectric layer 11 and a gate 12.
[0065] The epitaxial layer 2 , the silicon layer 8 , the gate dielectric layer 11 , and the gate 12 are sequentially stacked on the substrate 1 .
[0066] Preferably, the substrate 1 is 4H-SiC, and the epitaxial layer 2 is obtained by epitaxially growing a low-concentration N-type SiC drift layer on the surface of 4H-SiC.
[0067] The thickness of the SiC epitaxial layer 2 is 8 μm to 40 μm, and the room temperature carrier concentration after nitrogen doping is 5E14 cm -3 ~5E16 cm -3 .
[0068] The gate dielectric layer 11 is SiO2, Al2O3 or Hf2O3, which is a gate oxide layer, which is prepared by injecting a doped Si surface into a dielectric layer, and has a thickness of 20nm to 200nm.
[0069] A first deep P region 3, a second deep P region 4, a JFET region 5 and a first N+ region 6 are formed on the side of the SiC epitaxial layer 2 away from the substrate 1, wherein the first deep P region 3 and the second deep P region 4 are spaced apart at two side regions of the epitaxial layer 2, the JFET region 5 is located between the first deep P region 3 and the second deep P region 4, and the first N+ region 6 is formed in a partial region of the JFET region 5 and is arranged close to the silicon layer 8.
[0070] Among them, the P type of the P region is implanted with Al atoms, and the N type of the N+ region can be implanted with N or P atoms. The doping concentration of the first deep P region 3 and the second deep P region 4 is 1E16 cm -3 ~1E20 cm -3 , the depth is 0.5μm~5μm.
[0071] In an optional embodiment, since the main voltage-resistant part of the device is borne by SiC, the P-type implantation of the epitaxial layer SiC can not only achieve deep P implantation through channel implantation, but also achieve deep P region doping through multiple epitaxial implantations or smartcut methods.
[0072] It should be noted that, in the present invention, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.
[0073] In a specific embodiment, the doping concentration of the first deep P region 3 and the second deep P region 4 is 1E16 cm -3 ~1E20 cm -3 , the depth is 0.5μm~5μm. The specific value is not limited and can be set according to actual needs.
[0074] The doping ion concentration of JFET region 5 is 5E15 cm -3 ~1E18 cm -3 The ion implantation depth is 0.1 μm to 2 μm deeper than the first deep P region. The specific value is not limited and can be set according to actual needs.
[0075] The N+ region is a high-concentration N+ region with a doping ion concentration of 1E18 cm -3 ~1E21 cm -3 , the ion implantation depth is 0.1 μm to 2 μm. The specific value is not limited and can be set according to actual needs.
[0076] Furthermore, the thickness of the silicon layer 8 is 0.1 μm to 5 μm, and the N-type doping concentration is 5E14 cm -3~1E18cm -3 There is no limit on the specific value, just set it according to actual needs.
[0077] The first PN region 9 and the second PN region 10 are formed in the left and right regions of the silicon layer, respectively corresponding to the positions of the first deep P region 3 and the second deep P region 4; the second N+ region 7 is formed in a partial region of the silicon layer 8 and is arranged close to the gate dielectric layer.
[0078] The first PN region 9 and the second PN region 10 have the same PN region structure, and the PN region structure includes an N+ type region and a P type region, and the N+ type region is arranged in the upper region of the P type region and close to the outer side.
[0079] Specifically, Figure 1 As shown, the N+ type region 901 in the first PN region 9 is arranged in the upper left region of the P type region 902, and the N+ type region in the second PN region 10 is arranged in the upper right region of the P type region. The first PN region 9 and the second PN region 10 are formed by ion implantation to achieve P and N+ type doping of Si, and the doping concentration of the N+ type region is 1E17 cm -3 ~1E21 cm -3 , the doping concentration of the P-type region is 1E16 cm -3 ~1E18 cm -3 After the implantation, rapid thermal annealing is performed to activate the implantation. The specific value is not limited and can be set according to actual needs.
[0080] In an optional embodiment, the heterogeneously integrated cascode power device further includes a drain 14; Figure 1 As shown, the drain 14 is formed at the bottom of the substrate 1, on the gate dielectric layer 11 and in the silicon layer 8. The drain 14 located on the gate dielectric layer 11 is connected to the first N+ region 6 in ohmic contact; the bottom of the drain 14 located in the silicon layer 8 is connected to the second N+ region 7 in ohmic contact.
[0081] In an optional embodiment, the heterogeneously integrated cascode power device further includes a source 13; Figure 1 As shown, two source electrodes 13 are respectively formed on the two outer sides of the silicon layer 8 and the gate dielectric layer 11; the gate electrode 12 is arranged on the gate dielectric layer 11; the source electrode 13 located on the gate dielectric layer 22 is respectively connected with the N+ type regions in the first PN region 9 and the second PN region 10 by ohmic contact; the source electrode 13 located in the silicon layer 8 is respectively connected with the first deep P region 3 and the second deep P region 4 by ohmic contact.
[0082] That is, two sets of source-drain-gate structures are formed, namely source 13-drain 14 (located in silicon layer 8 and gate dielectric layer 11)-gate 12; first N+ region 6 (equivalent to the source of silicon carbide)-drain 14 (located at the bottom of substrate 1)-first deep P region 3 / second deep P region 4 (equivalent to the gate of silicon carbide), wherein the drain 14 located in the silicon layer 8 and the first N+ region 6 (equivalent to the source) share an electrode, and the source 13 and the first deep P region 3 / second deep P region 4 (equivalent to the gate) share an electrode.
[0083] Among them, Figure 1 As shown, the source 13 on the left is connected to the N+ region in the second PN region 10 by ohmic contact; the source 13 on the right is connected to the N+ region 901 in the first PN region 9 by ohmic contact.
[0084] Compared with the prior art, the heterogeneously integrated cascode power device provided in this embodiment has the following beneficial effects:
[0085] (1) The present invention can effectively transfer electrons in Si to SiC, thereby reducing the on-resistance, so that the device can have a lower on-resistance than SiC MOSFET and have high-voltage resistance comparable to SiC.
[0086] (2) The present invention can effectively shorten the size of the device periodic structure. Specifically, from a process perspective, the existing SiC power device has the smallest unit cell size of a half-package structure, and the unit cell size includes three parts: the P+ region, the trench region, and the N+ region. Due to process limitations, the minimum unit cell size can be reduced to 2μm; while the unit cell size of the structure of the present invention includes the P+ region and the JFET region, wherein the JFET region includes the N+ region, and the TSV is connected above the N+ region to form an ohmic contact with the source. The 100nm Si layer thickness can realize the control of the device switch, and the Si TSV etching depth-to-width ratio can be achieved at 10:1, so the TSV width in Si can be 10nm, and the SiC JFET can reach 0.5μm while ensuring a small on-resistance. When the P+ region width is 1μm, a unit cell size of 1.5μm can be achieved, which is the current SiC power device with the smallest unit cell size.
[0087] Example 2
[0088] This embodiment provides a method for preparing the heterogeneous integrated cascode type power device provided in Embodiment 1, such as Figure 2 As shown, the operation is as follows:
[0089] Step S1: growing an epitaxial layer on a substrate
[0090] Specifically, a low-concentration N-type SiC drift layer is epitaxially grown on the surface of 4H-SiC. The thickness of the SiC epitaxial layer is 8 μm to 40 μm, and the room temperature carrier concentration after nitrogen doping is 5E14 cm -3 ~5E16cm -3 .
[0091] Step S2: Implantation to form the first deep P region, the second deep P region, the JFET region and the N+ region
[0092] Specifically, ion implantation is performed selectively on the SiC epitaxial layer into a deep P-type region, a JFET region, and a high-concentration N+ region, followed by high-temperature activation, and a carbon film is used for surface protection.
[0093] The ion implantation may be a combination of channel implantation and non-channel implantation. The ion doping concentration and thickness of each region are described in detail in the structural description of the heterogeneous integrated cascode type power device, which will not be described in detail here.
[0094] Step S3: Deposition of silicon layer
[0095] A layer of polysilicon is deposited on the surface of the implanted epitaxial layer to obtain a polysilicon layer.
[0096] In an optional embodiment, Si can be either polycrystalline silicon or single crystal silicon.
[0097] Polysilicon can be formed by depositing a layer of polysilicon using methods such as PECVD and ALD, or by depositing amorphous silicon and then annealing it to form polysilicon.
[0098] Single crystal silicon can be produced by direct epitaxy or by Smartcut process.
[0099] Step S4: Create PN area
[0100] The silicon layer is implanted with N+ type and P type respectively by using a mask, and then annealed for activation to obtain a first PN region and a second PN region.
[0101] Step S5: Making a gate dielectric layer
[0102] A dielectric layer is made on the surface of the doped Si as a gate oxide layer, namely, a gate dielectric layer, whose material is SiO2, Al2O3, Hf2O3, etc., and whose thickness is between 20nm and 200nm.
[0103] Step S6: Making the gate
[0104] Doped polysilicon is deposited on the surface of the gate dielectric layer to form a gate.
[0105] Step S7: Making source and drain
[0106] Holes are dug on both sides of the gate to form source electrodes, and two source electrodes are formed on the two outer sides of the silicon layer and the gate dielectric layer respectively; the source electrode located on the gate dielectric layer is connected to the N+ type region in the first PN region and the second PN region by ohmic contact respectively; the source electrode located in the silicon layer is connected to the first deep P region and the second deep P region by ohmic contact respectively.
[0107] Metal is deposited at the bottom of the substrate and holes are dug on the gate dielectric layer and in the silicon layer to form a drain. The drain is formed at the bottom of the substrate, on the gate dielectric layer and in the silicon layer. The drain on the gate dielectric layer is connected to the first N+ region by ohmic contact; the bottom of the drain in the silicon layer is connected to the second N+ region by ohmic contact.
[0108] Since the preparation method is used to prepare heterogeneously integrated cascode power devices, the beneficial effects of heterogeneously integrated cascode power devices are also applicable to the preparation method. The beneficial effects can be referred to the above effect description and will not be elaborated here.
[0109] Example 3
[0110] On the basis of the above-mentioned embodiment 1 and embodiment 2, since the main voltage-resistant part of the device is borne by SiC, this embodiment can also selectively implement the doping of the first deep P region and the second deep P region by multiple epitaxial implantation or bond stripping (smartcut) method, and the obtained structure is as follows: Figure 3 As shown, the device structure also has the characteristic of improving the conduction characteristics of the device. For the rest of the same structure and its preparation method, refer to the introduction of Example 1 and Example 2, which will not be repeated here.
[0111] Example 4
[0112] On the basis of the above-mentioned embodiment 1 and embodiment 2, this embodiment can also selectively select the SiC voltage-resistant layer part as a semi-super junction or super junction structure to replace the JFET structure, and the obtained structure is as follows: Figure 4 As shown, the device structure also has the characteristic of improving the conduction characteristics of the device. For the rest of the same structure and its preparation method, refer to the introduction of Example 1 and Example 2, which will not be repeated here.
[0113] In the description of this specification, the description with reference to the terms "specific example" or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the embodiments of the present invention. In this specification, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification and the features of different embodiments or examples, unless they are contradictory.
[0114] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims
1. A heterogeneously integrated cascode power device, characterized in that: include: Substrate, epitaxial layer, first deep P region, second deep P region, JFET region, first N+ region, second N+ region, silicon layer, first PN region, second PN region, gate dielectric layer and gate; The epitaxial layer, the silicon layer, the gate dielectric layer, and the gate are sequentially stacked on the substrate; The first deep P region, the second deep P region, the JFET region and the first N+ region are formed on a side of the epitaxial layer away from the substrate, wherein the first deep P region and the second deep P region are arranged at two side regions of the epitaxial layer, the JFET region is located between the first deep P region and the second deep P region, and the first N+ region is formed in a partial region of the JFET region and is arranged close to the silicon layer; The first PN region and the second PN region are formed in the left and right side regions of the silicon layer, corresponding to the positions of the first deep P region and the second deep P region respectively; the second N+ region is formed in a partial region of the silicon layer and is arranged close to the gate dielectric layer.
2. The heterogeneously integrated cascode power device according to claim 1, characterized in that: The doping concentration of the first deep P region and the second deep P region is 1E16 cm -3 ~1E20 cm -3 , the depth is 0.5μm~5μm.
3. The heterogeneously integrated cascode power device according to claim 2, characterized in that: The doping ion concentration of the JFET region is 5E15 cm -3 ~1E18 cm -3 The ion implantation depth is 0.1 μm to 2 μm deeper than the first deep P region.
4. The heterogeneously integrated cascode power device according to claim 3, characterized in that: The N+ region is a high-concentration N+ region with a doping ion concentration of 1E18 cm -3 ~1E21 cm -3 The ion implantation depth is 0.1μm to 2μm.
5. The heterogeneously integrated cascode power device according to claim 1, characterized in that: The first PN region and the second PN region have the same PN region structure, and the PN region structure includes an N+ type region and a P type region, and the N+ type region is arranged in the upper region of the P type region and close to the outer side.
6. The heterogeneously integrated cascode power device according to claim 5, characterized in that: The doping concentration of the N+ region is 1E17 cm -3 ~1E21 cm -3 The doping concentration of the P-type region is 1E16 cm -3 ~1E18 cm -3 .
7. The heterogeneously integrated cascode power device according to claim 5, characterized in that: The heterogeneously integrated cascode power device further includes a drain; The drain is formed at the bottom of the substrate, on the gate dielectric layer and in the silicon layer; The drain electrode located on the gate dielectric layer is connected to the first N+ region in ohmic contact; the drain electrode located in the silicon layer is connected to the second N+ region in ohmic contact.
8. The heterogeneously integrated cascode power device according to claim 7, characterized in that: The heterogeneously integrated cascode power device further includes a source electrode; The two source electrodes are formed on two outer sides of the silicon layer and the gate dielectric layer, respectively, and the gate electrode is provided between the source electrode and the drain electrode on either side; the source electrode located on the gate dielectric layer is connected to the N+ type region in the first PN region and the second PN region in ohmic contact, respectively; The source electrode located in the silicon layer is connected to the first deep P region and the second deep P region in ohmic contact, respectively.
9. The heterogeneously integrated cascode power device according to claim 8, characterized in that: The substrate and the epitaxial layer are SiC; The gate dielectric layer is SiO2, Al2O3 or Hf2O3; The first PN region and the second PN region are obtained by P-type doping and N-type doping of Si.
10. A method for preparing a heterogeneously integrated cascode power device as claimed in any one of claims 1 to 9, characterized in that: include: growing an epitaxial layer on a substrate; Selectively implanting a first deep P region, a second deep P region, a JFET region and an N+ region into the epitaxial layer by ion implantation, activating at high temperature, and protecting the surface with a carbon film; Depositing a layer of polysilicon on the surface of the implanted epitaxial layer to obtain a silicon layer; Performing N+ type and P type implantation on the silicon layer respectively, and annealing and activating, to obtain a first PN region and a second PN region; Fabricate a gate dielectric layer on the surface of the polysilicon, and fabricate a gate on the surface of the gate dielectric layer; Holes are dug on both sides of the gate to form a source electrode, metal is deposited at the bottom of the substrate and holes are dug on the gate dielectric layer and in the silicon layer to form a drain electrode, thus obtaining a heterogeneously integrated cascode power device.